Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19691639	1			T1	21666		T2	375		T3	41242
all_values[1]	19691639	1			T1	21666		T2	375		T3	41242
all_values[2]	19691639	1			T1	21666		T2	375		T3	41242

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263009

1

T3

11140

T4

956

T14

894

auto[1]

58811908

1

T1

64998

T2

1125

T3

112586

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50259512

1

T1

58756

T2

957

T3

98483

auto[1]

8815405

1

T1

6242

T2

168

T3

25243

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	68356	1			T3	11140		T4	113		T15	484
all_values[0]	auto[0]	auto[1]	363	1			T4	2		T15	2		T25	2
all_values[0]	auto[1]	auto[0]	19601476	1			T1	21643		T2	371		T3	30089
all_values[0]	auto[1]	auto[1]	21444	1			T1	23		T2	4		T3	13
all_values[1]	auto[0]	auto[0]	100293	1			T4	40		T14	894		T15	486
all_values[1]	auto[0]	auto[1]	210	1			T4	1		T43	3		T60	4
all_values[1]	auto[1]	auto[0]	19590839	1			T1	21666		T2	375		T3	41242
all_values[1]	auto[1]	auto[1]	297	1			T4	3		T25	3		T43	2
all_values[2]	auto[0]	auto[0]	45364	1			T4	308		T39	456		T25	36
all_values[2]	auto[0]	auto[1]	48423	1			T4	492		T117	36		T43	3
all_values[2]	auto[1]	auto[0]	10853184	1			T1	15447		T2	211		T3	16012
all_values[2]	auto[1]	auto[1]	8744668	1			T1	6219		T2	164		T3	25230