Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138256

1

T1

26

T2

4

T4

310

auto[1]

133712

1

T1

26

T2

4

T3

34

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	101174	1			T1	21		T3	7		T4	171
len_1026_2046	6279	1			T3	1		T4	12		T5	2
len_514_1022	5240	1			T4	22		T14	1		T15	19
len_2_510	4156	1			T1	1		T4	15		T14	1
len_2056	234	1			T2	1		T4	8		T25	5
len_2048	346	1			T4	9		T15	3		T16	2
len_2040	217	1			T4	3		T43	8		T60	6
len_1032	191	1			T4	3		T25	9		T60	5
len_1024	1855	1			T4	5		T5	2		T15	3
len_1016	184	1			T2	2		T4	2		T43	5
len_520	227	1			T4	9		T25	4		T43	3
len_512	374	1			T3	1		T4	7		T15	5
len_504	211	1			T4	1		T22	1		T25	6
len_8	1282	1			T3	8		T4	15		T25	10
len_0	14014	1			T1	4		T2	1		T4	40

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

101

1

T5

1

T25

2

T129

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	53199	1			T1	11		T4	81		T5	7
auto[0]	len_1026_2046	3246	1			T4	7		T5	2		T15	23
auto[0]	len_514_1022	3567	1			T4	11		T15	11		T16	13
auto[0]	len_2_510	2252	1			T1	1		T4	10		T15	9
auto[0]	len_2056	112	1			T4	3		T25	2		T43	2
auto[0]	len_2048	170	1			T4	5		T15	1		T16	1
auto[0]	len_2040	119	1			T4	1		T43	4		T60	1
auto[0]	len_1032	103	1			T4	2		T25	4		T60	3
auto[0]	len_1024	276	1			T4	4		T5	1		T15	2
auto[0]	len_1016	96	1			T2	2		T4	1		T43	3
auto[0]	len_520	121	1			T4	3		T43	2		T130	2
auto[0]	len_512	215	1			T4	3		T15	3		T16	2
auto[0]	len_504	121	1			T4	1		T22	1		T25	2
auto[0]	len_8	34	1			T130	1		T131	1		T113	3
auto[0]	len_0	5497	1			T1	1		T4	23		T5	4
auto[1]	len_2050_plus	47975	1			T1	10		T3	7		T4	90
auto[1]	len_1026_2046	3033	1			T3	1		T4	5		T15	10
auto[1]	len_514_1022	1673	1			T4	11		T14	1		T15	8
auto[1]	len_2_510	1904	1			T4	5		T14	1		T15	4
auto[1]	len_2056	122	1			T2	1		T4	5		T25	3
auto[1]	len_2048	176	1			T4	4		T15	2		T16	1
auto[1]	len_2040	98	1			T4	2		T43	4		T60	5
auto[1]	len_1032	88	1			T4	1		T25	5		T60	2
auto[1]	len_1024	1579	1			T4	1		T5	1		T15	1
auto[1]	len_1016	88	1			T4	1		T43	2		T60	4
auto[1]	len_520	106	1			T4	6		T25	4		T43	1
auto[1]	len_512	159	1			T3	1		T4	4		T15	2
auto[1]	len_504	90	1			T25	4		T60	1		T132	2
auto[1]	len_8	1248	1			T3	8		T4	15		T25	10
auto[1]	len_0	8517	1			T1	3		T2	1		T4	17

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

56

1

T25

2

T129

2

T71

2

auto[1]

len_upper

45

1

T5

1

T43

2

T33

1