Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4782704 1 T1 7032 T2 116 T3 10756
auto[1] 3192189 1 T1 3848 T2 52 T3 9664


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3155968 1 T1 6461 T2 44 T3 3544
auto[1] 4818925 1 T1 4419 T2 124 T3 16876


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3509636 1 T1 5138 T2 32 T4 16436
auto[1] 4465257 1 T1 5742 T2 136 T3 20420


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4825672 1 T1 6585 T2 84 T3 13523
auto[1] 3149221 1 T1 4295 T2 84 T3 6897


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7294538 1 T1 10494 T2 166 T3 19541
fifo_depth[1] 126640 1 T1 235 T2 1 T3 148
fifo_depth[2] 95586 1 T1 104 T2 1 T3 135
fifo_depth[3] 74302 1 T1 33 T3 130 T4 116
fifo_depth[4] 67712 1 T1 13 T3 130 T4 15
fifo_depth[5] 52847 1 T1 1 T3 117 T4 2
fifo_depth[6] 42668 1 T3 92 T4 1 T5 156
fifo_depth[7] 27084 1 T3 67 T5 132 T14 55


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 680355 1 T1 386 T2 2 T3 879
auto[1] 7294538 1 T1 10494 T2 166 T3 19541


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7965647 1 T1 10880 T2 168 T3 20420
auto[1] 9246 1 T17 33 T25 729 T20 506


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 30481 1 T1 44 T4 21 T5 253
auto[0] auto[0] auto[0] auto[0] auto[1] 30193 1 T1 13 T4 57 T5 152
auto[0] auto[0] auto[0] auto[1] auto[0] 40507 1 T1 87 T4 54 T5 5
auto[0] auto[0] auto[0] auto[1] auto[1] 23634 1 T1 5 T4 35 T5 102
auto[0] auto[0] auto[1] auto[0] auto[0] 129701 1 T1 20 T4 53 T15 42
auto[0] auto[0] auto[1] auto[0] auto[1] 31202 1 T1 24 T4 27 T15 46
auto[0] auto[0] auto[1] auto[1] auto[0] 29404 1 T1 56 T4 94 T14 263
auto[0] auto[0] auto[1] auto[1] auto[1] 28350 1 T4 42 T5 74 T14 162
auto[0] auto[1] auto[0] auto[0] auto[0] 38493 1 T1 52 T3 16 T4 332
auto[0] auto[1] auto[0] auto[0] auto[1] 44178 1 T1 30 T4 8 T14 10
auto[0] auto[1] auto[0] auto[1] auto[0] 44598 1 T4 38 T5 212 T14 6
auto[0] auto[1] auto[0] auto[1] auto[1] 36810 1 T1 8 T4 118 T5 115
auto[0] auto[1] auto[1] auto[0] auto[0] 55090 1 T3 155 T4 16 T14 126
auto[0] auto[1] auto[1] auto[0] auto[1] 44684 1 T1 25 T2 2 T4 174
auto[0] auto[1] auto[1] auto[1] auto[0] 36477 1 T4 2 T5 122 T14 9
auto[0] auto[1] auto[1] auto[1] auto[1] 36553 1 T1 22 T3 708 T4 250
auto[1] auto[0] auto[0] auto[0] auto[0] 203869 1 T1 1019 T2 32 T4 1053
auto[1] auto[0] auto[0] auto[0] auto[1] 186762 1 T1 511 T4 1874 T5 1064
auto[1] auto[0] auto[0] auto[1] auto[0] 204444 1 T1 1363 T4 1404 T5 40
auto[1] auto[0] auto[0] auto[1] auto[1] 216702 1 T1 79 T4 1413 T5 378
auto[1] auto[0] auto[1] auto[0] auto[0] 1752457 1 T1 405 T4 2074 T5 2876
auto[1] auto[0] auto[1] auto[0] auto[1] 197161 1 T1 416 T4 1225 T14 406
auto[1] auto[0] auto[1] auto[1] auto[0] 205674 1 T1 902 T4 2411 T5 1
auto[1] auto[0] auto[1] auto[1] auto[1] 199095 1 T1 194 T4 4599 T5 226
auto[1] auto[1] auto[0] auto[0] auto[0] 515627 1 T1 1820 T3 13 T4 7252
auto[1] auto[1] auto[0] auto[0] auto[1] 501951 1 T1 729 T2 12 T3 1201
auto[1] auto[1] auto[0] auto[1] auto[0] 467487 1 T1 273 T3 2314 T4 3467
auto[1] auto[1] auto[0] auto[1] auto[1] 570232 1 T1 428 T4 20359 T5 374
auto[1] auto[1] auto[1] auto[0] auto[0] 518244 1 T1 543 T3 9367 T4 2032
auto[1] auto[1] auto[1] auto[0] auto[1] 502611 1 T1 1381 T2 70 T3 4
auto[1] auto[1] auto[1] auto[1] auto[0] 553119 1 T1 1 T2 52 T3 1658
auto[1] auto[1] auto[1] auto[1] auto[1] 499103 1 T1 430 T3 4984 T4 7937


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 234120 1 T1 1063 T2 32 T4 1074
auto[0] auto[0] auto[0] auto[0] auto[1] 215218 1 T1 524 T4 1931 T5 1216
auto[0] auto[0] auto[0] auto[1] auto[0] 244307 1 T1 1450 T4 1458 T5 45
auto[0] auto[0] auto[0] auto[1] auto[1] 240210 1 T1 84 T4 1448 T5 480
auto[0] auto[0] auto[1] auto[0] auto[0] 1881272 1 T1 425 T4 2127 T5 2876
auto[0] auto[0] auto[1] auto[0] auto[1] 227720 1 T1 440 T4 1252 T14 406
auto[0] auto[0] auto[1] auto[1] auto[0] 234847 1 T1 958 T4 2505 T5 1
auto[0] auto[0] auto[1] auto[1] auto[1] 226489 1 T1 194 T4 4641 T5 300
auto[0] auto[1] auto[0] auto[0] auto[0] 553520 1 T1 1872 T3 29 T4 7584
auto[0] auto[1] auto[0] auto[0] auto[1] 545359 1 T1 759 T2 12 T3 1201
auto[0] auto[1] auto[0] auto[1] auto[0] 511030 1 T1 273 T3 2314 T4 3505
auto[0] auto[1] auto[0] auto[1] auto[1] 606821 1 T1 436 T4 20477 T5 489
auto[0] auto[1] auto[1] auto[0] auto[0] 572854 1 T1 543 T3 9522 T4 2048
auto[0] auto[1] auto[1] auto[0] auto[1] 547105 1 T1 1406 T2 72 T3 4
auto[0] auto[1] auto[1] auto[1] auto[0] 589148 1 T1 1 T2 52 T3 1658
auto[0] auto[1] auto[1] auto[1] auto[1] 535627 1 T1 452 T3 5692 T4 8187
auto[1] auto[0] auto[0] auto[0] auto[0] 230 1 T20 26 T21 51 T6 4
auto[1] auto[0] auto[0] auto[0] auto[1] 1737 1 T25 100 T21 5 T135 582
auto[1] auto[0] auto[0] auto[1] auto[0] 644 1 T21 9 T136 247 T137 14
auto[1] auto[0] auto[0] auto[1] auto[1] 126 1 T20 1 T138 6 T24 23
auto[1] auto[0] auto[1] auto[0] auto[0] 886 1 T25 624 T20 86 T139 6
auto[1] auto[0] auto[1] auto[0] auto[1] 643 1 T20 218 T21 1 T137 32
auto[1] auto[0] auto[1] auto[1] auto[0] 231 1 T137 74 T135 6 T140 9
auto[1] auto[0] auto[1] auto[1] auto[1] 956 1 T21 132 T139 281 T6 77
auto[1] auto[1] auto[0] auto[0] auto[0] 600 1 T21 5 T136 176 T140 113
auto[1] auto[1] auto[0] auto[0] auto[1] 770 1 T17 20 T25 5 T20 16
auto[1] auto[1] auto[0] auto[1] auto[0] 1055 1 T21 11 T135 154 T140 42
auto[1] auto[1] auto[0] auto[1] auto[1] 221 1 T20 112 T137 21 T135 2
auto[1] auto[1] auto[1] auto[0] auto[0] 480 1 T17 13 T20 42 T21 4
auto[1] auto[1] auto[1] auto[0] auto[1] 190 1 T21 7 T137 16 T135 13
auto[1] auto[1] auto[1] auto[1] auto[0] 448 1 T20 5 T21 3 T138 319
auto[1] auto[1] auto[1] auto[1] auto[1] 29 1 T138 2 T24 11 T61 16


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 203869 1 T1 1019 T2 32 T4 1053
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 186762 1 T1 511 T4 1874 T5 1064
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 204444 1 T1 1363 T4 1404 T5 40
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 216702 1 T1 79 T4 1413 T5 378
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1752457 1 T1 405 T4 2074 T5 2876
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 197161 1 T1 416 T4 1225 T14 406
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 205674 1 T1 902 T4 2411 T5 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 199095 1 T1 194 T4 4599 T5 226
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 515627 1 T1 1820 T3 13 T4 7252
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 501951 1 T1 729 T2 12 T3 1201
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 467487 1 T1 273 T3 2314 T4 3467
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 570232 1 T1 428 T4 20359 T5 374
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 518244 1 T1 543 T3 9367 T4 2032
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 502611 1 T1 1381 T2 70 T3 4
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 553119 1 T1 1 T2 52 T3 1658
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 499103 1 T1 430 T3 4984 T4 7937
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4482 1 T1 29 T4 13 T5 49
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3549 1 T1 9 T4 36 T5 21
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4927 1 T1 55 T4 33 T5 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 4345 1 T1 4 T4 21 T5 11
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 40712 1 T1 7 T4 37 T15 10
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 4456 1 T1 15 T4 15 T15 1
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4477 1 T1 34 T4 61 T14 52
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3902 1 T4 25 T5 10 T14 19
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6657 1 T1 34 T3 4 T4 201
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 7269 1 T1 15 T4 5 T14 1
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6518 1 T4 19 T5 28 T25 82
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6495 1 T1 4 T4 68 T5 15
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8477 1 T3 33 T4 7 T14 25
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6765 1 T1 15 T2 1 T4 108
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6598 1 T5 22 T16 4 T38 11
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 7011 1 T1 14 T3 111 T4 145
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3522 1 T1 11 T4 8 T5 51
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2850 1 T1 4 T4 17 T5 18
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3973 1 T1 20 T4 15 T5 1
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3289 1 T4 10 T5 17 T14 5
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 25702 1 T1 10 T4 14 T15 11
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3785 1 T1 5 T4 9 T15 9
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3644 1 T1 15 T4 29 T14 46
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2975 1 T4 15 T5 12 T14 20
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5487 1 T1 10 T3 3 T4 91
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 6091 1 T1 13 T4 2 T14 2
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5418 1 T4 12 T5 32 T25 85
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5345 1 T1 4 T4 38 T5 19
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6890 1 T3 23 T4 5 T14 25
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5720 1 T1 7 T2 1 T4 50
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5213 1 T5 16 T14 3 T16 3
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5682 1 T1 5 T3 109 T4 78
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2816 1 T1 3 T5 48 T15 7
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2212 1 T4 4 T5 29 T15 2
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 3042 1 T1 8 T4 6 T17 15
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2440 1 T1 1 T4 4 T5 17
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 18148 1 T1 3 T4 1 T15 7
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2749 1 T1 2 T4 3 T15 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2802 1 T1 6 T4 4 T14 50
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2178 1 T4 2 T5 10 T14 26
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4464 1 T1 5 T4 38 T14 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 5228 1 T1 2 T4 1 T14 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4505 1 T4 6 T5 25 T14 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4353 1 T4 8 T5 13 T25 134
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5563 1 T3 34 T4 1 T14 21
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4777 1 T1 1 T4 16 T14 30
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4077 1 T4 1 T5 20 T16 2
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4948 1 T1 2 T3 96 T4 21
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2741 1 T5 41 T15 6 T16 3
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2280 1 T5 21 T15 2 T39 2
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 3025 1 T1 4 T16 6 T17 18
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2306 1 T5 15 T14 4 T15 52
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 13546 1 T4 1 T15 8 T22 1061
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2584 1 T1 2 T15 23 T25 37
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2747 1 T1 1 T14 45 T15 27
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2131 1 T5 7 T14 28 T15 4
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4364 1 T1 3 T3 3 T4 2
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4859 1 T14 3 T16 1 T25 125
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4374 1 T4 1 T5 24 T14 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3929 1 T4 3 T5 18 T15 6
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5496 1 T3 19 T4 2 T14 22
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4618 1 T1 2 T14 36 T15 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4021 1 T4 1 T5 16 T16 5
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4691 1 T1 1 T3 108 T4 5
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2141 1 T1 1 T5 22 T15 3
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1721 1 T5 18 T15 3 T25 127
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2241 1 T5 1 T17 12 T25 151
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1778 1 T5 16 T14 11 T16 2
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 9493 1 T15 1 T22 724 T25 107
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1906 1 T15 2 T25 32 T129 28
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 2120 1 T14 32 T15 2 T25 89
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1577 1 T5 10 T14 25 T15 2
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3407 1 T3 1 T25 291 T129 15
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4294 1 T14 1 T25 130 T129 15
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3591 1 T5 35 T14 1 T25 71
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3371 1 T4 1 T5 18 T25 104
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4041 1 T3 22 T14 16 T17 58
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3841 1 T14 31 T40 92 T25 33
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3319 1 T5 21 T14 1 T16 4
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4006 1 T3 94 T4 1 T5 51
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1880 1 T5 19 T40 31 T25 52
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1515 1 T5 16 T15 1 T25 105
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1972 1 T5 2 T17 15 T25 105
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1444 1 T5 9 T14 8 T16 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6500 1 T15 2 T22 392 T25 99
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1561 1 T15 2 T25 31 T129 27
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1616 1 T14 26 T15 19 T25 85
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1430 1 T5 12 T14 19 T15 2
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3009 1 T3 2 T14 1 T25 241
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3409 1 T14 1 T17 2 T25 104
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2940 1 T5 26 T14 2 T25 46
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2663 1 T5 15 T15 7 T25 89
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3751 1 T3 18 T4 1 T14 9
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3018 1 T14 23 T40 60 T25 22
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2675 1 T5 9 T25 32 T129 17
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3285 1 T3 72 T5 48 T16 1
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1158 1 T5 13 T15 1 T40 19
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 964 1 T5 15 T15 1 T25 76
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1213 1 T17 18 T25 99 T129 15
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 934 1 T5 11 T14 4 T25 15
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 3646 1 T15 2 T22 160 T25 57
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1022 1 T25 30 T129 20 T141 6
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1121 1 T14 9 T15 1 T25 65
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 936 1 T5 8 T14 14 T15 2
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1765 1 T3 2 T14 1 T25 170
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2171 1 T14 1 T25 75 T129 5
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2012 1 T5 25 T25 27 T129 4
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1711 1 T5 10 T25 61 T142 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2377 1 T3 5 T14 7 T17 58
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2036 1 T14 18 T40 34 T25 22
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1795 1 T5 10 T14 1 T25 23
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2223 1 T3 60 T5 40 T25 23

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