Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19691639	1			T1	21666		T2	375		T3	41242
all_pins[1]	19691639	1			T1	21666		T2	375		T3	41242
all_pins[2]	19691639	1			T1	21666		T2	375		T3	41242

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50307600	1			T1	58756		T2	956		T3	98481
values[0x1]	8767317	1			T1	6242		T2	169		T3	25245
transitions[0x0=>0x1]	8767138	1			T1	6242		T2	169		T3	25245
transitions[0x1=>0x0]	8767151	1			T1	6242		T2	169		T3	25245

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19669312	1			T1	21643		T2	370		T3	41227
all_pins[0]	values[0x1]	22327	1			T1	23		T2	5		T3	15
all_pins[0]	transitions[0x0=>0x1]	22247	1			T1	23		T2	5		T3	15
all_pins[0]	transitions[0x1=>0x0]	8744601	1			T1	6219		T2	164		T3	25230
all_pins[1]	values[0x0]	19691317	1			T1	21666		T2	375		T3	41242
all_pins[1]	values[0x1]	322	1			T4	3		T25	3		T43	2
all_pins[1]	transitions[0x0=>0x1]	272	1			T4	2		T25	3		T43	1
all_pins[1]	transitions[0x1=>0x0]	22277	1			T1	23		T2	5		T3	15
all_pins[2]	values[0x0]	10946971	1			T1	15447		T2	211		T3	16012
all_pins[2]	values[0x1]	8744668	1			T1	6219		T2	164		T3	25230
all_pins[2]	transitions[0x0=>0x1]	8744619	1			T1	6219		T2	164		T3	25230
all_pins[2]	transitions[0x1=>0x0]	273	1			T4	3		T25	3		T43	2