Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 974 1 T4 11 T43 14 T60 17
all_values[1] 974 1 T4 11 T43 14 T60 17
all_values[2] 974 1 T4 11 T43 14 T60 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1473 1 T4 10 T43 19 T60 29
auto[1] 1449 1 T4 23 T43 23 T60 22


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1004 1 T4 11 T43 15 T60 13
auto[1] 1918 1 T4 22 T43 27 T60 38


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1646 1 T4 22 T43 26 T60 26
auto[1] 1276 1 T4 11 T43 16 T60 25


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 177 1 T4 2 T60 4 T33 1
all_values[0] auto[0] auto[0] auto[1] 92 1 T60 2 T33 2 T6 4
all_values[0] auto[0] auto[1] auto[0] 181 1 T4 3 T43 4 T60 2
all_values[0] auto[0] auto[1] auto[1] 99 1 T4 2 T43 3 T60 1
all_values[0] auto[1] auto[0] auto[1] 210 1 T43 3 T60 4 T33 1
all_values[0] auto[1] auto[1] auto[1] 215 1 T4 4 T43 4 T60 4
all_values[1] auto[0] auto[0] auto[0] 139 1 T43 3 T60 1 T33 2
all_values[1] auto[0] auto[0] auto[1] 130 1 T43 2 T60 4 T33 1
all_values[1] auto[0] auto[1] auto[0] 167 1 T4 3 T43 2 T60 1
all_values[1] auto[0] auto[1] auto[1] 127 1 T4 4 T43 2 T60 2
all_values[1] auto[1] auto[0] auto[1] 216 1 T4 1 T43 4 T60 6
all_values[1] auto[1] auto[1] auto[1] 195 1 T4 3 T43 1 T60 3
all_values[2] auto[0] auto[0] auto[0] 175 1 T4 2 T43 4 T60 2
all_values[2] auto[0] auto[0] auto[1] 115 1 T4 3 T43 1 T60 3
all_values[2] auto[0] auto[1] auto[0] 165 1 T4 1 T43 2 T60 3
all_values[2] auto[0] auto[1] auto[1] 79 1 T4 2 T43 3 T60 1
all_values[2] auto[1] auto[0] auto[1] 219 1 T4 2 T43 2 T60 3
all_values[2] auto[1] auto[1] auto[1] 221 1 T4 1 T43 2 T60 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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