Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4935	1			T1	6		T2	1		T3	2
sha2_none	4904	1			T1	6		T2	1		T3	5
sha2_512	8279	1			T1	7		T2	1		T3	4
sha2_384	7935	1			T1	6		T2	3		T3	5
sha2_256	6999	1			T1	10		T3	6		T4	82

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20284

1

T1

21

T2

4

T3

15

auto[1]

13146

1

T1

14

T2

2

T3

7

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12938

1

T1

22

T2

2

T3

9

auto[1]

20492

1

T1

13

T2

4

T3

13

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17462

1

T1

20

T2

5

T3

22

disabled

15968

1

T1

15

T2

1

T4

193

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5239	1			T1	3		T2	1		T3	4
key_none	8200	1			T1	2		T2	2		T3	6
key_1024	4762	1			T1	4		T3	4		T4	54
key_512	4268	1			T1	4		T2	2		T3	3
key_384	3875	1			T1	5		T3	3		T4	44
key_256	3700	1			T1	8		T2	1		T3	1
key_128	3310	1			T1	9		T3	1		T4	54

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20522

1

T1

18

T2

3

T3

12

auto[1]

12908

1

T1

17

T2

3

T3

10

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

33223

1

T1

35

T2

6

T3

22

disabled

207

1

T4

3

T25

2

T29

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1827

1

T1

6

T3

2

T4

25

enabled

auto[0]

auto[0]

auto[1]

1823

1

T1

4

T2

1

T3

5

enabled

auto[0]

auto[1]

auto[0]

1794

1

T1

1

T3

2

T4

31

enabled

auto[0]

auto[1]

auto[1]

1862

1

T1

2

T4

39

T5

2

enabled

auto[1]

auto[0]

auto[0]

4481

1

T1

1

T3

6

T4

30

enabled

auto[1]

auto[0]

auto[1]

1888

1

T1

4

T2

2

T3

2

enabled

auto[1]

auto[1]

auto[0]

1987

1

T1

1

T2

2

T3

2

enabled

auto[1]

auto[1]

auto[1]

1800

1

T1

1

T3

3

T4

33

disabled

auto[0]

auto[0]

auto[0]

1396

1

T1

2

T2

1

T4

23

disabled

auto[0]

auto[0]

auto[1]

1359

1

T1

2

T4

26

T5

5

disabled

auto[0]

auto[1]

auto[0]

1458

1

T1

4

T4

16

T5

2

disabled

auto[0]

auto[1]

auto[1]

1419

1

T1

1

T4

20

T5

5

disabled

auto[1]

auto[0]

auto[0]

6166

1

T1

1

T4

30

T5

2

disabled

auto[1]

auto[0]

auto[1]

1344

1

T1

1

T4

20

T14

1

disabled

auto[1]

auto[1]

auto[0]

1413

1

T1

2

T4

30

T5

1

disabled

auto[1]

auto[1]

auto[1]

1413

1

T1

2

T4

28

T5

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17384

1

T1

20

T2

5

T3

22

enabled

disabled

78

1

T25

2

T29

1

T128

1

disabled

disabled

129

1

T4

3

T65

1

T116

4

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15839

1

T1

15

T2

1

T4

190

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1266	1			T4	19		T5	2		T14	1
key_invalid	sha2_none	945	1			T4	12		T16	1		T38	2
key_invalid	sha2_512	989	1			T3	1		T4	20		T5	1
key_invalid	sha2_384	976	1			T1	1		T2	1		T3	1
key_invalid	sha2_256	970	1			T1	2		T3	2		T4	14
key_none	sha2_invalid	604	1			T1	1		T3	2		T4	12
key_none	sha2_none	654	1			T1	1		T2	1		T3	2
key_none	sha2_512	2633	1			T4	11		T5	1		T14	2
key_none	sha2_384	2609	1			T2	1		T3	2		T4	11
key_none	sha2_256	1654	1			T4	14		T5	1		T15	1
key_1024	sha2_invalid	566	1			T1	2		T4	10		T5	1
key_1024	sha2_none	654	1			T3	2		T4	9		T17	2
key_1024	sha2_512	1818	1			T1	1		T3	1		T4	13
key_1024	sha2_384	966	1			T1	1		T3	1		T4	11
key_512	sha2_invalid	642	1			T1	1		T2	1		T4	7
key_512	sha2_none	638	1			T1	1		T4	15		T14	1
key_512	sha2_512	685	1			T2	1		T4	8		T5	2
key_512	sha2_384	1288	1			T1	1		T3	1		T4	11
key_512	sha2_256	969	1			T1	1		T3	2		T4	11
key_384	sha2_invalid	653	1			T4	14		T5	1		T14	1
key_384	sha2_none	652	1			T1	1		T4	9		T5	1
key_384	sha2_512	716	1			T1	1		T3	1		T4	6
key_384	sha2_384	681	1			T1	2		T4	5		T14	2
key_384	sha2_256	1132	1			T1	1		T3	2		T4	10
key_256	sha2_invalid	586	1			T1	2		T4	14		T5	1
key_256	sha2_none	705	1			T3	1		T4	9		T16	1
key_256	sha2_512	744	1			T1	2		T4	15		T5	3
key_256	sha2_384	726	1			T2	1		T4	16		T16	1
key_256	sha2_256	889	1			T1	4		T4	15		T5	1
key_128	sha2_invalid	597	1			T4	9		T14	1		T15	1
key_128	sha2_none	642	1			T1	3		T4	16		T5	1
key_128	sha2_512	678	1			T1	3		T3	1		T4	10
key_128	sha2_384	678	1			T1	1		T4	10		T15	1
key_128	sha2_256	669	1			T1	2		T4	8		T14	3

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

705

1

T4

10

T14

1

T15

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1266	1			T4	19		T5	2		T14	1
key_invalid	sha2_none	945	1			T4	12		T16	1		T38	2
key_invalid	sha2_512	989	1			T3	1		T4	20		T5	1
key_invalid	sha2_384	976	1			T1	1		T2	1		T3	1
key_invalid	sha2_256	970	1			T1	2		T3	2		T4	14
key_none	sha2_invalid	604	1			T1	1		T3	2		T4	12
key_none	sha2_none	654	1			T1	1		T2	1		T3	2
key_none	sha2_512	2633	1			T4	11		T5	1		T14	2
key_none	sha2_384	2609	1			T2	1		T3	2		T4	11
key_none	sha2_256	1654	1			T4	14		T5	1		T15	1
key_1024	sha2_invalid	566	1			T1	2		T4	10		T5	1
key_1024	sha2_none	654	1			T3	2		T4	9		T17	2
key_1024	sha2_512	1818	1			T1	1		T3	1		T4	13
key_1024	sha2_384	966	1			T1	1		T3	1		T4	11
key_1024	sha2_256	705	1			T4	10		T14	1		T15	1
key_512	sha2_invalid	642	1			T1	1		T2	1		T4	7
key_512	sha2_none	638	1			T1	1		T4	15		T14	1
key_512	sha2_512	685	1			T2	1		T4	8		T5	2
key_512	sha2_384	1288	1			T1	1		T3	1		T4	11
key_512	sha2_256	969	1			T1	1		T3	2		T4	11
key_384	sha2_invalid	653	1			T4	14		T5	1		T14	1
key_384	sha2_none	652	1			T1	1		T4	9		T5	1
key_384	sha2_512	716	1			T1	1		T3	1		T4	6
key_384	sha2_384	681	1			T1	2		T4	5		T14	2
key_384	sha2_256	1132	1			T1	1		T3	2		T4	10
key_256	sha2_invalid	586	1			T1	2		T4	14		T5	1
key_256	sha2_none	705	1			T3	1		T4	9		T16	1
key_256	sha2_512	744	1			T1	2		T4	15		T5	3
key_256	sha2_384	726	1			T2	1		T4	16		T16	1
key_256	sha2_256	889	1			T1	4		T4	15		T5	1
key_128	sha2_invalid	597	1			T4	9		T14	1		T15	1
key_128	sha2_none	642	1			T1	3		T4	16		T5	1
key_128	sha2_512	678	1			T1	3		T3	1		T4	10
key_128	sha2_384	678	1			T1	1		T4	10		T15	1
key_128	sha2_256	669	1			T1	2		T4	8		T14	3