Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 659
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T531 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2952502569 Jul 20 06:27:57 PM PDT 24 Jul 20 06:28:01 PM PDT 24 17565381 ps
T532 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2753231078 Jul 20 06:27:56 PM PDT 24 Jul 20 06:27:59 PM PDT 24 13928712 ps
T533 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2371236277 Jul 20 06:27:48 PM PDT 24 Jul 20 06:27:52 PM PDT 24 1210048817 ps
T534 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3267263183 Jul 20 06:28:00 PM PDT 24 Jul 20 06:28:05 PM PDT 24 12725581 ps
T535 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.331028175 Jul 20 06:27:39 PM PDT 24 Jul 20 06:27:42 PM PDT 24 221465224 ps
T536 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2834867451 Jul 20 06:27:48 PM PDT 24 Jul 20 06:27:52 PM PDT 24 59567321 ps
T108 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3270883192 Jul 20 06:27:35 PM PDT 24 Jul 20 06:27:36 PM PDT 24 68798891 ps
T57 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.101516238 Jul 20 06:27:37 PM PDT 24 Jul 20 06:27:40 PM PDT 24 1250874076 ps
T537 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1060927117 Jul 20 06:27:52 PM PDT 24 Jul 20 06:27:54 PM PDT 24 12793200 ps
T538 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3587635895 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:54 PM PDT 24 15891935 ps
T539 /workspace/coverage/cover_reg_top/19.hmac_intr_test.4248528877 Jul 20 06:27:54 PM PDT 24 Jul 20 06:27:57 PM PDT 24 15482813 ps
T540 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3542584435 Jul 20 06:27:55 PM PDT 24 Jul 20 06:27:57 PM PDT 24 25919083 ps
T541 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3946267679 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:00 PM PDT 24 16000727 ps
T542 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.999819879 Jul 20 06:27:35 PM PDT 24 Jul 20 06:27:40 PM PDT 24 165877974 ps
T543 /workspace/coverage/cover_reg_top/34.hmac_intr_test.769173410 Jul 20 06:28:01 PM PDT 24 Jul 20 06:28:06 PM PDT 24 37471778 ps
T544 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2744838107 Jul 20 06:27:27 PM PDT 24 Jul 20 06:27:32 PM PDT 24 529847130 ps
T545 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2162955390 Jul 20 06:27:37 PM PDT 24 Jul 20 06:27:41 PM PDT 24 153363641 ps
T546 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3016908247 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:53 PM PDT 24 15611088 ps
T547 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3218709964 Jul 20 06:27:38 PM PDT 24 Jul 20 06:27:41 PM PDT 24 152312059 ps
T548 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3533467683 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:00 PM PDT 24 72775157 ps
T549 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1621420065 Jul 20 06:27:32 PM PDT 24 Jul 20 06:27:33 PM PDT 24 12402696 ps
T58 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1232285696 Jul 20 06:27:53 PM PDT 24 Jul 20 06:27:56 PM PDT 24 672730973 ps
T550 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2135034455 Jul 20 06:27:50 PM PDT 24 Jul 20 06:27:52 PM PDT 24 44378013 ps
T551 /workspace/coverage/cover_reg_top/36.hmac_intr_test.974691515 Jul 20 06:27:57 PM PDT 24 Jul 20 06:28:00 PM PDT 24 22952215 ps
T59 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3587271728 Jul 20 06:27:49 PM PDT 24 Jul 20 06:27:54 PM PDT 24 3807326466 ps
T109 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2867006307 Jul 20 06:27:47 PM PDT 24 Jul 20 06:27:50 PM PDT 24 149915015 ps
T552 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.866695794 Jul 20 06:27:42 PM PDT 24 Jul 20 06:27:46 PM PDT 24 249220339 ps
T94 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.350836329 Jul 20 06:27:37 PM PDT 24 Jul 20 06:27:39 PM PDT 24 76221352 ps
T95 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1368530242 Jul 20 06:27:52 PM PDT 24 Jul 20 06:28:05 PM PDT 24 4192668150 ps
T123 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3850232086 Jul 20 06:27:34 PM PDT 24 Jul 20 06:27:38 PM PDT 24 479975228 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2055343502 Jul 20 06:27:40 PM PDT 24 Jul 20 06:27:44 PM PDT 24 57675325 ps
T97 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.464697503 Jul 20 06:27:57 PM PDT 24 Jul 20 06:28:01 PM PDT 24 37497651 ps
T98 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2330817472 Jul 20 06:27:56 PM PDT 24 Jul 20 06:27:59 PM PDT 24 19395813 ps
T553 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.874965321 Jul 20 06:27:35 PM PDT 24 Jul 20 06:27:38 PM PDT 24 51707281 ps
T118 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3861538969 Jul 20 06:27:44 PM PDT 24 Jul 20 06:27:46 PM PDT 24 164932105 ps
T119 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3870184296 Jul 20 06:27:31 PM PDT 24 Jul 20 06:27:35 PM PDT 24 668378902 ps
T110 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.585467802 Jul 20 06:27:44 PM PDT 24 Jul 20 06:27:47 PM PDT 24 129850621 ps
T554 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3227649910 Jul 20 06:27:40 PM PDT 24 Jul 20 06:27:43 PM PDT 24 72518324 ps
T111 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1765972257 Jul 20 06:27:40 PM PDT 24 Jul 20 06:27:42 PM PDT 24 20597981 ps
T112 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1344959906 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:54 PM PDT 24 188512746 ps
T99 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3826864893 Jul 20 06:27:42 PM PDT 24 Jul 20 06:27:44 PM PDT 24 67920522 ps
T555 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1171573750 Jul 20 06:27:44 PM PDT 24 Jul 20 06:38:56 PM PDT 24 68615739030 ps
T124 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2599932285 Jul 20 06:27:46 PM PDT 24 Jul 20 06:27:48 PM PDT 24 92837819 ps
T556 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2910644492 Jul 20 06:27:27 PM PDT 24 Jul 20 06:27:30 PM PDT 24 129378474 ps
T557 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3576062222 Jul 20 06:27:32 PM PDT 24 Jul 20 06:27:41 PM PDT 24 1762318771 ps
T558 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2355265117 Jul 20 06:28:01 PM PDT 24 Jul 20 06:28:07 PM PDT 24 13779797 ps
T559 /workspace/coverage/cover_reg_top/21.hmac_intr_test.457471327 Jul 20 06:27:53 PM PDT 24 Jul 20 06:27:55 PM PDT 24 42025467 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.761528264 Jul 20 06:27:44 PM PDT 24 Jul 20 06:27:46 PM PDT 24 36349825 ps
T561 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3275251739 Jul 20 06:27:54 PM PDT 24 Jul 20 06:27:57 PM PDT 24 47466194 ps
T562 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1783163625 Jul 20 06:27:31 PM PDT 24 Jul 20 06:27:36 PM PDT 24 363319917 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3212537523 Jul 20 06:27:26 PM PDT 24 Jul 20 06:27:38 PM PDT 24 217505587 ps
T563 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3558080598 Jul 20 06:27:57 PM PDT 24 Jul 20 06:28:02 PM PDT 24 11318734 ps
T564 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2055410691 Jul 20 06:27:50 PM PDT 24 Jul 20 06:27:52 PM PDT 24 71714279 ps
T565 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1119974253 Jul 20 06:27:59 PM PDT 24 Jul 20 06:28:07 PM PDT 24 180910714 ps
T566 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.281413225 Jul 20 06:27:42 PM PDT 24 Jul 20 06:27:46 PM PDT 24 297747288 ps
T101 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1725058375 Jul 20 06:27:44 PM PDT 24 Jul 20 06:27:45 PM PDT 24 33812142 ps
T567 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3701128268 Jul 20 06:27:53 PM PDT 24 Jul 20 06:27:55 PM PDT 24 22013538 ps
T568 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1952670094 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:00 PM PDT 24 109655196 ps
T120 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1785672819 Jul 20 06:27:40 PM PDT 24 Jul 20 06:27:45 PM PDT 24 198737527 ps
T569 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.212495270 Jul 20 06:27:37 PM PDT 24 Jul 20 06:27:44 PM PDT 24 759639233 ps
T570 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.373237335 Jul 20 06:27:52 PM PDT 24 Jul 20 06:27:57 PM PDT 24 646324918 ps
T121 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3064582062 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:55 PM PDT 24 356445458 ps
T571 /workspace/coverage/cover_reg_top/24.hmac_intr_test.692475948 Jul 20 06:27:55 PM PDT 24 Jul 20 06:27:58 PM PDT 24 57336418 ps
T122 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.539540300 Jul 20 06:27:23 PM PDT 24 Jul 20 06:27:29 PM PDT 24 191035082 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3390626546 Jul 20 06:27:33 PM PDT 24 Jul 20 06:27:34 PM PDT 24 42838502 ps
T572 /workspace/coverage/cover_reg_top/9.hmac_intr_test.616289957 Jul 20 06:27:39 PM PDT 24 Jul 20 06:27:41 PM PDT 24 71805275 ps
T573 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2514946295 Jul 20 06:27:35 PM PDT 24 Jul 20 06:27:37 PM PDT 24 232236001 ps
T574 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2342370559 Jul 20 06:27:55 PM PDT 24 Jul 20 06:27:58 PM PDT 24 26085325 ps
T125 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2258519457 Jul 20 06:27:32 PM PDT 24 Jul 20 06:27:35 PM PDT 24 305613755 ps
T575 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1560797564 Jul 20 06:27:24 PM PDT 24 Jul 20 06:27:27 PM PDT 24 56288634 ps
T576 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.152630006 Jul 20 06:27:52 PM PDT 24 Jul 20 06:27:55 PM PDT 24 55039254 ps
T577 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4046148765 Jul 20 06:27:38 PM PDT 24 Jul 20 06:27:39 PM PDT 24 13708945 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.788102301 Jul 20 06:27:24 PM PDT 24 Jul 20 06:27:32 PM PDT 24 339738517 ps
T578 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1526401030 Jul 20 06:27:33 PM PDT 24 Jul 20 06:27:35 PM PDT 24 63803889 ps
T104 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.4137077810 Jul 20 06:27:46 PM PDT 24 Jul 20 06:27:48 PM PDT 24 41870390 ps
T579 /workspace/coverage/cover_reg_top/18.hmac_intr_test.230621702 Jul 20 06:27:55 PM PDT 24 Jul 20 06:27:57 PM PDT 24 15685711 ps
T580 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1783961975 Jul 20 06:27:32 PM PDT 24 Jul 20 06:27:33 PM PDT 24 29842706 ps
T581 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.339082343 Jul 20 06:27:28 PM PDT 24 Jul 20 06:27:31 PM PDT 24 90251987 ps
T582 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2099733521 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:00 PM PDT 24 31309252 ps
T583 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3319735614 Jul 20 06:27:49 PM PDT 24 Jul 20 06:27:51 PM PDT 24 55900074 ps
T584 /workspace/coverage/cover_reg_top/10.hmac_intr_test.403844491 Jul 20 06:27:54 PM PDT 24 Jul 20 06:27:57 PM PDT 24 87651016 ps
T585 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1055910409 Jul 20 06:27:55 PM PDT 24 Jul 20 06:27:57 PM PDT 24 15676578 ps
T586 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2853084649 Jul 20 06:27:41 PM PDT 24 Jul 20 06:27:43 PM PDT 24 16344772 ps
T126 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.643737887 Jul 20 06:27:54 PM PDT 24 Jul 20 06:27:59 PM PDT 24 315539375 ps
T587 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1850475174 Jul 20 06:27:32 PM PDT 24 Jul 20 06:27:34 PM PDT 24 50549731 ps
T588 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3668295257 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:52 PM PDT 24 12717336 ps
T589 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3453333640 Jul 20 06:27:38 PM PDT 24 Jul 20 06:27:42 PM PDT 24 603121377 ps
T590 /workspace/coverage/cover_reg_top/13.hmac_intr_test.356888379 Jul 20 06:27:50 PM PDT 24 Jul 20 06:27:52 PM PDT 24 55801843 ps
T591 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1667732702 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:01 PM PDT 24 359695944 ps
T105 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4023099753 Jul 20 06:27:59 PM PDT 24 Jul 20 06:28:05 PM PDT 24 158598841 ps
T592 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3091238615 Jul 20 06:27:37 PM PDT 24 Jul 20 06:27:40 PM PDT 24 193802986 ps
T593 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.488847740 Jul 20 06:27:55 PM PDT 24 Jul 20 06:27:59 PM PDT 24 74376966 ps
T594 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4034740994 Jul 20 06:27:26 PM PDT 24 Jul 20 06:27:31 PM PDT 24 161474714 ps
T595 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1039313431 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:00 PM PDT 24 48028997 ps
T596 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4008769281 Jul 20 06:27:30 PM PDT 24 Jul 20 06:27:32 PM PDT 24 257853737 ps
T597 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.408676880 Jul 20 06:27:58 PM PDT 24 Jul 20 06:28:03 PM PDT 24 20623574 ps
T598 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2149771489 Jul 20 06:27:34 PM PDT 24 Jul 20 06:27:37 PM PDT 24 116650680 ps
T599 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4251457968 Jul 20 06:28:02 PM PDT 24 Jul 20 06:28:07 PM PDT 24 14778605 ps
T600 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3860452240 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:54 PM PDT 24 148273270 ps
T601 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.304870767 Jul 20 06:27:34 PM PDT 24 Jul 20 06:27:35 PM PDT 24 30904568 ps
T602 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.123398519 Jul 20 06:27:27 PM PDT 24 Jul 20 06:27:30 PM PDT 24 13579772 ps
T603 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2966636476 Jul 20 06:27:49 PM PDT 24 Jul 20 06:27:51 PM PDT 24 102823351 ps
T604 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2057283628 Jul 20 06:27:54 PM PDT 24 Jul 20 06:28:00 PM PDT 24 452936102 ps
T605 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4011910002 Jul 20 06:27:53 PM PDT 24 Jul 20 06:27:59 PM PDT 24 267855543 ps
T606 /workspace/coverage/cover_reg_top/5.hmac_intr_test.478959676 Jul 20 06:27:36 PM PDT 24 Jul 20 06:27:37 PM PDT 24 12817969 ps
T607 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3664156849 Jul 20 06:27:31 PM PDT 24 Jul 20 06:27:32 PM PDT 24 182516338 ps
T608 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3995402906 Jul 20 06:27:41 PM PDT 24 Jul 20 06:27:45 PM PDT 24 388620935 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2206216994 Jul 20 06:27:46 PM PDT 24 Jul 20 06:27:47 PM PDT 24 16201752 ps
T610 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.515011157 Jul 20 06:27:53 PM PDT 24 Jul 20 06:27:57 PM PDT 24 37361435 ps
T611 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2696539558 Jul 20 06:27:23 PM PDT 24 Jul 20 06:27:26 PM PDT 24 85626768 ps
T612 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3536211838 Jul 20 06:27:28 PM PDT 24 Jul 20 06:27:31 PM PDT 24 69480618 ps
T613 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2041280551 Jul 20 06:27:42 PM PDT 24 Jul 20 06:27:44 PM PDT 24 51149766 ps
T127 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4005934093 Jul 20 06:27:36 PM PDT 24 Jul 20 06:27:42 PM PDT 24 4277576559 ps
T614 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.93176475 Jul 20 06:27:57 PM PDT 24 Jul 20 06:28:05 PM PDT 24 989594131 ps
T615 /workspace/coverage/cover_reg_top/0.hmac_intr_test.188882213 Jul 20 06:27:26 PM PDT 24 Jul 20 06:27:29 PM PDT 24 54829468 ps
T616 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2007740141 Jul 20 06:27:55 PM PDT 24 Jul 20 06:27:58 PM PDT 24 55470581 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.673603248 Jul 20 06:27:24 PM PDT 24 Jul 20 06:27:27 PM PDT 24 22467422 ps
T618 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4058223392 Jul 20 06:27:57 PM PDT 24 Jul 20 06:28:00 PM PDT 24 65068650 ps
T619 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2568688632 Jul 20 06:27:46 PM PDT 24 Jul 20 06:27:49 PM PDT 24 176150146 ps
T620 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1742472872 Jul 20 06:27:36 PM PDT 24 Jul 20 06:27:40 PM PDT 24 190828688 ps
T621 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2652781037 Jul 20 06:27:52 PM PDT 24 Jul 20 06:27:55 PM PDT 24 28118154 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1260176959 Jul 20 06:27:42 PM PDT 24 Jul 20 06:27:45 PM PDT 24 1257956288 ps
T623 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1530386547 Jul 20 06:27:36 PM PDT 24 Jul 20 06:27:38 PM PDT 24 20895247 ps
T624 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2691885902 Jul 20 06:27:37 PM PDT 24 Jul 20 06:27:39 PM PDT 24 30708913 ps
T625 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4286046847 Jul 20 06:27:38 PM PDT 24 Jul 20 06:27:40 PM PDT 24 87321423 ps
T626 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.134239366 Jul 20 06:27:27 PM PDT 24 Jul 20 06:27:30 PM PDT 24 22047075 ps
T627 /workspace/coverage/cover_reg_top/16.hmac_intr_test.150796145 Jul 20 06:27:48 PM PDT 24 Jul 20 06:27:49 PM PDT 24 30502160 ps
T628 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2851883630 Jul 20 06:27:52 PM PDT 24 Jul 20 06:27:54 PM PDT 24 12322091 ps
T629 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2924261695 Jul 20 06:27:50 PM PDT 24 Jul 20 06:27:53 PM PDT 24 472501803 ps
T630 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1506307267 Jul 20 06:27:52 PM PDT 24 Jul 20 06:27:54 PM PDT 24 51518306 ps
T631 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2582582490 Jul 20 06:27:58 PM PDT 24 Jul 20 06:28:03 PM PDT 24 45268639 ps
T632 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3973452097 Jul 20 06:27:50 PM PDT 24 Jul 20 06:27:51 PM PDT 24 16809190 ps
T633 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3139087719 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:01 PM PDT 24 146592003 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2605014280 Jul 20 06:27:25 PM PDT 24 Jul 20 06:27:41 PM PDT 24 1220591259 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1152423297 Jul 20 06:27:24 PM PDT 24 Jul 20 06:27:36 PM PDT 24 555476472 ps
T636 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.782187974 Jul 20 06:27:46 PM PDT 24 Jul 20 06:27:50 PM PDT 24 83848812 ps
T637 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.538390515 Jul 20 06:27:54 PM PDT 24 Jul 20 06:27:58 PM PDT 24 368559521 ps
T638 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2405698062 Jul 20 06:27:23 PM PDT 24 Jul 20 06:27:28 PM PDT 24 55684707 ps
T639 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.975906431 Jul 20 06:27:59 PM PDT 24 Jul 20 06:28:04 PM PDT 24 87997385 ps
T640 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3824001617 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:54 PM PDT 24 281364604 ps
T641 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.713607072 Jul 20 06:27:55 PM PDT 24 Jul 20 06:28:01 PM PDT 24 1287733020 ps
T642 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1240123735 Jul 20 06:27:45 PM PDT 24 Jul 20 06:27:48 PM PDT 24 409466670 ps
T643 /workspace/coverage/cover_reg_top/3.hmac_intr_test.400013821 Jul 20 06:27:45 PM PDT 24 Jul 20 06:27:46 PM PDT 24 36098472 ps
T644 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2772225025 Jul 20 06:27:23 PM PDT 24 Jul 20 06:27:26 PM PDT 24 141180848 ps
T645 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.163990903 Jul 20 06:27:48 PM PDT 24 Jul 20 06:31:39 PM PDT 24 15028070960 ps
T646 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2436031728 Jul 20 06:27:38 PM PDT 24 Jul 20 06:27:40 PM PDT 24 32987910 ps
T647 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2047525441 Jul 20 06:27:33 PM PDT 24 Jul 20 06:27:36 PM PDT 24 60789191 ps
T648 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.943821264 Jul 20 06:27:43 PM PDT 24 Jul 20 06:27:46 PM PDT 24 331543035 ps
T649 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.880976739 Jul 20 06:27:34 PM PDT 24 Jul 20 06:27:37 PM PDT 24 116388315 ps
T650 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2516077486 Jul 20 06:27:56 PM PDT 24 Jul 20 06:28:03 PM PDT 24 448827489 ps
T651 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2434446078 Jul 20 06:27:40 PM PDT 24 Jul 20 06:27:42 PM PDT 24 31597266 ps
T652 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3405292945 Jul 20 06:27:54 PM PDT 24 Jul 20 06:27:56 PM PDT 24 12475280 ps
T653 /workspace/coverage/cover_reg_top/47.hmac_intr_test.473149582 Jul 20 06:27:54 PM PDT 24 Jul 20 06:27:56 PM PDT 24 57389390 ps
T654 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2924445843 Jul 20 06:27:38 PM PDT 24 Jul 20 06:27:45 PM PDT 24 302930617 ps
T655 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3577636849 Jul 20 06:27:23 PM PDT 24 Jul 20 06:27:26 PM PDT 24 43474204 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2133095477 Jul 20 06:27:32 PM PDT 24 Jul 20 06:27:34 PM PDT 24 58973255 ps
T657 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2545470214 Jul 20 06:27:30 PM PDT 24 Jul 20 06:27:31 PM PDT 24 97629961 ps
T658 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2480937042 Jul 20 06:27:46 PM PDT 24 Jul 20 06:27:48 PM PDT 24 28287008 ps
T659 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.154734806 Jul 20 06:27:51 PM PDT 24 Jul 20 06:27:53 PM PDT 24 43142569 ps

Test location /workspace/coverage/default/5.hmac_stress_all.2172437785
Short name T4
Test name
Test status
Simulation time 261231150905 ps
CPU time 1975.39 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 06:25:00 PM PDT 24
Peak memory 753956 kb
Host smart-4d95d84d-ad43-4563-a0d3-83c61ab0e808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172437785 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2172437785
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1642457387
Short name T23
Test name
Test status
Simulation time 415770201788 ps
CPU time 7908.18 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 08:04:08 PM PDT 24
Peak memory 829744 kb
Host smart-009162bf-8833-479d-8506-a90b2693d175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642457387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1642457387
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3877765017
Short name T25
Test name
Test status
Simulation time 17761550824 ps
CPU time 1755.08 seconds
Started Jul 20 05:52:41 PM PDT 24
Finished Jul 20 06:21:59 PM PDT 24
Peak memory 737916 kb
Host smart-fd033359-0adc-4013-8b95-637b18d8d4c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877765017 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3877765017
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3850232086
Short name T123
Test name
Test status
Simulation time 479975228 ps
CPU time 2.87 seconds
Started Jul 20 06:27:34 PM PDT 24
Finished Jul 20 06:27:38 PM PDT 24
Peak memory 199816 kb
Host smart-f61ddb7d-553b-40ee-8929-1fa693d7e29c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850232086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3850232086
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1006518423
Short name T44
Test name
Test status
Simulation time 458526914 ps
CPU time 1.04 seconds
Started Jul 20 05:51:52 PM PDT 24
Finished Jul 20 05:51:54 PM PDT 24
Peak memory 219744 kb
Host smart-b25f59f2-478e-4e0b-b0ba-88b2352bae21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006518423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1006518423
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.410210311
Short name T9
Test name
Test status
Simulation time 9207117941 ps
CPU time 91.91 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:53:36 PM PDT 24
Peak memory 200368 kb
Host smart-041a054f-e2f2-4d82-be13-db4d3b4c8702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410210311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.410210311
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3158610299
Short name T21
Test name
Test status
Simulation time 4547136602 ps
CPU time 63.98 seconds
Started Jul 20 05:52:21 PM PDT 24
Finished Jul 20 05:53:26 PM PDT 24
Peak memory 216708 kb
Host smart-6bd25232-486a-4277-8d64-d94aec3e2ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158610299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3158610299
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_stress_all.178476630
Short name T60
Test name
Test status
Simulation time 177345286076 ps
CPU time 2540.08 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 06:34:37 PM PDT 24
Peak memory 788504 kb
Host smart-d68f060e-e0e6-448f-9b3a-cba402104e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178476630 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.178476630
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2808063770
Short name T18
Test name
Test status
Simulation time 100316228 ps
CPU time 0.63 seconds
Started Jul 20 05:51:53 PM PDT 24
Finished Jul 20 05:51:54 PM PDT 24
Peak memory 196156 kb
Host smart-675d6d0e-ddcf-48fd-a06c-5f8780697a14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808063770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2808063770
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2330817472
Short name T98
Test name
Test status
Simulation time 19395813 ps
CPU time 0.82 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:27:59 PM PDT 24
Peak memory 199480 kb
Host smart-cd3ffa43-a487-4dce-8f41-5917efadd733
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330817472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2330817472
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3064582062
Short name T121
Test name
Test status
Simulation time 356445458 ps
CPU time 2.81 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:55 PM PDT 24
Peak memory 199728 kb
Host smart-4adc05fe-bfa8-4b55-9e18-9beb6e1b998b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064582062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3064582062
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.643737887
Short name T126
Test name
Test status
Simulation time 315539375 ps
CPU time 3.1 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:27:59 PM PDT 24
Peak memory 199744 kb
Host smart-db5e55f9-5e80-4573-b6be-97287ea7d9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643737887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.643737887
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3883545887
Short name T138
Test name
Test status
Simulation time 925587002 ps
CPU time 52.3 seconds
Started Jul 20 05:52:30 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 200304 kb
Host smart-86b57a87-e7a1-47b5-b45c-15a674bbb8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883545887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3883545887
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1126457405
Short name T250
Test name
Test status
Simulation time 9137952228 ps
CPU time 497.48 seconds
Started Jul 20 05:51:39 PM PDT 24
Finished Jul 20 05:59:57 PM PDT 24
Peak memory 200292 kb
Host smart-dccb4c95-97eb-4f9c-a2e8-1d2bf8287dec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1126457405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1126457405
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2030912626
Short name T12
Test name
Test status
Simulation time 113926805269 ps
CPU time 1383.42 seconds
Started Jul 20 05:51:41 PM PDT 24
Finished Jul 20 06:14:45 PM PDT 24
Peak memory 677756 kb
Host smart-baa2e352-2dbd-408e-b6ac-37a70b986c17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030912626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2030912626
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3590754863
Short name T36
Test name
Test status
Simulation time 15145876537 ps
CPU time 68.96 seconds
Started Jul 20 05:52:12 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 200392 kb
Host smart-649047d9-a398-499f-91cc-2a22aa8b1aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590754863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3590754863
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2924445843
Short name T654
Test name
Test status
Simulation time 302930617 ps
CPU time 5.99 seconds
Started Jul 20 06:27:38 PM PDT 24
Finished Jul 20 06:27:45 PM PDT 24
Peak memory 199712 kb
Host smart-996bed60-c4fc-478d-a120-2ca5c7e38bdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924445843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2924445843
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3212537523
Short name T100
Test name
Test status
Simulation time 217505587 ps
CPU time 9.97 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:38 PM PDT 24
Peak memory 199664 kb
Host smart-8334e302-6efe-4d28-aa79-3ba3fbdeae2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212537523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3212537523
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2545470214
Short name T657
Test name
Test status
Simulation time 97629961 ps
CPU time 0.87 seconds
Started Jul 20 06:27:30 PM PDT 24
Finished Jul 20 06:27:31 PM PDT 24
Peak memory 199316 kb
Host smart-dc6d7579-754c-4822-a92b-a4ce0f78732a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545470214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2545470214
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3536211838
Short name T612
Test name
Test status
Simulation time 69480618 ps
CPU time 2.18 seconds
Started Jul 20 06:27:28 PM PDT 24
Finished Jul 20 06:27:31 PM PDT 24
Peak memory 199724 kb
Host smart-ec7afc40-1895-492d-b892-6019c4b08568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536211838 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3536211838
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2206216994
Short name T609
Test name
Test status
Simulation time 16201752 ps
CPU time 0.73 seconds
Started Jul 20 06:27:46 PM PDT 24
Finished Jul 20 06:27:47 PM PDT 24
Peak memory 197888 kb
Host smart-4533dd76-eb7c-409f-9010-c539a355ed4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206216994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2206216994
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.188882213
Short name T615
Test name
Test status
Simulation time 54829468 ps
CPU time 0.61 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 194704 kb
Host smart-ec3343de-453d-48df-a306-29a3c6a72ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188882213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.188882213
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2133095477
Short name T656
Test name
Test status
Simulation time 58973255 ps
CPU time 1.22 seconds
Started Jul 20 06:27:32 PM PDT 24
Finished Jul 20 06:27:34 PM PDT 24
Peak memory 198272 kb
Host smart-fa5354e0-fa8d-4a2c-aafe-6b30cca2785a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133095477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2133095477
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4008769281
Short name T596
Test name
Test status
Simulation time 257853737 ps
CPU time 1.64 seconds
Started Jul 20 06:27:30 PM PDT 24
Finished Jul 20 06:27:32 PM PDT 24
Peak memory 199728 kb
Host smart-b357184e-7ab2-4cf2-9a18-77ca68ec17c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008769281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.4008769281
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1783163625
Short name T562
Test name
Test status
Simulation time 363319917 ps
CPU time 4.75 seconds
Started Jul 20 06:27:31 PM PDT 24
Finished Jul 20 06:27:36 PM PDT 24
Peak memory 199756 kb
Host smart-ef8250e7-251a-4d2f-91d4-1f3c806b0cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783163625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1783163625
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2055343502
Short name T96
Test name
Test status
Simulation time 57675325 ps
CPU time 3.12 seconds
Started Jul 20 06:27:40 PM PDT 24
Finished Jul 20 06:27:44 PM PDT 24
Peak memory 199720 kb
Host smart-5eada0f4-c57c-4b0a-ba05-699f452f8245
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055343502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2055343502
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3656439507
Short name T527
Test name
Test status
Simulation time 219380155 ps
CPU time 9.53 seconds
Started Jul 20 06:27:43 PM PDT 24
Finished Jul 20 06:27:53 PM PDT 24
Peak memory 198844 kb
Host smart-ef3a9195-38d5-4b26-af32-fb684cf4111c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656439507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3656439507
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.123398519
Short name T602
Test name
Test status
Simulation time 13579772 ps
CPU time 0.72 seconds
Started Jul 20 06:27:27 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 197428 kb
Host smart-ba5f7577-0163-4f43-a754-e3bc5807f1b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123398519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.123398519
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.134239366
Short name T626
Test name
Test status
Simulation time 22047075 ps
CPU time 1.22 seconds
Started Jul 20 06:27:27 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 199708 kb
Host smart-813ae918-4f61-4490-8626-6a7191cfdc73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134239366 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.134239366
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1850475174
Short name T587
Test name
Test status
Simulation time 50549731 ps
CPU time 0.91 seconds
Started Jul 20 06:27:32 PM PDT 24
Finished Jul 20 06:27:34 PM PDT 24
Peak memory 199512 kb
Host smart-a214bdd5-266d-444e-9b29-62e12a380a06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850475174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1850475174
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4046148765
Short name T577
Test name
Test status
Simulation time 13708945 ps
CPU time 0.64 seconds
Started Jul 20 06:27:38 PM PDT 24
Finished Jul 20 06:27:39 PM PDT 24
Peak memory 194708 kb
Host smart-3d8ffdd6-0936-492c-8fce-3e44eee987ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046148765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4046148765
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.339082343
Short name T581
Test name
Test status
Simulation time 90251987 ps
CPU time 1.67 seconds
Started Jul 20 06:27:28 PM PDT 24
Finished Jul 20 06:27:31 PM PDT 24
Peak memory 199764 kb
Host smart-dc92d276-5e33-465a-b68a-4ef661b2941d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339082343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.339082343
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2744838107
Short name T544
Test name
Test status
Simulation time 529847130 ps
CPU time 2.78 seconds
Started Jul 20 06:27:27 PM PDT 24
Finished Jul 20 06:27:32 PM PDT 24
Peak memory 199748 kb
Host smart-f941e07f-cd52-4b46-89c4-78928bd3fdff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744838107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2744838107
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2258519457
Short name T125
Test name
Test status
Simulation time 305613755 ps
CPU time 2.69 seconds
Started Jul 20 06:27:32 PM PDT 24
Finished Jul 20 06:27:35 PM PDT 24
Peak memory 199732 kb
Host smart-3d1f66b6-9974-4c62-a4c8-8f7fde33a871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258519457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2258519457
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.154734806
Short name T659
Test name
Test status
Simulation time 43142569 ps
CPU time 1.27 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:53 PM PDT 24
Peak memory 199620 kb
Host smart-b444f1ee-373f-4169-bf83-8c8021fc9cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154734806 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.154734806
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2853084649
Short name T586
Test name
Test status
Simulation time 16344772 ps
CPU time 0.7 seconds
Started Jul 20 06:27:41 PM PDT 24
Finished Jul 20 06:27:43 PM PDT 24
Peak memory 197892 kb
Host smart-cb99912d-92d2-416a-84f4-ca476371eb64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853084649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2853084649
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.403844491
Short name T584
Test name
Test status
Simulation time 87651016 ps
CPU time 0.63 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 194744 kb
Host smart-22a5d3bd-a856-4563-ba61-900ca2a79c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403844491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.403844491
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2924261695
Short name T629
Test name
Test status
Simulation time 472501803 ps
CPU time 1.71 seconds
Started Jul 20 06:27:50 PM PDT 24
Finished Jul 20 06:27:53 PM PDT 24
Peak memory 199808 kb
Host smart-b43a05a3-26b4-4d3b-9322-d0aa5fb4a164
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924261695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2924261695
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.713607072
Short name T641
Test name
Test status
Simulation time 1287733020 ps
CPU time 3.44 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 199732 kb
Host smart-f7843284-b852-443f-8a07-6a59d90588cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713607072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.713607072
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2599932285
Short name T124
Test name
Test status
Simulation time 92837819 ps
CPU time 2.01 seconds
Started Jul 20 06:27:46 PM PDT 24
Finished Jul 20 06:27:48 PM PDT 24
Peak memory 199728 kb
Host smart-4e90b7cc-fae2-45c8-84a3-6a76d106742a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599932285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2599932285
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1240123735
Short name T642
Test name
Test status
Simulation time 409466670 ps
CPU time 2.64 seconds
Started Jul 20 06:27:45 PM PDT 24
Finished Jul 20 06:27:48 PM PDT 24
Peak memory 199808 kb
Host smart-f3104448-abfa-4313-9d29-b711aa59187b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240123735 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1240123735
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2480937042
Short name T658
Test name
Test status
Simulation time 28287008 ps
CPU time 0.86 seconds
Started Jul 20 06:27:46 PM PDT 24
Finished Jul 20 06:27:48 PM PDT 24
Peak memory 198932 kb
Host smart-e8df4948-3a8e-4416-9f1f-39b3ea9e08e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480937042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2480937042
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2135034455
Short name T550
Test name
Test status
Simulation time 44378013 ps
CPU time 0.61 seconds
Started Jul 20 06:27:50 PM PDT 24
Finished Jul 20 06:27:52 PM PDT 24
Peak memory 194768 kb
Host smart-a9dd1c0f-6467-430a-b7d9-f12afdf8f663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135034455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2135034455
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3091238615
Short name T592
Test name
Test status
Simulation time 193802986 ps
CPU time 1.65 seconds
Started Jul 20 06:27:37 PM PDT 24
Finished Jul 20 06:27:40 PM PDT 24
Peak memory 199716 kb
Host smart-b19c6b94-9b8e-4845-962b-f9e094e07ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091238615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3091238615
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2371236277
Short name T533
Test name
Test status
Simulation time 1210048817 ps
CPU time 2.79 seconds
Started Jul 20 06:27:48 PM PDT 24
Finished Jul 20 06:27:52 PM PDT 24
Peak memory 199712 kb
Host smart-34e72593-5bb1-40ba-872d-abcc36c4161c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371236277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2371236277
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.4011910002
Short name T605
Test name
Test status
Simulation time 267855543 ps
CPU time 4 seconds
Started Jul 20 06:27:53 PM PDT 24
Finished Jul 20 06:27:59 PM PDT 24
Peak memory 199748 kb
Host smart-4c56c081-4d5e-4126-a58b-f6d9bc3550b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011910002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4011910002
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.761528264
Short name T560
Test name
Test status
Simulation time 36349825 ps
CPU time 2.32 seconds
Started Jul 20 06:27:44 PM PDT 24
Finished Jul 20 06:27:46 PM PDT 24
Peak memory 199800 kb
Host smart-8f822ada-50be-4527-b61a-6970b1523fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761528264 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.761528264
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.975906431
Short name T639
Test name
Test status
Simulation time 87997385 ps
CPU time 0.95 seconds
Started Jul 20 06:27:59 PM PDT 24
Finished Jul 20 06:28:04 PM PDT 24
Peak memory 199560 kb
Host smart-32aa80f6-7c82-4c9d-9e50-dbbbd297b2cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975906431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.975906431
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2652781037
Short name T621
Test name
Test status
Simulation time 28118154 ps
CPU time 0.63 seconds
Started Jul 20 06:27:52 PM PDT 24
Finished Jul 20 06:27:55 PM PDT 24
Peak memory 194632 kb
Host smart-223db83b-a982-4503-86e2-c087ee10c905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652781037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2652781037
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.585467802
Short name T110
Test name
Test status
Simulation time 129850621 ps
CPU time 2.32 seconds
Started Jul 20 06:27:44 PM PDT 24
Finished Jul 20 06:27:47 PM PDT 24
Peak memory 199716 kb
Host smart-291d46f5-7494-4602-86ab-ab0c09443475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585467802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.585467802
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2516077486
Short name T650
Test name
Test status
Simulation time 448827489 ps
CPU time 3.81 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:03 PM PDT 24
Peak memory 199768 kb
Host smart-7f456507-3f9c-47a4-b58e-01b4bcc69845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516077486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2516077486
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.782187974
Short name T636
Test name
Test status
Simulation time 83848812 ps
CPU time 2.9 seconds
Started Jul 20 06:27:46 PM PDT 24
Finished Jul 20 06:27:50 PM PDT 24
Peak memory 199708 kb
Host smart-54e85c2d-73c5-4950-8b18-d56ec6d0a88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782187974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.782187974
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3824001617
Short name T640
Test name
Test status
Simulation time 281364604 ps
CPU time 1.32 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 199552 kb
Host smart-33276bf0-e605-479a-b959-b58d659eade6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824001617 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3824001617
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1055910409
Short name T585
Test name
Test status
Simulation time 15676578 ps
CPU time 0.72 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 197676 kb
Host smart-df34474f-1f71-4c3e-99f1-3d8dec416089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055910409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1055910409
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.356888379
Short name T590
Test name
Test status
Simulation time 55801843 ps
CPU time 0.62 seconds
Started Jul 20 06:27:50 PM PDT 24
Finished Jul 20 06:27:52 PM PDT 24
Peak memory 194728 kb
Host smart-5e7217eb-3ac0-47ec-8489-c7104a683901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356888379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.356888379
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3139087719
Short name T633
Test name
Test status
Simulation time 146592003 ps
CPU time 1.72 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 199748 kb
Host smart-b6120d22-c573-4988-b76a-e007fc2da591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139087719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3139087719
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.373237335
Short name T570
Test name
Test status
Simulation time 646324918 ps
CPU time 3.44 seconds
Started Jul 20 06:27:52 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 199736 kb
Host smart-65f36436-2c4e-4cc1-8cfc-7efca85bcd69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373237335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.373237335
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3587271728
Short name T59
Test name
Test status
Simulation time 3807326466 ps
CPU time 4.09 seconds
Started Jul 20 06:27:49 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 199788 kb
Host smart-b7c2d91f-b57b-47d1-b0c2-b38b780995bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587271728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3587271728
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.163990903
Short name T645
Test name
Test status
Simulation time 15028070960 ps
CPU time 229.59 seconds
Started Jul 20 06:27:48 PM PDT 24
Finished Jul 20 06:31:39 PM PDT 24
Peak memory 215284 kb
Host smart-89693ab9-4aca-4653-87ab-ba4d99606239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163990903 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.163990903
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3946267679
Short name T541
Test name
Test status
Simulation time 16000727 ps
CPU time 0.65 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 194568 kb
Host smart-f984f724-f666-4a56-9d33-7fd3e63078cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946267679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3946267679
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2867006307
Short name T109
Test name
Test status
Simulation time 149915015 ps
CPU time 2.34 seconds
Started Jul 20 06:27:47 PM PDT 24
Finished Jul 20 06:27:50 PM PDT 24
Peak memory 199572 kb
Host smart-f44c37ee-ba49-4d18-815c-19fbf4a95903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867006307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2867006307
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1667732702
Short name T591
Test name
Test status
Simulation time 359695944 ps
CPU time 1.85 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 199744 kb
Host smart-caca82a1-fef9-416d-94ff-0e8093a15246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667732702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1667732702
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2568688632
Short name T619
Test name
Test status
Simulation time 176150146 ps
CPU time 2.44 seconds
Started Jul 20 06:27:46 PM PDT 24
Finished Jul 20 06:27:49 PM PDT 24
Peak memory 199812 kb
Host smart-7e925080-eb84-4849-b028-8202f10edace
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568688632 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2568688632
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.4137077810
Short name T104
Test name
Test status
Simulation time 41870390 ps
CPU time 0.97 seconds
Started Jul 20 06:27:46 PM PDT 24
Finished Jul 20 06:27:48 PM PDT 24
Peak memory 199588 kb
Host smart-9b25277b-e1aa-4604-b149-2454cca54da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137077810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.4137077810
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3668295257
Short name T588
Test name
Test status
Simulation time 12717336 ps
CPU time 0.59 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:52 PM PDT 24
Peak memory 194596 kb
Host smart-1b3b2a79-5f27-4058-bbfd-aea463e78bfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668295257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3668295257
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1952670094
Short name T568
Test name
Test status
Simulation time 109655196 ps
CPU time 1.89 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 199724 kb
Host smart-96cdbb86-7162-42a6-aaeb-1ba4f5389392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952670094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1952670094
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.866695794
Short name T552
Test name
Test status
Simulation time 249220339 ps
CPU time 3.32 seconds
Started Jul 20 06:27:42 PM PDT 24
Finished Jul 20 06:27:46 PM PDT 24
Peak memory 199704 kb
Host smart-4428ca13-fdec-4f2d-9f25-9770fc71218e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866695794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.866695794
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1232285696
Short name T58
Test name
Test status
Simulation time 672730973 ps
CPU time 1.71 seconds
Started Jul 20 06:27:53 PM PDT 24
Finished Jul 20 06:27:56 PM PDT 24
Peak memory 199736 kb
Host smart-322af9ad-c246-4ac6-a244-796f6c7de332
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232285696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1232285696
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.538390515
Short name T637
Test name
Test status
Simulation time 368559521 ps
CPU time 2.3 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:27:58 PM PDT 24
Peak memory 199720 kb
Host smart-bf9b3f86-c822-4d04-9447-1a69c709f9a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538390515 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.538390515
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1725058375
Short name T101
Test name
Test status
Simulation time 33812142 ps
CPU time 0.94 seconds
Started Jul 20 06:27:44 PM PDT 24
Finished Jul 20 06:27:45 PM PDT 24
Peak memory 199448 kb
Host smart-5f91b8af-0391-4437-abb5-ae0a1c939179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725058375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1725058375
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.150796145
Short name T627
Test name
Test status
Simulation time 30502160 ps
CPU time 0.62 seconds
Started Jul 20 06:27:48 PM PDT 24
Finished Jul 20 06:27:49 PM PDT 24
Peak memory 194616 kb
Host smart-195c3be8-1568-4013-a3b5-6b33dc778b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150796145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.150796145
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.515011157
Short name T610
Test name
Test status
Simulation time 37361435 ps
CPU time 1.73 seconds
Started Jul 20 06:27:53 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 199736 kb
Host smart-754f1b9a-1922-4fd2-aa10-905b0dff5f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515011157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.515011157
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.93176475
Short name T614
Test name
Test status
Simulation time 989594131 ps
CPU time 4.36 seconds
Started Jul 20 06:27:57 PM PDT 24
Finished Jul 20 06:28:05 PM PDT 24
Peak memory 199732 kb
Host smart-9c619ec0-5fa4-498e-b7d1-019cfb7102d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93176475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.93176475
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3995402906
Short name T608
Test name
Test status
Simulation time 388620935 ps
CPU time 3.15 seconds
Started Jul 20 06:27:41 PM PDT 24
Finished Jul 20 06:27:45 PM PDT 24
Peak memory 199784 kb
Host smart-e6a1e9dd-76ea-4e82-a3ab-cd631be6b070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995402906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3995402906
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3860452240
Short name T600
Test name
Test status
Simulation time 148273270 ps
CPU time 2.43 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 207988 kb
Host smart-c172e8f6-74e8-4feb-8eb0-9bd7c12def0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860452240 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3860452240
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.464697503
Short name T97
Test name
Test status
Simulation time 37497651 ps
CPU time 0.94 seconds
Started Jul 20 06:27:57 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 199500 kb
Host smart-d9666e8a-c9ab-49fb-8c3a-ff96225555f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464697503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.464697503
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2851883630
Short name T628
Test name
Test status
Simulation time 12322091 ps
CPU time 0.58 seconds
Started Jul 20 06:27:52 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 194580 kb
Host smart-8d158029-0d02-4354-84b4-4cc43b11c540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851883630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2851883630
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.557228798
Short name T107
Test name
Test status
Simulation time 550545481 ps
CPU time 1.63 seconds
Started Jul 20 06:27:45 PM PDT 24
Finished Jul 20 06:27:47 PM PDT 24
Peak memory 199720 kb
Host smart-a57e7978-5e2a-4ed2-932e-ad293384ddc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557228798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.557228798
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2834867451
Short name T536
Test name
Test status
Simulation time 59567321 ps
CPU time 3.02 seconds
Started Jul 20 06:27:48 PM PDT 24
Finished Jul 20 06:27:52 PM PDT 24
Peak memory 199764 kb
Host smart-eee2f2b6-189d-4cc7-8059-fbc896a6ab3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834867451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2834867451
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3861538969
Short name T118
Test name
Test status
Simulation time 164932105 ps
CPU time 1.78 seconds
Started Jul 20 06:27:44 PM PDT 24
Finished Jul 20 06:27:46 PM PDT 24
Peak memory 199796 kb
Host smart-bdbf46ff-7b6c-40d0-b0ed-ed884681ea8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861538969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3861538969
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.488847740
Short name T593
Test name
Test status
Simulation time 74376966 ps
CPU time 1.77 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:27:59 PM PDT 24
Peak memory 199724 kb
Host smart-41c18c3d-498f-49a3-abe2-202483d4c459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488847740 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.488847740
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2041280551
Short name T613
Test name
Test status
Simulation time 51149766 ps
CPU time 0.82 seconds
Started Jul 20 06:27:42 PM PDT 24
Finished Jul 20 06:27:44 PM PDT 24
Peak memory 199548 kb
Host smart-7cb99671-b74c-48df-ac39-c866054c887a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041280551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2041280551
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.230621702
Short name T579
Test name
Test status
Simulation time 15685711 ps
CPU time 0.63 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 194596 kb
Host smart-1adfa423-236c-4ffe-b917-dee9ca3e6dd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230621702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.230621702
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.408676880
Short name T597
Test name
Test status
Simulation time 20623574 ps
CPU time 1.1 seconds
Started Jul 20 06:27:58 PM PDT 24
Finished Jul 20 06:28:03 PM PDT 24
Peak memory 198488 kb
Host smart-dbec75c0-a5e9-4f23-9b26-d96d5dc1a635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408676880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.408676880
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.152630006
Short name T576
Test name
Test status
Simulation time 55039254 ps
CPU time 1.44 seconds
Started Jul 20 06:27:52 PM PDT 24
Finished Jul 20 06:27:55 PM PDT 24
Peak memory 199808 kb
Host smart-e2264adb-c5d3-4b1f-a97e-911d09935491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152630006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.152630006
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1171573750
Short name T555
Test name
Test status
Simulation time 68615739030 ps
CPU time 670.8 seconds
Started Jul 20 06:27:44 PM PDT 24
Finished Jul 20 06:38:56 PM PDT 24
Peak memory 224428 kb
Host smart-3e03bd11-6f31-4b8e-9eef-3d329b7e4a1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171573750 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1171573750
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.4023099753
Short name T105
Test name
Test status
Simulation time 158598841 ps
CPU time 1 seconds
Started Jul 20 06:27:59 PM PDT 24
Finished Jul 20 06:28:05 PM PDT 24
Peak memory 199588 kb
Host smart-231ae137-f15f-420e-9ca9-518daf280b11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023099753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.4023099753
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.4248528877
Short name T539
Test name
Test status
Simulation time 15482813 ps
CPU time 0.61 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 194644 kb
Host smart-1c55da07-8494-4200-8d29-6e5bd8918c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248528877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4248528877
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1344959906
Short name T112
Test name
Test status
Simulation time 188512746 ps
CPU time 1.21 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 198080 kb
Host smart-b13863a0-153b-4c15-8b3e-a950bf0b08fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344959906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1344959906
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1119974253
Short name T565
Test name
Test status
Simulation time 180910714 ps
CPU time 3.59 seconds
Started Jul 20 06:27:59 PM PDT 24
Finished Jul 20 06:28:07 PM PDT 24
Peak memory 199756 kb
Host smart-dec45419-fc59-49dd-bd9e-5f33b1cac311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119974253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1119974253
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2057283628
Short name T604
Test name
Test status
Simulation time 452936102 ps
CPU time 4.04 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 199712 kb
Host smart-3f18cec6-7e58-4fb3-8c04-ad98dcef844a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057283628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2057283628
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1152423297
Short name T635
Test name
Test status
Simulation time 555476472 ps
CPU time 8.71 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:36 PM PDT 24
Peak memory 199472 kb
Host smart-c3551cf1-9aaf-48b2-89ab-3c6233f32ba9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152423297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1152423297
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2605014280
Short name T634
Test name
Test status
Simulation time 1220591259 ps
CPU time 13.73 seconds
Started Jul 20 06:27:25 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 199732 kb
Host smart-29f10934-6244-48b2-a15e-9250d90f07ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605014280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2605014280
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3577636849
Short name T655
Test name
Test status
Simulation time 43474204 ps
CPU time 0.98 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:26 PM PDT 24
Peak memory 199540 kb
Host smart-f872e79c-2551-4355-896c-38831229a9de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577636849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3577636849
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2910644492
Short name T556
Test name
Test status
Simulation time 129378474 ps
CPU time 1.22 seconds
Started Jul 20 06:27:27 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 199628 kb
Host smart-166e62d7-487d-43c3-b55c-f5a9312fe7d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910644492 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2910644492
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.673603248
Short name T617
Test name
Test status
Simulation time 22467422 ps
CPU time 0.84 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:27 PM PDT 24
Peak memory 199508 kb
Host smart-5d847fa3-e8c1-4a7e-ad4a-31b1b46c2b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673603248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.673603248
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1560797564
Short name T575
Test name
Test status
Simulation time 56288634 ps
CPU time 0.62 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:27 PM PDT 24
Peak memory 194664 kb
Host smart-a100ff4c-f39c-40a7-8bb6-7b843fe8b360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560797564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1560797564
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.880976739
Short name T649
Test name
Test status
Simulation time 116388315 ps
CPU time 1.88 seconds
Started Jul 20 06:27:34 PM PDT 24
Finished Jul 20 06:27:37 PM PDT 24
Peak memory 199752 kb
Host smart-c10ddab4-5772-4979-acda-5e123ee194ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880976739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.880976739
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2162955390
Short name T545
Test name
Test status
Simulation time 153363641 ps
CPU time 3.22 seconds
Started Jul 20 06:27:37 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 199828 kb
Host smart-93d2a3fd-2d3d-4ac1-9a24-69b4e45afe5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162955390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2162955390
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1506307267
Short name T630
Test name
Test status
Simulation time 51518306 ps
CPU time 0.61 seconds
Started Jul 20 06:27:52 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 194856 kb
Host smart-d8fb2927-d32b-4e59-8de9-ac62385acd90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506307267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1506307267
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.457471327
Short name T559
Test name
Test status
Simulation time 42025467 ps
CPU time 0.61 seconds
Started Jul 20 06:27:53 PM PDT 24
Finished Jul 20 06:27:55 PM PDT 24
Peak memory 194604 kb
Host smart-3b0d179d-8c0b-4422-bfb0-d968e2d0a674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457471327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.457471327
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3701128268
Short name T567
Test name
Test status
Simulation time 22013538 ps
CPU time 0.58 seconds
Started Jul 20 06:27:53 PM PDT 24
Finished Jul 20 06:27:55 PM PDT 24
Peak memory 194580 kb
Host smart-6d908c3e-f505-45c5-91da-5be2b0d4133b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701128268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3701128268
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2099733521
Short name T582
Test name
Test status
Simulation time 31309252 ps
CPU time 0.63 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 194776 kb
Host smart-73e8313c-bbf2-46e1-92ad-f79206e3b657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099733521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2099733521
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.692475948
Short name T571
Test name
Test status
Simulation time 57336418 ps
CPU time 0.62 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:27:58 PM PDT 24
Peak memory 194604 kb
Host smart-34e9e828-0de3-4d6e-9601-4f93b5b15dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692475948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.692475948
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2753231078
Short name T532
Test name
Test status
Simulation time 13928712 ps
CPU time 0.61 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:27:59 PM PDT 24
Peak memory 194708 kb
Host smart-43fbcc61-789c-48c0-9472-ede931b2903d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753231078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2753231078
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3533467683
Short name T548
Test name
Test status
Simulation time 72775157 ps
CPU time 0.63 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 194772 kb
Host smart-aaa416be-9cab-4c64-92ef-97c49e577f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533467683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3533467683
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3275251739
Short name T561
Test name
Test status
Simulation time 47466194 ps
CPU time 0.6 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 194588 kb
Host smart-1e17b819-bfab-462a-b9b0-bb2d94f2f4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275251739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3275251739
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4251457968
Short name T599
Test name
Test status
Simulation time 14778605 ps
CPU time 0.61 seconds
Started Jul 20 06:28:02 PM PDT 24
Finished Jul 20 06:28:07 PM PDT 24
Peak memory 194760 kb
Host smart-efe6e74a-379b-472b-a2be-cfda9969667c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251457968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4251457968
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3587635895
Short name T538
Test name
Test status
Simulation time 15891935 ps
CPU time 0.62 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 194624 kb
Host smart-b4dbb5d6-1f1e-4df1-8541-9741a65b5798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587635895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3587635895
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.788102301
Short name T103
Test name
Test status
Simulation time 339738517 ps
CPU time 5.89 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:32 PM PDT 24
Peak memory 199696 kb
Host smart-5398265c-0793-4fbd-b2f7-1786c6dbad00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788102301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.788102301
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.212495270
Short name T569
Test name
Test status
Simulation time 759639233 ps
CPU time 5.93 seconds
Started Jul 20 06:27:37 PM PDT 24
Finished Jul 20 06:27:44 PM PDT 24
Peak memory 198308 kb
Host smart-7debafc3-9c72-495f-96df-d2f8e1af3b7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212495270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.212495270
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3664156849
Short name T607
Test name
Test status
Simulation time 182516338 ps
CPU time 1.02 seconds
Started Jul 20 06:27:31 PM PDT 24
Finished Jul 20 06:27:32 PM PDT 24
Peak memory 199512 kb
Host smart-b48c8977-c83e-4e95-bd93-9792d5857e20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664156849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3664156849
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2696539558
Short name T611
Test name
Test status
Simulation time 85626768 ps
CPU time 1.23 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:26 PM PDT 24
Peak memory 199572 kb
Host smart-82dcf0f1-dfab-499a-a8af-597956ac9054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696539558 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2696539558
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2772225025
Short name T644
Test name
Test status
Simulation time 141180848 ps
CPU time 0.92 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:26 PM PDT 24
Peak memory 199488 kb
Host smart-5ce04d03-0644-46b5-a1f7-062dbef1aa92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772225025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2772225025
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.400013821
Short name T643
Test name
Test status
Simulation time 36098472 ps
CPU time 0.61 seconds
Started Jul 20 06:27:45 PM PDT 24
Finished Jul 20 06:27:46 PM PDT 24
Peak memory 194836 kb
Host smart-098d1ac0-6eea-49b8-a201-8f80e06bcdd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400013821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.400013821
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4286046847
Short name T625
Test name
Test status
Simulation time 87321423 ps
CPU time 1.2 seconds
Started Jul 20 06:27:38 PM PDT 24
Finished Jul 20 06:27:40 PM PDT 24
Peak memory 198200 kb
Host smart-df890c36-25cd-48ef-9334-97183f4dfe52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286046847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4286046847
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4034740994
Short name T594
Test name
Test status
Simulation time 161474714 ps
CPU time 3.63 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:31 PM PDT 24
Peak memory 199744 kb
Host smart-ca6ae9e2-ecc7-4cdc-a8c0-b41049d91165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034740994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4034740994
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.101516238
Short name T57
Test name
Test status
Simulation time 1250874076 ps
CPU time 1.85 seconds
Started Jul 20 06:27:37 PM PDT 24
Finished Jul 20 06:27:40 PM PDT 24
Peak memory 199708 kb
Host smart-f068e352-1625-4df5-aa91-749d3fe489a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101516238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.101516238
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2055410691
Short name T564
Test name
Test status
Simulation time 71714279 ps
CPU time 0.63 seconds
Started Jul 20 06:27:50 PM PDT 24
Finished Jul 20 06:27:52 PM PDT 24
Peak memory 194680 kb
Host smart-471691c8-dc8d-43b2-91c4-21df92e3b38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055410691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2055410691
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2342370559
Short name T574
Test name
Test status
Simulation time 26085325 ps
CPU time 0.58 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:27:58 PM PDT 24
Peak memory 194584 kb
Host smart-13c4866b-3e0c-4ee7-875b-4905d6fca221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342370559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2342370559
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3319735614
Short name T583
Test name
Test status
Simulation time 55900074 ps
CPU time 0.66 seconds
Started Jul 20 06:27:49 PM PDT 24
Finished Jul 20 06:27:51 PM PDT 24
Peak memory 194620 kb
Host smart-940a3772-7395-4733-ad79-0580fd87df47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319735614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3319735614
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2355265117
Short name T558
Test name
Test status
Simulation time 13779797 ps
CPU time 0.59 seconds
Started Jul 20 06:28:01 PM PDT 24
Finished Jul 20 06:28:07 PM PDT 24
Peak memory 194596 kb
Host smart-f5dec485-63e8-4793-b577-18e8c80cd8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355265117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2355265117
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.769173410
Short name T543
Test name
Test status
Simulation time 37471778 ps
CPU time 0.59 seconds
Started Jul 20 06:28:01 PM PDT 24
Finished Jul 20 06:28:06 PM PDT 24
Peak memory 194588 kb
Host smart-a5adb327-41e4-44a1-acfd-0a3f0cb8706d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769173410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.769173410
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3973452097
Short name T632
Test name
Test status
Simulation time 16809190 ps
CPU time 0.61 seconds
Started Jul 20 06:27:50 PM PDT 24
Finished Jul 20 06:27:51 PM PDT 24
Peak memory 194708 kb
Host smart-51a885ca-5522-413c-8d65-6433cd5f7607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973452097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3973452097
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.974691515
Short name T551
Test name
Test status
Simulation time 22952215 ps
CPU time 0.55 seconds
Started Jul 20 06:27:57 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 194596 kb
Host smart-a6d7384b-7bfe-4b1f-b4a4-2078e107bb55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974691515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.974691515
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1092145653
Short name T529
Test name
Test status
Simulation time 16589872 ps
CPU time 0.63 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:27:59 PM PDT 24
Peak memory 194780 kb
Host smart-9be2f871-1da3-4a8c-91cf-792df0d4adc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092145653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1092145653
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2952502569
Short name T531
Test name
Test status
Simulation time 17565381 ps
CPU time 0.65 seconds
Started Jul 20 06:27:57 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 194628 kb
Host smart-941c8d7b-5476-4d23-8c3d-a85c632922a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952502569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2952502569
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3267263183
Short name T534
Test name
Test status
Simulation time 12725581 ps
CPU time 0.56 seconds
Started Jul 20 06:28:00 PM PDT 24
Finished Jul 20 06:28:05 PM PDT 24
Peak memory 194716 kb
Host smart-8886a655-c988-4f5f-9a5a-c27f3c429c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267263183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3267263183
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3576062222
Short name T557
Test name
Test status
Simulation time 1762318771 ps
CPU time 8.4 seconds
Started Jul 20 06:27:32 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 199224 kb
Host smart-e682a5da-7796-4c72-a62f-f47f21098cb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576062222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3576062222
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1368530242
Short name T95
Test name
Test status
Simulation time 4192668150 ps
CPU time 11.36 seconds
Started Jul 20 06:27:52 PM PDT 24
Finished Jul 20 06:28:05 PM PDT 24
Peak memory 199848 kb
Host smart-9d0863ff-fe14-4115-8f30-536b9751f652
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368530242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1368530242
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3390626546
Short name T102
Test name
Test status
Simulation time 42838502 ps
CPU time 0.73 seconds
Started Jul 20 06:27:33 PM PDT 24
Finished Jul 20 06:27:34 PM PDT 24
Peak memory 197388 kb
Host smart-c2edb0d1-e784-4b09-b4d9-35da653348e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390626546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3390626546
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.331028175
Short name T535
Test name
Test status
Simulation time 221465224 ps
CPU time 1.74 seconds
Started Jul 20 06:27:39 PM PDT 24
Finished Jul 20 06:27:42 PM PDT 24
Peak memory 199804 kb
Host smart-f7b33286-07dd-41f3-916a-eaf079f0c7d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331028175 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.331028175
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3826864893
Short name T99
Test name
Test status
Simulation time 67920522 ps
CPU time 0.72 seconds
Started Jul 20 06:27:42 PM PDT 24
Finished Jul 20 06:27:44 PM PDT 24
Peak memory 197488 kb
Host smart-74e3ccd8-c51e-456e-9815-c94f47990497
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826864893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3826864893
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2691885902
Short name T624
Test name
Test status
Simulation time 30708913 ps
CPU time 0.62 seconds
Started Jul 20 06:27:37 PM PDT 24
Finished Jul 20 06:27:39 PM PDT 24
Peak memory 194828 kb
Host smart-ac06a3e7-f1cc-4d47-9410-47e2d538aaa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691885902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2691885902
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3270883192
Short name T108
Test name
Test status
Simulation time 68798891 ps
CPU time 1 seconds
Started Jul 20 06:27:35 PM PDT 24
Finished Jul 20 06:27:36 PM PDT 24
Peak memory 199744 kb
Host smart-7cf7c071-02d3-4960-b1e0-39c63e311a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270883192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3270883192
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2405698062
Short name T638
Test name
Test status
Simulation time 55684707 ps
CPU time 2.65 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:28 PM PDT 24
Peak memory 199792 kb
Host smart-f40398ef-fe71-43b3-9d41-6010b63dd6b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405698062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2405698062
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.539540300
Short name T122
Test name
Test status
Simulation time 191035082 ps
CPU time 3.38 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 199720 kb
Host smart-c7714bca-8fa2-4227-9b54-2538dd7f7aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539540300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.539540300
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1891462833
Short name T528
Test name
Test status
Simulation time 55447318 ps
CPU time 0.61 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 194588 kb
Host smart-a801c0f4-708a-495f-8054-d2b3513cfdaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891462833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1891462833
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3016908247
Short name T546
Test name
Test status
Simulation time 15611088 ps
CPU time 0.61 seconds
Started Jul 20 06:27:51 PM PDT 24
Finished Jul 20 06:27:53 PM PDT 24
Peak memory 194644 kb
Host smart-7fd0bcce-11c7-47dc-b82a-eab24dbae978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016908247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3016908247
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1060927117
Short name T537
Test name
Test status
Simulation time 12793200 ps
CPU time 0.6 seconds
Started Jul 20 06:27:52 PM PDT 24
Finished Jul 20 06:27:54 PM PDT 24
Peak memory 194604 kb
Host smart-3963821a-77c9-4875-bb37-a2457d149df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060927117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1060927117
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2582582490
Short name T631
Test name
Test status
Simulation time 45268639 ps
CPU time 0.66 seconds
Started Jul 20 06:27:58 PM PDT 24
Finished Jul 20 06:28:03 PM PDT 24
Peak memory 194668 kb
Host smart-7dc319c9-4ab7-4a1c-ae14-d59923d05d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582582490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2582582490
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3558080598
Short name T563
Test name
Test status
Simulation time 11318734 ps
CPU time 0.61 seconds
Started Jul 20 06:27:57 PM PDT 24
Finished Jul 20 06:28:02 PM PDT 24
Peak memory 194624 kb
Host smart-581eae8d-9f1c-4187-bb44-0cbfdeaaa925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558080598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3558080598
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3542584435
Short name T540
Test name
Test status
Simulation time 25919083 ps
CPU time 0.59 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:27:57 PM PDT 24
Peak memory 194700 kb
Host smart-89539cc3-9b19-45d3-892f-e6a2ca7338f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542584435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3542584435
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3405292945
Short name T652
Test name
Test status
Simulation time 12475280 ps
CPU time 0.59 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:27:56 PM PDT 24
Peak memory 194588 kb
Host smart-a93fd9dd-2a7f-4f57-90bc-0803cc9a9402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405292945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3405292945
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.473149582
Short name T653
Test name
Test status
Simulation time 57389390 ps
CPU time 0.6 seconds
Started Jul 20 06:27:54 PM PDT 24
Finished Jul 20 06:27:56 PM PDT 24
Peak memory 194576 kb
Host smart-5d669684-8a55-47bc-8f7c-c791deb533b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473149582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.473149582
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1039313431
Short name T595
Test name
Test status
Simulation time 48028997 ps
CPU time 0.62 seconds
Started Jul 20 06:27:56 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 194652 kb
Host smart-2ca446e0-2862-49a4-9938-31b715c839f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039313431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1039313431
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4058223392
Short name T618
Test name
Test status
Simulation time 65068650 ps
CPU time 0.57 seconds
Started Jul 20 06:27:57 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 194728 kb
Host smart-12020f6a-28ba-4b42-85b2-2dcce22082c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058223392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4058223392
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1530386547
Short name T623
Test name
Test status
Simulation time 20895247 ps
CPU time 1.26 seconds
Started Jul 20 06:27:36 PM PDT 24
Finished Jul 20 06:27:38 PM PDT 24
Peak memory 199700 kb
Host smart-1202000a-3441-46b2-bdd1-7c087d159182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530386547 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1530386547
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1765972257
Short name T111
Test name
Test status
Simulation time 20597981 ps
CPU time 1.02 seconds
Started Jul 20 06:27:40 PM PDT 24
Finished Jul 20 06:27:42 PM PDT 24
Peak memory 199408 kb
Host smart-0d01a2fd-2405-45b1-bfb2-90e669a16984
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765972257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1765972257
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.478959676
Short name T606
Test name
Test status
Simulation time 12817969 ps
CPU time 0.62 seconds
Started Jul 20 06:27:36 PM PDT 24
Finished Jul 20 06:27:37 PM PDT 24
Peak memory 194520 kb
Host smart-981a451a-d4ec-4330-9bcb-5dfb8eb41549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478959676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.478959676
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1260176959
Short name T622
Test name
Test status
Simulation time 1257956288 ps
CPU time 2.26 seconds
Started Jul 20 06:27:42 PM PDT 24
Finished Jul 20 06:27:45 PM PDT 24
Peak memory 199736 kb
Host smart-dce286e5-7818-4a75-bf41-facf3ffd0a1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260176959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1260176959
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.281413225
Short name T566
Test name
Test status
Simulation time 297747288 ps
CPU time 3.16 seconds
Started Jul 20 06:27:42 PM PDT 24
Finished Jul 20 06:27:46 PM PDT 24
Peak memory 199736 kb
Host smart-8f24b50a-9183-4371-9668-7a9e567bf506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281413225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.281413225
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3453333640
Short name T589
Test name
Test status
Simulation time 603121377 ps
CPU time 3.2 seconds
Started Jul 20 06:27:38 PM PDT 24
Finished Jul 20 06:27:42 PM PDT 24
Peak memory 199692 kb
Host smart-1846d3fd-edfa-42d7-86a6-1cf809a2e5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453333640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3453333640
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3227649910
Short name T554
Test name
Test status
Simulation time 72518324 ps
CPU time 1.74 seconds
Started Jul 20 06:27:40 PM PDT 24
Finished Jul 20 06:27:43 PM PDT 24
Peak memory 199780 kb
Host smart-3a87c30e-6b5b-4153-9973-647b07492598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227649910 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3227649910
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.350836329
Short name T94
Test name
Test status
Simulation time 76221352 ps
CPU time 0.73 seconds
Started Jul 20 06:27:37 PM PDT 24
Finished Jul 20 06:27:39 PM PDT 24
Peak memory 197360 kb
Host smart-8d174113-fabf-41ee-b892-c4c0c19079ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350836329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.350836329
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1783961975
Short name T580
Test name
Test status
Simulation time 29842706 ps
CPU time 0.61 seconds
Started Jul 20 06:27:32 PM PDT 24
Finished Jul 20 06:27:33 PM PDT 24
Peak memory 194616 kb
Host smart-54c54908-45e7-4301-9be6-a286544920a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783961975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1783961975
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.943821264
Short name T648
Test name
Test status
Simulation time 331543035 ps
CPU time 2.28 seconds
Started Jul 20 06:27:43 PM PDT 24
Finished Jul 20 06:27:46 PM PDT 24
Peak memory 199716 kb
Host smart-8dac6f60-f250-44ed-be07-2b0fc0750cab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943821264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.943821264
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.999819879
Short name T542
Test name
Test status
Simulation time 165877974 ps
CPU time 3.63 seconds
Started Jul 20 06:27:35 PM PDT 24
Finished Jul 20 06:27:40 PM PDT 24
Peak memory 199724 kb
Host smart-db4e7ce2-f8d9-42d2-b213-887e1d7cc730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999819879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.999819879
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1785672819
Short name T120
Test name
Test status
Simulation time 198737527 ps
CPU time 3.83 seconds
Started Jul 20 06:27:40 PM PDT 24
Finished Jul 20 06:27:45 PM PDT 24
Peak memory 199728 kb
Host smart-b36bd35e-de91-4525-8169-1f3f9aab9628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785672819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1785672819
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1526401030
Short name T578
Test name
Test status
Simulation time 63803889 ps
CPU time 1.8 seconds
Started Jul 20 06:27:33 PM PDT 24
Finished Jul 20 06:27:35 PM PDT 24
Peak memory 199764 kb
Host smart-9b13c15e-865d-468d-8559-edfb2ca3d755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526401030 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1526401030
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.304870767
Short name T601
Test name
Test status
Simulation time 30904568 ps
CPU time 0.85 seconds
Started Jul 20 06:27:34 PM PDT 24
Finished Jul 20 06:27:35 PM PDT 24
Peak memory 199044 kb
Host smart-aeb44e22-7de1-40bf-99ef-3c0bf7384f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304870767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.304870767
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1621420065
Short name T549
Test name
Test status
Simulation time 12402696 ps
CPU time 0.6 seconds
Started Jul 20 06:27:32 PM PDT 24
Finished Jul 20 06:27:33 PM PDT 24
Peak memory 194636 kb
Host smart-27276068-84fe-4917-8d98-212701eed68d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621420065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1621420065
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2149771489
Short name T598
Test name
Test status
Simulation time 116650680 ps
CPU time 1.93 seconds
Started Jul 20 06:27:34 PM PDT 24
Finished Jul 20 06:27:37 PM PDT 24
Peak memory 199716 kb
Host smart-bbb50630-5c69-405a-9003-7999bfbc3018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149771489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2149771489
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2434446078
Short name T651
Test name
Test status
Simulation time 31597266 ps
CPU time 1.63 seconds
Started Jul 20 06:27:40 PM PDT 24
Finished Jul 20 06:27:42 PM PDT 24
Peak memory 199740 kb
Host smart-41b5197b-a1a1-4bff-9914-43c9174decfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434446078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2434446078
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3870184296
Short name T119
Test name
Test status
Simulation time 668378902 ps
CPU time 2.98 seconds
Started Jul 20 06:27:31 PM PDT 24
Finished Jul 20 06:27:35 PM PDT 24
Peak memory 199732 kb
Host smart-58f9a94a-bbf5-4e63-84ef-2006a90fa0bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870184296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3870184296
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2047525441
Short name T647
Test name
Test status
Simulation time 60789191 ps
CPU time 1.83 seconds
Started Jul 20 06:27:33 PM PDT 24
Finished Jul 20 06:27:36 PM PDT 24
Peak memory 199772 kb
Host smart-ba6afdc0-e834-4995-b04a-1cec39af4c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047525441 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2047525441
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2436031728
Short name T646
Test name
Test status
Simulation time 32987910 ps
CPU time 0.72 seconds
Started Jul 20 06:27:38 PM PDT 24
Finished Jul 20 06:27:40 PM PDT 24
Peak memory 198040 kb
Host smart-73dc2d4f-7373-416b-9bc3-c699d7dde8be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436031728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2436031728
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2007740141
Short name T616
Test name
Test status
Simulation time 55470581 ps
CPU time 0.66 seconds
Started Jul 20 06:27:55 PM PDT 24
Finished Jul 20 06:27:58 PM PDT 24
Peak memory 194636 kb
Host smart-bfec2f9b-39ac-43b5-8ed6-9c237f743d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007740141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2007740141
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.419196477
Short name T106
Test name
Test status
Simulation time 374558553 ps
CPU time 1.69 seconds
Started Jul 20 06:27:33 PM PDT 24
Finished Jul 20 06:27:36 PM PDT 24
Peak memory 199720 kb
Host smart-61619b32-5e78-4a1d-94ed-17b9d9d10ee4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419196477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.419196477
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2221908346
Short name T530
Test name
Test status
Simulation time 286698559 ps
CPU time 1.6 seconds
Started Jul 20 06:27:42 PM PDT 24
Finished Jul 20 06:27:44 PM PDT 24
Peak memory 199776 kb
Host smart-d2596aed-60ed-4118-b868-56ff031716c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221908346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2221908346
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.874965321
Short name T553
Test name
Test status
Simulation time 51707281 ps
CPU time 1.74 seconds
Started Jul 20 06:27:35 PM PDT 24
Finished Jul 20 06:27:38 PM PDT 24
Peak memory 199784 kb
Host smart-423633f3-1087-4c46-a9ea-80e83ab39f27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874965321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.874965321
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3218709964
Short name T547
Test name
Test status
Simulation time 152312059 ps
CPU time 1.86 seconds
Started Jul 20 06:27:38 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 199752 kb
Host smart-1e6a9676-a154-4aab-b9ff-fe84eea05bf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218709964 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3218709964
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2514946295
Short name T573
Test name
Test status
Simulation time 232236001 ps
CPU time 0.83 seconds
Started Jul 20 06:27:35 PM PDT 24
Finished Jul 20 06:27:37 PM PDT 24
Peak memory 199564 kb
Host smart-df273a1e-4bf7-4d50-8b53-6e0c7a97acf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514946295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2514946295
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.616289957
Short name T572
Test name
Test status
Simulation time 71805275 ps
CPU time 0.6 seconds
Started Jul 20 06:27:39 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 194692 kb
Host smart-c3f55a6d-b75b-49e7-9c08-726c122a2172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616289957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.616289957
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2966636476
Short name T603
Test name
Test status
Simulation time 102823351 ps
CPU time 1.57 seconds
Started Jul 20 06:27:49 PM PDT 24
Finished Jul 20 06:27:51 PM PDT 24
Peak memory 199520 kb
Host smart-6933f92e-0acb-45c0-9668-40eec1eb8ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966636476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2966636476
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1742472872
Short name T620
Test name
Test status
Simulation time 190828688 ps
CPU time 3.7 seconds
Started Jul 20 06:27:36 PM PDT 24
Finished Jul 20 06:27:40 PM PDT 24
Peak memory 199568 kb
Host smart-b1b3040e-39bc-472e-b4c9-50200c5a4ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742472872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1742472872
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4005934093
Short name T127
Test name
Test status
Simulation time 4277576559 ps
CPU time 4.47 seconds
Started Jul 20 06:27:36 PM PDT 24
Finished Jul 20 06:27:42 PM PDT 24
Peak memory 199780 kb
Host smart-8f8fa3b9-3d2b-4e10-87f0-747a8f39e4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005934093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4005934093
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1553235694
Short name T244
Test name
Test status
Simulation time 19963860408 ps
CPU time 61.78 seconds
Started Jul 20 05:51:44 PM PDT 24
Finished Jul 20 05:52:47 PM PDT 24
Peak memory 200212 kb
Host smart-42916c61-1d8f-48bc-a415-3e1f59b854f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1553235694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1553235694
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3149317583
Short name T341
Test name
Test status
Simulation time 1245316341 ps
CPU time 5.66 seconds
Started Jul 20 05:51:31 PM PDT 24
Finished Jul 20 05:51:38 PM PDT 24
Peak memory 200252 kb
Host smart-c957913d-6c40-4b6c-b0f8-534045c62b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149317583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3149317583
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.905301428
Short name T295
Test name
Test status
Simulation time 6894670341 ps
CPU time 1110.78 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 06:10:18 PM PDT 24
Peak memory 725212 kb
Host smart-5813153f-d293-4ee8-a49a-c97d82ac7e66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905301428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.905301428
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1781288651
Short name T400
Test name
Test status
Simulation time 18996821174 ps
CPU time 133.91 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 200300 kb
Host smart-9ad339d3-2e15-4c7c-96b1-035329950035
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781288651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1781288651
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1343034048
Short name T429
Test name
Test status
Simulation time 415026123 ps
CPU time 8.49 seconds
Started Jul 20 05:51:36 PM PDT 24
Finished Jul 20 05:51:45 PM PDT 24
Peak memory 200268 kb
Host smart-4a6e7604-7a16-4b35-af9d-ea502e57bc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343034048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1343034048
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2643937320
Short name T47
Test name
Test status
Simulation time 973719190 ps
CPU time 1.17 seconds
Started Jul 20 05:51:38 PM PDT 24
Finished Jul 20 05:51:40 PM PDT 24
Peak memory 219616 kb
Host smart-b7e40a60-f899-4232-9a37-4fde3eab5bcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643937320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2643937320
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3151413357
Short name T352
Test name
Test status
Simulation time 2401447607 ps
CPU time 3.76 seconds
Started Jul 20 05:51:40 PM PDT 24
Finished Jul 20 05:51:50 PM PDT 24
Peak memory 200284 kb
Host smart-b9132058-60b2-4179-a461-1e8aecc9d035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151413357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3151413357
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2657430137
Short name T468
Test name
Test status
Simulation time 306358561224 ps
CPU time 2349.24 seconds
Started Jul 20 05:51:51 PM PDT 24
Finished Jul 20 06:31:01 PM PDT 24
Peak memory 783188 kb
Host smart-cb971d48-2825-498b-8cf6-9bfe64601e87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657430137 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2657430137
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1650206379
Short name T62
Test name
Test status
Simulation time 359685263586 ps
CPU time 4811.64 seconds
Started Jul 20 05:51:40 PM PDT 24
Finished Jul 20 07:11:53 PM PDT 24
Peak memory 833368 kb
Host smart-f5879bdc-19c8-43cb-baa0-afeeb64a1f0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650206379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1650206379
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2666638996
Short name T412
Test name
Test status
Simulation time 5382195475 ps
CPU time 42.77 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 05:52:33 PM PDT 24
Peak memory 200344 kb
Host smart-7f2205ce-5bbd-4989-a8be-8ee1974a0fa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2666638996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2666638996
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1769063974
Short name T358
Test name
Test status
Simulation time 34090924280 ps
CPU time 59.88 seconds
Started Jul 20 05:51:37 PM PDT 24
Finished Jul 20 05:52:37 PM PDT 24
Peak memory 200352 kb
Host smart-62855138-57df-4e40-9493-107a10bbb50d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1769063974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1769063974
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1067563323
Short name T254
Test name
Test status
Simulation time 17266111834 ps
CPU time 75.03 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 05:53:06 PM PDT 24
Peak memory 200276 kb
Host smart-e74842eb-471f-4bdd-9262-d2138b85b502
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1067563323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1067563323
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3049279692
Short name T336
Test name
Test status
Simulation time 620449573029 ps
CPU time 2338.54 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 06:31:04 PM PDT 24
Peak memory 215956 kb
Host smart-6cc41a1d-ec37-413e-a7d3-041afa950831
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3049279692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3049279692
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.4003622428
Short name T253
Test name
Test status
Simulation time 885357842028 ps
CPU time 2613.78 seconds
Started Jul 20 05:51:44 PM PDT 24
Finished Jul 20 06:35:18 PM PDT 24
Peak memory 215680 kb
Host smart-2c43c8b5-1293-4739-9436-528865308a7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4003622428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.4003622428
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.253718280
Short name T390
Test name
Test status
Simulation time 1458267260 ps
CPU time 25.79 seconds
Started Jul 20 05:51:44 PM PDT 24
Finished Jul 20 05:52:11 PM PDT 24
Peak memory 200300 kb
Host smart-3451a97a-234e-40f9-806e-bd88eef0dcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253718280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.253718280
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.544925804
Short name T490
Test name
Test status
Simulation time 22008991 ps
CPU time 0.57 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 05:52:00 PM PDT 24
Peak memory 195772 kb
Host smart-4627179e-0a6e-48b7-a238-6ca57bc0fd32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544925804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.544925804
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3385985583
Short name T282
Test name
Test status
Simulation time 2506049256 ps
CPU time 34.28 seconds
Started Jul 20 05:51:43 PM PDT 24
Finished Jul 20 05:52:18 PM PDT 24
Peak memory 200328 kb
Host smart-43eeeb53-8381-4df2-888b-2410dfba0075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385985583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3385985583
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2002393135
Short name T150
Test name
Test status
Simulation time 5268216044 ps
CPU time 68.91 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:53:11 PM PDT 24
Peak memory 200360 kb
Host smart-44b8bb7f-c6cd-4099-aa01-e771cd025cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002393135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2002393135
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3351349742
Short name T367
Test name
Test status
Simulation time 9286237869 ps
CPU time 888.68 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 06:06:35 PM PDT 24
Peak memory 764236 kb
Host smart-249c7778-69a1-4075-a9fd-7a07038e9ea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351349742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3351349742
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.371905672
Short name T407
Test name
Test status
Simulation time 2080874444 ps
CPU time 28.03 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 05:52:27 PM PDT 24
Peak memory 200204 kb
Host smart-1f4eec0b-f162-41c6-aed1-51d48fcb314e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371905672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.371905672
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2756220288
Short name T348
Test name
Test status
Simulation time 4042648443 ps
CPU time 16.9 seconds
Started Jul 20 05:51:49 PM PDT 24
Finished Jul 20 05:52:07 PM PDT 24
Peak memory 200292 kb
Host smart-e7ed6ef9-7c6c-4976-949b-77a26f7f82e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756220288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2756220288
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3557754838
Short name T489
Test name
Test status
Simulation time 64665382 ps
CPU time 1.01 seconds
Started Jul 20 05:51:40 PM PDT 24
Finished Jul 20 05:51:42 PM PDT 24
Peak memory 199420 kb
Host smart-d5ddc44e-e46b-4c5b-811a-17f86532e5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557754838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3557754838
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1679070285
Short name T434
Test name
Test status
Simulation time 74257217199 ps
CPU time 1555.21 seconds
Started Jul 20 05:51:33 PM PDT 24
Finished Jul 20 06:17:30 PM PDT 24
Peak memory 764548 kb
Host smart-723afa1f-05bf-4fb4-9261-93ca8bf6dd7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679070285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1679070285
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2071984060
Short name T288
Test name
Test status
Simulation time 5675134619 ps
CPU time 69.79 seconds
Started Jul 20 05:51:43 PM PDT 24
Finished Jul 20 05:52:53 PM PDT 24
Peak memory 200316 kb
Host smart-e11eb90e-552f-4b65-918b-bf6c9dcd6b18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2071984060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2071984060
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2700235543
Short name T90
Test name
Test status
Simulation time 6689726168 ps
CPU time 54.15 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:52:42 PM PDT 24
Peak memory 200364 kb
Host smart-0579fe72-740d-473c-9dac-fe8d843ceaf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2700235543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2700235543
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2237807822
Short name T146
Test name
Test status
Simulation time 7627064026 ps
CPU time 130.87 seconds
Started Jul 20 05:51:52 PM PDT 24
Finished Jul 20 05:54:04 PM PDT 24
Peak memory 200296 kb
Host smart-fc5b73a9-3fc7-430b-84a3-f81a3a8f4086
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2237807822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2237807822
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2173454501
Short name T374
Test name
Test status
Simulation time 18752887259 ps
CPU time 543.37 seconds
Started Jul 20 05:51:31 PM PDT 24
Finished Jul 20 06:00:36 PM PDT 24
Peak memory 200360 kb
Host smart-e456185a-bc41-463d-a67d-c95712c427bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2173454501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2173454501
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3257681179
Short name T411
Test name
Test status
Simulation time 39083778626 ps
CPU time 2115.32 seconds
Started Jul 20 05:51:42 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 216476 kb
Host smart-a01d1390-66ba-4f79-8358-1a86a2fc0a38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3257681179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3257681179
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.959872244
Short name T266
Test name
Test status
Simulation time 1698992709070 ps
CPU time 2306.29 seconds
Started Jul 20 05:51:56 PM PDT 24
Finished Jul 20 06:30:23 PM PDT 24
Peak memory 215844 kb
Host smart-ea9f26fc-556b-4557-b72c-fa3593e348d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=959872244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.959872244
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2968647503
Short name T344
Test name
Test status
Simulation time 2223942272 ps
CPU time 26.75 seconds
Started Jul 20 05:51:55 PM PDT 24
Finished Jul 20 05:52:23 PM PDT 24
Peak memory 200244 kb
Host smart-12d5a627-9d83-4396-8132-e91c1c5078b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968647503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2968647503
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.731507967
Short name T41
Test name
Test status
Simulation time 49720817 ps
CPU time 0.58 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:52:05 PM PDT 24
Peak memory 196200 kb
Host smart-e4875040-369a-4f0d-a652-204177ddcb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731507967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.731507967
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3573422852
Short name T347
Test name
Test status
Simulation time 4072671290 ps
CPU time 103.46 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 215708 kb
Host smart-9a227321-9158-4ba4-a6e9-bafa384d5047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573422852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3573422852
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3194774386
Short name T445
Test name
Test status
Simulation time 1520983888 ps
CPU time 13.21 seconds
Started Jul 20 05:52:04 PM PDT 24
Finished Jul 20 05:52:19 PM PDT 24
Peak memory 200300 kb
Host smart-d9745eb2-0853-4ad5-bf84-1a24cbb94824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194774386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3194774386
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2992510978
Short name T148
Test name
Test status
Simulation time 44506306749 ps
CPU time 802.88 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 06:05:42 PM PDT 24
Peak memory 687108 kb
Host smart-ac8b03cb-8322-4cb2-8694-031505a8aed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992510978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2992510978
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.387666634
Short name T149
Test name
Test status
Simulation time 2663717177 ps
CPU time 76.74 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:53:33 PM PDT 24
Peak memory 200300 kb
Host smart-0a18b39b-9b71-45e8-a2bb-ed34c8690bfc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387666634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.387666634
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2896275038
Short name T144
Test name
Test status
Simulation time 2556324748 ps
CPU time 22.37 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:52:28 PM PDT 24
Peak memory 200188 kb
Host smart-f60a51db-a302-4a0a-b46e-d4f324f1a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896275038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2896275038
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.969205889
Short name T159
Test name
Test status
Simulation time 2955153929 ps
CPU time 13.09 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:52:28 PM PDT 24
Peak memory 200308 kb
Host smart-22f56838-3396-4616-8e96-84d3e6fe930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969205889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.969205889
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.523909354
Short name T43
Test name
Test status
Simulation time 43487983967 ps
CPU time 1809.45 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 06:22:09 PM PDT 24
Peak memory 791480 kb
Host smart-97e9e7db-6b11-42e7-a2b4-768bc20b0959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523909354 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.523909354
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.368791160
Short name T35
Test name
Test status
Simulation time 275158488 ps
CPU time 16.42 seconds
Started Jul 20 05:52:20 PM PDT 24
Finished Jul 20 05:52:37 PM PDT 24
Peak memory 200264 kb
Host smart-27ffd28e-cfc8-4d76-b955-b2417702db1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368791160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.368791160
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2647529744
Short name T42
Test name
Test status
Simulation time 20138087 ps
CPU time 0.56 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:52:03 PM PDT 24
Peak memory 195164 kb
Host smart-b9058875-1e6c-4a09-85c9-b5fe3873aee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647529744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2647529744
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1779558570
Short name T432
Test name
Test status
Simulation time 262329038 ps
CPU time 14.37 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:52:30 PM PDT 24
Peak memory 200292 kb
Host smart-9de605d7-5633-49f9-a0a0-3eea8fd4bf1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779558570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1779558570
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3954802319
Short name T228
Test name
Test status
Simulation time 377422693 ps
CPU time 33.73 seconds
Started Jul 20 05:52:06 PM PDT 24
Finished Jul 20 05:52:41 PM PDT 24
Peak memory 245288 kb
Host smart-314008f4-88e3-46d3-9c38-f2c6fa99f5f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954802319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3954802319
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2624698826
Short name T220
Test name
Test status
Simulation time 3233957962 ps
CPU time 88.94 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:53:53 PM PDT 24
Peak memory 200292 kb
Host smart-a288fec9-37d4-4069-bee3-4ab4f1f34d3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624698826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2624698826
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1799887182
Short name T343
Test name
Test status
Simulation time 9160686820 ps
CPU time 123.56 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 200356 kb
Host smart-b66d4332-71ef-4c84-9aa7-7b2a0f1c24cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799887182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1799887182
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.4265444098
Short name T132
Test name
Test status
Simulation time 1005715128 ps
CPU time 11.89 seconds
Started Jul 20 05:52:04 PM PDT 24
Finished Jul 20 05:52:18 PM PDT 24
Peak memory 200248 kb
Host smart-cad8c6bc-863d-4b7e-b4d1-72814b7d91b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265444098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.4265444098
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4130167529
Short name T435
Test name
Test status
Simulation time 177561470519 ps
CPU time 1628.57 seconds
Started Jul 20 05:52:19 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 758192 kb
Host smart-0b64f55c-4e94-4ce2-914a-d914f0e3c36b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130167529 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4130167529
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2808156482
Short name T318
Test name
Test status
Simulation time 3580300657 ps
CPU time 42.24 seconds
Started Jul 20 05:52:12 PM PDT 24
Finished Jul 20 05:52:55 PM PDT 24
Peak memory 200328 kb
Host smart-0bbce35d-aa7d-4ac6-932e-2a3d88de919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808156482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2808156482
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3118883592
Short name T163
Test name
Test status
Simulation time 20557545 ps
CPU time 0.58 seconds
Started Jul 20 05:52:07 PM PDT 24
Finished Jul 20 05:52:09 PM PDT 24
Peak memory 195180 kb
Host smart-940eee2a-e407-4dcf-96aa-66e409edecd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118883592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3118883592
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.388753749
Short name T243
Test name
Test status
Simulation time 1864504256 ps
CPU time 76.16 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 05:53:28 PM PDT 24
Peak memory 200196 kb
Host smart-25abd9ca-3d6f-4aee-b3ad-0f5d82da1fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388753749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.388753749
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2597981576
Short name T365
Test name
Test status
Simulation time 16387756162 ps
CPU time 68.63 seconds
Started Jul 20 05:52:07 PM PDT 24
Finished Jul 20 05:53:17 PM PDT 24
Peak memory 200332 kb
Host smart-48b676d4-dd7e-413e-8b70-5478ccc73673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597981576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2597981576
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1989782940
Short name T404
Test name
Test status
Simulation time 16933321359 ps
CPU time 1276.85 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 06:13:34 PM PDT 24
Peak memory 782708 kb
Host smart-62e71f71-d382-4b9c-8b4a-4b744cf597ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989782940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1989782940
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.670899776
Short name T29
Test name
Test status
Simulation time 83073220483 ps
CPU time 72.15 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:53:17 PM PDT 24
Peak memory 200484 kb
Host smart-c353645f-126a-4cc9-8cdc-241f633ca181
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670899776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.670899776
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3685937217
Short name T262
Test name
Test status
Simulation time 7282794152 ps
CPU time 26.24 seconds
Started Jul 20 05:52:10 PM PDT 24
Finished Jul 20 05:52:37 PM PDT 24
Peak memory 200368 kb
Host smart-1d6480be-f16f-4807-b92d-bd928e542b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685937217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3685937217
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1392101123
Short name T217
Test name
Test status
Simulation time 1829482986 ps
CPU time 5.92 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 05:52:06 PM PDT 24
Peak memory 200296 kb
Host smart-43bc3006-0281-4755-8ced-32b0f090c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392101123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1392101123
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2632679367
Short name T477
Test name
Test status
Simulation time 1896577700 ps
CPU time 102.38 seconds
Started Jul 20 05:52:09 PM PDT 24
Finished Jul 20 05:53:51 PM PDT 24
Peak memory 200140 kb
Host smart-3f02a832-6a00-477a-a349-7b6b2f393625
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632679367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2632679367
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2676005116
Short name T84
Test name
Test status
Simulation time 3607705510 ps
CPU time 113.53 seconds
Started Jul 20 05:52:08 PM PDT 24
Finished Jul 20 05:54:02 PM PDT 24
Peak memory 200300 kb
Host smart-e0f0eac3-e0b5-4451-b295-1dd516205aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676005116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2676005116
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1025056656
Short name T73
Test name
Test status
Simulation time 21061720 ps
CPU time 0.63 seconds
Started Jul 20 05:52:10 PM PDT 24
Finished Jul 20 05:52:11 PM PDT 24
Peak memory 196176 kb
Host smart-4201de1a-99e4-4060-b09d-2e2a67fdddf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025056656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1025056656
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2785108721
Short name T207
Test name
Test status
Simulation time 9760834172 ps
CPU time 66.73 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:53:25 PM PDT 24
Peak memory 200308 kb
Host smart-0c2415f6-640a-419d-949f-ecef2cd28854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785108721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2785108721
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1918227273
Short name T135
Test name
Test status
Simulation time 4398200752 ps
CPU time 65.47 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:53:34 PM PDT 24
Peak memory 200492 kb
Host smart-c2a91567-e2e8-4ed4-92f5-17bede69d113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918227273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1918227273
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1083194569
Short name T498
Test name
Test status
Simulation time 14849047015 ps
CPU time 1351.07 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 06:14:35 PM PDT 24
Peak memory 773012 kb
Host smart-9b3549df-bc6b-4163-986e-86c7d3615e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083194569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1083194569
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3006703368
Short name T363
Test name
Test status
Simulation time 1497889664 ps
CPU time 25.16 seconds
Started Jul 20 05:52:10 PM PDT 24
Finished Jul 20 05:52:35 PM PDT 24
Peak memory 200168 kb
Host smart-5be5e573-0c32-4906-9d5e-d9be238a2ac8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006703368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3006703368
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.469506967
Short name T478
Test name
Test status
Simulation time 1645923324 ps
CPU time 88.11 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:53:33 PM PDT 24
Peak memory 200292 kb
Host smart-51781ae7-2382-4a4a-85b3-6d39394d44ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469506967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.469506967
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1905825751
Short name T509
Test name
Test status
Simulation time 226085941 ps
CPU time 2.48 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:52:18 PM PDT 24
Peak memory 200248 kb
Host smart-c1cfb7e1-a09e-4bea-a225-b04a1b917f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905825751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1905825751
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2164054093
Short name T505
Test name
Test status
Simulation time 31417126691 ps
CPU time 393.23 seconds
Started Jul 20 05:52:09 PM PDT 24
Finished Jul 20 05:58:43 PM PDT 24
Peak memory 200336 kb
Host smart-1f83f861-484d-44e8-808b-01873b00ff35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164054093 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2164054093
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2146018532
Short name T437
Test name
Test status
Simulation time 2715560091 ps
CPU time 6.72 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 05:52:07 PM PDT 24
Peak memory 200360 kb
Host smart-a43743b7-ac6d-48dd-958b-71eb7f629a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146018532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2146018532
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1185200476
Short name T238
Test name
Test status
Simulation time 20187804 ps
CPU time 0.59 seconds
Started Jul 20 05:52:04 PM PDT 24
Finished Jul 20 05:52:07 PM PDT 24
Peak memory 195932 kb
Host smart-867320f2-de37-4295-a1c3-a86173df16b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185200476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1185200476
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1292352576
Short name T157
Test name
Test status
Simulation time 340397933 ps
CPU time 17.46 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:52:22 PM PDT 24
Peak memory 200424 kb
Host smart-830d820d-d464-4790-b0a0-227fe63f52cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292352576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1292352576
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3566415188
Short name T441
Test name
Test status
Simulation time 3084495797 ps
CPU time 52.53 seconds
Started Jul 20 05:52:05 PM PDT 24
Finished Jul 20 05:52:59 PM PDT 24
Peak memory 200328 kb
Host smart-7801a0ba-21c5-4b8c-85bc-ce4daddbcf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566415188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3566415188
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3553614649
Short name T500
Test name
Test status
Simulation time 2454915794 ps
CPU time 497.24 seconds
Started Jul 20 05:52:09 PM PDT 24
Finished Jul 20 06:00:27 PM PDT 24
Peak memory 675996 kb
Host smart-78551be1-c942-4156-b596-1712680002c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3553614649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3553614649
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1723820687
Short name T313
Test name
Test status
Simulation time 5613385159 ps
CPU time 154.77 seconds
Started Jul 20 05:52:13 PM PDT 24
Finished Jul 20 05:54:48 PM PDT 24
Peak memory 200344 kb
Host smart-63e8a480-703f-41d1-8657-5d6ba746934c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723820687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1723820687
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.122057124
Short name T30
Test name
Test status
Simulation time 37505476168 ps
CPU time 125.83 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 200500 kb
Host smart-aed70f0a-89df-4160-99f0-4b56375237b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122057124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.122057124
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2216920592
Short name T357
Test name
Test status
Simulation time 417028052 ps
CPU time 10.09 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:52:27 PM PDT 24
Peak memory 200300 kb
Host smart-f55b1ebc-4d56-4964-9cf0-e17f522f96e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216920592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2216920592
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.817626004
Short name T68
Test name
Test status
Simulation time 430523512347 ps
CPU time 1835.59 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 06:22:35 PM PDT 24
Peak memory 676040 kb
Host smart-1c6fb7fd-ad31-4127-bf9c-5fb2509b9513
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817626004 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.817626004
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.746350730
Short name T331
Test name
Test status
Simulation time 5244212665 ps
CPU time 93.39 seconds
Started Jul 20 05:52:04 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 200336 kb
Host smart-91150eb7-86b2-4195-99ea-2532f6709d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746350730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.746350730
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1931022969
Short name T507
Test name
Test status
Simulation time 14642976 ps
CPU time 0.6 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:52:17 PM PDT 24
Peak memory 196868 kb
Host smart-610bdb0b-478d-46ad-9acb-41e0cfe2c34e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931022969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1931022969
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2880538681
Short name T188
Test name
Test status
Simulation time 528075350 ps
CPU time 32.09 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 05:52:32 PM PDT 24
Peak memory 200224 kb
Host smart-cdeae770-0022-4616-a24e-ce880f82ee9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880538681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2880538681
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1682649530
Short name T466
Test name
Test status
Simulation time 602194254 ps
CPU time 8.92 seconds
Started Jul 20 05:52:12 PM PDT 24
Finished Jul 20 05:52:22 PM PDT 24
Peak memory 200296 kb
Host smart-c43042b2-4f4f-486c-b27b-8ef1ea4ff5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682649530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1682649530
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2326084400
Short name T219
Test name
Test status
Simulation time 13810209670 ps
CPU time 488.38 seconds
Started Jul 20 05:52:21 PM PDT 24
Finished Jul 20 06:00:30 PM PDT 24
Peak memory 469620 kb
Host smart-dab9bdff-6b26-4ad0-92fc-116d73e0467f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326084400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2326084400
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2361248786
Short name T436
Test name
Test status
Simulation time 1254283770 ps
CPU time 65.9 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:53:11 PM PDT 24
Peak memory 200280 kb
Host smart-3fe316d0-7813-4e44-8984-c459117d36d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361248786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2361248786
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2916817186
Short name T153
Test name
Test status
Simulation time 3319964866 ps
CPU time 77.13 seconds
Started Jul 20 05:52:04 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 200384 kb
Host smart-9cb36079-866b-455a-8fea-f0fb9bad0a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916817186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2916817186
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3299607855
Short name T375
Test name
Test status
Simulation time 435196699 ps
CPU time 9.49 seconds
Started Jul 20 05:52:07 PM PDT 24
Finished Jul 20 05:52:17 PM PDT 24
Peak memory 200252 kb
Host smart-3ff60147-6a23-4f30-9bb8-404f474ee5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299607855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3299607855
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3792291688
Short name T322
Test name
Test status
Simulation time 181705132726 ps
CPU time 1092.81 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 06:10:13 PM PDT 24
Peak memory 707344 kb
Host smart-3036974e-3a88-45a8-9b2d-618ec960635c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792291688 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3792291688
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.814185974
Short name T181
Test name
Test status
Simulation time 22699775269 ps
CPU time 103.61 seconds
Started Jul 20 05:52:04 PM PDT 24
Finished Jul 20 05:53:50 PM PDT 24
Peak memory 200196 kb
Host smart-ce526fb5-be57-4c4f-aa92-c7dfb3264fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814185974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.814185974
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.81474282
Short name T176
Test name
Test status
Simulation time 19550936 ps
CPU time 0.61 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:52:19 PM PDT 24
Peak memory 195116 kb
Host smart-43ca3cc0-434f-434e-b801-c015e193defc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81474282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.81474282
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2627901379
Short name T451
Test name
Test status
Simulation time 16106604521 ps
CPU time 83.96 seconds
Started Jul 20 05:52:12 PM PDT 24
Finished Jul 20 05:53:37 PM PDT 24
Peak memory 200268 kb
Host smart-44c5594c-0c88-4a1a-b984-1b5124e94f50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627901379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2627901379
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.486459815
Short name T276
Test name
Test status
Simulation time 3808017914 ps
CPU time 69.53 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 05:53:21 PM PDT 24
Peak memory 200328 kb
Host smart-de7b4b42-2438-4930-8266-3abfc5119a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486459815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.486459815
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4224884052
Short name T189
Test name
Test status
Simulation time 4810370051 ps
CPU time 583.78 seconds
Started Jul 20 05:52:06 PM PDT 24
Finished Jul 20 06:01:52 PM PDT 24
Peak memory 686184 kb
Host smart-b1c5ccd1-bf8b-4485-a598-dbbbbe50f3c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224884052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4224884052
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1636768197
Short name T372
Test name
Test status
Simulation time 13470165465 ps
CPU time 74.81 seconds
Started Jul 20 05:52:10 PM PDT 24
Finished Jul 20 05:53:25 PM PDT 24
Peak memory 200440 kb
Host smart-21cc4b39-1eb7-4e89-9efc-d5ef16214ad8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636768197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1636768197
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4113880470
Short name T449
Test name
Test status
Simulation time 1902825946 ps
CPU time 108.41 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:53:53 PM PDT 24
Peak memory 200272 kb
Host smart-3a51a2e4-fc8d-458b-bef3-0d333b4521ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113880470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4113880470
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2335807508
Short name T53
Test name
Test status
Simulation time 655411433 ps
CPU time 5.63 seconds
Started Jul 20 05:52:13 PM PDT 24
Finished Jul 20 05:52:20 PM PDT 24
Peak memory 200284 kb
Host smart-b49192c7-4fca-40b1-a3c5-ec9a74837758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335807508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2335807508
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.731446272
Short name T69
Test name
Test status
Simulation time 254607851495 ps
CPU time 1472.25 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 06:16:44 PM PDT 24
Peak memory 694968 kb
Host smart-474ea4c2-c507-422b-947c-5c39d75e07b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731446272 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.731446272
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1983040268
Short name T165
Test name
Test status
Simulation time 4248525455 ps
CPU time 36.72 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:52:41 PM PDT 24
Peak memory 200280 kb
Host smart-4d36b877-4daf-47b1-936d-9ddea94ed9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983040268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1983040268
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1133769883
Short name T395
Test name
Test status
Simulation time 23918098 ps
CPU time 0.61 seconds
Started Jul 20 05:52:08 PM PDT 24
Finished Jul 20 05:52:09 PM PDT 24
Peak memory 196192 kb
Host smart-7367b075-fdad-4dec-b106-71481abc5cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133769883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1133769883
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3814190619
Short name T294
Test name
Test status
Simulation time 1013258949 ps
CPU time 58.45 seconds
Started Jul 20 05:52:05 PM PDT 24
Finished Jul 20 05:53:05 PM PDT 24
Peak memory 200312 kb
Host smart-3af0b184-77b9-4fea-bfcd-77ac87a582a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814190619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3814190619
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2562118752
Short name T139
Test name
Test status
Simulation time 1931716348 ps
CPU time 19.71 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:52:22 PM PDT 24
Peak memory 200360 kb
Host smart-860ab0a9-100b-40a5-8333-ba82c6c50e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562118752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2562118752
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2772555897
Short name T269
Test name
Test status
Simulation time 21789964741 ps
CPU time 417.85 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:59:12 PM PDT 24
Peak memory 614824 kb
Host smart-8086f1e6-c3fc-4e44-bd85-f70e23d7cf57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772555897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2772555897
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3793768775
Short name T471
Test name
Test status
Simulation time 11286912720 ps
CPU time 34.36 seconds
Started Jul 20 05:52:07 PM PDT 24
Finished Jul 20 05:52:42 PM PDT 24
Peak memory 200304 kb
Host smart-55ed5dc9-350d-4cb2-972d-47f82de7d531
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793768775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3793768775
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1169163198
Short name T306
Test name
Test status
Simulation time 6852828570 ps
CPU time 91.79 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 200316 kb
Host smart-f6bf03f4-910d-4f6f-adaf-a16687993b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169163198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1169163198
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2134874417
Short name T405
Test name
Test status
Simulation time 162473716 ps
CPU time 8.19 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:52:11 PM PDT 24
Peak memory 200300 kb
Host smart-90b6a57a-3696-4f77-a69e-d0118c3ea80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134874417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2134874417
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.741538338
Short name T65
Test name
Test status
Simulation time 89017020122 ps
CPU time 1510.35 seconds
Started Jul 20 05:52:09 PM PDT 24
Finished Jul 20 06:17:21 PM PDT 24
Peak memory 690844 kb
Host smart-316d588b-6ae8-4acb-a837-880171709b82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741538338 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.741538338
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4097996834
Short name T115
Test name
Test status
Simulation time 4150149812 ps
CPU time 67.23 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:53:11 PM PDT 24
Peak memory 200488 kb
Host smart-0cfe7de3-ba75-4dd9-92dc-100313d8bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097996834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4097996834
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3019714241
Short name T345
Test name
Test status
Simulation time 42020348 ps
CPU time 0.59 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:52:24 PM PDT 24
Peak memory 195856 kb
Host smart-bf9c6e91-ff2c-45aa-b754-7abd204255ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019714241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3019714241
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.57402346
Short name T370
Test name
Test status
Simulation time 479726533 ps
CPU time 13.36 seconds
Started Jul 20 05:52:21 PM PDT 24
Finished Jul 20 05:52:36 PM PDT 24
Peak memory 200256 kb
Host smart-33990348-8efd-4815-9277-91813ef6f5f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57402346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.57402346
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.144555096
Short name T383
Test name
Test status
Simulation time 433459493 ps
CPU time 22.27 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:52:37 PM PDT 24
Peak memory 200004 kb
Host smart-71fcd9b7-8c31-4788-a8ae-985b196328ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144555096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.144555096
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.83917638
Short name T185
Test name
Test status
Simulation time 18667784442 ps
CPU time 796.32 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 06:05:40 PM PDT 24
Peak memory 680656 kb
Host smart-243e07cb-257f-4ed0-b0cf-d1d3a1dc4ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83917638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.83917638
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.249723298
Short name T394
Test name
Test status
Simulation time 22167330449 ps
CPU time 116.58 seconds
Started Jul 20 05:52:30 PM PDT 24
Finished Jul 20 05:54:27 PM PDT 24
Peak memory 200436 kb
Host smart-314684be-3541-49bc-931a-1075c2980759
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249723298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.249723298
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2307954768
Short name T76
Test name
Test status
Simulation time 2207002677 ps
CPU time 123.75 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:54:33 PM PDT 24
Peak memory 200324 kb
Host smart-a46a2791-91fd-4e6b-b300-3e829358918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307954768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2307954768
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2829507920
Short name T161
Test name
Test status
Simulation time 117542355 ps
CPU time 1.91 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:52:20 PM PDT 24
Peak memory 200236 kb
Host smart-ff735990-1b21-4f49-a385-a2cb77017d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829507920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2829507920
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2503151327
Short name T496
Test name
Test status
Simulation time 126144527468 ps
CPU time 819.08 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 06:06:03 PM PDT 24
Peak memory 696324 kb
Host smart-38318149-37ea-4d27-8538-b55059bf24d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503151327 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2503151327
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2187918252
Short name T208
Test name
Test status
Simulation time 1863925024 ps
CPU time 37.2 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:52:56 PM PDT 24
Peak memory 200220 kb
Host smart-951880d7-45c9-4c96-a3d7-3bbb33807037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187918252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2187918252
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1650173329
Short name T263
Test name
Test status
Simulation time 24435003 ps
CPU time 0.57 seconds
Started Jul 20 05:52:31 PM PDT 24
Finished Jul 20 05:52:32 PM PDT 24
Peak memory 195788 kb
Host smart-26efc007-df6f-40b5-a92d-aead66722f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650173329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1650173329
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3975905979
Short name T461
Test name
Test status
Simulation time 3376965052 ps
CPU time 42.87 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 05:53:01 PM PDT 24
Peak memory 200292 kb
Host smart-530f1366-8eda-4d76-aca1-c549b9e65323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975905979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3975905979
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.401187492
Short name T323
Test name
Test status
Simulation time 598587586 ps
CPU time 15.87 seconds
Started Jul 20 05:52:09 PM PDT 24
Finished Jul 20 05:52:26 PM PDT 24
Peak memory 200280 kb
Host smart-b3162a94-12bf-4d10-acd7-c8834f0cb620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401187492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.401187492
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3852337536
Short name T452
Test name
Test status
Simulation time 29993005120 ps
CPU time 875.78 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 06:06:52 PM PDT 24
Peak memory 765136 kb
Host smart-db89d299-c85f-473c-b33b-963074c81922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852337536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3852337536
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3208099964
Short name T251
Test name
Test status
Simulation time 2299750468 ps
CPU time 31.61 seconds
Started Jul 20 05:52:18 PM PDT 24
Finished Jul 20 05:52:51 PM PDT 24
Peak memory 200296 kb
Host smart-6130098a-6e00-418f-95ef-70bb350de9cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208099964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3208099964
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1410840871
Short name T264
Test name
Test status
Simulation time 1214684326 ps
CPU time 66.12 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:53:35 PM PDT 24
Peak memory 200268 kb
Host smart-f8ab9209-9c8c-429d-9974-1852183dfef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410840871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1410840871
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.30455175
Short name T197
Test name
Test status
Simulation time 854404927 ps
CPU time 9.46 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 05:52:21 PM PDT 24
Peak memory 200256 kb
Host smart-0255b8f0-ed1c-4402-a526-4ff3ad8c6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30455175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.30455175
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3789519250
Short name T155
Test name
Test status
Simulation time 1000085386 ps
CPU time 28.71 seconds
Started Jul 20 05:52:12 PM PDT 24
Finished Jul 20 05:52:42 PM PDT 24
Peak memory 200268 kb
Host smart-431855e1-3383-4978-8e92-4cb279e25f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789519250 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3789519250
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1465277674
Short name T93
Test name
Test status
Simulation time 1738726309 ps
CPU time 40.7 seconds
Started Jul 20 05:52:12 PM PDT 24
Finished Jul 20 05:52:54 PM PDT 24
Peak memory 200256 kb
Host smart-cd68f382-2fb8-4da1-8d2d-9ac049839568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465277674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1465277674
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.336087016
Short name T206
Test name
Test status
Simulation time 18873900 ps
CPU time 0.66 seconds
Started Jul 20 05:51:57 PM PDT 24
Finished Jul 20 05:51:58 PM PDT 24
Peak memory 196188 kb
Host smart-a0afe7b2-a6f6-4902-9027-c5ab92116302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336087016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.336087016
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3425027430
Short name T245
Test name
Test status
Simulation time 6168814305 ps
CPU time 88.42 seconds
Started Jul 20 05:51:53 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 200316 kb
Host smart-6ca8a016-1dfb-4bad-a96b-258ae94c262b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425027430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3425027430
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2832769929
Short name T409
Test name
Test status
Simulation time 23320427821 ps
CPU time 58.34 seconds
Started Jul 20 05:51:45 PM PDT 24
Finished Jul 20 05:52:44 PM PDT 24
Peak memory 200480 kb
Host smart-ccd4910a-d3b7-4d10-9283-dd07abd57c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832769929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2832769929
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.502080475
Short name T378
Test name
Test status
Simulation time 2872255027 ps
CPU time 462.25 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:59:30 PM PDT 24
Peak memory 618464 kb
Host smart-0cb7c41b-bd1e-44b1-aee8-2ccd1f2dac01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=502080475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.502080475
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3742760984
Short name T487
Test name
Test status
Simulation time 27091612141 ps
CPU time 37.89 seconds
Started Jul 20 05:51:43 PM PDT 24
Finished Jul 20 05:52:22 PM PDT 24
Peak memory 200288 kb
Host smart-0623fcb0-dcfa-4c5c-8622-8baf19c7236a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742760984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3742760984
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.143418666
Short name T38
Test name
Test status
Simulation time 51476023386 ps
CPU time 160.52 seconds
Started Jul 20 05:51:53 PM PDT 24
Finished Jul 20 05:54:34 PM PDT 24
Peak memory 200356 kb
Host smart-f7121a6c-0dc8-4a73-9e8a-fec2128b8a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143418666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.143418666
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3685246561
Short name T45
Test name
Test status
Simulation time 63962955 ps
CPU time 0.89 seconds
Started Jul 20 05:51:47 PM PDT 24
Finished Jul 20 05:51:49 PM PDT 24
Peak memory 218500 kb
Host smart-f92dc0c4-9c0b-494d-9a61-26d54073a0d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685246561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3685246561
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3778276410
Short name T416
Test name
Test status
Simulation time 2545904290 ps
CPU time 10.01 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 05:52:01 PM PDT 24
Peak memory 200260 kb
Host smart-45da3568-d347-48da-95d5-d6d9b5836b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778276410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3778276410
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2676785635
Short name T260
Test name
Test status
Simulation time 33910891286 ps
CPU time 608.84 seconds
Started Jul 20 05:51:48 PM PDT 24
Finished Jul 20 06:01:58 PM PDT 24
Peak memory 200308 kb
Host smart-aa824dc8-2b0c-4174-abc0-ef13c536cb49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676785635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2676785635
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.983351010
Short name T11
Test name
Test status
Simulation time 1365507445978 ps
CPU time 1425.47 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 06:15:47 PM PDT 24
Peak memory 645272 kb
Host smart-929e342b-39b2-4fa9-95aa-d1ed92f64f80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983351010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.983351010
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1055782595
Short name T259
Test name
Test status
Simulation time 12343636885 ps
CPU time 71.93 seconds
Started Jul 20 05:51:55 PM PDT 24
Finished Jul 20 05:53:08 PM PDT 24
Peak memory 200312 kb
Host smart-fd50eabe-5f13-44f8-9119-12158ed0af54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1055782595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1055782595
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3744064426
Short name T147
Test name
Test status
Simulation time 8869911727 ps
CPU time 55.1 seconds
Started Jul 20 05:51:57 PM PDT 24
Finished Jul 20 05:52:52 PM PDT 24
Peak memory 200296 kb
Host smart-e185a7f2-7955-4058-b740-034818bfa3d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3744064426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3744064426
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1297106167
Short name T179
Test name
Test status
Simulation time 7027689167 ps
CPU time 80.06 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 200300 kb
Host smart-ec79f1ed-8a18-4c69-a6b0-7081926195a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1297106167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1297106167
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1340076678
Short name T271
Test name
Test status
Simulation time 22183779588 ps
CPU time 577.14 seconds
Started Jul 20 05:51:49 PM PDT 24
Finished Jul 20 06:01:27 PM PDT 24
Peak memory 200256 kb
Host smart-b761c581-9833-4443-9226-87171cfe37e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1340076678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1340076678
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2662791952
Short name T166
Test name
Test status
Simulation time 190769400174 ps
CPU time 1934.24 seconds
Started Jul 20 05:51:49 PM PDT 24
Finished Jul 20 06:24:04 PM PDT 24
Peak memory 216088 kb
Host smart-fbbf75a8-ad4c-401b-aada-a8fce7a90638
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2662791952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2662791952
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.252701155
Short name T130
Test name
Test status
Simulation time 136863556263 ps
CPU time 2447.73 seconds
Started Jul 20 05:51:47 PM PDT 24
Finished Jul 20 06:32:36 PM PDT 24
Peak memory 216500 kb
Host smart-825e0112-0e06-4c6a-b515-d9373868f94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=252701155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.252701155
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3572831190
Short name T80
Test name
Test status
Simulation time 6726309337 ps
CPU time 92.55 seconds
Started Jul 20 05:51:45 PM PDT 24
Finished Jul 20 05:53:18 PM PDT 24
Peak memory 200256 kb
Host smart-a2d8efbf-fd95-44ed-9330-78a09da1a85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572831190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3572831190
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2813125143
Short name T286
Test name
Test status
Simulation time 38950973 ps
CPU time 0.58 seconds
Started Jul 20 05:52:13 PM PDT 24
Finished Jul 20 05:52:15 PM PDT 24
Peak memory 196872 kb
Host smart-7bfa1948-14d9-427f-8aa7-85b24a594c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813125143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2813125143
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4004903449
Short name T508
Test name
Test status
Simulation time 10348056748 ps
CPU time 90.37 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 200428 kb
Host smart-960b40d2-0f30-496a-84a6-f8a4492d8491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004903449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4004903449
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2182906377
Short name T364
Test name
Test status
Simulation time 4757429701 ps
CPU time 61.95 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:53:20 PM PDT 24
Peak memory 200340 kb
Host smart-d5514654-e3e3-4d38-bfd2-3236ea148652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182906377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2182906377
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.317287340
Short name T235
Test name
Test status
Simulation time 10270710730 ps
CPU time 470.47 seconds
Started Jul 20 05:52:31 PM PDT 24
Finished Jul 20 06:00:22 PM PDT 24
Peak memory 726380 kb
Host smart-d406fbed-73bc-43ea-a638-aba12e7b9054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317287340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.317287340
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1735336261
Short name T141
Test name
Test status
Simulation time 3048002947 ps
CPU time 175.07 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 200344 kb
Host smart-08f5a668-ab70-4a83-af2f-3f9ce787fe72
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735336261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1735336261
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2178607376
Short name T297
Test name
Test status
Simulation time 30218467258 ps
CPU time 93.37 seconds
Started Jul 20 05:52:31 PM PDT 24
Finished Jul 20 05:54:10 PM PDT 24
Peak memory 200352 kb
Host smart-405faa29-5dbf-4ce3-9791-cbfaf260e2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178607376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2178607376
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3990713571
Short name T501
Test name
Test status
Simulation time 97824144 ps
CPU time 1.61 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:52:20 PM PDT 24
Peak memory 200260 kb
Host smart-7b64f557-5981-4add-9325-2ca715630a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990713571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3990713571
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2352752372
Short name T178
Test name
Test status
Simulation time 28423751738 ps
CPU time 373.61 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:58:39 PM PDT 24
Peak memory 200296 kb
Host smart-d1c60b1c-e7e5-4b55-b070-08e42933d451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352752372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2352752372
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2726130482
Short name T1
Test name
Test status
Simulation time 6726748600 ps
CPU time 120.17 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 05:54:18 PM PDT 24
Peak memory 200444 kb
Host smart-ebf39517-1afa-4888-a892-bf477fd485ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726130482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2726130482
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3135411559
Short name T277
Test name
Test status
Simulation time 16173171 ps
CPU time 0.58 seconds
Started Jul 20 05:52:34 PM PDT 24
Finished Jul 20 05:52:35 PM PDT 24
Peak memory 196196 kb
Host smart-ef494e94-1cb2-4154-aebc-e704b1962af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135411559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3135411559
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1973459298
Short name T298
Test name
Test status
Simulation time 3749153227 ps
CPU time 53.53 seconds
Started Jul 20 05:52:30 PM PDT 24
Finished Jul 20 05:53:24 PM PDT 24
Peak memory 208576 kb
Host smart-3a6b919c-6b3e-4b3d-8971-62e8622cefdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973459298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1973459298
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.629053951
Short name T516
Test name
Test status
Simulation time 644766425 ps
CPU time 37.24 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:53:01 PM PDT 24
Peak memory 200248 kb
Host smart-6621ecaa-2309-4946-b3fe-902f32efc3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629053951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.629053951
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4007081445
Short name T224
Test name
Test status
Simulation time 13989968538 ps
CPU time 549.5 seconds
Started Jul 20 05:52:34 PM PDT 24
Finished Jul 20 06:01:44 PM PDT 24
Peak memory 641724 kb
Host smart-9359b270-48f2-4332-87d6-cb1c871973fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007081445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4007081445
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1265972754
Short name T393
Test name
Test status
Simulation time 2613699409 ps
CPU time 35.98 seconds
Started Jul 20 05:52:32 PM PDT 24
Finished Jul 20 05:53:09 PM PDT 24
Peak memory 200340 kb
Host smart-9d56b4e5-4925-4cbb-ab71-8b7c48173d42
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265972754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1265972754
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1037521593
Short name T433
Test name
Test status
Simulation time 3196624265 ps
CPU time 124.51 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 05:54:31 PM PDT 24
Peak memory 200316 kb
Host smart-f59a9547-d4f7-47ca-96c9-e36a5e2b955b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037521593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1037521593
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1419246402
Short name T184
Test name
Test status
Simulation time 149561429 ps
CPU time 5.98 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 05:52:31 PM PDT 24
Peak memory 200248 kb
Host smart-01df410b-d659-4e91-a194-463cf02dc7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419246402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1419246402
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2850582765
Short name T387
Test name
Test status
Simulation time 7217158729 ps
CPU time 391.8 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:58:46 PM PDT 24
Peak memory 216748 kb
Host smart-acba0c70-fafc-4dc1-8c11-d5f02eb23a74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850582765 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2850582765
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4242034196
Short name T495
Test name
Test status
Simulation time 2041069711 ps
CPU time 93.56 seconds
Started Jul 20 05:52:19 PM PDT 24
Finished Jul 20 05:53:54 PM PDT 24
Peak memory 200256 kb
Host smart-2fdb7f88-0504-4d4f-8104-f55a32516c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242034196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4242034196
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3879426567
Short name T524
Test name
Test status
Simulation time 180992734 ps
CPU time 0.58 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:52:19 PM PDT 24
Peak memory 195168 kb
Host smart-acfea16f-87c5-4177-b522-98d3fcdc6af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879426567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3879426567
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3141435560
Short name T203
Test name
Test status
Simulation time 2287047260 ps
CPU time 37.58 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:53:02 PM PDT 24
Peak memory 200316 kb
Host smart-1216d1f8-aa8b-4922-89af-971e81dca103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141435560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3141435560
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3481110387
Short name T20
Test name
Test status
Simulation time 1002634521 ps
CPU time 54.99 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 200404 kb
Host smart-2f9cef34-2733-4e53-a20d-24a32c7d3b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481110387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3481110387
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3480578413
Short name T493
Test name
Test status
Simulation time 1911101681 ps
CPU time 359.44 seconds
Started Jul 20 05:52:20 PM PDT 24
Finished Jul 20 05:58:20 PM PDT 24
Peak memory 628612 kb
Host smart-02fd41ea-6c86-447d-912f-1e351ef499d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480578413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3480578413
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1806469029
Short name T128
Test name
Test status
Simulation time 2257342461 ps
CPU time 29.31 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:52:45 PM PDT 24
Peak memory 200284 kb
Host smart-f80b2502-f32e-4544-88c0-2d84ec2dc151
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806469029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1806469029
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2761565077
Short name T145
Test name
Test status
Simulation time 6099718734 ps
CPU time 86.49 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:53:50 PM PDT 24
Peak memory 200220 kb
Host smart-01d7ac40-ee2b-4655-a8d0-ab3ca0cc4647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761565077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2761565077
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2894644513
Short name T497
Test name
Test status
Simulation time 367476624 ps
CPU time 6.16 seconds
Started Jul 20 05:52:33 PM PDT 24
Finished Jul 20 05:52:40 PM PDT 24
Peak memory 200292 kb
Host smart-78a0a250-de02-4f1e-90f6-8ebbddb3bfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894644513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2894644513
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2989805709
Short name T455
Test name
Test status
Simulation time 6187024177 ps
CPU time 614.54 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 06:02:41 PM PDT 24
Peak memory 657096 kb
Host smart-65b06268-ecbf-4208-ae47-7cecc8bbf000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989805709 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2989805709
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2080265686
Short name T517
Test name
Test status
Simulation time 1966639572 ps
CPU time 35.46 seconds
Started Jul 20 05:52:13 PM PDT 24
Finished Jul 20 05:52:49 PM PDT 24
Peak memory 200136 kb
Host smart-cb764370-c688-4b46-ba02-c27c50471f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080265686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2080265686
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.552387180
Short name T195
Test name
Test status
Simulation time 20701990 ps
CPU time 0.59 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 05:52:18 PM PDT 24
Peak memory 196188 kb
Host smart-5990faf7-2e7c-426a-8aa8-48167e6310b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552387180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.552387180
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2202845921
Short name T50
Test name
Test status
Simulation time 8876146351 ps
CPU time 27.11 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:52:51 PM PDT 24
Peak memory 200364 kb
Host smart-1992d764-4cc6-4841-984e-a3b96e750cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202845921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2202845921
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3998450265
Short name T479
Test name
Test status
Simulation time 567941335 ps
CPU time 7.88 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 05:52:26 PM PDT 24
Peak memory 200240 kb
Host smart-90fa5e78-29b6-4385-8c49-8e501e887b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998450265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3998450265
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1562158479
Short name T212
Test name
Test status
Simulation time 3653695882 ps
CPU time 624.75 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 06:02:42 PM PDT 24
Peak memory 688772 kb
Host smart-365ac510-15a4-4117-83ce-aff804c53f96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562158479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1562158479
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3452519983
Short name T283
Test name
Test status
Simulation time 751775622 ps
CPU time 41.6 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 05:53:07 PM PDT 24
Peak memory 200144 kb
Host smart-89dba677-2c0d-4bbf-9b0d-62fdbbd0c676
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452519983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3452519983
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3690935436
Short name T457
Test name
Test status
Simulation time 2624215122 ps
CPU time 68.11 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:53:32 PM PDT 24
Peak memory 200368 kb
Host smart-1b2de6e3-661b-4e22-9dee-3d4047980a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690935436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3690935436
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1378392916
Short name T481
Test name
Test status
Simulation time 57464318 ps
CPU time 2.84 seconds
Started Jul 20 05:52:30 PM PDT 24
Finished Jul 20 05:52:33 PM PDT 24
Peak memory 200244 kb
Host smart-90373bab-31c8-436b-9713-0f2594263e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378392916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1378392916
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2622307608
Short name T280
Test name
Test status
Simulation time 98845154 ps
CPU time 1.87 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:52:42 PM PDT 24
Peak memory 200100 kb
Host smart-692b4798-df42-4dee-ad7d-2a71e1d0d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622307608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2622307608
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2928798839
Short name T360
Test name
Test status
Simulation time 14674250 ps
CPU time 0.59 seconds
Started Jul 20 05:52:19 PM PDT 24
Finished Jul 20 05:52:21 PM PDT 24
Peak memory 196872 kb
Host smart-b7e0f235-2d9a-4974-bb9a-3479e36f06b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928798839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2928798839
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2210795338
Short name T325
Test name
Test status
Simulation time 3722838919 ps
CPU time 42.59 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:52:59 PM PDT 24
Peak memory 200304 kb
Host smart-978750a9-b55e-4954-8765-f508e34b5f4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210795338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2210795338
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1221757185
Short name T424
Test name
Test status
Simulation time 1127034264 ps
CPU time 17.1 seconds
Started Jul 20 05:52:18 PM PDT 24
Finished Jul 20 05:52:36 PM PDT 24
Peak memory 200152 kb
Host smart-08d8f3d4-ef3e-4e45-b260-eacce2b448dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221757185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1221757185
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3543464959
Short name T291
Test name
Test status
Simulation time 3203327106 ps
CPU time 542.11 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 06:01:21 PM PDT 24
Peak memory 636092 kb
Host smart-7a29b2a3-bde1-4464-86b2-d9c5ae02b24c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543464959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3543464959
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.639503176
Short name T463
Test name
Test status
Simulation time 39577247798 ps
CPU time 138.36 seconds
Started Jul 20 05:52:18 PM PDT 24
Finished Jul 20 05:54:38 PM PDT 24
Peak memory 200344 kb
Host smart-ef20adc8-0287-4237-baf6-b683ecb78b2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639503176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.639503176
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.90114493
Short name T249
Test name
Test status
Simulation time 2780584656 ps
CPU time 14.98 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:52:55 PM PDT 24
Peak memory 199520 kb
Host smart-c8900f1f-cab7-4edc-9bcb-405b629e8ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90114493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.90114493
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3739884985
Short name T202
Test name
Test status
Simulation time 46290974 ps
CPU time 2.06 seconds
Started Jul 20 05:52:19 PM PDT 24
Finished Jul 20 05:52:22 PM PDT 24
Peak memory 200156 kb
Host smart-b3297654-d201-4967-be7a-288b1454c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739884985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3739884985
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1438557801
Short name T164
Test name
Test status
Simulation time 8412287742 ps
CPU time 118.74 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 05:54:25 PM PDT 24
Peak memory 200264 kb
Host smart-093c4149-479e-40d9-be25-91ef20267042
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438557801 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1438557801
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1030964151
Short name T265
Test name
Test status
Simulation time 2172638372 ps
CPU time 27.04 seconds
Started Jul 20 05:52:27 PM PDT 24
Finished Jul 20 05:52:56 PM PDT 24
Peak memory 200356 kb
Host smart-3a3abfbd-52ae-4b0e-8e99-768404fbda06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030964151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1030964151
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.811074824
Short name T177
Test name
Test status
Simulation time 43922569 ps
CPU time 0.61 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 05:52:18 PM PDT 24
Peak memory 196188 kb
Host smart-b52c6967-3787-4bf6-8ec5-12fe0bcaac6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811074824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.811074824
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2484583850
Short name T462
Test name
Test status
Simulation time 222550054 ps
CPU time 13.23 seconds
Started Jul 20 05:52:33 PM PDT 24
Finished Jul 20 05:52:47 PM PDT 24
Peak memory 200204 kb
Host smart-2759486f-74b6-4ae1-9d97-524a59fd06fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484583850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2484583850
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1892631381
Short name T227
Test name
Test status
Simulation time 282594393 ps
CPU time 5.75 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:52:25 PM PDT 24
Peak memory 200296 kb
Host smart-b7e10066-9777-46f2-b453-5512e06c7edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892631381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1892631381
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1082618021
Short name T134
Test name
Test status
Simulation time 7289384375 ps
CPU time 1391.13 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 06:15:26 PM PDT 24
Peak memory 780528 kb
Host smart-3c6daac2-e7cd-4384-8e89-0dbe72ce80a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082618021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1082618021
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3842119631
Short name T355
Test name
Test status
Simulation time 15624160284 ps
CPU time 159.19 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:54:54 PM PDT 24
Peak memory 200300 kb
Host smart-3f527773-b7a6-4f1c-85a6-d092616c887c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842119631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3842119631
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1218473255
Short name T255
Test name
Test status
Simulation time 40188339910 ps
CPU time 175.64 seconds
Started Jul 20 05:52:34 PM PDT 24
Finished Jul 20 05:55:30 PM PDT 24
Peak memory 200368 kb
Host smart-d300b70a-e594-4cfb-8342-1c6e90ad28b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218473255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1218473255
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.335400869
Short name T502
Test name
Test status
Simulation time 1040906973 ps
CPU time 11.96 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:52:42 PM PDT 24
Peak memory 200240 kb
Host smart-f8d1d480-86ef-44ac-9c42-189a8e0d578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335400869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.335400869
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1713997148
Short name T160
Test name
Test status
Simulation time 85987529607 ps
CPU time 2086.75 seconds
Started Jul 20 05:52:18 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 806020 kb
Host smart-eff10c6c-c57f-46c2-8f11-2db9d91e6c7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713997148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1713997148
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2194720837
Short name T72
Test name
Test status
Simulation time 9023514159 ps
CPU time 73.48 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:53:30 PM PDT 24
Peak memory 200288 kb
Host smart-d7d7749d-9b42-404a-b28d-29a51564e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194720837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2194720837
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2581494528
Short name T504
Test name
Test status
Simulation time 14162988 ps
CPU time 0.59 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 05:52:13 PM PDT 24
Peak memory 196324 kb
Host smart-d4eb2349-ca0c-40e6-a979-762b48df4535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581494528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2581494528
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2522327766
Short name T320
Test name
Test status
Simulation time 4994455349 ps
CPU time 76.38 seconds
Started Jul 20 05:52:29 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 200336 kb
Host smart-c02927e7-9669-4f4b-adf4-302009a2993a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522327766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2522327766
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2007046661
Short name T305
Test name
Test status
Simulation time 1153482942 ps
CPU time 59.47 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 05:53:26 PM PDT 24
Peak memory 200200 kb
Host smart-e65815be-f6c3-48ea-98b8-06b89b86d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007046661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2007046661
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2240503163
Short name T307
Test name
Test status
Simulation time 14539701873 ps
CPU time 747.64 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 06:04:43 PM PDT 24
Peak memory 675076 kb
Host smart-2fc38e10-915f-404b-bb6d-7ae86b26b2b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240503163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2240503163
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.925577450
Short name T503
Test name
Test status
Simulation time 845369692 ps
CPU time 11.12 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:52:28 PM PDT 24
Peak memory 200216 kb
Host smart-1cead760-8a09-493c-a9d6-2fb8fff5dec4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925577450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.925577450
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3455047363
Short name T87
Test name
Test status
Simulation time 21360316722 ps
CPU time 154.18 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:54:50 PM PDT 24
Peak memory 200316 kb
Host smart-efae7b6b-35f0-43b6-9839-04c87629c948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455047363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3455047363
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2015595777
Short name T2
Test name
Test status
Simulation time 876951249 ps
CPU time 3.49 seconds
Started Jul 20 05:52:13 PM PDT 24
Finished Jul 20 05:52:17 PM PDT 24
Peak memory 200248 kb
Host smart-e34c789e-a571-4858-a4bc-cf12f1981cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015595777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2015595777
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3762330619
Short name T66
Test name
Test status
Simulation time 246494807104 ps
CPU time 1492.92 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 06:17:12 PM PDT 24
Peak memory 473884 kb
Host smart-ed2b20c5-0773-480f-b06e-10cdaf619ebe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762330619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3762330619
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3355712353
Short name T446
Test name
Test status
Simulation time 5366838490 ps
CPU time 93.78 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 200104 kb
Host smart-a616ea03-d68e-4538-af56-c43fd3013ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355712353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3355712353
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2809270725
Short name T366
Test name
Test status
Simulation time 13778614 ps
CPU time 0.6 seconds
Started Jul 20 05:52:29 PM PDT 24
Finished Jul 20 05:52:30 PM PDT 24
Peak memory 195960 kb
Host smart-be4f8970-e2b3-4a1d-92f7-bf520524704d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809270725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2809270725
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3406097181
Short name T425
Test name
Test status
Simulation time 1558447296 ps
CPU time 88.71 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:53:58 PM PDT 24
Peak memory 200256 kb
Host smart-6b065aa7-0a0c-459c-ab05-c9b05f1191ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406097181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3406097181
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.527323399
Short name T211
Test name
Test status
Simulation time 10305231060 ps
CPU time 45.65 seconds
Started Jul 20 05:52:29 PM PDT 24
Finished Jul 20 05:53:16 PM PDT 24
Peak memory 216692 kb
Host smart-ff428a6e-fd8e-4fd8-87b2-c4a7ad83ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527323399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.527323399
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3123759916
Short name T183
Test name
Test status
Simulation time 4638235269 ps
CPU time 1011.63 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 06:09:15 PM PDT 24
Peak memory 749824 kb
Host smart-35f704e2-92d5-4a05-9694-30410b9e1617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123759916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3123759916
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.693968319
Short name T377
Test name
Test status
Simulation time 7985332588 ps
CPU time 114.8 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 200308 kb
Host smart-60f06f3d-0fb9-46bb-86a7-76b8745ab6fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693968319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.693968319
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2282964204
Short name T492
Test name
Test status
Simulation time 2441866120 ps
CPU time 71.03 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 200304 kb
Host smart-4716c82c-78b9-4e5e-a09d-41005dbc2f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282964204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2282964204
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.76671548
Short name T506
Test name
Test status
Simulation time 48404585 ps
CPU time 2.56 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:52:18 PM PDT 24
Peak memory 200300 kb
Host smart-e7a580eb-3bcf-404b-9a08-15afd35f025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76671548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.76671548
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2495407263
Short name T136
Test name
Test status
Simulation time 37993964570 ps
CPU time 2296.93 seconds
Started Jul 20 05:52:32 PM PDT 24
Finished Jul 20 06:30:50 PM PDT 24
Peak memory 729300 kb
Host smart-c69537c1-9c62-495b-97a4-23d347486d65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495407263 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2495407263
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1896158961
Short name T114
Test name
Test status
Simulation time 5780390588 ps
CPU time 96.89 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:53:52 PM PDT 24
Peak memory 200388 kb
Host smart-a2727d98-3a6e-49c8-994f-b2141b4cf73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896158961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1896158961
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2305082184
Short name T473
Test name
Test status
Simulation time 18259857 ps
CPU time 0.57 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:52:17 PM PDT 24
Peak memory 196176 kb
Host smart-3b57ace2-510d-4980-a065-b3ce8e4c13b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305082184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2305082184
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.650753081
Short name T19
Test name
Test status
Simulation time 3822182385 ps
CPU time 97 seconds
Started Jul 20 05:52:29 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 200312 kb
Host smart-74a7b8ac-4eea-4f22-ad7a-dc8638ac8967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650753081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.650753081
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1652660142
Short name T117
Test name
Test status
Simulation time 6201195769 ps
CPU time 32.13 seconds
Started Jul 20 05:52:14 PM PDT 24
Finished Jul 20 05:52:48 PM PDT 24
Peak memory 200316 kb
Host smart-16669ec7-0a07-4d0c-b5b8-b8d726631f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652660142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1652660142
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2510336761
Short name T518
Test name
Test status
Simulation time 9628595582 ps
CPU time 762.94 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 06:05:00 PM PDT 24
Peak memory 708340 kb
Host smart-9c5b44c8-6122-4593-96f2-bfe0a14358f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510336761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2510336761
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.820602277
Short name T192
Test name
Test status
Simulation time 47392988963 ps
CPU time 171.72 seconds
Started Jul 20 05:52:15 PM PDT 24
Finished Jul 20 05:55:08 PM PDT 24
Peak memory 200300 kb
Host smart-783132d3-f804-4ae5-adb2-08ac250d5f5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820602277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.820602277
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.173730330
Short name T376
Test name
Test status
Simulation time 7037773002 ps
CPU time 108.66 seconds
Started Jul 20 05:52:16 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 200368 kb
Host smart-0f821fd0-14c5-48c5-bc21-f57c3fe794bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173730330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.173730330
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.688480347
Short name T85
Test name
Test status
Simulation time 2766030231 ps
CPU time 17.05 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 05:52:55 PM PDT 24
Peak memory 200364 kb
Host smart-cef127be-a64c-4b66-b687-62d6506007d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688480347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.688480347
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3649177807
Short name T33
Test name
Test status
Simulation time 249021412492 ps
CPU time 2344.09 seconds
Started Jul 20 05:52:29 PM PDT 24
Finished Jul 20 06:31:35 PM PDT 24
Peak memory 771192 kb
Host smart-e7c1b837-0487-4ba9-a331-d6708552b1d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649177807 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3649177807
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.149447519
Short name T353
Test name
Test status
Simulation time 1562220845 ps
CPU time 72.14 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 05:53:42 PM PDT 24
Peak memory 200376 kb
Host smart-c136d7fe-f5b6-4f19-93f4-e64277410a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149447519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.149447519
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1892827982
Short name T388
Test name
Test status
Simulation time 22610360 ps
CPU time 0.59 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:52:39 PM PDT 24
Peak memory 196112 kb
Host smart-4c6c0783-c5d2-4ead-90a5-4c4fcc08483e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892827982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1892827982
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3097214878
Short name T522
Test name
Test status
Simulation time 1155837795 ps
CPU time 69.33 seconds
Started Jul 20 05:52:41 PM PDT 24
Finished Jul 20 05:53:53 PM PDT 24
Peak memory 200288 kb
Host smart-fa1df5f1-1322-471e-8f5e-260f355d2e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097214878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3097214878
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3976040193
Short name T173
Test name
Test status
Simulation time 12424408969 ps
CPU time 490.64 seconds
Started Jul 20 05:52:34 PM PDT 24
Finished Jul 20 06:00:46 PM PDT 24
Peak memory 638996 kb
Host smart-2f436b8e-2574-44a4-b3cb-cf2f8c0ee70c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976040193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3976040193
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1337609704
Short name T289
Test name
Test status
Simulation time 1518082135 ps
CPU time 87.99 seconds
Started Jul 20 05:52:17 PM PDT 24
Finished Jul 20 05:53:47 PM PDT 24
Peak memory 200216 kb
Host smart-ed233e5e-64c9-470c-b28c-517ff70ccdaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337609704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1337609704
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.543189604
Short name T169
Test name
Test status
Simulation time 10739511314 ps
CPU time 142.8 seconds
Started Jul 20 05:52:31 PM PDT 24
Finished Jul 20 05:54:54 PM PDT 24
Peak memory 200260 kb
Host smart-ac5a31a5-d483-4736-a8be-475d82ac5c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543189604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.543189604
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.890824521
Short name T194
Test name
Test status
Simulation time 551600706 ps
CPU time 7.51 seconds
Started Jul 20 05:52:27 PM PDT 24
Finished Jul 20 05:52:35 PM PDT 24
Peak memory 200192 kb
Host smart-22a6eb14-bc8e-4ebb-914f-e782154d9ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890824521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.890824521
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2689651216
Short name T116
Test name
Test status
Simulation time 57077003313 ps
CPU time 2096.5 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 06:27:34 PM PDT 24
Peak memory 806624 kb
Host smart-f8f29afd-18ff-477e-834a-fc692f045515
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689651216 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2689651216
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.468876509
Short name T346
Test name
Test status
Simulation time 4579714086 ps
CPU time 59.8 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:53:41 PM PDT 24
Peak memory 200260 kb
Host smart-1e43c0e8-3794-4b4a-a027-f757cbea3afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468876509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.468876509
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.840771849
Short name T293
Test name
Test status
Simulation time 25157789 ps
CPU time 0.58 seconds
Started Jul 20 05:51:55 PM PDT 24
Finished Jul 20 05:51:56 PM PDT 24
Peak memory 196140 kb
Host smart-080cb68c-c7e3-443c-817a-f99cff1576ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840771849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.840771849
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2466323856
Short name T329
Test name
Test status
Simulation time 735608451 ps
CPU time 27.09 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 05:52:27 PM PDT 24
Peak memory 200228 kb
Host smart-605bf165-51bb-40b3-858e-e9760ac600ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466323856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2466323856
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1918232713
Short name T15
Test name
Test status
Simulation time 16475533944 ps
CPU time 54.19 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:52:41 PM PDT 24
Peak memory 200360 kb
Host smart-721579b9-d3e9-4d29-8368-70fe2a0d57a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918232713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1918232713
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3461715012
Short name T337
Test name
Test status
Simulation time 22884642919 ps
CPU time 1258.54 seconds
Started Jul 20 05:51:53 PM PDT 24
Finished Jul 20 06:12:53 PM PDT 24
Peak memory 739544 kb
Host smart-3416f201-0ce0-4402-9346-2ebe711b5516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461715012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3461715012
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1462687144
Short name T63
Test name
Test status
Simulation time 12888584939 ps
CPU time 164.14 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 05:54:43 PM PDT 24
Peak memory 200304 kb
Host smart-bcd37c62-803d-47dd-96da-b6dfe78ef48e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462687144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1462687144
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.4030534574
Short name T267
Test name
Test status
Simulation time 9662252597 ps
CPU time 140.28 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 200384 kb
Host smart-b4f8c242-cded-475c-bffa-589b3dc5a052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030534574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.4030534574
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3192306030
Short name T46
Test name
Test status
Simulation time 561735556 ps
CPU time 0.89 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:52:05 PM PDT 24
Peak memory 218676 kb
Host smart-217b5391-b830-4bf7-ac28-f88d30939c18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192306030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3192306030
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1528331066
Short name T399
Test name
Test status
Simulation time 130366769 ps
CPU time 6.2 seconds
Started Jul 20 05:51:55 PM PDT 24
Finished Jul 20 05:52:02 PM PDT 24
Peak memory 200236 kb
Host smart-9c74d937-2919-4550-8790-3f9906982694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528331066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1528331066
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3579344282
Short name T137
Test name
Test status
Simulation time 9053492181 ps
CPU time 498.93 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 06:00:20 PM PDT 24
Peak memory 200244 kb
Host smart-d07b1c88-ff54-4d6c-a715-d97ba5785def
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579344282 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3579344282
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.735057328
Short name T7
Test name
Test status
Simulation time 274834218018 ps
CPU time 4069.55 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 06:59:41 PM PDT 24
Peak memory 794296 kb
Host smart-d2468656-5bac-44ee-89a4-23a34b5ecd7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735057328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.735057328
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2220460349
Short name T520
Test name
Test status
Simulation time 4718332998 ps
CPU time 48.83 seconds
Started Jul 20 05:51:56 PM PDT 24
Finished Jul 20 05:52:46 PM PDT 24
Peak memory 200348 kb
Host smart-3b9ca9bf-092b-440e-a431-fc7666ecfbed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2220460349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2220460349
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.61810253
Short name T56
Test name
Test status
Simulation time 3197692884 ps
CPU time 53.16 seconds
Started Jul 20 05:51:40 PM PDT 24
Finished Jul 20 05:52:33 PM PDT 24
Peak memory 200364 kb
Host smart-dbb40501-3264-4139-a791-5bd7f022bcd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=61810253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.61810253
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1579334588
Short name T172
Test name
Test status
Simulation time 3202015268 ps
CPU time 118.69 seconds
Started Jul 20 05:51:49 PM PDT 24
Finished Jul 20 05:53:48 PM PDT 24
Peak memory 200320 kb
Host smart-ecbe86d3-2e19-4a40-baa1-c77ea4c4d997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1579334588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1579334588
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2553653927
Short name T396
Test name
Test status
Simulation time 164703446339 ps
CPU time 694.98 seconds
Started Jul 20 05:51:58 PM PDT 24
Finished Jul 20 06:03:33 PM PDT 24
Peak memory 200296 kb
Host smart-aeb5dac5-9a2c-458e-a6cc-9a8a6aa648ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2553653927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2553653927
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.844937178
Short name T470
Test name
Test status
Simulation time 240634185804 ps
CPU time 2495.95 seconds
Started Jul 20 05:51:54 PM PDT 24
Finished Jul 20 06:33:31 PM PDT 24
Peak memory 216248 kb
Host smart-6faac0cc-045a-4bed-a0e2-77d7f7cc8e6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=844937178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.844937178
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2054052622
Short name T299
Test name
Test status
Simulation time 593331706494 ps
CPU time 2404.15 seconds
Started Jul 20 05:51:58 PM PDT 24
Finished Jul 20 06:32:03 PM PDT 24
Peak memory 216548 kb
Host smart-cb74fe28-41c9-4c22-bdf9-17f78a5b5f5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2054052622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2054052622
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.995901976
Short name T292
Test name
Test status
Simulation time 11422793071 ps
CPU time 130.75 seconds
Started Jul 20 05:51:47 PM PDT 24
Finished Jul 20 05:53:59 PM PDT 24
Peak memory 200292 kb
Host smart-fba22737-3693-4a31-a3d4-d17f06b3e514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995901976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.995901976
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1846196809
Short name T170
Test name
Test status
Simulation time 37281569 ps
CPU time 0.58 seconds
Started Jul 20 05:52:19 PM PDT 24
Finished Jul 20 05:52:21 PM PDT 24
Peak memory 195812 kb
Host smart-2f17f2b5-336c-4114-a2d7-1b56c424f0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846196809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1846196809
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2178544047
Short name T472
Test name
Test status
Simulation time 367392143 ps
CPU time 22.45 seconds
Started Jul 20 05:52:43 PM PDT 24
Finished Jul 20 05:53:07 PM PDT 24
Peak memory 200240 kb
Host smart-590cbf68-843a-4e4f-86dd-bb2136349d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178544047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2178544047
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3339283735
Short name T232
Test name
Test status
Simulation time 2258434667 ps
CPU time 12.15 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 05:52:50 PM PDT 24
Peak memory 200308 kb
Host smart-78d735db-1e4a-4d50-9eb5-703a1678e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339283735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3339283735
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2562057240
Short name T3
Test name
Test status
Simulation time 8328762700 ps
CPU time 650.45 seconds
Started Jul 20 05:52:49 PM PDT 24
Finished Jul 20 06:03:41 PM PDT 24
Peak memory 674804 kb
Host smart-74655ef6-bd1a-4571-8836-14afde5dc759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562057240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2562057240
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3325588951
Short name T521
Test name
Test status
Simulation time 5787426584 ps
CPU time 168.98 seconds
Started Jul 20 05:52:30 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 200292 kb
Host smart-9ff181ad-47d5-4b29-aacf-bcb0febc5364
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325588951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3325588951
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2554782493
Short name T5
Test name
Test status
Simulation time 9750758994 ps
CPU time 99.54 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 200328 kb
Host smart-2a5cf755-47cd-4775-9179-a573ae54eafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554782493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2554782493
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1697448716
Short name T334
Test name
Test status
Simulation time 302019477 ps
CPU time 2.32 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:52:41 PM PDT 24
Peak memory 200244 kb
Host smart-16b26c3d-7be6-4c2a-ad60-4513f4c231a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697448716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1697448716
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1230454851
Short name T342
Test name
Test status
Simulation time 86256372378 ps
CPU time 2312.26 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 06:31:09 PM PDT 24
Peak memory 734776 kb
Host smart-7e2df730-9891-45dd-af7c-7f534ddb18e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230454851 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1230454851
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2229755955
Short name T242
Test name
Test status
Simulation time 2329331784 ps
CPU time 61.36 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 200300 kb
Host smart-75c2ee3d-30e6-4361-9b71-347136d76dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229755955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2229755955
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.795582454
Short name T519
Test name
Test status
Simulation time 142893930 ps
CPU time 0.61 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:52:24 PM PDT 24
Peak memory 196184 kb
Host smart-f230940c-a9b0-49c1-b8ca-bd82df8cd79b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795582454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.795582454
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2028850365
Short name T403
Test name
Test status
Simulation time 498453665 ps
CPU time 14.58 seconds
Started Jul 20 05:52:35 PM PDT 24
Finished Jul 20 05:52:50 PM PDT 24
Peak memory 200252 kb
Host smart-ea384bf4-2440-44bf-9e4b-2d01a9af3265
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028850365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2028850365
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2370216810
Short name T201
Test name
Test status
Simulation time 2738151827 ps
CPU time 43.79 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 200348 kb
Host smart-e3c09fa0-3766-4ce5-ba00-773a62620a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370216810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2370216810
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2022849641
Short name T278
Test name
Test status
Simulation time 234596480 ps
CPU time 19.54 seconds
Started Jul 20 05:52:49 PM PDT 24
Finished Jul 20 05:53:10 PM PDT 24
Peak memory 248416 kb
Host smart-17914a7a-780a-43f2-84b3-a657c16684ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022849641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2022849641
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.742411911
Short name T174
Test name
Test status
Simulation time 2640800818 ps
CPU time 44.65 seconds
Started Jul 20 05:52:34 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 200292 kb
Host smart-295a2b46-d920-451f-bf26-02463cc18d06
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742411911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.742411911
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1562399845
Short name T415
Test name
Test status
Simulation time 303674160 ps
CPU time 1.91 seconds
Started Jul 20 05:52:35 PM PDT 24
Finished Jul 20 05:52:37 PM PDT 24
Peak memory 200232 kb
Host smart-af4d97a6-2ab1-4f10-8544-9af9e1bc6a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562399845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1562399845
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1226121914
Short name T351
Test name
Test status
Simulation time 3406195010 ps
CPU time 14.5 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:52:55 PM PDT 24
Peak memory 199420 kb
Host smart-35dd538c-8e57-47d3-9b79-316c897566bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226121914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1226121914
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2236890182
Short name T27
Test name
Test status
Simulation time 62079140701 ps
CPU time 1861.84 seconds
Started Jul 20 05:52:42 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 759768 kb
Host smart-a457b199-c4ca-49e8-8e10-fd499bbc3b00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236890182 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2236890182
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2747880971
Short name T81
Test name
Test status
Simulation time 9859088180 ps
CPU time 120.67 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 05:54:25 PM PDT 24
Peak memory 200320 kb
Host smart-55cbdc2e-accb-44d1-9db6-0a799c2e76eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747880971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2747880971
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3071560000
Short name T419
Test name
Test status
Simulation time 16453710 ps
CPU time 0.6 seconds
Started Jul 20 05:52:26 PM PDT 24
Finished Jul 20 05:52:28 PM PDT 24
Peak memory 196180 kb
Host smart-9e7b4fcc-747d-4d09-8634-05ab23e3b284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071560000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3071560000
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1769431307
Short name T427
Test name
Test status
Simulation time 3165358941 ps
CPU time 31.39 seconds
Started Jul 20 05:52:26 PM PDT 24
Finished Jul 20 05:52:58 PM PDT 24
Peak memory 200252 kb
Host smart-13853141-049f-4a69-9310-0df46e0ebc85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769431307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1769431307
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2139559409
Short name T443
Test name
Test status
Simulation time 2929450835 ps
CPU time 8.96 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:52:34 PM PDT 24
Peak memory 200356 kb
Host smart-17e589df-4ae2-4ca5-a950-c4246e7baa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139559409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2139559409
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3632103967
Short name T314
Test name
Test status
Simulation time 5380346607 ps
CPU time 504.79 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 06:01:05 PM PDT 24
Peak memory 685008 kb
Host smart-fd67ef42-e3ee-4ae2-8d86-a3110aa2810a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632103967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3632103967
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3405987198
Short name T191
Test name
Test status
Simulation time 5526331201 ps
CPU time 153.5 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 05:54:58 PM PDT 24
Peak memory 200200 kb
Host smart-a23da7f2-49c1-4888-a138-53c37a547ee5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405987198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3405987198
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1449670350
Short name T474
Test name
Test status
Simulation time 467242548 ps
CPU time 6.47 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:52:45 PM PDT 24
Peak memory 200244 kb
Host smart-5820b372-88bb-462f-a6eb-894814e9bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449670350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1449670350
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1995235859
Short name T442
Test name
Test status
Simulation time 1111692467 ps
CPU time 5.01 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 05:52:42 PM PDT 24
Peak memory 200196 kb
Host smart-828592ba-9c3e-4431-bedc-92612d666035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995235859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1995235859
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.495506732
Short name T491
Test name
Test status
Simulation time 128401050364 ps
CPU time 1727.96 seconds
Started Jul 20 05:52:26 PM PDT 24
Finished Jul 20 06:21:15 PM PDT 24
Peak memory 709436 kb
Host smart-d15c0896-274e-43e1-961a-56ea577f86a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495506732 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.495506732
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3808329555
Short name T480
Test name
Test status
Simulation time 19408561421 ps
CPU time 132.31 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 05:54:37 PM PDT 24
Peak memory 200200 kb
Host smart-052c977a-268c-44b7-a359-754bcb591409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808329555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3808329555
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.402016106
Short name T317
Test name
Test status
Simulation time 12520040 ps
CPU time 0.58 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 05:52:27 PM PDT 24
Peak memory 195160 kb
Host smart-b87e3064-f104-45f7-8efd-1f2f4f268f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402016106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.402016106
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1868844201
Short name T303
Test name
Test status
Simulation time 1450341219 ps
CPU time 85.02 seconds
Started Jul 20 05:52:33 PM PDT 24
Finished Jul 20 05:53:59 PM PDT 24
Peak memory 200252 kb
Host smart-21de8bcc-9bcb-4da7-9b7b-6c81a88db7f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1868844201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1868844201
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1969949001
Short name T214
Test name
Test status
Simulation time 15343092949 ps
CPU time 54.52 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:53:20 PM PDT 24
Peak memory 208548 kb
Host smart-8a315c73-dc87-4b06-82bf-06e09bd80e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969949001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1969949001
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1617975360
Short name T380
Test name
Test status
Simulation time 3105321359 ps
CPU time 484.99 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 06:00:30 PM PDT 24
Peak memory 690232 kb
Host smart-63406955-0086-4b4e-9b0c-6b2eae61e04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617975360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1617975360
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1448473825
Short name T447
Test name
Test status
Simulation time 11313455905 ps
CPU time 81.92 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 05:53:59 PM PDT 24
Peak memory 200292 kb
Host smart-675b816c-ae1b-4101-802e-3f4300d966ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448473825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1448473825
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.797424362
Short name T71
Test name
Test status
Simulation time 12202650790 ps
CPU time 63.01 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:53:27 PM PDT 24
Peak memory 200376 kb
Host smart-8f18009f-3f7e-4247-9f78-7495658a9c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797424362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.797424362
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3596247293
Short name T482
Test name
Test status
Simulation time 170990813 ps
CPU time 2.65 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:52:26 PM PDT 24
Peak memory 200256 kb
Host smart-29c99a01-88ad-41a3-9a31-2a90bcd74e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596247293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3596247293
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3667110498
Short name T418
Test name
Test status
Simulation time 806345494 ps
CPU time 9.64 seconds
Started Jul 20 05:52:20 PM PDT 24
Finished Jul 20 05:52:31 PM PDT 24
Peak memory 200252 kb
Host smart-44eecdfa-4044-42fe-b864-7d815dfb3012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667110498 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3667110498
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4205532822
Short name T439
Test name
Test status
Simulation time 15677597358 ps
CPU time 40.76 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 200344 kb
Host smart-a5093d29-e7de-4314-83b4-619702e85757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205532822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4205532822
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.307517513
Short name T304
Test name
Test status
Simulation time 19468638 ps
CPU time 0.59 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:52:43 PM PDT 24
Peak memory 196804 kb
Host smart-252cfb19-e421-49e1-a80f-29d073b93d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307517513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.307517513
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3830016704
Short name T456
Test name
Test status
Simulation time 2218783929 ps
CPU time 66.92 seconds
Started Jul 20 05:52:27 PM PDT 24
Finished Jul 20 05:53:35 PM PDT 24
Peak memory 200276 kb
Host smart-d0ddc827-8e87-4df8-a818-334359c04d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830016704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3830016704
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2290661158
Short name T270
Test name
Test status
Simulation time 1271602709 ps
CPU time 19.6 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:53:00 PM PDT 24
Peak memory 200184 kb
Host smart-424866ba-9eaa-4226-81f4-4b6034113a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290661158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2290661158
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2970510626
Short name T328
Test name
Test status
Simulation time 5323454872 ps
CPU time 750.03 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 06:05:09 PM PDT 24
Peak memory 520868 kb
Host smart-5d78b250-df62-4f2a-937d-2cb2e04c2a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970510626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2970510626
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.788227149
Short name T397
Test name
Test status
Simulation time 2053833356 ps
CPU time 13.68 seconds
Started Jul 20 05:52:45 PM PDT 24
Finished Jul 20 05:52:59 PM PDT 24
Peak memory 200212 kb
Host smart-87f57125-4443-4568-9f92-41a383125135
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788227149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.788227149
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3291445410
Short name T256
Test name
Test status
Simulation time 57207245297 ps
CPU time 110.78 seconds
Started Jul 20 05:52:35 PM PDT 24
Finished Jul 20 05:54:26 PM PDT 24
Peak memory 200296 kb
Host smart-ba53ae06-832c-42c4-b912-2a3b85f05255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291445410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3291445410
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3667208587
Short name T444
Test name
Test status
Simulation time 3450277830 ps
CPU time 14.51 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 05:52:39 PM PDT 24
Peak memory 200252 kb
Host smart-10c6c79a-da51-4027-9f89-1562ac0f9532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667208587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3667208587
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3718087586
Short name T408
Test name
Test status
Simulation time 48047067187 ps
CPU time 399.07 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:59:04 PM PDT 24
Peak memory 635392 kb
Host smart-1cd10a81-15cb-41ef-98a7-8f04dc8a3de8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718087586 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3718087586
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4192307081
Short name T200
Test name
Test status
Simulation time 2467532813 ps
CPU time 34.23 seconds
Started Jul 20 05:52:21 PM PDT 24
Finished Jul 20 05:52:56 PM PDT 24
Peak memory 200316 kb
Host smart-0271ae44-7146-4c60-a185-3ecbbfb9ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192307081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4192307081
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1177920112
Short name T486
Test name
Test status
Simulation time 38212060 ps
CPU time 0.57 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:52:24 PM PDT 24
Peak memory 196188 kb
Host smart-934abb01-7f93-4ec3-bfc0-8f59d9e66583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177920112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1177920112
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3846300884
Short name T26
Test name
Test status
Simulation time 1338037788 ps
CPU time 77.13 seconds
Started Jul 20 05:52:42 PM PDT 24
Finished Jul 20 05:54:01 PM PDT 24
Peak memory 200188 kb
Host smart-05f66777-37db-432d-9283-2e5ab2be77c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3846300884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3846300884
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1257849730
Short name T16
Test name
Test status
Simulation time 2403693300 ps
CPU time 30.86 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:52:56 PM PDT 24
Peak memory 200220 kb
Host smart-37f23735-9d30-4ab6-868b-8a79df9ffe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257849730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1257849730
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3371378113
Short name T499
Test name
Test status
Simulation time 60192364779 ps
CPU time 838.15 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 06:06:35 PM PDT 24
Peak memory 775520 kb
Host smart-d21ba0bb-7cb3-4cc4-b059-62993e17be5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371378113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3371378113
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3222553239
Short name T274
Test name
Test status
Simulation time 6390672717 ps
CPU time 52.5 seconds
Started Jul 20 05:52:27 PM PDT 24
Finished Jul 20 05:53:20 PM PDT 24
Peak memory 200340 kb
Host smart-a0e2bf50-c6c0-4185-b859-e0acd8b8bac7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222553239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3222553239
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.466955734
Short name T460
Test name
Test status
Simulation time 18404504261 ps
CPU time 92.35 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:54:13 PM PDT 24
Peak memory 208476 kb
Host smart-4cb7cf5f-2134-479b-9813-f4db5bdb8718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466955734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.466955734
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1333609027
Short name T34
Test name
Test status
Simulation time 1270291282 ps
CPU time 14.24 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 05:52:52 PM PDT 24
Peak memory 200232 kb
Host smart-cf27e361-2e8a-459f-b22e-075eae81abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333609027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1333609027
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3591765997
Short name T423
Test name
Test status
Simulation time 77653460695 ps
CPU time 1268.93 seconds
Started Jul 20 05:52:28 PM PDT 24
Finished Jul 20 06:13:39 PM PDT 24
Peak memory 659808 kb
Host smart-ce00f0d9-7c20-4a43-ac30-3d487fa99749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591765997 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3591765997
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1361298368
Short name T349
Test name
Test status
Simulation time 5790758551 ps
CPU time 97.4 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 200216 kb
Host smart-00a41851-fc10-4e10-84f1-4bf82b8bfc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361298368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1361298368
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3664915349
Short name T215
Test name
Test status
Simulation time 14241218 ps
CPU time 0.61 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:52:26 PM PDT 24
Peak memory 196872 kb
Host smart-d1d5d9b1-6448-46fa-b8f6-a71f913e22b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664915349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3664915349
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1011038249
Short name T467
Test name
Test status
Simulation time 5224115732 ps
CPU time 73.7 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 200404 kb
Host smart-a9a619e2-6343-46ae-b1c2-f8f059496776
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011038249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1011038249
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2567076793
Short name T287
Test name
Test status
Simulation time 30171552287 ps
CPU time 51.84 seconds
Started Jul 20 05:52:27 PM PDT 24
Finished Jul 20 05:53:19 PM PDT 24
Peak memory 215888 kb
Host smart-6156e973-afaa-4d8f-b40a-f52f7ee6dc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567076793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2567076793
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2871750277
Short name T133
Test name
Test status
Simulation time 12594422302 ps
CPU time 898.37 seconds
Started Jul 20 05:52:19 PM PDT 24
Finished Jul 20 06:07:19 PM PDT 24
Peak memory 718072 kb
Host smart-8d7d4cc6-c345-4a12-bfa4-3668629e2f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871750277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2871750277
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3825417979
Short name T40
Test name
Test status
Simulation time 11215002706 ps
CPU time 161.19 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:55:19 PM PDT 24
Peak memory 200248 kb
Host smart-55660cf8-13ad-4139-a00b-847b56cff82c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825417979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3825417979
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2146268714
Short name T414
Test name
Test status
Simulation time 122572129 ps
CPU time 3.24 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:52:44 PM PDT 24
Peak memory 200184 kb
Host smart-1de83eac-43ad-4ad8-a6e6-3225b6100567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146268714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2146268714
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1677230060
Short name T248
Test name
Test status
Simulation time 528218578 ps
CPU time 11.5 seconds
Started Jul 20 05:52:32 PM PDT 24
Finished Jul 20 05:52:44 PM PDT 24
Peak memory 200232 kb
Host smart-5efeb111-d433-4d99-a9e0-3c0a402e7776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677230060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1677230060
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2352346975
Short name T389
Test name
Test status
Simulation time 30792687980 ps
CPU time 90.72 seconds
Started Jul 20 05:52:24 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 200312 kb
Host smart-e3277270-dd0c-47d1-a8a9-2eb84119fa0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352346975 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2352346975
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1160622063
Short name T171
Test name
Test status
Simulation time 9759950656 ps
CPU time 76.59 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 05:53:43 PM PDT 24
Peak memory 200352 kb
Host smart-b542f577-e5bd-4a65-8abe-cd25a91e0965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160622063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1160622063
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2014816329
Short name T156
Test name
Test status
Simulation time 34243565 ps
CPU time 0.59 seconds
Started Jul 20 05:52:46 PM PDT 24
Finished Jul 20 05:52:47 PM PDT 24
Peak memory 195172 kb
Host smart-88230e39-154c-4034-92f5-235dcf7753e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014816329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2014816329
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2089006922
Short name T229
Test name
Test status
Simulation time 208293307 ps
CPU time 11.47 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:52:54 PM PDT 24
Peak memory 200156 kb
Host smart-4585e0e9-5fae-4652-ae70-2508c9fb85fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089006922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2089006922
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.105086368
Short name T510
Test name
Test status
Simulation time 957668761 ps
CPU time 13.63 seconds
Started Jul 20 05:52:21 PM PDT 24
Finished Jul 20 05:52:35 PM PDT 24
Peak memory 200288 kb
Host smart-b5c42b74-b905-4806-b06f-2ec58e621f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105086368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.105086368
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2901378388
Short name T216
Test name
Test status
Simulation time 3915675338 ps
CPU time 729.76 seconds
Started Jul 20 05:52:25 PM PDT 24
Finished Jul 20 06:04:36 PM PDT 24
Peak memory 686472 kb
Host smart-a53399c3-aca4-4f64-8f11-5d2e77fb070f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901378388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2901378388
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2590625601
Short name T450
Test name
Test status
Simulation time 8354497342 ps
CPU time 142.95 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:55:06 PM PDT 24
Peak memory 200240 kb
Host smart-58fd5408-9432-4c74-85ff-74ff35eab4ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590625601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2590625601
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1398686657
Short name T167
Test name
Test status
Simulation time 11271377545 ps
CPU time 138.11 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:55:01 PM PDT 24
Peak memory 216476 kb
Host smart-95ab5a01-0485-4569-8616-90223f0a0486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398686657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1398686657
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1883581182
Short name T199
Test name
Test status
Simulation time 1762229826 ps
CPU time 1.67 seconds
Started Jul 20 05:52:22 PM PDT 24
Finished Jul 20 05:52:26 PM PDT 24
Peak memory 200288 kb
Host smart-b5197b63-3ef1-43f5-9b1d-d8b8db1b925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883581182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1883581182
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.499006291
Short name T321
Test name
Test status
Simulation time 18884731457 ps
CPU time 2434.14 seconds
Started Jul 20 05:52:23 PM PDT 24
Finished Jul 20 06:32:59 PM PDT 24
Peak memory 794376 kb
Host smart-77b3304a-2f0d-4465-a536-c3590d541c13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499006291 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.499006291
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3282824966
Short name T488
Test name
Test status
Simulation time 9173916582 ps
CPU time 104.78 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:54:28 PM PDT 24
Peak memory 200216 kb
Host smart-e5e1d844-8adc-4b9a-998b-8d1f4572ac50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282824966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3282824966
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.955440032
Short name T239
Test name
Test status
Simulation time 11211057 ps
CPU time 0.59 seconds
Started Jul 20 05:52:32 PM PDT 24
Finished Jul 20 05:52:33 PM PDT 24
Peak memory 195164 kb
Host smart-7c85d8ad-af11-4fa9-8110-a16a49c31578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955440032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.955440032
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3215858899
Short name T494
Test name
Test status
Simulation time 4164897109 ps
CPU time 85.55 seconds
Started Jul 20 05:52:29 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 216568 kb
Host smart-7bfe5411-464e-4005-a0d2-77d0dee01f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215858899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3215858899
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2076048497
Short name T333
Test name
Test status
Simulation time 2864867589 ps
CPU time 141.15 seconds
Started Jul 20 05:52:32 PM PDT 24
Finished Jul 20 05:54:54 PM PDT 24
Peak memory 432588 kb
Host smart-f58ce3e8-85be-44bc-8fe4-6e525aecbc87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076048497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2076048497
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.602830318
Short name T338
Test name
Test status
Simulation time 6556278243 ps
CPU time 114.19 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:54:32 PM PDT 24
Peak memory 200344 kb
Host smart-f6404839-057c-4999-8b08-5d813ab88566
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602830318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.602830318
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.932676619
Short name T162
Test name
Test status
Simulation time 4966075768 ps
CPU time 46.92 seconds
Started Jul 20 05:52:36 PM PDT 24
Finished Jul 20 05:53:24 PM PDT 24
Peak memory 200368 kb
Host smart-67981a8f-e4dd-4722-87e0-0fb9240aa98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932676619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.932676619
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3993336892
Short name T350
Test name
Test status
Simulation time 100422467 ps
CPU time 2.12 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 05:52:40 PM PDT 24
Peak memory 200200 kb
Host smart-ee4546b2-0687-4ca3-ad6c-d6627cc8263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993336892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3993336892
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2489456187
Short name T83
Test name
Test status
Simulation time 10097540036 ps
CPU time 1368.85 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 06:15:28 PM PDT 24
Peak memory 729240 kb
Host smart-fa247be6-9a83-4705-a1bd-8e1b5f91dcaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489456187 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2489456187
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2702121662
Short name T369
Test name
Test status
Simulation time 677370987 ps
CPU time 8.77 seconds
Started Jul 20 05:52:35 PM PDT 24
Finished Jul 20 05:52:45 PM PDT 24
Peak memory 200180 kb
Host smart-99f21f9f-945f-4fff-9b4d-09a4e23a00c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702121662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2702121662
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.716278633
Short name T241
Test name
Test status
Simulation time 30635793 ps
CPU time 0.58 seconds
Started Jul 20 05:52:53 PM PDT 24
Finished Jul 20 05:52:54 PM PDT 24
Peak memory 196192 kb
Host smart-8af37c52-ebc6-439f-95a7-705c44489425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716278633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.716278633
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1060314594
Short name T196
Test name
Test status
Simulation time 325856633 ps
CPU time 16.2 seconds
Started Jul 20 05:52:43 PM PDT 24
Finished Jul 20 05:53:00 PM PDT 24
Peak memory 200228 kb
Host smart-b44d53cb-b26c-4e92-8892-97a2d7d311f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060314594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1060314594
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2530404213
Short name T362
Test name
Test status
Simulation time 4201495318 ps
CPU time 13.73 seconds
Started Jul 20 05:52:45 PM PDT 24
Finished Jul 20 05:52:59 PM PDT 24
Peak memory 200364 kb
Host smart-c89b89ec-cc27-4dcc-9ab0-c0939697dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530404213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2530404213
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1023472498
Short name T302
Test name
Test status
Simulation time 5751765539 ps
CPU time 1128.24 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 06:11:30 PM PDT 24
Peak memory 767188 kb
Host smart-2947ab6e-76c8-4b7b-afb9-06ccc15f1e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023472498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1023472498
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.922721547
Short name T74
Test name
Test status
Simulation time 2504559237 ps
CPU time 41.73 seconds
Started Jul 20 05:52:33 PM PDT 24
Finished Jul 20 05:53:15 PM PDT 24
Peak memory 200300 kb
Host smart-fd459f1c-849c-4634-956d-417b37c27ecc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922721547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.922721547
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4284253720
Short name T312
Test name
Test status
Simulation time 8501526323 ps
CPU time 169.47 seconds
Started Jul 20 05:52:31 PM PDT 24
Finished Jul 20 05:55:21 PM PDT 24
Peak memory 200416 kb
Host smart-943ef733-bd7d-4492-b2d6-cc3a1f5874b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284253720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4284253720
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1834702384
Short name T75
Test name
Test status
Simulation time 304586671 ps
CPU time 3.95 seconds
Started Jul 20 05:52:34 PM PDT 24
Finished Jul 20 05:52:39 PM PDT 24
Peak memory 200212 kb
Host smart-ef827f2f-e592-4f62-a173-cac08ae30814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834702384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1834702384
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3869905485
Short name T154
Test name
Test status
Simulation time 8820414460 ps
CPU time 110.3 seconds
Started Jul 20 05:52:33 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 200280 kb
Host smart-e6eb161e-07b7-44fb-87fd-79565bd9c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869905485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3869905485
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2011287960
Short name T79
Test name
Test status
Simulation time 54239511 ps
CPU time 0.6 seconds
Started Jul 20 05:51:57 PM PDT 24
Finished Jul 20 05:51:58 PM PDT 24
Peak memory 196192 kb
Host smart-f3d54ffd-8d0e-44a7-9963-8e3c76766793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011287960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2011287960
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.686011509
Short name T401
Test name
Test status
Simulation time 8362692497 ps
CPU time 114.63 seconds
Started Jul 20 05:51:54 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 200384 kb
Host smart-3c60e491-af51-4c1e-b165-b825e29a4196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686011509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.686011509
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3023472155
Short name T246
Test name
Test status
Simulation time 723680793 ps
CPU time 6.73 seconds
Started Jul 20 05:51:54 PM PDT 24
Finished Jul 20 05:52:01 PM PDT 24
Peak memory 200296 kb
Host smart-61f412fc-efdc-4ca3-a462-4146950eb727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023472155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3023472155
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.4097710277
Short name T28
Test name
Test status
Simulation time 3059080756 ps
CPU time 487.53 seconds
Started Jul 20 05:51:55 PM PDT 24
Finished Jul 20 06:00:03 PM PDT 24
Peak memory 672384 kb
Host smart-29864eef-73b2-488a-a794-3c9e34ceaecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097710277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.4097710277
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3301053582
Short name T526
Test name
Test status
Simulation time 73798580 ps
CPU time 4.46 seconds
Started Jul 20 05:51:47 PM PDT 24
Finished Jul 20 05:51:52 PM PDT 24
Peak memory 200072 kb
Host smart-5388d8d7-3d36-4cc1-930d-9acd2ec30824
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301053582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3301053582
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3266497484
Short name T14
Test name
Test status
Simulation time 2106558619 ps
CPU time 78.97 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:53:06 PM PDT 24
Peak memory 200216 kb
Host smart-df140952-557c-49ac-ae1e-0c391d45df14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266497484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3266497484
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1065754859
Short name T48
Test name
Test status
Simulation time 91008068 ps
CPU time 1 seconds
Started Jul 20 05:51:54 PM PDT 24
Finished Jul 20 05:51:56 PM PDT 24
Peak memory 219712 kb
Host smart-ac46ba5c-a4e7-414c-b0ca-4085b8722f51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065754859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1065754859
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1867579525
Short name T335
Test name
Test status
Simulation time 805822027 ps
CPU time 9.02 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:51:56 PM PDT 24
Peak memory 200244 kb
Host smart-2e22df04-171d-4205-a74f-97bfaa307ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867579525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1867579525
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3265107102
Short name T484
Test name
Test status
Simulation time 203951780574 ps
CPU time 1404.24 seconds
Started Jul 20 05:51:57 PM PDT 24
Finished Jul 20 06:15:22 PM PDT 24
Peak memory 759152 kb
Host smart-2adfd3ed-5e23-4d81-8992-b009521bd80d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265107102 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3265107102
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2781621310
Short name T6
Test name
Test status
Simulation time 13685164944 ps
CPU time 1062 seconds
Started Jul 20 05:51:48 PM PDT 24
Finished Jul 20 06:09:31 PM PDT 24
Peak memory 686960 kb
Host smart-f3130660-4d48-4f6c-b144-c266feb49d81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781621310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2781621310
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2371437108
Short name T309
Test name
Test status
Simulation time 5236067282 ps
CPU time 42.8 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 05:52:44 PM PDT 24
Peak memory 200260 kb
Host smart-6d25eff2-40fb-40a3-b4d3-346ed3d75779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2371437108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2371437108
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2945362211
Short name T339
Test name
Test status
Simulation time 5595808528 ps
CPU time 88.82 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:53:32 PM PDT 24
Peak memory 200204 kb
Host smart-74f6e1ce-0e40-4ffc-a379-789d8cb9a63e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2945362211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2945362211
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2436469220
Short name T410
Test name
Test status
Simulation time 9930988060 ps
CPU time 72.9 seconds
Started Jul 20 05:51:54 PM PDT 24
Finished Jul 20 05:53:07 PM PDT 24
Peak memory 200220 kb
Host smart-00034bb3-d8b8-4cad-8220-5af7a7d73920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2436469220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2436469220
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2835310990
Short name T22
Test name
Test status
Simulation time 38639920374 ps
CPU time 537.89 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 06:01:04 PM PDT 24
Peak memory 200172 kb
Host smart-9cc2ea4b-7ea4-46fa-bc3d-eeea0e2a2026
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2835310990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2835310990
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1262533116
Short name T371
Test name
Test status
Simulation time 413574493212 ps
CPU time 2470.03 seconds
Started Jul 20 05:51:47 PM PDT 24
Finished Jul 20 06:32:58 PM PDT 24
Peak memory 215696 kb
Host smart-37ebebb3-a0a8-4468-bda8-fc588e091169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1262533116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1262533116
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1361364887
Short name T379
Test name
Test status
Simulation time 198865286253 ps
CPU time 2582.09 seconds
Started Jul 20 05:51:55 PM PDT 24
Finished Jul 20 06:34:58 PM PDT 24
Peak memory 215916 kb
Host smart-6a726396-8637-4aa2-8728-ae6c30c675f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1361364887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1361364887
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3356679850
Short name T523
Test name
Test status
Simulation time 12169006528 ps
CPU time 132.35 seconds
Started Jul 20 05:51:48 PM PDT 24
Finished Jul 20 05:54:01 PM PDT 24
Peak memory 200356 kb
Host smart-c206af2f-004c-487a-8967-2714ecc8861f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356679850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3356679850
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.22686148
Short name T49
Test name
Test status
Simulation time 21760137 ps
CPU time 0.64 seconds
Started Jul 20 05:52:49 PM PDT 24
Finished Jul 20 05:52:50 PM PDT 24
Peak memory 195116 kb
Host smart-befaf4ba-50d0-49b4-8f09-22f0fa65df5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22686148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.22686148
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1171037849
Short name T421
Test name
Test status
Simulation time 33454009828 ps
CPU time 101.08 seconds
Started Jul 20 05:52:41 PM PDT 24
Finished Jul 20 05:54:25 PM PDT 24
Peak memory 215784 kb
Host smart-eb7d7aca-1f5f-454c-908b-9179a8539cea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171037849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1171037849
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2343005109
Short name T51
Test name
Test status
Simulation time 3011652846 ps
CPU time 54.32 seconds
Started Jul 20 05:52:45 PM PDT 24
Finished Jul 20 05:53:40 PM PDT 24
Peak memory 200292 kb
Host smart-3002b7a3-55b7-406a-885f-82bd1e07ac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343005109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2343005109
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.337516303
Short name T182
Test name
Test status
Simulation time 1340447502 ps
CPU time 216.24 seconds
Started Jul 20 05:52:32 PM PDT 24
Finished Jul 20 05:56:09 PM PDT 24
Peak memory 605760 kb
Host smart-b1bc51e7-8335-4a5e-aa89-0ace20f1642e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337516303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.337516303
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2444341592
Short name T385
Test name
Test status
Simulation time 12216674565 ps
CPU time 83.12 seconds
Started Jul 20 05:52:35 PM PDT 24
Finished Jul 20 05:53:58 PM PDT 24
Peak memory 200300 kb
Host smart-461f67c5-ba62-44ac-b67b-323f8db01bca
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444341592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2444341592
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2360745693
Short name T213
Test name
Test status
Simulation time 9449306529 ps
CPU time 87.54 seconds
Started Jul 20 05:52:32 PM PDT 24
Finished Jul 20 05:54:00 PM PDT 24
Peak memory 200296 kb
Host smart-d6073d6b-3944-446c-875e-c0f969d69330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360745693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2360745693
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1398147648
Short name T187
Test name
Test status
Simulation time 1063428183 ps
CPU time 13.74 seconds
Started Jul 20 05:52:35 PM PDT 24
Finished Jul 20 05:52:50 PM PDT 24
Peak memory 200296 kb
Host smart-d6ad8fbe-3960-45a4-b324-e33f5735fbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398147648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1398147648
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1376745502
Short name T301
Test name
Test status
Simulation time 580325714 ps
CPU time 5.11 seconds
Started Jul 20 05:52:53 PM PDT 24
Finished Jul 20 05:52:59 PM PDT 24
Peak memory 200136 kb
Host smart-ef208d3e-9264-44cb-bded-0dcf5164c4c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376745502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1376745502
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2853590598
Short name T448
Test name
Test status
Simulation time 2159423074 ps
CPU time 38.38 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:53:20 PM PDT 24
Peak memory 200360 kb
Host smart-e1ac73a7-bb88-4569-8942-47333d5f860b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853590598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2853590598
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3874895931
Short name T272
Test name
Test status
Simulation time 45607705 ps
CPU time 0.57 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:52:42 PM PDT 24
Peak memory 195120 kb
Host smart-c09d6f84-39dd-4575-bd96-730d8faceb02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874895931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3874895931
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.492704880
Short name T10
Test name
Test status
Simulation time 4019426099 ps
CPU time 121.61 seconds
Started Jul 20 05:52:56 PM PDT 24
Finished Jul 20 05:54:58 PM PDT 24
Peak memory 215704 kb
Host smart-04f91db5-20a4-4893-92a1-6264f128e99a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492704880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.492704880
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.807784628
Short name T234
Test name
Test status
Simulation time 13298469388 ps
CPU time 362.65 seconds
Started Jul 20 05:52:47 PM PDT 24
Finished Jul 20 05:58:50 PM PDT 24
Peak memory 673696 kb
Host smart-6f8c236b-6c95-42e5-b05f-67da5ab17237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807784628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.807784628
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2312533396
Short name T91
Test name
Test status
Simulation time 12052366735 ps
CPU time 223.55 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:56:24 PM PDT 24
Peak memory 200292 kb
Host smart-a32b96d8-d066-4a59-9253-f030ca7b3ab5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312533396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2312533396
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3606701239
Short name T39
Test name
Test status
Simulation time 1447238303 ps
CPU time 23.51 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:53:06 PM PDT 24
Peak memory 200204 kb
Host smart-d507748d-9288-4395-8198-ddaf3ddd321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606701239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3606701239
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3048989788
Short name T175
Test name
Test status
Simulation time 813512700 ps
CPU time 13.27 seconds
Started Jul 20 05:52:51 PM PDT 24
Finished Jul 20 05:53:05 PM PDT 24
Peak memory 200248 kb
Host smart-58110114-fe20-4698-b38b-a26842c0787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048989788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3048989788
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3968980493
Short name T54
Test name
Test status
Simulation time 78863105056 ps
CPU time 2742.38 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 06:38:25 PM PDT 24
Peak memory 812540 kb
Host smart-a9aac439-38a7-4d09-bafd-70ff7dd3f104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968980493 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3968980493
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3706250515
Short name T31
Test name
Test status
Simulation time 2796347370 ps
CPU time 43.86 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 200364 kb
Host smart-efa826d6-84ae-47b3-888e-4c207af8336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706250515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3706250515
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1390255855
Short name T420
Test name
Test status
Simulation time 15453817 ps
CPU time 0.54 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:52:40 PM PDT 24
Peak memory 195088 kb
Host smart-b09864e5-adea-43d3-809f-3b4030d53d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390255855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1390255855
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.43127129
Short name T475
Test name
Test status
Simulation time 6449434299 ps
CPU time 50.76 seconds
Started Jul 20 05:52:43 PM PDT 24
Finished Jul 20 05:53:35 PM PDT 24
Peak memory 200252 kb
Host smart-9d3db4c7-04e5-406d-b7d8-abb0d57fb83a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43127129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.43127129
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2180229130
Short name T158
Test name
Test status
Simulation time 18732415328 ps
CPU time 49.13 seconds
Started Jul 20 05:52:47 PM PDT 24
Finished Jul 20 05:53:37 PM PDT 24
Peak memory 200292 kb
Host smart-ec1750b0-7d79-479a-938b-a62438ed35ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180229130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2180229130
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.431739034
Short name T428
Test name
Test status
Simulation time 34597574074 ps
CPU time 813.86 seconds
Started Jul 20 05:52:37 PM PDT 24
Finished Jul 20 06:06:13 PM PDT 24
Peak memory 717168 kb
Host smart-84554f5b-edb2-4a3a-bb08-92943f1e538d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431739034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.431739034
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2109514847
Short name T210
Test name
Test status
Simulation time 7856365633 ps
CPU time 95.51 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:54:15 PM PDT 24
Peak memory 200348 kb
Host smart-4acd65a2-2773-4530-b0b8-c6c4fc7f5ea9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109514847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2109514847
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1674747105
Short name T273
Test name
Test status
Simulation time 1180016845 ps
CPU time 34.24 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 200260 kb
Host smart-2ed62154-9e34-4378-aee1-b6560f2a3625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674747105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1674747105
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3809394858
Short name T483
Test name
Test status
Simulation time 775954206 ps
CPU time 13.8 seconds
Started Jul 20 05:52:34 PM PDT 24
Finished Jul 20 05:52:48 PM PDT 24
Peak memory 200312 kb
Host smart-db453b8e-258d-44c2-9e5f-1ca8e48de75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809394858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3809394858
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2305394536
Short name T140
Test name
Test status
Simulation time 23116513099 ps
CPU time 693.5 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 06:04:16 PM PDT 24
Peak memory 274764 kb
Host smart-1e5fe8e0-836f-486f-8bed-eb661730498c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305394536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2305394536
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.354015213
Short name T326
Test name
Test status
Simulation time 2246420757 ps
CPU time 107.37 seconds
Started Jul 20 05:52:40 PM PDT 24
Finished Jul 20 05:54:29 PM PDT 24
Peak memory 200360 kb
Host smart-6d7c3feb-c0d8-421e-81c9-33b43dbe1f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354015213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.354015213
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3294397556
Short name T223
Test name
Test status
Simulation time 39011028 ps
CPU time 0.58 seconds
Started Jul 20 05:52:53 PM PDT 24
Finished Jul 20 05:52:55 PM PDT 24
Peak memory 196100 kb
Host smart-590aacf2-314f-4edb-8411-e2d2a2e6b046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294397556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3294397556
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.283992207
Short name T316
Test name
Test status
Simulation time 3295044941 ps
CPU time 56.1 seconds
Started Jul 20 05:52:55 PM PDT 24
Finished Jul 20 05:53:52 PM PDT 24
Peak memory 200256 kb
Host smart-f22cb920-59bf-4885-8680-0e19046feb38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283992207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.283992207
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4187898618
Short name T226
Test name
Test status
Simulation time 1805641738 ps
CPU time 26.08 seconds
Started Jul 20 05:52:38 PM PDT 24
Finished Jul 20 05:53:06 PM PDT 24
Peak memory 200204 kb
Host smart-fb44e2c1-2a3c-4425-90ca-42f5d4eaa90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187898618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4187898618
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2483075489
Short name T308
Test name
Test status
Simulation time 7532059687 ps
CPU time 335 seconds
Started Jul 20 05:52:39 PM PDT 24
Finished Jul 20 05:58:16 PM PDT 24
Peak memory 632180 kb
Host smart-12a476cb-2384-47d5-a24f-eb3bad33ab58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483075489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2483075489
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3568564515
Short name T221
Test name
Test status
Simulation time 12965048298 ps
CPU time 76.7 seconds
Started Jul 20 05:52:47 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 200340 kb
Host smart-281b9e78-fcfd-487f-930a-589a577f4ea4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568564515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3568564515
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3056343353
Short name T431
Test name
Test status
Simulation time 2726089278 ps
CPU time 48.81 seconds
Started Jul 20 05:52:49 PM PDT 24
Finished Jul 20 05:53:38 PM PDT 24
Peak memory 200360 kb
Host smart-83c26c48-6c7d-4836-bc35-9a8377ec31db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056343353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3056343353
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2116812034
Short name T438
Test name
Test status
Simulation time 295331415 ps
CPU time 5.93 seconds
Started Jul 20 05:52:47 PM PDT 24
Finished Jul 20 05:52:54 PM PDT 24
Peak memory 200252 kb
Host smart-b0bcfd67-ae94-49d1-bc91-d8f4c23460af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116812034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2116812034
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2719864340
Short name T430
Test name
Test status
Simulation time 172974997239 ps
CPU time 679.49 seconds
Started Jul 20 05:52:48 PM PDT 24
Finished Jul 20 06:04:08 PM PDT 24
Peak memory 475040 kb
Host smart-8f78c0e0-5496-4573-b85a-6d17dd6ca89e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719864340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2719864340
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4256330822
Short name T32
Test name
Test status
Simulation time 7346465910 ps
CPU time 129.94 seconds
Started Jul 20 05:52:48 PM PDT 24
Finished Jul 20 05:54:58 PM PDT 24
Peak memory 200320 kb
Host smart-c4f151a8-56b6-4936-ae9a-a2f338d12773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256330822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4256330822
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1755578680
Short name T275
Test name
Test status
Simulation time 21152099 ps
CPU time 0.6 seconds
Started Jul 20 05:52:52 PM PDT 24
Finished Jul 20 05:52:54 PM PDT 24
Peak memory 196176 kb
Host smart-16945799-0312-46c1-b916-092786517eb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755578680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1755578680
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1940986019
Short name T279
Test name
Test status
Simulation time 4522045571 ps
CPU time 50.11 seconds
Started Jul 20 05:52:52 PM PDT 24
Finished Jul 20 05:53:43 PM PDT 24
Peak memory 200228 kb
Host smart-5ea43712-946b-4592-b558-59e065b14106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940986019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1940986019
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1096532811
Short name T381
Test name
Test status
Simulation time 2206933019 ps
CPU time 27.54 seconds
Started Jul 20 05:52:54 PM PDT 24
Finished Jul 20 05:53:23 PM PDT 24
Peak memory 200356 kb
Host smart-3349b821-7aa2-4bd1-a4ab-bb586d8bbf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096532811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1096532811
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1545334093
Short name T152
Test name
Test status
Simulation time 10186826432 ps
CPU time 902.58 seconds
Started Jul 20 05:52:53 PM PDT 24
Finished Jul 20 06:07:57 PM PDT 24
Peak memory 743908 kb
Host smart-b2c21bcf-fecc-4492-a744-f78ac0173345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545334093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1545334093
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1715066149
Short name T86
Test name
Test status
Simulation time 50142759900 ps
CPU time 154.11 seconds
Started Jul 20 05:52:51 PM PDT 24
Finished Jul 20 05:55:26 PM PDT 24
Peak memory 200288 kb
Host smart-20c6f6cd-576c-469c-9691-7f32339d1a46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715066149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1715066149
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.534248910
Short name T454
Test name
Test status
Simulation time 2732325283 ps
CPU time 158.99 seconds
Started Jul 20 05:52:57 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 200316 kb
Host smart-084b2815-5a97-42b5-8cfd-d466beb25675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534248910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.534248910
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3920466796
Short name T131
Test name
Test status
Simulation time 17609629 ps
CPU time 0.75 seconds
Started Jul 20 05:52:50 PM PDT 24
Finished Jul 20 05:52:51 PM PDT 24
Peak memory 198324 kb
Host smart-013f8eb3-9a46-40e6-b7ea-cc2cf559e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920466796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3920466796
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1505216987
Short name T113
Test name
Test status
Simulation time 5439549641 ps
CPU time 302.86 seconds
Started Jul 20 05:52:50 PM PDT 24
Finished Jul 20 05:57:54 PM PDT 24
Peak memory 208760 kb
Host smart-da68114e-e082-403d-98ae-8a619d669b8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505216987 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1505216987
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3761049195
Short name T422
Test name
Test status
Simulation time 4935289225 ps
CPU time 82.82 seconds
Started Jul 20 05:52:54 PM PDT 24
Finished Jul 20 05:54:18 PM PDT 24
Peak memory 200312 kb
Host smart-7695d215-23e2-4ff1-8e50-23c542c68a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761049195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3761049195
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3847075018
Short name T236
Test name
Test status
Simulation time 48031409 ps
CPU time 0.6 seconds
Started Jul 20 05:52:47 PM PDT 24
Finished Jul 20 05:52:49 PM PDT 24
Peak memory 196192 kb
Host smart-de8b6b24-36e7-478e-a71a-fcfee9f1a28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847075018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3847075018
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2294179744
Short name T168
Test name
Test status
Simulation time 785680665 ps
CPU time 46.97 seconds
Started Jul 20 05:52:55 PM PDT 24
Finished Jul 20 05:53:43 PM PDT 24
Peak memory 200192 kb
Host smart-2e8db392-2030-4c4a-aa42-dab2e8f0fa73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2294179744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2294179744
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.437004750
Short name T218
Test name
Test status
Simulation time 10449393227 ps
CPU time 35.32 seconds
Started Jul 20 05:52:47 PM PDT 24
Finished Jul 20 05:53:24 PM PDT 24
Peak memory 200296 kb
Host smart-77c733eb-d8dd-46e9-8572-58ec931e0c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437004750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.437004750
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2826259261
Short name T204
Test name
Test status
Simulation time 4062355096 ps
CPU time 71.58 seconds
Started Jul 20 05:52:46 PM PDT 24
Finished Jul 20 05:53:59 PM PDT 24
Peak memory 331940 kb
Host smart-d92c3ddf-c604-4769-bff2-0df32bd14727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2826259261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2826259261
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1187854225
Short name T257
Test name
Test status
Simulation time 245758586765 ps
CPU time 262.17 seconds
Started Jul 20 05:52:49 PM PDT 24
Finished Jul 20 05:57:12 PM PDT 24
Peak memory 200340 kb
Host smart-f7c1c794-b087-4e9b-8da0-a59e36e41299
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187854225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1187854225
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1478658091
Short name T143
Test name
Test status
Simulation time 19831833872 ps
CPU time 64.57 seconds
Started Jul 20 05:52:59 PM PDT 24
Finished Jul 20 05:54:04 PM PDT 24
Peak memory 200212 kb
Host smart-46eb25c8-db98-4c07-a434-419348d68cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478658091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1478658091
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3083860290
Short name T465
Test name
Test status
Simulation time 4608917777 ps
CPU time 11.15 seconds
Started Jul 20 05:52:50 PM PDT 24
Finished Jul 20 05:53:02 PM PDT 24
Peak memory 200312 kb
Host smart-90c7710c-27cd-498c-9c89-2109089f0f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083860290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3083860290
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.532015929
Short name T359
Test name
Test status
Simulation time 47091973578 ps
CPU time 567.65 seconds
Started Jul 20 05:52:48 PM PDT 24
Finished Jul 20 06:02:16 PM PDT 24
Peak memory 591964 kb
Host smart-6355761d-f231-48b8-b7f8-f74188720b19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532015929 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.532015929
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1094718820
Short name T237
Test name
Test status
Simulation time 17428330445 ps
CPU time 54.76 seconds
Started Jul 20 05:52:46 PM PDT 24
Finished Jul 20 05:53:41 PM PDT 24
Peak memory 200320 kb
Host smart-c38ba339-8867-462b-b925-998cf96aafb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094718820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1094718820
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2914538129
Short name T180
Test name
Test status
Simulation time 15936301 ps
CPU time 0.62 seconds
Started Jul 20 05:52:57 PM PDT 24
Finished Jul 20 05:52:58 PM PDT 24
Peak memory 196208 kb
Host smart-56608b17-f203-43b1-aa11-8255e0c9b416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914538129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2914538129
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4231512015
Short name T209
Test name
Test status
Simulation time 199895212 ps
CPU time 11.54 seconds
Started Jul 20 05:52:54 PM PDT 24
Finished Jul 20 05:53:07 PM PDT 24
Peak memory 200224 kb
Host smart-a901629b-8c4b-4a69-ac8a-ba547241b2e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231512015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4231512015
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1166347900
Short name T402
Test name
Test status
Simulation time 669372349 ps
CPU time 18.45 seconds
Started Jul 20 05:52:51 PM PDT 24
Finished Jul 20 05:53:11 PM PDT 24
Peak memory 200236 kb
Host smart-71f8ffa8-7b9c-408b-a3c7-66b67c1dfb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166347900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1166347900
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3720917273
Short name T284
Test name
Test status
Simulation time 4100236142 ps
CPU time 776.53 seconds
Started Jul 20 05:52:48 PM PDT 24
Finished Jul 20 06:05:45 PM PDT 24
Peak memory 709644 kb
Host smart-8797ac12-9c47-4aba-a001-09ef97f447d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720917273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3720917273
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.740756705
Short name T319
Test name
Test status
Simulation time 12452445950 ps
CPU time 185.02 seconds
Started Jul 20 05:52:57 PM PDT 24
Finished Jul 20 05:56:03 PM PDT 24
Peak memory 200292 kb
Host smart-9202e86c-6d31-4ea7-a92e-7b70f727b4b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740756705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.740756705
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.22374351
Short name T310
Test name
Test status
Simulation time 4959509373 ps
CPU time 84.9 seconds
Started Jul 20 05:52:57 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 200352 kb
Host smart-089af68d-3149-400c-8a42-653d1686bb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22374351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.22374351
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3673335177
Short name T296
Test name
Test status
Simulation time 2050602336 ps
CPU time 11.09 seconds
Started Jul 20 05:52:51 PM PDT 24
Finished Jul 20 05:53:03 PM PDT 24
Peak memory 200304 kb
Host smart-54529bbc-b7f1-4c50-b5c3-650af3b24404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673335177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3673335177
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2472403072
Short name T469
Test name
Test status
Simulation time 1578414808 ps
CPU time 87.16 seconds
Started Jul 20 05:52:59 PM PDT 24
Finished Jul 20 05:54:27 PM PDT 24
Peak memory 200208 kb
Host smart-bad86f8e-1bd6-4387-8eed-2f1f3c4e1fff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472403072 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2472403072
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3547077191
Short name T332
Test name
Test status
Simulation time 5209930326 ps
CPU time 67.49 seconds
Started Jul 20 05:53:01 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 200320 kb
Host smart-59435ac4-85cb-45b6-a33e-d096d0db7b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547077191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3547077191
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2462095412
Short name T193
Test name
Test status
Simulation time 44498552 ps
CPU time 0.58 seconds
Started Jul 20 05:53:02 PM PDT 24
Finished Jul 20 05:53:03 PM PDT 24
Peak memory 195832 kb
Host smart-6037ddc0-dd60-4db7-b46b-6c1283abb461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462095412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2462095412
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1857417748
Short name T225
Test name
Test status
Simulation time 528848084 ps
CPU time 29.37 seconds
Started Jul 20 05:52:57 PM PDT 24
Finished Jul 20 05:53:27 PM PDT 24
Peak memory 200224 kb
Host smart-8d23006c-73d0-40fb-b3e8-9cb49d89fe3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857417748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1857417748
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3811632290
Short name T17
Test name
Test status
Simulation time 2555381091 ps
CPU time 32.19 seconds
Started Jul 20 05:52:58 PM PDT 24
Finished Jul 20 05:53:31 PM PDT 24
Peak memory 200316 kb
Host smart-14b6dfc8-9510-4100-a4dc-6eef1f310d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811632290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3811632290
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1868950180
Short name T459
Test name
Test status
Simulation time 6571248350 ps
CPU time 208.67 seconds
Started Jul 20 05:52:56 PM PDT 24
Finished Jul 20 05:56:25 PM PDT 24
Peak memory 629964 kb
Host smart-7fee7159-a5e1-4507-9ea7-ab2694c13a57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1868950180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1868950180
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.110204123
Short name T78
Test name
Test status
Simulation time 34056867970 ps
CPU time 104.63 seconds
Started Jul 20 05:52:54 PM PDT 24
Finished Jul 20 05:54:39 PM PDT 24
Peak memory 200296 kb
Host smart-be73ad8b-d301-4ce1-a805-eb64259c16a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110204123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.110204123
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3354884014
Short name T426
Test name
Test status
Simulation time 32862670363 ps
CPU time 145.78 seconds
Started Jul 20 05:52:53 PM PDT 24
Finished Jul 20 05:55:20 PM PDT 24
Peak memory 200256 kb
Host smart-e7d92e1a-bc78-4264-88d0-367da9c88d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354884014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3354884014
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2858287813
Short name T88
Test name
Test status
Simulation time 716035019 ps
CPU time 4.86 seconds
Started Jul 20 05:53:02 PM PDT 24
Finished Jul 20 05:53:07 PM PDT 24
Peak memory 200248 kb
Host smart-9161867f-6876-41a3-8aad-cfecf02cc9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858287813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2858287813
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3504647393
Short name T231
Test name
Test status
Simulation time 13688973390 ps
CPU time 427.25 seconds
Started Jul 20 05:52:56 PM PDT 24
Finished Jul 20 06:00:04 PM PDT 24
Peak memory 466160 kb
Host smart-ad8bc0d4-8c31-4326-9725-7317825debfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504647393 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3504647393
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3889238655
Short name T384
Test name
Test status
Simulation time 27872501740 ps
CPU time 86.86 seconds
Started Jul 20 05:52:58 PM PDT 24
Finished Jul 20 05:54:25 PM PDT 24
Peak memory 200316 kb
Host smart-eb5452f5-60c4-4fcb-b1a6-229ebe4bac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889238655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3889238655
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1667225645
Short name T417
Test name
Test status
Simulation time 13391082 ps
CPU time 0.62 seconds
Started Jul 20 05:53:02 PM PDT 24
Finished Jul 20 05:53:03 PM PDT 24
Peak memory 196876 kb
Host smart-3015562c-fc10-40bd-aad3-87ef851ffe08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667225645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1667225645
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2662822435
Short name T511
Test name
Test status
Simulation time 2612351915 ps
CPU time 81.64 seconds
Started Jul 20 05:52:55 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 200292 kb
Host smart-94e4dcac-a1fc-4074-af9f-abdfa0e62ef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662822435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2662822435
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1913736465
Short name T391
Test name
Test status
Simulation time 1555974697 ps
CPU time 16.51 seconds
Started Jul 20 05:53:00 PM PDT 24
Finished Jul 20 05:53:17 PM PDT 24
Peak memory 200260 kb
Host smart-603213f2-65c4-4bf8-8f50-cf78c38f883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913736465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1913736465
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1759487630
Short name T52
Test name
Test status
Simulation time 4303471851 ps
CPU time 381.11 seconds
Started Jul 20 05:52:58 PM PDT 24
Finished Jul 20 05:59:20 PM PDT 24
Peak memory 674456 kb
Host smart-08a98294-35ba-461a-9fb7-b2a475ae186c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759487630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1759487630
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.92555076
Short name T247
Test name
Test status
Simulation time 9609503279 ps
CPU time 88.83 seconds
Started Jul 20 05:52:53 PM PDT 24
Finished Jul 20 05:54:23 PM PDT 24
Peak memory 200484 kb
Host smart-e63a220f-8b62-46f2-8c36-edd8eb43a295
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92555076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.92555076
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.678873289
Short name T458
Test name
Test status
Simulation time 2827129952 ps
CPU time 156.61 seconds
Started Jul 20 05:53:00 PM PDT 24
Finished Jul 20 05:55:37 PM PDT 24
Peak memory 200340 kb
Host smart-7c49ee1d-8fad-4b17-b474-795e322872ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678873289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.678873289
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3595188673
Short name T252
Test name
Test status
Simulation time 949802370 ps
CPU time 12.3 seconds
Started Jul 20 05:53:00 PM PDT 24
Finished Jul 20 05:53:13 PM PDT 24
Peak memory 200252 kb
Host smart-f0432f11-d4e5-42ae-9ecd-7d9258e5ab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595188673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3595188673
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3847417060
Short name T515
Test name
Test status
Simulation time 273440484110 ps
CPU time 2542.23 seconds
Started Jul 20 05:52:56 PM PDT 24
Finished Jul 20 06:35:19 PM PDT 24
Peak memory 777720 kb
Host smart-7d12c38d-8f6f-4917-8a37-6e5a1a115dfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847417060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3847417060
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3983816936
Short name T82
Test name
Test status
Simulation time 9372036267 ps
CPU time 128.66 seconds
Started Jul 20 05:52:55 PM PDT 24
Finished Jul 20 05:55:05 PM PDT 24
Peak memory 200372 kb
Host smart-deae26bd-2c06-4c06-ad2b-b01f8f4abab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983816936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3983816936
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.786229447
Short name T300
Test name
Test status
Simulation time 11481094 ps
CPU time 0.58 seconds
Started Jul 20 05:53:02 PM PDT 24
Finished Jul 20 05:53:03 PM PDT 24
Peak memory 195068 kb
Host smart-a5703d6f-d3c8-474e-a9d2-a6ed50a2835f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786229447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.786229447
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3554599643
Short name T513
Test name
Test status
Simulation time 1660110810 ps
CPU time 95.77 seconds
Started Jul 20 05:52:54 PM PDT 24
Finished Jul 20 05:54:31 PM PDT 24
Peak memory 200232 kb
Host smart-d0987bdf-7e3f-433d-8b58-e3c54daa0690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3554599643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3554599643
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3359632680
Short name T64
Test name
Test status
Simulation time 11771294069 ps
CPU time 12.67 seconds
Started Jul 20 05:52:55 PM PDT 24
Finished Jul 20 05:53:09 PM PDT 24
Peak memory 200360 kb
Host smart-8c885290-a67f-4885-b8c9-d65388c7ed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359632680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3359632680
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.582566260
Short name T151
Test name
Test status
Simulation time 457045085 ps
CPU time 17.57 seconds
Started Jul 20 05:52:57 PM PDT 24
Finished Jul 20 05:53:16 PM PDT 24
Peak memory 217664 kb
Host smart-d184f5b4-11a3-484d-8685-df014f5e84d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582566260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.582566260
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.583514499
Short name T476
Test name
Test status
Simulation time 7892615553 ps
CPU time 93.99 seconds
Started Jul 20 05:52:59 PM PDT 24
Finished Jul 20 05:54:34 PM PDT 24
Peak memory 200304 kb
Host smart-3c925234-134c-49d2-86f1-bcc2903ae8a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583514499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.583514499
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2827304686
Short name T142
Test name
Test status
Simulation time 4103034888 ps
CPU time 109.79 seconds
Started Jul 20 05:52:56 PM PDT 24
Finished Jul 20 05:54:47 PM PDT 24
Peak memory 200324 kb
Host smart-93d03ddd-0c63-47ab-acc8-9c06e75f0cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827304686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2827304686
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3940744876
Short name T413
Test name
Test status
Simulation time 207231679 ps
CPU time 2.87 seconds
Started Jul 20 05:53:00 PM PDT 24
Finished Jul 20 05:53:03 PM PDT 24
Peak memory 200240 kb
Host smart-cb92f60d-d02b-4101-9129-69ceb521da6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940744876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3940744876
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2552825656
Short name T230
Test name
Test status
Simulation time 2920220416 ps
CPU time 163.33 seconds
Started Jul 20 05:53:05 PM PDT 24
Finished Jul 20 05:55:49 PM PDT 24
Peak memory 200308 kb
Host smart-5a366180-7fe5-4a82-bba4-067e99bbe7ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552825656 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2552825656
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2939680643
Short name T186
Test name
Test status
Simulation time 3135253272 ps
CPU time 79.3 seconds
Started Jul 20 05:52:55 PM PDT 24
Finished Jul 20 05:54:15 PM PDT 24
Peak memory 200488 kb
Host smart-11130a4c-4d9c-4706-af37-34842d9f3f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939680643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2939680643
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1499474810
Short name T356
Test name
Test status
Simulation time 23964734 ps
CPU time 0.56 seconds
Started Jul 20 05:52:05 PM PDT 24
Finished Jul 20 05:52:07 PM PDT 24
Peak memory 195848 kb
Host smart-0f0b0dab-c711-4dcd-934a-b5ff01f30360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499474810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1499474810
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1914764622
Short name T324
Test name
Test status
Simulation time 8638047632 ps
CPU time 76.85 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:53:20 PM PDT 24
Peak memory 200296 kb
Host smart-3d142372-734e-42be-9ae7-f10ac7eb68e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914764622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1914764622
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.434410357
Short name T330
Test name
Test status
Simulation time 1828138662 ps
CPU time 23.5 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:52:29 PM PDT 24
Peak memory 200296 kb
Host smart-dfc0f7c3-c515-4eae-b560-d3c66fa98ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434410357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.434410357
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1785346713
Short name T327
Test name
Test status
Simulation time 7384758287 ps
CPU time 653.48 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 06:02:59 PM PDT 24
Peak memory 706052 kb
Host smart-8b43acb0-ad1a-4dc7-93b6-33edaca6a5e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785346713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1785346713
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2429659186
Short name T240
Test name
Test status
Simulation time 760397867 ps
CPU time 11.03 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:52:14 PM PDT 24
Peak memory 200168 kb
Host smart-e76f8e5a-6343-4e79-81be-18aaf3e55586
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429659186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2429659186
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4098828498
Short name T129
Test name
Test status
Simulation time 3289354785 ps
CPU time 93.82 seconds
Started Jul 20 05:51:48 PM PDT 24
Finished Jul 20 05:53:22 PM PDT 24
Peak memory 200380 kb
Host smart-98559244-196c-454e-8d1e-2192fcd34d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098828498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4098828498
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1791479684
Short name T233
Test name
Test status
Simulation time 564506696 ps
CPU time 1.37 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 05:51:53 PM PDT 24
Peak memory 200180 kb
Host smart-d7c74273-9e16-47e4-bc80-296702ba2ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791479684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1791479684
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1257239464
Short name T61
Test name
Test status
Simulation time 1071525187294 ps
CPU time 4590.41 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 07:08:34 PM PDT 24
Peak memory 803232 kb
Host smart-c7d1966d-10f4-4d21-bcea-591f98a81c4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257239464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1257239464
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3943171327
Short name T205
Test name
Test status
Simulation time 9375081828 ps
CPU time 126.66 seconds
Started Jul 20 05:51:47 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 200316 kb
Host smart-5cf5994e-65c2-4dd8-9ed9-bf13b51c3336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943171327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3943171327
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2356594606
Short name T354
Test name
Test status
Simulation time 29926782 ps
CPU time 0.58 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:52:06 PM PDT 24
Peak memory 196860 kb
Host smart-0ce97f80-d04c-478a-bb13-200ba318a190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356594606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2356594606
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2108372336
Short name T198
Test name
Test status
Simulation time 54611317 ps
CPU time 2.99 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:52:08 PM PDT 24
Peak memory 200164 kb
Host smart-9c783a2b-6b62-4848-a607-f2ef6bec140d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108372336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2108372336
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.258268257
Short name T37
Test name
Test status
Simulation time 923310973 ps
CPU time 15.03 seconds
Started Jul 20 05:51:52 PM PDT 24
Finished Jul 20 05:52:08 PM PDT 24
Peak memory 200256 kb
Host smart-04b3150f-5e45-4a3f-b236-0786c0559fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258268257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.258268257
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1685872542
Short name T368
Test name
Test status
Simulation time 22425533609 ps
CPU time 1118.88 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 06:10:44 PM PDT 24
Peak memory 769276 kb
Host smart-e7c9b6c7-1f09-4803-a400-6902d20621f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685872542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1685872542
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2058996289
Short name T398
Test name
Test status
Simulation time 2215986632 ps
CPU time 28.77 seconds
Started Jul 20 05:52:11 PM PDT 24
Finished Jul 20 05:52:40 PM PDT 24
Peak memory 200300 kb
Host smart-ca283cd5-97a8-4ac2-9bc6-879e0c4d694a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058996289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2058996289
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.102680867
Short name T485
Test name
Test status
Simulation time 1224178110 ps
CPU time 70.96 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:53:17 PM PDT 24
Peak memory 200316 kb
Host smart-6f9e4f87-3fe3-4522-9816-9ea8f7ff55d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102680867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.102680867
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1005083636
Short name T261
Test name
Test status
Simulation time 188251080 ps
CPU time 3.6 seconds
Started Jul 20 05:52:13 PM PDT 24
Finished Jul 20 05:52:17 PM PDT 24
Peak memory 200256 kb
Host smart-da30173d-36ae-44a8-bbcf-333df8c7bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005083636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1005083636
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2845349108
Short name T382
Test name
Test status
Simulation time 15260979335 ps
CPU time 171.93 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 05:54:53 PM PDT 24
Peak memory 208512 kb
Host smart-aa2df458-ae34-47fd-999e-2d4245a176f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845349108 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2845349108
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1282409863
Short name T8
Test name
Test status
Simulation time 54077839262 ps
CPU time 1345.35 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 06:14:31 PM PDT 24
Peak memory 685872 kb
Host smart-e89cbb98-1e46-4d40-94db-e3fbd1e2cd14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282409863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1282409863
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2698982264
Short name T406
Test name
Test status
Simulation time 1810837066 ps
CPU time 33.54 seconds
Started Jul 20 05:51:54 PM PDT 24
Finished Jul 20 05:52:28 PM PDT 24
Peak memory 200296 kb
Host smart-0524b22b-fb3c-4bca-92cb-aa5ac71d6c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698982264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2698982264
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2607075696
Short name T373
Test name
Test status
Simulation time 14812274 ps
CPU time 0.61 seconds
Started Jul 20 05:51:56 PM PDT 24
Finished Jul 20 05:51:57 PM PDT 24
Peak memory 196864 kb
Host smart-6ed75540-0ea9-446a-ba57-a4a2dd3a185f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607075696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2607075696
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4107875914
Short name T285
Test name
Test status
Simulation time 6603003822 ps
CPU time 95.63 seconds
Started Jul 20 05:51:54 PM PDT 24
Finished Jul 20 05:53:30 PM PDT 24
Peak memory 200300 kb
Host smart-2da5ec5c-74a4-435b-ab6f-bc7b158503bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107875914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4107875914
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1171827515
Short name T290
Test name
Test status
Simulation time 2157024642 ps
CPU time 20.58 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 05:52:20 PM PDT 24
Peak memory 200328 kb
Host smart-c094b11d-edda-4794-9d88-338e90b205e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171827515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1171827515
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1760199295
Short name T190
Test name
Test status
Simulation time 18846311951 ps
CPU time 548.38 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 06:01:09 PM PDT 24
Peak memory 689820 kb
Host smart-83892400-8074-4411-8aa4-26ea989a39be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760199295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1760199295
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1885154334
Short name T464
Test name
Test status
Simulation time 13324406834 ps
CPU time 220.06 seconds
Started Jul 20 05:52:06 PM PDT 24
Finished Jul 20 05:55:48 PM PDT 24
Peak memory 200300 kb
Host smart-62d453ef-ae8f-4ed9-9f81-b6790157fe6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885154334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1885154334
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2881347530
Short name T514
Test name
Test status
Simulation time 2717384153 ps
CPU time 159.21 seconds
Started Jul 20 05:52:05 PM PDT 24
Finished Jul 20 05:54:46 PM PDT 24
Peak memory 200320 kb
Host smart-7e4469de-5b3a-462e-89dc-6bf46066a215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881347530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2881347530
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.373772815
Short name T89
Test name
Test status
Simulation time 1750883846 ps
CPU time 5.73 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:52:07 PM PDT 24
Peak memory 200252 kb
Host smart-32df6ec3-0793-4fa6-a449-3650c4ed6741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373772815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.373772815
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2356448924
Short name T92
Test name
Test status
Simulation time 114655472645 ps
CPU time 2120.14 seconds
Started Jul 20 05:51:55 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 749660 kb
Host smart-ad110fbc-b530-4e24-86ca-76a3dfb1bb71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356448924 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2356448924
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.588523015
Short name T13
Test name
Test status
Simulation time 199556643251 ps
CPU time 570.14 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 06:01:34 PM PDT 24
Peak memory 210136 kb
Host smart-696831b1-843c-43b4-a8ea-262a28d24e9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588523015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.588523015
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2732072546
Short name T55
Test name
Test status
Simulation time 7248674389 ps
CPU time 102.56 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:53:44 PM PDT 24
Peak memory 200320 kb
Host smart-a8a6e7f2-6e27-497d-a30c-51f04b2bc977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732072546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2732072546
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2363057913
Short name T258
Test name
Test status
Simulation time 27482203 ps
CPU time 0.62 seconds
Started Jul 20 05:52:06 PM PDT 24
Finished Jul 20 05:52:08 PM PDT 24
Peak memory 195044 kb
Host smart-d8e5d82d-2d1a-4b71-82b1-25b01d7d2125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363057913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2363057913
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.305031384
Short name T386
Test name
Test status
Simulation time 601984011 ps
CPU time 1.99 seconds
Started Jul 20 05:51:48 PM PDT 24
Finished Jul 20 05:51:51 PM PDT 24
Peak memory 200124 kb
Host smart-7d41ffb6-0d08-4868-a2e1-66cdf1d4d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305031384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.305031384
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3819603059
Short name T392
Test name
Test status
Simulation time 3275350641 ps
CPU time 517.06 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 06:00:43 PM PDT 24
Peak memory 475432 kb
Host smart-b6ad48af-55a2-49c2-9072-4a3ae46d2c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819603059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3819603059
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3213424322
Short name T361
Test name
Test status
Simulation time 26262872819 ps
CPU time 101.18 seconds
Started Jul 20 05:51:52 PM PDT 24
Finished Jul 20 05:53:34 PM PDT 24
Peak memory 200220 kb
Host smart-5ee2ec47-2e24-4e7e-a754-2c6e38e89de0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213424322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3213424322
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3504553329
Short name T453
Test name
Test status
Simulation time 29239517899 ps
CPU time 75.08 seconds
Started Jul 20 05:51:49 PM PDT 24
Finished Jul 20 05:53:05 PM PDT 24
Peak memory 200304 kb
Host smart-fa3c3e05-169d-4ee1-9f6f-848084919a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504553329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3504553329
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.977691718
Short name T281
Test name
Test status
Simulation time 734619333 ps
CPU time 11.43 seconds
Started Jul 20 05:51:59 PM PDT 24
Finished Jul 20 05:52:11 PM PDT 24
Peak memory 200280 kb
Host smart-3bbcf2f2-306d-4cd6-8ec4-3d5cb4c688f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977691718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.977691718
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.753034183
Short name T67
Test name
Test status
Simulation time 106452265657 ps
CPU time 1162.97 seconds
Started Jul 20 05:52:04 PM PDT 24
Finished Jul 20 06:11:30 PM PDT 24
Peak memory 676496 kb
Host smart-a2f99069-69a2-4ab6-927f-5dbe8192b6a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753034183 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.753034183
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.290947525
Short name T24
Test name
Test status
Simulation time 164259629146 ps
CPU time 6393.4 seconds
Started Jul 20 05:51:56 PM PDT 24
Finished Jul 20 07:38:31 PM PDT 24
Peak memory 827452 kb
Host smart-85cb7d59-e7c4-457a-ac9f-92d75b62ef52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290947525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.290947525
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4019932392
Short name T512
Test name
Test status
Simulation time 2059036503 ps
CPU time 29.05 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:52:33 PM PDT 24
Peak memory 200252 kb
Host smart-334aa704-47b9-48fa-bea3-3ff58da97174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019932392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4019932392
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3785548643
Short name T315
Test name
Test status
Simulation time 14335524 ps
CPU time 0.59 seconds
Started Jul 20 05:52:03 PM PDT 24
Finished Jul 20 05:52:06 PM PDT 24
Peak memory 196656 kb
Host smart-f18ea0da-412c-4d5d-8020-5a35a62f601f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785548643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3785548643
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.697201691
Short name T311
Test name
Test status
Simulation time 11228123153 ps
CPU time 88.88 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:53:32 PM PDT 24
Peak memory 216572 kb
Host smart-24243267-8608-4540-bcee-42b56522efed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697201691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.697201691
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2558654059
Short name T525
Test name
Test status
Simulation time 892780473 ps
CPU time 45.51 seconds
Started Jul 20 05:52:02 PM PDT 24
Finished Jul 20 05:52:50 PM PDT 24
Peak memory 200300 kb
Host smart-461aad22-f3df-431e-b5ba-80e020e28c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558654059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2558654059
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4101973431
Short name T340
Test name
Test status
Simulation time 5611003410 ps
CPU time 456.45 seconds
Started Jul 20 05:51:58 PM PDT 24
Finished Jul 20 05:59:35 PM PDT 24
Peak memory 687248 kb
Host smart-e30b9f1a-1a7e-48d8-b378-6b0513f88656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101973431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4101973431
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2313707996
Short name T222
Test name
Test status
Simulation time 5897838794 ps
CPU time 104.1 seconds
Started Jul 20 05:51:51 PM PDT 24
Finished Jul 20 05:53:36 PM PDT 24
Peak memory 200296 kb
Host smart-ce4a50c0-457b-4d4c-88d1-defba152de0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313707996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2313707996
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.864704990
Short name T268
Test name
Test status
Simulation time 41663326404 ps
CPU time 113.21 seconds
Started Jul 20 05:52:08 PM PDT 24
Finished Jul 20 05:54:02 PM PDT 24
Peak memory 200264 kb
Host smart-057c4d6d-934d-48c1-9d72-5e3db5769557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864704990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.864704990
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1209662666
Short name T77
Test name
Test status
Simulation time 1003336035 ps
CPU time 12.94 seconds
Started Jul 20 05:52:05 PM PDT 24
Finished Jul 20 05:52:19 PM PDT 24
Peak memory 200212 kb
Host smart-b77e5060-e3f1-4f30-85e8-921449cd9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209662666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1209662666
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2809937384
Short name T70
Test name
Test status
Simulation time 266928425369 ps
CPU time 1457.69 seconds
Started Jul 20 05:52:05 PM PDT 24
Finished Jul 20 06:16:25 PM PDT 24
Peak memory 689196 kb
Host smart-875b1903-97a3-48bb-b985-6a34f354245d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809937384 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2809937384
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2111993717
Short name T440
Test name
Test status
Simulation time 7052536104 ps
CPU time 91.09 seconds
Started Jul 20 05:52:01 PM PDT 24
Finished Jul 20 05:53:35 PM PDT 24
Peak memory 200260 kb
Host smart-bd18aec9-384a-407f-92e1-57d122c1d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111993717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2111993717
Directory /workspace/9.hmac_wipe_secret/latest
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