Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17590832	1			T1	173134		T2	13820		T3	177035
all_values[1]	17590832	1			T1	173134		T2	13820		T3	177035
all_values[2]	17590832	1			T1	173134		T2	13820		T3	177035

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243894

1

T1

4541

T3

2173

T4

3662

auto[1]

52528602

1

T1

514861

T2

41460

T3

528932

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44940532

1

T1

434300

T2

36389

T3

449171

auto[1]

7831964

1

T1

85102

T2

5071

T3

81934

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98977	1			T1	1		T3	533		T5	3
all_values[0]	auto[0]	auto[1]	340	1			T16	2		T7	4		T115	2
all_values[0]	auto[1]	auto[0]	17472101	1			T1	172992		T2	13800		T3	176324
all_values[0]	auto[1]	auto[1]	19414	1			T1	141		T2	20		T3	178
all_values[1]	auto[0]	auto[0]	65950	1			T3	642		T11	5		T30	1700
all_values[1]	auto[0]	auto[1]	218	1			T11	2		T8	5		T66	1
all_values[1]	auto[1]	auto[0]	17524354	1			T1	173133		T2	13820		T3	176393
all_values[1]	auto[1]	auto[1]	310	1			T1	1		T11	1		T21	1
all_values[2]	auto[0]	auto[0]	36362	1			T1	4327		T3	3		T4	1598
all_values[2]	auto[0]	auto[1]	42047	1			T1	213		T3	995		T4	2064
all_values[2]	auto[1]	auto[0]	9742788	1			T1	83847		T2	8769		T3	95276
all_values[2]	auto[1]	auto[1]	7769635	1			T1	84747		T2	5051		T3	80761