Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

143707

1

T1

970

T2

12

T3

1426

auto[1]

140932

1

T1

332

T2

26

T3

1108

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	110115	1			T1	494		T2	16		T3	932
len_1026_2046	6411	1			T1	6		T3	39		T16	3
len_514_1022	4452	1			T1	95		T2	1		T3	166
len_2_510	4065	1			T1	4		T3	17		T18	1
len_2056	153	1			T1	1		T11	10		T109	3
len_2048	312	1			T1	5		T3	3		T16	1
len_2040	110	1			T1	2		T11	5		T109	2
len_1032	164	1			T1	2		T11	5		T26	6
len_1024	1823	1			T1	7		T3	4		T19	3
len_1016	162	1			T1	2		T3	1		T11	2
len_520	208	1			T1	2		T26	8		T109	3
len_512	308	1			T1	2		T3	6		T19	2
len_504	324	1			T1	1		T11	6		T109	6
len_8	999	1			T1	20		T3	3		T5	9
len_0	12714	1			T1	8		T2	2		T3	96

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

113

1

T3

3

T19

1

T28

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	56428	1			T1	375		T2	4		T3	569
auto[0]	len_1026_2046	3714	1			T1	4		T3	26		T16	3
auto[0]	len_514_1022	2621	1			T1	85		T3	87		T19	4
auto[0]	len_2_510	2826	1			T1	4		T3	9		T19	3
auto[0]	len_2056	89	1			T11	6		T109	2		T123	2
auto[0]	len_2048	167	1			T1	4		T3	3		T19	1
auto[0]	len_2040	65	1			T1	1		T11	3		T123	2
auto[0]	len_1032	90	1			T11	3		T59	1		T66	2
auto[0]	len_1024	263	1			T1	4		T3	2		T19	2
auto[0]	len_1016	85	1			T11	2		T26	1		T30	1
auto[0]	len_520	92	1			T1	2		T26	5		T109	3
auto[0]	len_512	170	1			T1	1		T3	3		T19	1
auto[0]	len_504	119	1			T11	2		T109	5		T59	2
auto[0]	len_8	15	1			T124	1		T125	1		T126	1
auto[0]	len_0	5110	1			T1	5		T2	2		T3	14
auto[1]	len_2050_plus	53687	1			T1	119		T2	12		T3	363
auto[1]	len_1026_2046	2697	1			T1	2		T3	13		T19	4
auto[1]	len_514_1022	1831	1			T1	10		T2	1		T3	79
auto[1]	len_2_510	1239	1			T3	8		T18	1		T19	2
auto[1]	len_2056	64	1			T1	1		T11	4		T109	1
auto[1]	len_2048	145	1			T1	1		T16	1		T11	3
auto[1]	len_2040	45	1			T1	1		T11	2		T109	2
auto[1]	len_1032	74	1			T1	2		T11	2		T26	6
auto[1]	len_1024	1560	1			T1	3		T3	2		T19	1
auto[1]	len_1016	77	1			T1	2		T3	1		T26	7
auto[1]	len_520	116	1			T26	3		T62	5		T67	2
auto[1]	len_512	138	1			T1	1		T3	3		T19	1
auto[1]	len_504	205	1			T1	1		T11	4		T109	1
auto[1]	len_8	984	1			T1	20		T3	3		T5	9
auto[1]	len_0	7604	1			T1	3		T3	82		T4	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

44

1

T3

1

T19

1

T28

1

auto[1]

len_upper

69

1

T3

2

T20

1

T127

2