Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::save_and_restore_cg

Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

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Summary for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	9	0	9	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size_cp	3	0	3	100.00	100	1	1	0
save_and_restore_cp	3	0	3	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sar_type_x_digest_size	9	0	9	100.00	100	1	1	0

Summary for Variable digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for digest_size_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_512	222	1			T1	2		T3	4		T4	1
sha2_384	226	1			T1	1		T3	5		T4	1
sha2_256	174	1			T1	2		T3	3		T11	3

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Summary for Variable save_and_restore_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for save_and_restore_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	215	1			T1	4		T3	4		T4	2
different_context	197	1			T1	1		T3	4		T19	2
same_context	210	1			T3	4		T16	1		T19	1

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Summary for Cross sar_type_x_digest_size

Samples crossed: save_and_restore_cp digest_size_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	9	0	9	100.00

Automatically Generated Cross Bins for sar_type_x_digest_size

Bins

save_and_restore_cp	digest_size_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
stop_and_continue	sha2_512	77	1			T1	2		T3	2		T4	1
stop_and_continue	sha2_384	81	1			T1	1		T3	2		T4	1
stop_and_continue	sha2_256	57	1			T1	1		T31	1		T8	1
different_context	sha2_512	71	1			T3	1		T19	2		T28	2
different_context	sha2_384	68	1			T3	2		T11	2		T31	1
different_context	sha2_256	58	1			T1	1		T3	1		T11	2
same_context	sha2_512	74	1			T3	1		T19	1		T11	1
same_context	sha2_384	77	1			T3	1		T16	1		T11	3
same_context	sha2_256	59	1			T3	2		T11	1		T20	1