Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4525611 1 T1 23958 T2 3724 T3 34465
auto[1] 2819410 1 T1 41664 T2 3113 T3 31790


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2902923 1 T1 36025 T2 3001 T3 38390
auto[1] 4442098 1 T1 29597 T2 3836 T3 27865


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3164364 1 T1 13965 T2 2106 T3 24573
auto[1] 4180657 1 T1 51657 T2 4731 T3 41682


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4490294 1 T1 41418 T2 2479 T3 38187
auto[1] 2854727 1 T1 24204 T2 4358 T3 28068


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6725430 1 T1 64653 T2 6739 T3 65460
fifo_depth[1] 111473 1 T1 596 T2 75 T3 542
fifo_depth[2] 83296 1 T1 269 T2 21 T3 181
fifo_depth[3] 65776 1 T1 53 T2 2 T3 36
fifo_depth[4] 59740 1 T1 42 T3 30 T4 3
fifo_depth[5] 47529 1 T1 2 T3 1 T5 260
fifo_depth[6] 38466 1 T1 4 T3 5 T5 175
fifo_depth[7] 25044 1 T1 2 T5 163 T19 5


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 619591 1 T1 969 T2 98 T3 795
auto[1] 6725430 1 T1 64653 T2 6739 T3 65460


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7333841 1 T1 65622 T2 6837 T3 66255
auto[1] 11180 1 T21 160 T114 3 T128 68


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 22716 1 T3 84 T16 14 T6 84
auto[0] auto[0] auto[0] auto[0] auto[1] 33570 1 T1 5 T2 9 T3 51
auto[0] auto[0] auto[0] auto[1] auto[0] 30341 1 T1 151 T3 22 T4 9
auto[0] auto[0] auto[0] auto[1] auto[1] 30367 1 T3 14 T4 5 T15 19
auto[0] auto[0] auto[1] auto[0] auto[0] 124903 1 T1 53 T2 12 T3 16
auto[0] auto[0] auto[1] auto[0] auto[1] 29230 1 T1 11 T3 63 T4 6
auto[0] auto[0] auto[1] auto[1] auto[0] 25123 1 T1 94 T3 15 T4 44
auto[0] auto[0] auto[1] auto[1] auto[1] 27580 1 T1 43 T2 10 T3 103
auto[0] auto[1] auto[0] auto[0] auto[0] 38413 1 T1 11 T3 63 T5 658
auto[0] auto[1] auto[0] auto[0] auto[1] 34817 1 T1 62 T2 21 T3 55
auto[0] auto[1] auto[0] auto[1] auto[0] 38968 1 T1 174 T3 159 T5 795
auto[0] auto[1] auto[0] auto[1] auto[1] 36893 1 T1 66 T3 28 T4 10
auto[0] auto[1] auto[1] auto[0] auto[0] 44648 1 T1 22 T2 4 T3 11
auto[0] auto[1] auto[1] auto[0] auto[1] 34309 1 T1 82 T2 33 T3 23
auto[0] auto[1] auto[1] auto[1] auto[0] 31585 1 T1 173 T2 7 T3 52
auto[0] auto[1] auto[1] auto[1] auto[1] 36128 1 T1 22 T2 2 T3 36
auto[1] auto[0] auto[0] auto[0] auto[0] 172767 1 T1 1162 T3 4202 T16 217
auto[1] auto[0] auto[0] auto[0] auto[1] 174874 1 T1 199 T2 267 T3 2922
auto[1] auto[0] auto[0] auto[1] auto[0] 179462 1 T1 4189 T2 274 T3 2284
auto[1] auto[0] auto[0] auto[1] auto[1] 166396 1 T1 24 T2 389 T3 2306
auto[1] auto[0] auto[1] auto[0] auto[0] 1608268 1 T1 1998 T2 579 T3 2612
auto[1] auto[0] auto[1] auto[0] auto[1] 176566 1 T1 1241 T2 1 T3 2779
auto[1] auto[0] auto[1] auto[1] auto[0] 171988 1 T1 2609 T2 23 T3 707
auto[1] auto[0] auto[1] auto[1] auto[1] 190213 1 T1 2186 T2 542 T3 6393
auto[1] auto[1] auto[0] auto[0] auto[0] 506383 1 T1 6491 T2 608 T3 6798
auto[1] auto[1] auto[0] auto[0] auto[1] 510880 1 T1 4688 T2 898 T3 7151
auto[1] auto[1] auto[0] auto[1] auto[0] 474603 1 T1 10960 T3 10323 T4 218
auto[1] auto[1] auto[0] auto[1] auto[1] 451473 1 T1 7843 T2 535 T3 1928
auto[1] auto[1] auto[1] auto[0] auto[0] 544795 1 T1 3233 T2 240 T3 5223
auto[1] auto[1] auto[1] auto[0] auto[1] 468472 1 T1 4700 T2 1052 T3 2412
auto[1] auto[1] auto[1] auto[1] auto[0] 475331 1 T1 10098 T2 732 T3 5616
auto[1] auto[1] auto[1] auto[1] auto[1] 452959 1 T1 3032 T2 599 T3 1804


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 195254 1 T1 1162 T3 4286 T16 231
auto[0] auto[0] auto[0] auto[0] auto[1] 207508 1 T1 204 T2 276 T3 2973
auto[0] auto[0] auto[0] auto[1] auto[0] 209247 1 T1 4340 T2 274 T3 2306
auto[0] auto[0] auto[0] auto[1] auto[1] 195782 1 T1 24 T2 389 T3 2320
auto[0] auto[0] auto[1] auto[0] auto[0] 1731958 1 T1 2051 T2 591 T3 2628
auto[0] auto[0] auto[1] auto[0] auto[1] 205271 1 T1 1252 T2 1 T3 2842
auto[0] auto[0] auto[1] auto[1] auto[0] 195370 1 T1 2703 T2 23 T3 722
auto[0] auto[0] auto[1] auto[1] auto[1] 215675 1 T1 2229 T2 552 T3 6496
auto[0] auto[1] auto[0] auto[0] auto[0] 544493 1 T1 6502 T2 608 T3 6861
auto[0] auto[1] auto[0] auto[0] auto[1] 545181 1 T1 4750 T2 919 T3 7206
auto[0] auto[1] auto[0] auto[1] auto[0] 513403 1 T1 11134 T3 10482 T4 218
auto[0] auto[1] auto[0] auto[1] auto[1] 488192 1 T1 7909 T2 535 T3 1956
auto[0] auto[1] auto[1] auto[0] auto[0] 588791 1 T1 3255 T2 244 T3 5234
auto[0] auto[1] auto[1] auto[0] auto[1] 502460 1 T1 4782 T2 1085 T3 2435
auto[0] auto[1] auto[1] auto[1] auto[0] 506506 1 T1 10271 T2 739 T3 5668
auto[0] auto[1] auto[1] auto[1] auto[1] 488750 1 T1 3054 T2 601 T3 1840
auto[1] auto[0] auto[0] auto[0] auto[0] 229 1 T21 42 T128 56 T129 9
auto[1] auto[0] auto[0] auto[0] auto[1] 936 1 T130 61 T129 6 T131 144
auto[1] auto[0] auto[0] auto[1] auto[0] 556 1 T21 9 T81 14 T131 90
auto[1] auto[0] auto[0] auto[1] auto[1] 981 1 T114 3 T81 6 T131 6
auto[1] auto[0] auto[1] auto[0] auto[0] 1213 1 T21 16 T128 12 T130 22
auto[1] auto[0] auto[1] auto[0] auto[1] 525 1 T21 4 T23 5 T24 352
auto[1] auto[0] auto[1] auto[1] auto[0] 1741 1 T21 31 T130 504 T129 245
auto[1] auto[0] auto[1] auto[1] auto[1] 2118 1 T130 44 T132 2 T133 22
auto[1] auto[1] auto[0] auto[0] auto[0] 303 1 T130 32 T129 7 T132 3
auto[1] auto[1] auto[0] auto[0] auto[1] 516 1 T134 1 T135 1 T56 109
auto[1] auto[1] auto[0] auto[1] auto[0] 168 1 T21 58 T130 7 T73 1
auto[1] auto[1] auto[0] auto[1] auto[1] 174 1 T81 17 T23 44 T136 6
auto[1] auto[1] auto[1] auto[0] auto[0] 652 1 T35 364 T131 9 T137 13
auto[1] auto[1] auto[1] auto[0] auto[1] 321 1 T35 4 T131 139 T138 4
auto[1] auto[1] auto[1] auto[1] auto[0] 410 1 T130 22 T133 2 T131 244
auto[1] auto[1] auto[1] auto[1] auto[1] 337 1 T133 106 T35 3 T139 4


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 172767 1 T1 1162 T3 4202 T16 217
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 174874 1 T1 199 T2 267 T3 2922
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 179462 1 T1 4189 T2 274 T3 2284
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 166396 1 T1 24 T2 389 T3 2306
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1608268 1 T1 1998 T2 579 T3 2612
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 176566 1 T1 1241 T2 1 T3 2779
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 171988 1 T1 2609 T2 23 T3 707
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 190213 1 T1 2186 T2 542 T3 6393
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 506383 1 T1 6491 T2 608 T3 6798
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 510880 1 T1 4688 T2 898 T3 7151
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 474603 1 T1 10960 T3 10323 T4 218
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 451473 1 T1 7843 T2 535 T3 1928
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 544795 1 T1 3233 T2 240 T3 5223
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 468472 1 T1 4700 T2 1052 T3 2412
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 475331 1 T1 10098 T2 732 T3 5616
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 452959 1 T1 3032 T2 599 T3 1804
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3627 1 T3 62 T16 8 T6 14
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3151 1 T1 4 T2 8 T3 29
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3330 1 T1 52 T3 7 T4 7
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3585 1 T3 12 T4 3 T15 11
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 37769 1 T1 34 T2 8 T3 11
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 4002 1 T1 5 T3 55 T4 4
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3274 1 T1 61 T3 7 T4 31
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3373 1 T1 21 T2 10 T3 74
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6162 1 T1 6 T3 37 T5 97
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6140 1 T1 34 T2 16 T3 33
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6642 1 T1 125 T3 115 T5 123
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5558 1 T1 43 T3 21 T4 7
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8513 1 T1 19 T2 1 T3 7
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5457 1 T1 58 T2 27 T3 11
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5789 1 T1 122 T2 4 T3 32
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5101 1 T1 12 T2 1 T3 29
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2900 1 T3 19 T16 4 T6 15
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2437 1 T1 1 T2 1 T3 15
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2688 1 T1 55 T3 7 T4 2
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2996 1 T3 1 T4 1 T15 7
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 23481 1 T1 15 T2 4 T3 2
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3209 1 T1 4 T3 6 T4 1
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2688 1 T1 25 T3 3 T4 11
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2630 1 T1 10 T3 24 T4 7
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 4965 1 T1 3 T3 22 T5 96
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4882 1 T1 22 T2 4 T3 18
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5419 1 T1 43 T3 34 T5 121
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4704 1 T1 19 T3 5 T4 2
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6725 1 T1 3 T2 3 T3 1
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4550 1 T1 18 T2 6 T3 7
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4735 1 T1 44 T2 3 T3 17
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4287 1 T1 7 T5 19 T16 3
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2513 1 T3 1 T16 2 T6 15
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1991 1 T3 4 T16 5 T6 41
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2048 1 T1 10 T3 1 T15 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2128 1 T3 1 T15 1 T6 2
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 16631 1 T1 3 T3 3 T4 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2532 1 T1 2 T3 2 T4 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1890 1 T1 8 T3 3 T4 2
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2059 1 T1 1 T3 4 T11 3
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4161 1 T1 2 T5 103 T19 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4190 1 T1 4 T2 1 T3 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4579 1 T1 5 T3 8 T5 119
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4056 1 T1 4 T3 2 T4 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5674 1 T3 3 T140 3 T108 38
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3929 1 T1 6 T4 5 T6 38
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 3858 1 T1 5 T3 2 T5 37
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3537 1 T1 3 T2 1 T3 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2446 1 T3 1 T6 15 T115 2
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1991 1 T3 3 T16 1 T19 2
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2190 1 T1 33 T3 7 T6 14
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2363 1 T4 1 T6 5 T11 3
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 12141 1 T1 1 T4 2 T108 16
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2359 1 T19 4 T6 5 T108 24
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1815 1 T3 1 T19 6 T108 10
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2067 1 T1 4 T3 1 T11 2
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4087 1 T3 3 T5 94 T11 3
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3963 1 T1 1 T3 2 T16 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4393 1 T1 1 T3 1 T5 111
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3743 1 T16 1 T19 23 T6 14
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5196 1 T108 35 T11 7 T27 109
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3705 1 T3 4 T6 34 T108 22
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3655 1 T1 2 T3 1 T5 29
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3626 1 T3 6 T5 24 T6 23
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1880 1 T6 10 T11 8 T21 17
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1679 1 T16 1 T6 28 T11 2
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1581 1 T6 17 T108 16 T11 16
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1617 1 T6 6 T11 1 T28 4
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 8832 1 T108 10 T11 8 T31 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1809 1 T19 3 T6 3 T108 27
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1461 1 T19 4 T108 11 T11 22
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1618 1 T1 1 T11 1 T28 10
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3472 1 T5 86 T28 2 T21 5
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3447 1 T1 1 T6 14 T108 9
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3697 1 T3 1 T5 125 T11 32
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3253 1 T19 1 T6 13 T108 2
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4220 1 T108 32 T11 6 T27 69
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3156 1 T6 27 T115 1 T108 16
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 2955 1 T5 22 T108 17 T21 40
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 2852 1 T5 27 T6 13 T108 32
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1482 1 T3 1 T6 12 T108 2
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1355 1 T19 3 T6 17 T28 3
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1441 1 T1 1 T6 12 T108 7
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1565 1 T6 1 T11 1 T28 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6441 1 T108 8 T11 11 T21 13
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1470 1 T19 2 T6 3 T108 22
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1228 1 T3 1 T19 3 T108 10
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1324 1 T1 3 T11 2 T28 5
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2723 1 T3 1 T5 58 T11 2
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2813 1 T3 1 T6 15 T108 5
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2986 1 T5 75 T11 37 T21 13
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2750 1 T19 21 T6 10 T108 2
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3424 1 T108 24 T11 3 T27 31
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2584 1 T3 1 T6 34 T108 11
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2346 1 T5 13 T108 11 T21 42
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2534 1 T5 29 T6 6 T108 20
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 901 1 T6 1 T108 1 T11 4
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 958 1 T6 11 T21 6 T109 40
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 873 1 T6 14 T108 10 T11 8
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1057 1 T6 8 T28 2 T21 3
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 3785 1 T108 6 T11 6 T21 12
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 935 1 T19 2 T6 3 T108 13
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 844 1 T19 1 T108 6 T11 8
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 839 1 T1 2 T141 1 T109 54
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1905 1 T5 66 T11 1 T28 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1911 1 T6 7 T108 6 T21 10
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1945 1 T5 69 T11 21 T21 21
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1859 1 T19 2 T6 13 T108 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2278 1 T108 28 T11 3 T27 3
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1803 1 T6 26 T108 8 T11 33
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1551 1 T5 7 T108 4 T21 40
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1600 1 T5 21 T6 6 T108 18

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