Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17590832	1			T1	173134		T2	13820		T3	177035
all_pins[1]	17590832	1			T1	173134		T2	13820		T3	177035
all_pins[2]	17590832	1			T1	173134		T2	13820		T3	177035

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44982298	1			T1	434507		T2	36388		T3	450156
values[0x1]	7790198	1			T1	84895		T2	5072		T3	80949
transitions[0x0=>0x1]	7790025	1			T1	84895		T2	5072		T3	80948
transitions[0x1=>0x0]	7790035	1			T1	84895		T2	5072		T3	80948

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17570594	1			T1	172987		T2	13799		T3	176847
all_pins[0]	values[0x1]	20238	1			T1	147		T2	21		T3	188
all_pins[0]	transitions[0x0=>0x1]	20170	1			T1	147		T2	21		T3	187
all_pins[0]	transitions[0x1=>0x0]	7769577	1			T1	84747		T2	5051		T3	80760
all_pins[1]	values[0x0]	17590507	1			T1	173133		T2	13820		T3	177035
all_pins[1]	values[0x1]	325	1			T1	1		T11	1		T21	2
all_pins[1]	transitions[0x0=>0x1]	273	1			T1	1		T21	2		T8	7
all_pins[1]	transitions[0x1=>0x0]	20186	1			T1	147		T2	21		T3	188
all_pins[2]	values[0x0]	9821197	1			T1	88387		T2	8769		T3	96274
all_pins[2]	values[0x1]	7769635	1			T1	84747		T2	5051		T3	80761
all_pins[2]	transitions[0x0=>0x1]	7769582	1			T1	84747		T2	5051		T3	80761
all_pins[2]	transitions[0x1=>0x0]	272	1			T1	1		T21	2		T8	4