Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1041 1 T1 4 T11 10 T8 17
all_values[1] 1041 1 T1 4 T11 10 T8 17
all_values[2] 1041 1 T1 4 T11 10 T8 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1527 1 T1 3 T11 12 T8 22
auto[1] 1596 1 T1 9 T11 18 T8 29


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1139 1 T1 8 T11 7 T8 14
auto[1] 1984 1 T1 4 T11 23 T8 37


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1810 1 T1 10 T11 14 T8 23
auto[1] 1313 1 T1 2 T11 16 T8 28


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 207 1 T1 1 T8 4 T66 2
all_values[0] auto[0] auto[0] auto[1] 102 1 T8 1 T66 1 T67 1
all_values[0] auto[0] auto[1] auto[0] 197 1 T1 1 T11 1 T8 4
all_values[0] auto[0] auto[1] auto[1] 117 1 T1 1 T8 1 T66 2
all_values[0] auto[1] auto[0] auto[1] 203 1 T11 2 T8 1 T67 5
all_values[0] auto[1] auto[1] auto[1] 215 1 T1 1 T11 7 T8 6
all_values[1] auto[0] auto[0] auto[0] 167 1 T11 3 T8 2 T67 6
all_values[1] auto[0] auto[0] auto[1] 118 1 T11 2 T8 3 T66 2
all_values[1] auto[0] auto[1] auto[0] 174 1 T1 2 T11 1 T67 5
all_values[1] auto[0] auto[1] auto[1] 136 1 T1 1 T11 1 T66 1
all_values[1] auto[1] auto[0] auto[1] 209 1 T11 2 T8 6 T66 2
all_values[1] auto[1] auto[1] auto[1] 237 1 T1 1 T11 1 T8 6
all_values[2] auto[0] auto[0] auto[0] 198 1 T1 2 T11 2 T8 1
all_values[2] auto[0] auto[0] auto[1] 94 1 T66 1 T67 4 T111 1
all_values[2] auto[0] auto[1] auto[0] 196 1 T1 2 T8 3 T67 9
all_values[2] auto[0] auto[1] auto[1] 104 1 T11 4 T8 4 T67 1
all_values[2] auto[1] auto[0] auto[1] 229 1 T11 1 T8 4 T66 1
all_values[2] auto[1] auto[1] auto[1] 220 1 T11 3 T8 5 T66 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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