Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4197	1			T1	58		T2	3		T3	61
sha2_none	4291	1			T1	43		T2	3		T3	41
sha2_512	7514	1			T1	54		T2	5		T3	62
sha2_384	7016	1			T1	46		T2	7		T3	59
sha2_256	6209	1			T1	48		T2	9		T3	76

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18290

1

T1

119

T2

15

T3

160

auto[1]

11326

1

T1

136

T2

12

T3

144

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11242

1

T1

120

T2

10

T3

166

auto[1]

18374

1

T1

135

T2

17

T3

138

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15499

1

T1

138

T2

18

T3

161

disabled

14117

1

T1

117

T2

9

T3

143

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4545	1			T1	50		T2	3		T3	58
key_none	7404	1			T1	39		T2	5		T3	41
key_1024	4348	1			T1	33		T2	2		T3	39
key_512	3732	1			T1	37		T2	5		T3	46
key_384	3429	1			T1	33		T2	5		T3	41
key_256	3133	1			T1	37		T2	4		T3	34
key_128	2932	1			T1	25		T2	3		T3	43

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18486

1

T1

150

T2

10

T3

148

auto[1]

11130

1

T1

105

T2

17

T3

156

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29444

1

T1

252

T2

27

T3

301

disabled

172

1

T1

3

T3

3

T11

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1603

1

T1

17

T2

2

T3

19

enabled

auto[0]

auto[0]

auto[1]

1571

1

T1

14

T2

3

T3

26

enabled

auto[0]

auto[1]

auto[0]

1678

1

T1

22

T3

26

T4

1

enabled

auto[0]

auto[1]

auto[1]

1529

1

T1

13

T2

2

T3

19

enabled

auto[1]

auto[0]

auto[0]

4279

1

T1

18

T2

2

T3

20

enabled

auto[1]

auto[0]

auto[1]

1590

1

T1

18

T2

4

T3

17

enabled

auto[1]

auto[1]

auto[0]

1672

1

T1

23

T2

2

T3

18

enabled

auto[1]

auto[1]

auto[1]

1577

1

T1

13

T2

3

T3

16

disabled

auto[0]

auto[0]

auto[0]

1174

1

T1

12

T3

21

T16

1

disabled

auto[0]

auto[0]

auto[1]

1263

1

T1

11

T2

1

T3

22

disabled

auto[0]

auto[1]

auto[0]

1234

1

T1

23

T2

1

T3

14

disabled

auto[0]

auto[1]

auto[1]

1190

1

T1

8

T2

1

T3

19

disabled

auto[1]

auto[0]

auto[0]

5619

1

T1

17

T2

2

T3

14

disabled

auto[1]

auto[0]

auto[1]

1191

1

T1

12

T2

1

T3

21

disabled

auto[1]

auto[1]

auto[0]

1227

1

T1

18

T2

1

T3

16

disabled

auto[1]

auto[1]

auto[1]

1219

1

T1

16

T2

2

T3

16

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15434

1

T1

138

T2

18

T3

160

enabled

disabled

65

1

T3

1

T11

1

T109

1

disabled

disabled

107

1

T1

3

T3

2

T11

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14010

1

T1

114

T2

9

T3

141

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1077	1			T1	15		T2	1		T3	13
key_invalid	sha2_none	857	1			T1	14		T3	7		T4	1
key_invalid	sha2_512	865	1			T1	9		T2	1		T3	14
key_invalid	sha2_384	833	1			T1	6		T3	5		T4	4
key_invalid	sha2_256	822	1			T1	5		T2	1		T3	17
key_none	sha2_invalid	520	1			T1	6		T2	1		T3	7
key_none	sha2_none	554	1			T1	4		T2	1		T3	4
key_none	sha2_512	2526	1			T1	11		T3	9		T4	1
key_none	sha2_384	2150	1			T1	9		T2	2		T3	9
key_none	sha2_256	1604	1			T1	7		T2	1		T3	11
key_1024	sha2_invalid	535	1			T1	7		T3	8		T19	2
key_1024	sha2_none	566	1			T1	5		T3	5		T5	1
key_1024	sha2_512	1734	1			T1	8		T3	9		T4	1
key_1024	sha2_384	927	1			T1	6		T3	9		T4	2
key_512	sha2_invalid	524	1			T1	15		T3	6		T4	1
key_512	sha2_none	576	1			T1	2		T3	7		T5	2
key_512	sha2_512	573	1			T1	6		T2	1		T3	10
key_512	sha2_384	1209	1			T1	5		T2	1		T3	11
key_512	sha2_256	802	1			T1	9		T2	3		T3	12
key_384	sha2_invalid	534	1			T1	7		T3	9		T4	1
key_384	sha2_none	594	1			T1	6		T3	7		T4	1
key_384	sha2_512	591	1			T1	6		T2	2		T3	9
key_384	sha2_384	585	1			T1	6		T2	2		T3	10
key_384	sha2_256	1067	1			T1	8		T2	1		T3	6
key_256	sha2_invalid	467	1			T1	3		T2	1		T3	6
key_256	sha2_none	586	1			T1	6		T2	1		T3	6
key_256	sha2_512	629	1			T1	10		T2	1		T3	3
key_256	sha2_384	652	1			T1	9		T3	10		T4	1
key_256	sha2_256	742	1			T1	8		T2	1		T3	7
key_128	sha2_invalid	515	1			T1	4		T3	12		T4	1
key_128	sha2_none	544	1			T1	6		T2	1		T3	5
key_128	sha2_512	577	1			T1	4		T3	8		T15	2
key_128	sha2_384	639	1			T1	5		T2	2		T3	4
key_128	sha2_256	614	1			T1	4		T3	14		T4	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

545

1

T1

7

T2

2

T3

8

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1077	1			T1	15		T2	1		T3	13
key_invalid	sha2_none	857	1			T1	14		T3	7		T4	1
key_invalid	sha2_512	865	1			T1	9		T2	1		T3	14
key_invalid	sha2_384	833	1			T1	6		T3	5		T4	4
key_invalid	sha2_256	822	1			T1	5		T2	1		T3	17
key_none	sha2_invalid	520	1			T1	6		T2	1		T3	7
key_none	sha2_none	554	1			T1	4		T2	1		T3	4
key_none	sha2_512	2526	1			T1	11		T3	9		T4	1
key_none	sha2_384	2150	1			T1	9		T2	2		T3	9
key_none	sha2_256	1604	1			T1	7		T2	1		T3	11
key_1024	sha2_invalid	535	1			T1	7		T3	8		T19	2
key_1024	sha2_none	566	1			T1	5		T3	5		T5	1
key_1024	sha2_512	1734	1			T1	8		T3	9		T4	1
key_1024	sha2_384	927	1			T1	6		T3	9		T4	2
key_1024	sha2_256	545	1			T1	7		T2	2		T3	8
key_512	sha2_invalid	524	1			T1	15		T3	6		T4	1
key_512	sha2_none	576	1			T1	2		T3	7		T5	2
key_512	sha2_512	573	1			T1	6		T2	1		T3	10
key_512	sha2_384	1209	1			T1	5		T2	1		T3	11
key_512	sha2_256	802	1			T1	9		T2	3		T3	12
key_384	sha2_invalid	534	1			T1	7		T3	9		T4	1
key_384	sha2_none	594	1			T1	6		T3	7		T4	1
key_384	sha2_512	591	1			T1	6		T2	2		T3	9
key_384	sha2_384	585	1			T1	6		T2	2		T3	10
key_384	sha2_256	1067	1			T1	8		T2	1		T3	6
key_256	sha2_invalid	467	1			T1	3		T2	1		T3	6
key_256	sha2_none	586	1			T1	6		T2	1		T3	6
key_256	sha2_512	629	1			T1	10		T2	1		T3	3
key_256	sha2_384	652	1			T1	9		T3	10		T4	1
key_256	sha2_256	742	1			T1	8		T2	1		T3	7
key_128	sha2_invalid	515	1			T1	4		T3	12		T4	1
key_128	sha2_none	544	1			T1	6		T2	1		T3	5
key_128	sha2_512	577	1			T1	4		T3	8		T15	2
key_128	sha2_384	639	1			T1	5		T2	2		T3	4
key_128	sha2_256	614	1			T1	4		T3	14		T4	1