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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 658
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T528 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1670655603 Jul 21 05:04:51 PM PDT 24 Jul 21 05:04:53 PM PDT 24 13135179 ps
T529 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3492873068 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:34 PM PDT 24 41365409 ps
T530 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2607380514 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:31 PM PDT 24 50455879 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1726636769 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:29 PM PDT 24 1506156913 ps
T52 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.467937185 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:37 PM PDT 24 448296585 ps
T531 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1825114703 Jul 21 05:04:49 PM PDT 24 Jul 21 05:04:50 PM PDT 24 50849735 ps
T91 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3509806131 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:31 PM PDT 24 27984731 ps
T53 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.584604227 Jul 21 05:04:44 PM PDT 24 Jul 21 05:04:49 PM PDT 24 909256603 ps
T102 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.116443495 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:29 PM PDT 24 21233026 ps
T532 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3032744194 Jul 21 05:04:41 PM PDT 24 Jul 21 05:04:43 PM PDT 24 63088959 ps
T98 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3447576172 Jul 21 05:04:29 PM PDT 24 Jul 21 05:04:44 PM PDT 24 324342384 ps
T533 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3927264961 Jul 21 05:04:37 PM PDT 24 Jul 21 05:04:41 PM PDT 24 169831311 ps
T534 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1477395412 Jul 21 05:04:57 PM PDT 24 Jul 21 05:04:58 PM PDT 24 13636882 ps
T92 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1712145957 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:39 PM PDT 24 61292992 ps
T535 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1854385573 Jul 21 05:04:43 PM PDT 24 Jul 21 05:04:44 PM PDT 24 12813099 ps
T103 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.897622115 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:40 PM PDT 24 86447852 ps
T536 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1022801204 Jul 21 05:04:54 PM PDT 24 Jul 21 05:04:56 PM PDT 24 16271593 ps
T104 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1035908494 Jul 21 05:04:19 PM PDT 24 Jul 21 05:04:21 PM PDT 24 61551980 ps
T93 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3920484263 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:28 PM PDT 24 31101329 ps
T537 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1817343346 Jul 21 05:04:16 PM PDT 24 Jul 21 05:04:18 PM PDT 24 56193606 ps
T105 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2340884521 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:29 PM PDT 24 82422019 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2631094315 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:42 PM PDT 24 1396009928 ps
T538 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1013656358 Jul 21 05:04:44 PM PDT 24 Jul 21 05:04:47 PM PDT 24 295922501 ps
T120 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2047535410 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:43 PM PDT 24 230251254 ps
T539 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3411676770 Jul 21 05:04:37 PM PDT 24 Jul 21 05:04:41 PM PDT 24 143374536 ps
T94 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3321409935 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:40 PM PDT 24 29722986 ps
T106 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3241994256 Jul 21 05:04:36 PM PDT 24 Jul 21 05:04:39 PM PDT 24 152749987 ps
T540 /workspace/coverage/cover_reg_top/32.hmac_intr_test.995702362 Jul 21 05:04:51 PM PDT 24 Jul 21 05:04:53 PM PDT 24 13798711 ps
T119 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.679803627 Jul 21 05:04:46 PM PDT 24 Jul 21 05:04:51 PM PDT 24 1083613189 ps
T541 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1289020064 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:28 PM PDT 24 23134943 ps
T542 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.762266738 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:35 PM PDT 24 41663319 ps
T543 /workspace/coverage/cover_reg_top/4.hmac_intr_test.264793661 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:36 PM PDT 24 14543989 ps
T544 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1055372899 Jul 21 05:04:29 PM PDT 24 Jul 21 05:04:40 PM PDT 24 713480661 ps
T545 /workspace/coverage/cover_reg_top/48.hmac_intr_test.169098872 Jul 21 05:05:01 PM PDT 24 Jul 21 05:05:02 PM PDT 24 37828235 ps
T95 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3997087018 Jul 21 05:04:43 PM PDT 24 Jul 21 05:04:44 PM PDT 24 38980716 ps
T546 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.628089172 Jul 21 05:04:31 PM PDT 24 Jul 21 05:04:42 PM PDT 24 882524625 ps
T96 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3473970415 Jul 21 05:04:29 PM PDT 24 Jul 21 05:04:38 PM PDT 24 509735409 ps
T547 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2656412799 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:27 PM PDT 24 114992105 ps
T548 /workspace/coverage/cover_reg_top/24.hmac_intr_test.683259506 Jul 21 05:04:54 PM PDT 24 Jul 21 05:04:55 PM PDT 24 73116694 ps
T107 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3485198083 Jul 21 05:04:40 PM PDT 24 Jul 21 05:04:42 PM PDT 24 61052804 ps
T549 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3911367322 Jul 21 05:04:31 PM PDT 24 Jul 21 05:04:33 PM PDT 24 42906175 ps
T97 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.547131759 Jul 21 05:04:42 PM PDT 24 Jul 21 05:04:43 PM PDT 24 68799148 ps
T100 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.638498744 Jul 21 05:04:36 PM PDT 24 Jul 21 05:04:37 PM PDT 24 157828116 ps
T116 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1846194031 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:43 PM PDT 24 907685696 ps
T550 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3505606136 Jul 21 05:04:43 PM PDT 24 Jul 21 05:04:47 PM PDT 24 870584256 ps
T551 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2762781553 Jul 21 05:04:42 PM PDT 24 Jul 21 05:04:45 PM PDT 24 256335494 ps
T117 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1473574663 Jul 21 05:04:37 PM PDT 24 Jul 21 05:04:39 PM PDT 24 327626801 ps
T552 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1214022901 Jul 21 05:04:31 PM PDT 24 Jul 21 05:04:32 PM PDT 24 33145351 ps
T553 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1770536369 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:37 PM PDT 24 147356953 ps
T554 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4288366880 Jul 21 05:04:43 PM PDT 24 Jul 21 05:04:45 PM PDT 24 33275894 ps
T555 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1902049654 Jul 21 05:04:53 PM PDT 24 Jul 21 05:04:54 PM PDT 24 15258636 ps
T556 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3269274224 Jul 21 05:04:53 PM PDT 24 Jul 21 05:04:55 PM PDT 24 12897182 ps
T557 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2448214583 Jul 21 05:04:47 PM PDT 24 Jul 21 05:04:48 PM PDT 24 106292598 ps
T558 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4028636585 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:28 PM PDT 24 47739797 ps
T559 /workspace/coverage/cover_reg_top/9.hmac_intr_test.656010164 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:33 PM PDT 24 27290916 ps
T560 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2016799755 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:29 PM PDT 24 217099569 ps
T561 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.683613026 Jul 21 05:04:49 PM PDT 24 Jul 21 05:04:50 PM PDT 24 23039057 ps
T562 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1832114845 Jul 21 05:04:37 PM PDT 24 Jul 21 05:04:41 PM PDT 24 112900240 ps
T563 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3906806561 Jul 21 05:04:17 PM PDT 24 Jul 21 05:04:22 PM PDT 24 305770792 ps
T118 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.932882804 Jul 21 05:04:31 PM PDT 24 Jul 21 05:04:36 PM PDT 24 4255859482 ps
T564 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.65124057 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:35 PM PDT 24 34048637 ps
T565 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2951781955 Jul 21 05:04:37 PM PDT 24 Jul 21 05:04:38 PM PDT 24 14068890 ps
T101 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1524796904 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:39 PM PDT 24 47295206 ps
T566 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2784035850 Jul 21 05:04:43 PM PDT 24 Jul 21 05:04:48 PM PDT 24 227675403 ps
T121 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.840446359 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:43 PM PDT 24 2431076061 ps
T567 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.575981743 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:38 PM PDT 24 870514471 ps
T568 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2397164858 Jul 21 05:04:33 PM PDT 24 Jul 21 05:04:35 PM PDT 24 25802410 ps
T569 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3321605027 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:29 PM PDT 24 734412491 ps
T570 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.669270956 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:28 PM PDT 24 203737033 ps
T571 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1553427965 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:35 PM PDT 24 266112114 ps
T572 /workspace/coverage/cover_reg_top/29.hmac_intr_test.173454509 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:51 PM PDT 24 12496150 ps
T573 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1444483007 Jul 21 05:04:38 PM PDT 24 Jul 21 05:04:42 PM PDT 24 55391321 ps
T574 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1177489081 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:35 PM PDT 24 456176888 ps
T575 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3095391774 Jul 21 05:04:33 PM PDT 24 Jul 21 05:04:34 PM PDT 24 15305430 ps
T576 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3968944959 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:32 PM PDT 24 64189937 ps
T577 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1418752192 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:33 PM PDT 24 46992602 ps
T578 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1252159462 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:30 PM PDT 24 69928640 ps
T579 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1482022638 Jul 21 05:04:45 PM PDT 24 Jul 21 05:04:48 PM PDT 24 140712063 ps
T580 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3359878424 Jul 21 05:04:46 PM PDT 24 Jul 21 05:04:48 PM PDT 24 13015781 ps
T581 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4179772478 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:27 PM PDT 24 13596047 ps
T582 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2533428914 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:35 PM PDT 24 71949030 ps
T583 /workspace/coverage/cover_reg_top/47.hmac_intr_test.705177062 Jul 21 05:04:57 PM PDT 24 Jul 21 05:04:59 PM PDT 24 11944617 ps
T584 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2935735641 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:38 PM PDT 24 290632964 ps
T585 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2104461073 Jul 21 05:04:44 PM PDT 24 Jul 21 05:15:40 PM PDT 24 49225927953 ps
T586 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4238171789 Jul 21 05:04:42 PM PDT 24 Jul 21 05:04:45 PM PDT 24 149520649 ps
T587 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.988462486 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:37 PM PDT 24 424759832 ps
T588 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3123031413 Jul 21 05:04:52 PM PDT 24 Jul 21 05:04:54 PM PDT 24 38890359 ps
T589 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1825481158 Jul 21 05:04:39 PM PDT 24 Jul 21 05:04:41 PM PDT 24 35286968 ps
T590 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2601142397 Jul 21 05:04:40 PM PDT 24 Jul 21 05:04:45 PM PDT 24 228432098 ps
T591 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1289100366 Jul 21 05:04:37 PM PDT 24 Jul 21 05:28:35 PM PDT 24 157128486980 ps
T592 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2130202972 Jul 21 05:04:52 PM PDT 24 Jul 21 05:04:54 PM PDT 24 14818643 ps
T593 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3472052046 Jul 21 05:04:54 PM PDT 24 Jul 21 05:04:55 PM PDT 24 142944642 ps
T594 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2246588361 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:52 PM PDT 24 68170677 ps
T595 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2947687810 Jul 21 05:04:35 PM PDT 24 Jul 21 05:04:37 PM PDT 24 66186013 ps
T596 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1395566289 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:27 PM PDT 24 81539447 ps
T597 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3876923908 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:27 PM PDT 24 85069369 ps
T598 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4094043027 Jul 21 05:04:56 PM PDT 24 Jul 21 05:04:57 PM PDT 24 29136292 ps
T599 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1795175029 Jul 21 05:04:31 PM PDT 24 Jul 21 05:04:35 PM PDT 24 58135448 ps
T600 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3529804506 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:33 PM PDT 24 38583382 ps
T601 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1825448612 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:53 PM PDT 24 356058282 ps
T602 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3968366140 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:39 PM PDT 24 587363483 ps
T603 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1393360481 Jul 21 05:04:59 PM PDT 24 Jul 21 05:05:00 PM PDT 24 17732719 ps
T604 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2159522106 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:27 PM PDT 24 56294976 ps
T605 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3632307158 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:27 PM PDT 24 26733117 ps
T606 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.629799963 Jul 21 05:04:51 PM PDT 24 Jul 21 05:04:54 PM PDT 24 175666164 ps
T607 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.765935893 Jul 21 05:04:35 PM PDT 24 Jul 21 05:04:36 PM PDT 24 45340754 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2984266002 Jul 21 05:04:17 PM PDT 24 Jul 21 05:04:18 PM PDT 24 21638955 ps
T609 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3177078280 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:37 PM PDT 24 54974945 ps
T610 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1661775427 Jul 21 05:04:37 PM PDT 24 Jul 21 05:04:38 PM PDT 24 14026010 ps
T611 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1109831594 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:28 PM PDT 24 23869823 ps
T612 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1802241851 Jul 21 05:04:37 PM PDT 24 Jul 21 05:04:42 PM PDT 24 509757124 ps
T122 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1205401684 Jul 21 05:04:49 PM PDT 24 Jul 21 05:04:52 PM PDT 24 93144698 ps
T613 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4268203404 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:34 PM PDT 24 323687259 ps
T614 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3854755096 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:31 PM PDT 24 610750973 ps
T615 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.957960932 Jul 21 05:04:35 PM PDT 24 Jul 21 05:04:37 PM PDT 24 211787194 ps
T616 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1833292535 Jul 21 05:04:44 PM PDT 24 Jul 21 05:04:47 PM PDT 24 258864968 ps
T617 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1968151303 Jul 21 05:04:49 PM PDT 24 Jul 21 05:04:50 PM PDT 24 52850586 ps
T618 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1072341165 Jul 21 05:04:43 PM PDT 24 Jul 21 05:04:44 PM PDT 24 45207251 ps
T619 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3021999219 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:32 PM PDT 24 11828945 ps
T620 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1433030358 Jul 21 05:04:53 PM PDT 24 Jul 21 05:04:55 PM PDT 24 61144806 ps
T621 /workspace/coverage/cover_reg_top/31.hmac_intr_test.4262771174 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:52 PM PDT 24 17206373 ps
T622 /workspace/coverage/cover_reg_top/23.hmac_intr_test.456560634 Jul 21 05:04:51 PM PDT 24 Jul 21 05:04:53 PM PDT 24 14928485 ps
T623 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.635701366 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:35 PM PDT 24 247766140 ps
T624 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4182111047 Jul 21 05:04:44 PM PDT 24 Jul 21 05:07:41 PM PDT 24 18244836624 ps
T625 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2900425270 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:28 PM PDT 24 422104960 ps
T626 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2804097089 Jul 21 05:04:36 PM PDT 24 Jul 21 05:13:39 PM PDT 24 234688393701 ps
T627 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1460767336 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:52 PM PDT 24 23755718 ps
T628 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4022850414 Jul 21 05:04:42 PM PDT 24 Jul 21 05:04:44 PM PDT 24 13332640 ps
T629 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2342155635 Jul 21 05:04:31 PM PDT 24 Jul 21 05:04:32 PM PDT 24 38379349 ps
T630 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.631647836 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:34 PM PDT 24 314984554 ps
T631 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1055941484 Jul 21 05:04:51 PM PDT 24 Jul 21 05:04:52 PM PDT 24 13586895 ps
T632 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2308917563 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:52 PM PDT 24 32082880 ps
T633 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3675206793 Jul 21 05:04:43 PM PDT 24 Jul 21 05:04:46 PM PDT 24 205061026 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3040126313 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:29 PM PDT 24 79814396 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1753053404 Jul 21 05:04:27 PM PDT 24 Jul 21 05:04:29 PM PDT 24 28861633 ps
T636 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.694737385 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:35 PM PDT 24 53175002 ps
T637 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2428060178 Jul 21 05:04:46 PM PDT 24 Jul 21 05:04:48 PM PDT 24 33785647 ps
T638 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1249127274 Jul 21 05:04:54 PM PDT 24 Jul 21 05:04:55 PM PDT 24 12478140 ps
T639 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3685507071 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:35 PM PDT 24 16161715 ps
T640 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1773929253 Jul 21 05:04:44 PM PDT 24 Jul 21 05:04:49 PM PDT 24 277503946 ps
T641 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2275172275 Jul 21 05:04:26 PM PDT 24 Jul 21 05:04:27 PM PDT 24 21417749 ps
T642 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3493359927 Jul 21 05:04:44 PM PDT 24 Jul 21 05:04:46 PM PDT 24 16747503 ps
T643 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.412216700 Jul 21 05:04:36 PM PDT 24 Jul 21 05:04:39 PM PDT 24 285948918 ps
T644 /workspace/coverage/cover_reg_top/46.hmac_intr_test.491658688 Jul 21 05:05:01 PM PDT 24 Jul 21 05:05:02 PM PDT 24 34046899 ps
T645 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3880911948 Jul 21 05:04:34 PM PDT 24 Jul 21 05:04:36 PM PDT 24 255941691 ps
T646 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1980265176 Jul 21 05:04:25 PM PDT 24 Jul 21 05:04:26 PM PDT 24 93411631 ps
T647 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3830375125 Jul 21 05:04:33 PM PDT 24 Jul 21 05:04:34 PM PDT 24 58172093 ps
T648 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2018059018 Jul 21 05:04:39 PM PDT 24 Jul 21 05:04:40 PM PDT 24 28254816 ps
T649 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1905195565 Jul 21 05:04:36 PM PDT 24 Jul 21 05:04:39 PM PDT 24 85509287 ps
T650 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2084923901 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:52 PM PDT 24 63331606 ps
T651 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1041242763 Jul 21 05:04:50 PM PDT 24 Jul 21 05:04:52 PM PDT 24 102880968 ps
T652 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2297998390 Jul 21 05:04:29 PM PDT 24 Jul 21 05:04:34 PM PDT 24 73028458 ps
T653 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1562519673 Jul 21 05:04:28 PM PDT 24 Jul 21 05:04:31 PM PDT 24 169123312 ps
T654 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2278134515 Jul 21 05:04:45 PM PDT 24 Jul 21 05:04:47 PM PDT 24 158169416 ps
T655 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2541897720 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:31 PM PDT 24 82960178 ps
T656 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3232444209 Jul 21 05:04:32 PM PDT 24 Jul 21 05:04:33 PM PDT 24 38075373 ps
T657 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2478834232 Jul 21 05:04:30 PM PDT 24 Jul 21 05:04:32 PM PDT 24 195456108 ps
T658 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1839186043 Jul 21 05:04:33 PM PDT 24 Jul 21 05:04:36 PM PDT 24 620851374 ps

Test location /workspace/coverage/default/42.hmac_stress_all.2247226120
Short name T1
Test name
Test status
Simulation time 88919999280 ps
CPU time 1927.73 seconds
Started Jul 21 05:29:19 PM PDT 24
Finished Jul 21 06:01:27 PM PDT 24
Peak memory 752700 kb
Host smart-f1af935e-2a30-46a7-bd40-ed04579fc517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247226120 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2247226120
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.63625800
Short name T9
Test name
Test status
Simulation time 302175807490 ps
CPU time 1378.2 seconds
Started Jul 21 05:25:01 PM PDT 24
Finished Jul 21 05:47:59 PM PDT 24
Peak memory 482912 kb
Host smart-df736b65-e36d-4392-97ae-c7f5b7b1bfb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=63625800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.63625800
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_stress_all.564861262
Short name T11
Test name
Test status
Simulation time 37502949855 ps
CPU time 428.23 seconds
Started Jul 21 05:29:58 PM PDT 24
Finished Jul 21 05:37:06 PM PDT 24
Peak memory 216460 kb
Host smart-76f69c0f-fa46-4579-b07f-4580bae8871b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564861262 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.564861262
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.584604227
Short name T53
Test name
Test status
Simulation time 909256603 ps
CPU time 4.3 seconds
Started Jul 21 05:04:44 PM PDT 24
Finished Jul 21 05:04:49 PM PDT 24
Peak memory 199584 kb
Host smart-e8898469-882b-4d8f-a04d-1f90162c9320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584604227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.584604227
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2523333710
Short name T12
Test name
Test status
Simulation time 70126187364 ps
CPU time 3526.02 seconds
Started Jul 21 05:25:19 PM PDT 24
Finished Jul 21 06:24:06 PM PDT 24
Peak memory 808048 kb
Host smart-cdd8faa0-de9d-4d1b-ac2f-7531f3443f6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523333710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2523333710
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.988955991
Short name T21
Test name
Test status
Simulation time 3711072007 ps
CPU time 55.24 seconds
Started Jul 21 05:28:31 PM PDT 24
Finished Jul 21 05:29:27 PM PDT 24
Peak memory 200212 kb
Host smart-4e2593ae-646a-402f-bd0c-e103cefc029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988955991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.988955991
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1739294478
Short name T36
Test name
Test status
Simulation time 13847361 ps
CPU time 0.59 seconds
Started Jul 21 05:22:37 PM PDT 24
Finished Jul 21 05:22:38 PM PDT 24
Peak memory 195116 kb
Host smart-88f95c2f-8dfe-44da-9225-41f7eb290249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739294478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1739294478
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3997087018
Short name T95
Test name
Test status
Simulation time 38980716 ps
CPU time 0.97 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:44 PM PDT 24
Peak memory 199240 kb
Host smart-0e22a8ec-cfe9-43e3-9e06-cc06393be620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997087018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3997087018
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2170005827
Short name T135
Test name
Test status
Simulation time 1405566736 ps
CPU time 74.13 seconds
Started Jul 21 05:22:47 PM PDT 24
Finished Jul 21 05:24:01 PM PDT 24
Peak memory 200244 kb
Host smart-1187c29b-c8f1-4853-a215-89566c3c78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170005827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2170005827
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1550346351
Short name T40
Test name
Test status
Simulation time 84723212 ps
CPU time 0.92 seconds
Started Jul 21 05:22:34 PM PDT 24
Finished Jul 21 05:22:35 PM PDT 24
Peak memory 218480 kb
Host smart-57babb99-3cc6-423c-8252-41fa46783428
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550346351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1550346351
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1498876290
Short name T84
Test name
Test status
Simulation time 3903825750 ps
CPU time 198.41 seconds
Started Jul 21 05:26:09 PM PDT 24
Finished Jul 21 05:29:27 PM PDT 24
Peak memory 216620 kb
Host smart-34b81a37-6c72-45f5-9eec-653481e94fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498876290 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1498876290
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4191398033
Short name T5
Test name
Test status
Simulation time 5373590633 ps
CPU time 904.66 seconds
Started Jul 21 05:25:57 PM PDT 24
Finished Jul 21 05:41:02 PM PDT 24
Peak memory 749928 kb
Host smart-16c008d1-9cf4-4c55-8702-afcda8640502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191398033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4191398033
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3950903696
Short name T3
Test name
Test status
Simulation time 176775744280 ps
CPU time 1454.53 seconds
Started Jul 21 05:27:08 PM PDT 24
Finished Jul 21 05:51:23 PM PDT 24
Peak memory 673644 kb
Host smart-1511e8ad-db05-4c73-aaa0-3d6d13d0ef56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950903696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3950903696
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1810853143
Short name T51
Test name
Test status
Simulation time 1170234383 ps
CPU time 4.53 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:31 PM PDT 24
Peak memory 199892 kb
Host smart-f098340b-d029-4ec8-83d4-da9fc1fa096a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810853143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1810853143
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.932882804
Short name T118
Test name
Test status
Simulation time 4255859482 ps
CPU time 4.51 seconds
Started Jul 21 05:04:31 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 199748 kb
Host smart-5fe4e45f-aa62-4cef-9565-5c052690ecbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932882804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.932882804
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1846194031
Short name T116
Test name
Test status
Simulation time 907685696 ps
CPU time 4.51 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:43 PM PDT 24
Peak memory 199684 kb
Host smart-94644b1e-cc42-4d01-ac0a-1170417bf35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846194031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1846194031
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3215250452
Short name T272
Test name
Test status
Simulation time 3249278070 ps
CPU time 29.56 seconds
Started Jul 21 05:22:29 PM PDT 24
Finished Jul 21 05:22:59 PM PDT 24
Peak memory 200136 kb
Host smart-b928e021-640d-494b-9d44-1ca3b6a45bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215250452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3215250452
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.384870364
Short name T124
Test name
Test status
Simulation time 215054579184 ps
CPU time 715.4 seconds
Started Jul 21 05:22:31 PM PDT 24
Finished Jul 21 05:34:27 PM PDT 24
Peak memory 200204 kb
Host smart-3d586ba9-f503-4eda-83ab-9dcb8d40bfd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=384870364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.384870364
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_smoke.4147810608
Short name T26
Test name
Test status
Simulation time 2006481211 ps
CPU time 8.37 seconds
Started Jul 21 05:22:40 PM PDT 24
Finished Jul 21 05:22:49 PM PDT 24
Peak memory 200064 kb
Host smart-d14207c4-4b66-49b6-910e-dcdf7b3824fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147810608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4147810608
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.631647836
Short name T630
Test name
Test status
Simulation time 314984554 ps
CPU time 6.13 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:34 PM PDT 24
Peak memory 199564 kb
Host smart-3a55ba5d-bae9-4e17-9bfe-82e9160d7323
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631647836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.631647836
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1055372899
Short name T544
Test name
Test status
Simulation time 713480661 ps
CPU time 11.06 seconds
Started Jul 21 05:04:29 PM PDT 24
Finished Jul 21 05:04:40 PM PDT 24
Peak memory 199692 kb
Host smart-76cbca77-c70e-46c1-a612-41fd848ac824
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055372899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1055372899
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2984266002
Short name T608
Test name
Test status
Simulation time 21638955 ps
CPU time 0.77 seconds
Started Jul 21 05:04:17 PM PDT 24
Finished Jul 21 05:04:18 PM PDT 24
Peak memory 197676 kb
Host smart-b6eb23b2-e31f-47b2-a847-2b75a9184fa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984266002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2984266002
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3876923908
Short name T597
Test name
Test status
Simulation time 85069369 ps
CPU time 1.23 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 199460 kb
Host smart-5d870fc7-758e-4c2b-9dec-4e2bfd8df9d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876923908 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3876923908
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1035908494
Short name T104
Test name
Test status
Simulation time 61551980 ps
CPU time 0.96 seconds
Started Jul 21 05:04:19 PM PDT 24
Finished Jul 21 05:04:21 PM PDT 24
Peak memory 199524 kb
Host smart-77a5fdbb-c090-4197-93c6-bb1f179e2b58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035908494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1035908494
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1289020064
Short name T541
Test name
Test status
Simulation time 23134943 ps
CPU time 0.6 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:28 PM PDT 24
Peak memory 194720 kb
Host smart-d5a12814-48e0-4d5a-b5cb-8a21722a1346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289020064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1289020064
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2900425270
Short name T625
Test name
Test status
Simulation time 422104960 ps
CPU time 2.34 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:28 PM PDT 24
Peak memory 199624 kb
Host smart-df764ad8-bff3-4f4c-9bc8-fd2492ec0d23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900425270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2900425270
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1817343346
Short name T537
Test name
Test status
Simulation time 56193606 ps
CPU time 1.42 seconds
Started Jul 21 05:04:16 PM PDT 24
Finished Jul 21 05:04:18 PM PDT 24
Peak memory 199736 kb
Host smart-6ceb07e8-130e-4a10-89fb-bee0e3ea9481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817343346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1817343346
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3906806561
Short name T563
Test name
Test status
Simulation time 305770792 ps
CPU time 4.5 seconds
Started Jul 21 05:04:17 PM PDT 24
Finished Jul 21 05:04:22 PM PDT 24
Peak memory 199692 kb
Host smart-299cbf9b-631e-4ea3-a213-da280a4f2f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906806561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3906806561
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1726636769
Short name T90
Test name
Test status
Simulation time 1506156913 ps
CPU time 3.36 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:29 PM PDT 24
Peak memory 199672 kb
Host smart-06aa2104-bfae-4bea-8285-21cc547b9c12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726636769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1726636769
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2631094315
Short name T99
Test name
Test status
Simulation time 1396009928 ps
CPU time 16.27 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:42 PM PDT 24
Peak memory 199660 kb
Host smart-caf64129-3e0e-42c4-bc7f-ccc60adb7105
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631094315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2631094315
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4028636585
Short name T558
Test name
Test status
Simulation time 47739797 ps
CPU time 0.72 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:28 PM PDT 24
Peak memory 197764 kb
Host smart-b742b3a9-edd1-4135-8701-ac113b475926
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028636585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4028636585
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.669270956
Short name T570
Test name
Test status
Simulation time 203737033 ps
CPU time 2.27 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:28 PM PDT 24
Peak memory 199572 kb
Host smart-4af0a196-d11b-42d0-81e9-aca584fcc49f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669270956 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.669270956
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2275172275
Short name T641
Test name
Test status
Simulation time 21417749 ps
CPU time 0.71 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 197800 kb
Host smart-72f4dbd9-68f0-49ba-b56d-25adaed00a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275172275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2275172275
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4179772478
Short name T581
Test name
Test status
Simulation time 13596047 ps
CPU time 0.61 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 194504 kb
Host smart-eda055c2-9fe7-4fb9-8b2f-528af7ec169b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179772478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4179772478
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.116443495
Short name T102
Test name
Test status
Simulation time 21233026 ps
CPU time 1.08 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:29 PM PDT 24
Peak memory 199496 kb
Host smart-ed7df64d-56c8-427e-9094-d406562fbbf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116443495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.116443495
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1252159462
Short name T578
Test name
Test status
Simulation time 69928640 ps
CPU time 3.77 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:30 PM PDT 24
Peak memory 199592 kb
Host smart-03d66ffb-b91b-4ea8-aab5-f411159488f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252159462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1252159462
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3232444209
Short name T656
Test name
Test status
Simulation time 38075373 ps
CPU time 1.04 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:33 PM PDT 24
Peak memory 199512 kb
Host smart-81b8cff0-32bf-4007-827b-fe5a514e721a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232444209 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3232444209
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.765935893
Short name T607
Test name
Test status
Simulation time 45340754 ps
CPU time 0.82 seconds
Started Jul 21 05:04:35 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 199072 kb
Host smart-30702008-1a4e-4f0c-b149-2014af2b03ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765935893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.765935893
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3492873068
Short name T529
Test name
Test status
Simulation time 41365409 ps
CPU time 0.6 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:34 PM PDT 24
Peak memory 194616 kb
Host smart-de802d83-ca3c-441d-ba3d-83cd11271cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492873068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3492873068
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2397164858
Short name T568
Test name
Test status
Simulation time 25802410 ps
CPU time 1.1 seconds
Started Jul 21 05:04:33 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199660 kb
Host smart-bca825e3-dfd7-49f3-81a1-091fa15d2a87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397164858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2397164858
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2935735641
Short name T584
Test name
Test status
Simulation time 290632964 ps
CPU time 3.72 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:38 PM PDT 24
Peak memory 199676 kb
Host smart-5b06a411-cb47-4af5-9e0c-e01369532d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935735641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2935735641
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2804097089
Short name T626
Test name
Test status
Simulation time 234688393701 ps
CPU time 541.69 seconds
Started Jul 21 05:04:36 PM PDT 24
Finished Jul 21 05:13:39 PM PDT 24
Peak memory 215720 kb
Host smart-ba083b2a-d2de-4dae-a15f-5cc06629bcda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804097089 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2804097089
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3321409935
Short name T94
Test name
Test status
Simulation time 29722986 ps
CPU time 0.97 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:40 PM PDT 24
Peak memory 199480 kb
Host smart-156bf9b4-eafa-485e-9d09-126fe9a290ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321409935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3321409935
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2951781955
Short name T565
Test name
Test status
Simulation time 14068890 ps
CPU time 0.62 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:04:38 PM PDT 24
Peak memory 194508 kb
Host smart-48e4e7c7-299d-44f3-bb40-8736d7787110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951781955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2951781955
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.897622115
Short name T103
Test name
Test status
Simulation time 86447852 ps
CPU time 1.74 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:40 PM PDT 24
Peak memory 199644 kb
Host smart-b21f3c95-4dea-4a8a-b7bd-af551a7607e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897622115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.897622115
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1825481158
Short name T589
Test name
Test status
Simulation time 35286968 ps
CPU time 1.87 seconds
Started Jul 21 05:04:39 PM PDT 24
Finished Jul 21 05:04:41 PM PDT 24
Peak memory 199696 kb
Host smart-f11d56ac-7f25-427b-a9f0-08aec66debca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825481158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1825481158
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.840446359
Short name T121
Test name
Test status
Simulation time 2431076061 ps
CPU time 4.35 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:43 PM PDT 24
Peak memory 199652 kb
Host smart-eb1d33ae-aaa1-4820-8ca0-dbbf1c405644
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840446359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.840446359
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1289100366
Short name T591
Test name
Test status
Simulation time 157128486980 ps
CPU time 1437.52 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:28:35 PM PDT 24
Peak memory 229608 kb
Host smart-7007faaa-7b79-444e-a083-750465eaacb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289100366 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1289100366
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1524796904
Short name T101
Test name
Test status
Simulation time 47295206 ps
CPU time 0.69 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:39 PM PDT 24
Peak memory 197284 kb
Host smart-f58a754c-29e4-4bb9-9887-0f886e9b8b83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524796904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1524796904
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1661775427
Short name T610
Test name
Test status
Simulation time 14026010 ps
CPU time 0.61 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:04:38 PM PDT 24
Peak memory 194504 kb
Host smart-18ebcd3b-abed-45d8-99f1-70ad18ac1d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661775427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1661775427
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3485198083
Short name T107
Test name
Test status
Simulation time 61052804 ps
CPU time 1.66 seconds
Started Jul 21 05:04:40 PM PDT 24
Finished Jul 21 05:04:42 PM PDT 24
Peak memory 199592 kb
Host smart-98149503-e636-425f-b877-fdedafefeb29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485198083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3485198083
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3032744194
Short name T532
Test name
Test status
Simulation time 63088959 ps
CPU time 1.45 seconds
Started Jul 21 05:04:41 PM PDT 24
Finished Jul 21 05:04:43 PM PDT 24
Peak memory 199548 kb
Host smart-d4d8cc83-03fc-4a24-b794-a1e01fe9c5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032744194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3032744194
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1905195565
Short name T649
Test name
Test status
Simulation time 85509287 ps
CPU time 2.47 seconds
Started Jul 21 05:04:36 PM PDT 24
Finished Jul 21 05:04:39 PM PDT 24
Peak memory 199796 kb
Host smart-e54be655-f672-4675-9252-a9e2278bfb66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905195565 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1905195565
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1712145957
Short name T92
Test name
Test status
Simulation time 61292992 ps
CPU time 0.71 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:39 PM PDT 24
Peak memory 197812 kb
Host smart-9fe69af3-caea-4a1e-81fd-4e36ba9f470c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712145957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1712145957
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2018059018
Short name T648
Test name
Test status
Simulation time 28254816 ps
CPU time 0.67 seconds
Started Jul 21 05:04:39 PM PDT 24
Finished Jul 21 05:04:40 PM PDT 24
Peak memory 194504 kb
Host smart-1f809f1d-6214-486c-9546-35605107b325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018059018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2018059018
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.412216700
Short name T643
Test name
Test status
Simulation time 285948918 ps
CPU time 2.29 seconds
Started Jul 21 05:04:36 PM PDT 24
Finished Jul 21 05:04:39 PM PDT 24
Peak memory 199700 kb
Host smart-fd4f0c52-9974-44c8-a8ba-b539ddccbfce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412216700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.412216700
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3411676770
Short name T539
Test name
Test status
Simulation time 143374536 ps
CPU time 3.57 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:04:41 PM PDT 24
Peak memory 199628 kb
Host smart-0b210ea2-f83b-4e0a-bb01-5debb1009878
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411676770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3411676770
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2601142397
Short name T590
Test name
Test status
Simulation time 228432098 ps
CPU time 4.2 seconds
Started Jul 21 05:04:40 PM PDT 24
Finished Jul 21 05:04:45 PM PDT 24
Peak memory 199708 kb
Host smart-0d977c25-4fe7-4806-adb8-c3155b45fa80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601142397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2601142397
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1444483007
Short name T573
Test name
Test status
Simulation time 55391321 ps
CPU time 3.51 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:42 PM PDT 24
Peak memory 207836 kb
Host smart-dee5560b-2996-4683-80ee-d8ca2e914c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444483007 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1444483007
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.638498744
Short name T100
Test name
Test status
Simulation time 157828116 ps
CPU time 0.73 seconds
Started Jul 21 05:04:36 PM PDT 24
Finished Jul 21 05:04:37 PM PDT 24
Peak memory 197684 kb
Host smart-5a79c075-2285-48ec-a8ce-77dee026e378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638498744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.638498744
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3583292358
Short name T525
Test name
Test status
Simulation time 22723714 ps
CPU time 0.6 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:44 PM PDT 24
Peak memory 194456 kb
Host smart-7f5a8088-fa3a-4a87-900c-ca36208fcc38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583292358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3583292358
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3241994256
Short name T106
Test name
Test status
Simulation time 152749987 ps
CPU time 2.63 seconds
Started Jul 21 05:04:36 PM PDT 24
Finished Jul 21 05:04:39 PM PDT 24
Peak memory 199692 kb
Host smart-4ea98e04-c05c-4143-83a2-00a85198ce28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241994256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3241994256
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.957960932
Short name T615
Test name
Test status
Simulation time 211787194 ps
CPU time 1.65 seconds
Started Jul 21 05:04:35 PM PDT 24
Finished Jul 21 05:04:37 PM PDT 24
Peak memory 199576 kb
Host smart-902618dc-79a9-4652-9e14-34d08eb7a4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957960932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.957960932
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2047535410
Short name T120
Test name
Test status
Simulation time 230251254 ps
CPU time 4.53 seconds
Started Jul 21 05:04:38 PM PDT 24
Finished Jul 21 05:04:43 PM PDT 24
Peak memory 199612 kb
Host smart-f86639a6-1e9c-488d-a1b3-c05ae28b3348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047535410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2047535410
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2762781553
Short name T551
Test name
Test status
Simulation time 256335494 ps
CPU time 1.82 seconds
Started Jul 21 05:04:42 PM PDT 24
Finished Jul 21 05:04:45 PM PDT 24
Peak memory 199660 kb
Host smart-e65baa42-0db5-4741-91e5-39ecae01cdf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762781553 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2762781553
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.683613026
Short name T561
Test name
Test status
Simulation time 23039057 ps
CPU time 0.67 seconds
Started Jul 21 05:04:49 PM PDT 24
Finished Jul 21 05:04:50 PM PDT 24
Peak memory 197124 kb
Host smart-2850c274-b4cb-44c9-910d-9b101136b3a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683613026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.683613026
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1854385573
Short name T535
Test name
Test status
Simulation time 12813099 ps
CPU time 0.57 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:44 PM PDT 24
Peak memory 194420 kb
Host smart-f8c8d2ff-4f03-4b59-886e-a8b39bcc93cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854385573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1854385573
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2278134515
Short name T654
Test name
Test status
Simulation time 158169416 ps
CPU time 1.74 seconds
Started Jul 21 05:04:45 PM PDT 24
Finished Jul 21 05:04:47 PM PDT 24
Peak memory 199740 kb
Host smart-c05b33a7-f276-4a2d-8857-10d15a225c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278134515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2278134515
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3927264961
Short name T533
Test name
Test status
Simulation time 169831311 ps
CPU time 2.64 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:04:41 PM PDT 24
Peak memory 199760 kb
Host smart-48e02531-8867-467c-aa47-7cf150d42b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927264961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3927264961
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1473574663
Short name T117
Test name
Test status
Simulation time 327626801 ps
CPU time 1.77 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:04:39 PM PDT 24
Peak memory 199576 kb
Host smart-db9fc704-e0a1-4712-bf68-7dabf7e4d748
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473574663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1473574663
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2104461073
Short name T585
Test name
Test status
Simulation time 49225927953 ps
CPU time 655.32 seconds
Started Jul 21 05:04:44 PM PDT 24
Finished Jul 21 05:15:40 PM PDT 24
Peak memory 216108 kb
Host smart-6a78bade-a05c-44b2-b5ca-492de6d2e934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104461073 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2104461073
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2448214583
Short name T557
Test name
Test status
Simulation time 106292598 ps
CPU time 0.92 seconds
Started Jul 21 05:04:47 PM PDT 24
Finished Jul 21 05:04:48 PM PDT 24
Peak memory 199568 kb
Host smart-9916d663-f99a-419c-92f1-b83de0188dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448214583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2448214583
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3493359927
Short name T642
Test name
Test status
Simulation time 16747503 ps
CPU time 0.61 seconds
Started Jul 21 05:04:44 PM PDT 24
Finished Jul 21 05:04:46 PM PDT 24
Peak memory 194640 kb
Host smart-3f85b290-9b0e-4cf5-8c14-16a7fdcc2585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493359927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3493359927
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4288366880
Short name T554
Test name
Test status
Simulation time 33275894 ps
CPU time 1.56 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:45 PM PDT 24
Peak memory 199576 kb
Host smart-82396d74-50d6-406b-88da-b9c735bd56c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288366880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.4288366880
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1013656358
Short name T538
Test name
Test status
Simulation time 295922501 ps
CPU time 1.83 seconds
Started Jul 21 05:04:44 PM PDT 24
Finished Jul 21 05:04:47 PM PDT 24
Peak memory 199756 kb
Host smart-baf9c72e-8cc6-4110-a678-c1f041c7ec1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013656358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1013656358
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1773929253
Short name T640
Test name
Test status
Simulation time 277503946 ps
CPU time 4.47 seconds
Started Jul 21 05:04:44 PM PDT 24
Finished Jul 21 05:04:49 PM PDT 24
Peak memory 199620 kb
Host smart-4583cc19-1d0c-4d70-aa98-7cc148c8feb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773929253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1773929253
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1825448612
Short name T601
Test name
Test status
Simulation time 356058282 ps
CPU time 1.78 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:53 PM PDT 24
Peak memory 199568 kb
Host smart-cfeb994d-b034-4d2c-bcb5-76a8732c82ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825448612 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1825448612
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.547131759
Short name T97
Test name
Test status
Simulation time 68799148 ps
CPU time 0.77 seconds
Started Jul 21 05:04:42 PM PDT 24
Finished Jul 21 05:04:43 PM PDT 24
Peak memory 199416 kb
Host smart-80d40946-8a13-4566-9474-b3144cd9ea82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547131759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.547131759
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4022850414
Short name T628
Test name
Test status
Simulation time 13332640 ps
CPU time 0.59 seconds
Started Jul 21 05:04:42 PM PDT 24
Finished Jul 21 05:04:44 PM PDT 24
Peak memory 194480 kb
Host smart-55089738-f3d7-485a-850a-806a0abbd3a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022850414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4022850414
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4238171789
Short name T586
Test name
Test status
Simulation time 149520649 ps
CPU time 1.63 seconds
Started Jul 21 05:04:42 PM PDT 24
Finished Jul 21 05:04:45 PM PDT 24
Peak memory 199712 kb
Host smart-0c1a0584-1d2d-49c0-be88-15306ebb1333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238171789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4238171789
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1482022638
Short name T579
Test name
Test status
Simulation time 140712063 ps
CPU time 2.55 seconds
Started Jul 21 05:04:45 PM PDT 24
Finished Jul 21 05:04:48 PM PDT 24
Peak memory 199708 kb
Host smart-01f869a9-9607-4899-96ae-9f8260b9d765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482022638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1482022638
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4182111047
Short name T624
Test name
Test status
Simulation time 18244836624 ps
CPU time 175.88 seconds
Started Jul 21 05:04:44 PM PDT 24
Finished Jul 21 05:07:41 PM PDT 24
Peak memory 216176 kb
Host smart-cb7e6175-6144-46d2-a014-9495d70080d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182111047 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.4182111047
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3359878424
Short name T580
Test name
Test status
Simulation time 13015781 ps
CPU time 0.63 seconds
Started Jul 21 05:04:46 PM PDT 24
Finished Jul 21 05:04:48 PM PDT 24
Peak memory 194620 kb
Host smart-6656d35c-0f03-4eb2-b942-07420403bd39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359878424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3359878424
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.629799963
Short name T606
Test name
Test status
Simulation time 175666164 ps
CPU time 2.15 seconds
Started Jul 21 05:04:51 PM PDT 24
Finished Jul 21 05:04:54 PM PDT 24
Peak memory 199560 kb
Host smart-79c7d92f-37d0-4e93-bfbe-2fd7d1c1daed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629799963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.629799963
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2784035850
Short name T566
Test name
Test status
Simulation time 227675403 ps
CPU time 3.98 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:48 PM PDT 24
Peak memory 199576 kb
Host smart-b5c8ef5b-9394-4c06-b328-e4a9ffa7a288
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784035850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2784035850
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.679803627
Short name T119
Test name
Test status
Simulation time 1083613189 ps
CPU time 4.14 seconds
Started Jul 21 05:04:46 PM PDT 24
Finished Jul 21 05:04:51 PM PDT 24
Peak memory 199688 kb
Host smart-156c8a6e-15a5-4ac3-a466-d48afc996da4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679803627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.679803627
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3505606136
Short name T550
Test name
Test status
Simulation time 870584256 ps
CPU time 3.9 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:47 PM PDT 24
Peak memory 215352 kb
Host smart-816a2e02-2fa9-4f79-9fb6-2445f4cfe86d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505606136 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3505606136
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2428060178
Short name T637
Test name
Test status
Simulation time 33785647 ps
CPU time 0.93 seconds
Started Jul 21 05:04:46 PM PDT 24
Finished Jul 21 05:04:48 PM PDT 24
Peak memory 199296 kb
Host smart-cd025e64-a357-4baf-acd0-682540c9ed3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428060178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2428060178
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1072341165
Short name T618
Test name
Test status
Simulation time 45207251 ps
CPU time 0.57 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:44 PM PDT 24
Peak memory 194492 kb
Host smart-123636eb-fe39-48e9-a5f4-6eea95c5f2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072341165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1072341165
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1833292535
Short name T616
Test name
Test status
Simulation time 258864968 ps
CPU time 2.32 seconds
Started Jul 21 05:04:44 PM PDT 24
Finished Jul 21 05:04:47 PM PDT 24
Peak memory 199756 kb
Host smart-d1c22c34-4656-4e09-bb76-bd92d5033ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833292535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1833292535
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3675206793
Short name T633
Test name
Test status
Simulation time 205061026 ps
CPU time 2.31 seconds
Started Jul 21 05:04:43 PM PDT 24
Finished Jul 21 05:04:46 PM PDT 24
Peak memory 199596 kb
Host smart-a9937870-74a1-44d5-a06a-c549fb64ee34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675206793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3675206793
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1205401684
Short name T122
Test name
Test status
Simulation time 93144698 ps
CPU time 2.82 seconds
Started Jul 21 05:04:49 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 199636 kb
Host smart-9bd36bb5-8361-44af-bc69-51c1f702a5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205401684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1205401684
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3854755096
Short name T614
Test name
Test status
Simulation time 610750973 ps
CPU time 3.37 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:31 PM PDT 24
Peak memory 199348 kb
Host smart-bc298571-ad9e-4f05-91fb-9a6a584a5c11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854755096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3854755096
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.988462486
Short name T587
Test name
Test status
Simulation time 424759832 ps
CPU time 9.79 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:37 PM PDT 24
Peak memory 199648 kb
Host smart-f8e3de0d-3b47-4f2b-b285-7519f54f8e5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988462486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.988462486
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3632307158
Short name T605
Test name
Test status
Simulation time 26733117 ps
CPU time 0.87 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 198656 kb
Host smart-af95edc7-031e-42d3-8217-d274999846f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632307158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3632307158
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3040126313
Short name T634
Test name
Test status
Simulation time 79814396 ps
CPU time 1.38 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:29 PM PDT 24
Peak memory 199760 kb
Host smart-60e1772f-d5d9-4665-af60-74f22ef3f127
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040126313 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3040126313
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1753053404
Short name T635
Test name
Test status
Simulation time 28861633 ps
CPU time 0.69 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:29 PM PDT 24
Peak memory 197252 kb
Host smart-df17f8d2-b66a-440c-abc4-82f7b1a7e9f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753053404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1753053404
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2656412799
Short name T547
Test name
Test status
Simulation time 114992105 ps
CPU time 0.67 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 194860 kb
Host smart-7e3a6ce7-fd82-4eb2-bd48-7068f5c5dfe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656412799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2656412799
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1980265176
Short name T646
Test name
Test status
Simulation time 93411631 ps
CPU time 1.26 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:26 PM PDT 24
Peak memory 199392 kb
Host smart-bc3de1ff-da7d-4c78-8fed-d13662348970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980265176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1980265176
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2016799755
Short name T560
Test name
Test status
Simulation time 217099569 ps
CPU time 2.36 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:29 PM PDT 24
Peak memory 199680 kb
Host smart-fbb8cf40-783d-4194-942b-62a3451bb2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016799755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2016799755
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3321605027
Short name T569
Test name
Test status
Simulation time 734412491 ps
CPU time 2.86 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:29 PM PDT 24
Peak memory 199692 kb
Host smart-1dee1a26-2fea-4fd3-a8fc-ac1d3343a78f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321605027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3321605027
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2130202972
Short name T592
Test name
Test status
Simulation time 14818643 ps
CPU time 0.63 seconds
Started Jul 21 05:04:52 PM PDT 24
Finished Jul 21 05:04:54 PM PDT 24
Peak memory 194496 kb
Host smart-a34d0248-4e43-4aaa-82ba-e3b2d81309aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130202972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2130202972
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1670655603
Short name T528
Test name
Test status
Simulation time 13135179 ps
CPU time 0.6 seconds
Started Jul 21 05:04:51 PM PDT 24
Finished Jul 21 05:04:53 PM PDT 24
Peak memory 194576 kb
Host smart-45ad068b-e98d-4709-be00-81e93935eae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670655603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1670655603
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1022801204
Short name T536
Test name
Test status
Simulation time 16271593 ps
CPU time 0.63 seconds
Started Jul 21 05:04:54 PM PDT 24
Finished Jul 21 05:04:56 PM PDT 24
Peak memory 194608 kb
Host smart-458e7e15-260a-4b73-bdce-3cf1124e483b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022801204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1022801204
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.456560634
Short name T622
Test name
Test status
Simulation time 14928485 ps
CPU time 0.61 seconds
Started Jul 21 05:04:51 PM PDT 24
Finished Jul 21 05:04:53 PM PDT 24
Peak memory 194592 kb
Host smart-ed99a0f3-9ec7-4118-8644-13deee163308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456560634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.456560634
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.683259506
Short name T548
Test name
Test status
Simulation time 73116694 ps
CPU time 0.68 seconds
Started Jul 21 05:04:54 PM PDT 24
Finished Jul 21 05:04:55 PM PDT 24
Peak memory 194688 kb
Host smart-1c7891dd-a6d4-4b71-9be1-bd55e3740fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683259506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.683259506
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2084923901
Short name T650
Test name
Test status
Simulation time 63331606 ps
CPU time 0.65 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 194664 kb
Host smart-b2e6484a-4fdc-411e-8191-4ed886ec24e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084923901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2084923901
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1249127274
Short name T638
Test name
Test status
Simulation time 12478140 ps
CPU time 0.76 seconds
Started Jul 21 05:04:54 PM PDT 24
Finished Jul 21 05:04:55 PM PDT 24
Peak memory 194648 kb
Host smart-3f5e21e0-fabc-4c7a-bfae-683a6b7c8850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249127274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1249127274
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3269274224
Short name T556
Test name
Test status
Simulation time 12897182 ps
CPU time 0.63 seconds
Started Jul 21 05:04:53 PM PDT 24
Finished Jul 21 05:04:55 PM PDT 24
Peak memory 194452 kb
Host smart-fdbbbed9-aa4d-44ed-8438-5ba1e022e4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269274224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3269274224
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3123031413
Short name T588
Test name
Test status
Simulation time 38890359 ps
CPU time 0.61 seconds
Started Jul 21 05:04:52 PM PDT 24
Finished Jul 21 05:04:54 PM PDT 24
Peak memory 194628 kb
Host smart-28c49b57-89bc-4dc5-8086-df3e3392e186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123031413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3123031413
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.173454509
Short name T572
Test name
Test status
Simulation time 12496150 ps
CPU time 0.58 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:51 PM PDT 24
Peak memory 194696 kb
Host smart-0721571b-8249-4413-a0a8-737af0c8f4bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173454509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.173454509
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4268203404
Short name T613
Test name
Test status
Simulation time 323687259 ps
CPU time 7.84 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:34 PM PDT 24
Peak memory 199444 kb
Host smart-e613b796-7afc-40f8-bba2-cd92f0d1d475
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268203404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4268203404
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3447576172
Short name T98
Test name
Test status
Simulation time 324342384 ps
CPU time 14.33 seconds
Started Jul 21 05:04:29 PM PDT 24
Finished Jul 21 05:04:44 PM PDT 24
Peak memory 199592 kb
Host smart-9a35546d-590a-42ac-82df-aac2853fb660
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447576172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3447576172
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2159522106
Short name T604
Test name
Test status
Simulation time 56294976 ps
CPU time 0.84 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 198884 kb
Host smart-00f30f38-24ef-4dc0-b311-82e5f756259b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159522106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2159522106
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1395566289
Short name T596
Test name
Test status
Simulation time 81539447 ps
CPU time 2.06 seconds
Started Jul 21 05:04:25 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 199744 kb
Host smart-2512fc6f-0d55-4561-98f8-08d7cd1367e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395566289 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1395566289
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3920484263
Short name T93
Test name
Test status
Simulation time 31101329 ps
CPU time 0.88 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:28 PM PDT 24
Peak memory 199084 kb
Host smart-cf1520ad-ccd7-403d-8acc-e5726102eb1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920484263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3920484263
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1246168777
Short name T524
Test name
Test status
Simulation time 58668597 ps
CPU time 0.63 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:27 PM PDT 24
Peak memory 194540 kb
Host smart-bf8666c9-25f8-4ab1-85a2-c54805532b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246168777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1246168777
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2340884521
Short name T105
Test name
Test status
Simulation time 82422019 ps
CPU time 1.09 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:29 PM PDT 24
Peak memory 198372 kb
Host smart-faa48f75-7130-43a4-adee-f6239ec3909c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340884521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2340884521
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2607380514
Short name T530
Test name
Test status
Simulation time 50455879 ps
CPU time 2.66 seconds
Started Jul 21 05:04:27 PM PDT 24
Finished Jul 21 05:04:31 PM PDT 24
Peak memory 199724 kb
Host smart-17d093b4-e346-4e12-af97-492104e8d768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607380514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2607380514
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1562519673
Short name T653
Test name
Test status
Simulation time 169123312 ps
CPU time 1.88 seconds
Started Jul 21 05:04:28 PM PDT 24
Finished Jul 21 05:04:31 PM PDT 24
Peak memory 199716 kb
Host smart-0886f652-5e0f-4ba6-b0cb-20c7529e2aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562519673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1562519673
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2246588361
Short name T594
Test name
Test status
Simulation time 68170677 ps
CPU time 0.59 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 194604 kb
Host smart-2df263b2-1ddf-4e0f-9b7f-624256b2ebdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246588361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2246588361
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.4262771174
Short name T621
Test name
Test status
Simulation time 17206373 ps
CPU time 0.6 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 194568 kb
Host smart-dd9f9f14-28aa-49f4-a746-008e852da97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262771174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4262771174
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.995702362
Short name T540
Test name
Test status
Simulation time 13798711 ps
CPU time 0.57 seconds
Started Jul 21 05:04:51 PM PDT 24
Finished Jul 21 05:04:53 PM PDT 24
Peak memory 194528 kb
Host smart-f2587326-2d50-4f9a-b0a4-62bf029cd145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995702362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.995702362
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1825114703
Short name T531
Test name
Test status
Simulation time 50849735 ps
CPU time 0.57 seconds
Started Jul 21 05:04:49 PM PDT 24
Finished Jul 21 05:04:50 PM PDT 24
Peak memory 194596 kb
Host smart-23fa4500-8b39-40a4-b965-0fdbd793243b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825114703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1825114703
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1968151303
Short name T617
Test name
Test status
Simulation time 52850586 ps
CPU time 0.63 seconds
Started Jul 21 05:04:49 PM PDT 24
Finished Jul 21 05:04:50 PM PDT 24
Peak memory 194672 kb
Host smart-04c835ca-8866-4e92-a5a9-c4cac68a6481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968151303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1968151303
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1055941484
Short name T631
Test name
Test status
Simulation time 13586895 ps
CPU time 0.58 seconds
Started Jul 21 05:04:51 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 194524 kb
Host smart-f49b07aa-416d-42d2-a34a-7ac34a9e17eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055941484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1055941484
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2308917563
Short name T632
Test name
Test status
Simulation time 32082880 ps
CPU time 0.62 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 194640 kb
Host smart-6eba703f-9ebf-4cab-9f35-9293b3c1d7de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308917563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2308917563
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1902049654
Short name T555
Test name
Test status
Simulation time 15258636 ps
CPU time 0.65 seconds
Started Jul 21 05:04:53 PM PDT 24
Finished Jul 21 05:04:54 PM PDT 24
Peak memory 194584 kb
Host smart-1ed169a3-1824-4fd8-8567-9203a71d4645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902049654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1902049654
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1433030358
Short name T620
Test name
Test status
Simulation time 61144806 ps
CPU time 0.6 seconds
Started Jul 21 05:04:53 PM PDT 24
Finished Jul 21 05:04:55 PM PDT 24
Peak memory 194424 kb
Host smart-f6649ece-168a-4d0c-99ef-5c9746202174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433030358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1433030358
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1041242763
Short name T651
Test name
Test status
Simulation time 102880968 ps
CPU time 0.62 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 194512 kb
Host smart-a628f640-ec69-4871-9779-594928ed6bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041242763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1041242763
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3473970415
Short name T96
Test name
Test status
Simulation time 509735409 ps
CPU time 8.67 seconds
Started Jul 21 05:04:29 PM PDT 24
Finished Jul 21 05:04:38 PM PDT 24
Peak memory 199676 kb
Host smart-0bfa8f6e-1fe9-469f-8fda-2fb1638203b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473970415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3473970415
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.628089172
Short name T546
Test name
Test status
Simulation time 882524625 ps
CPU time 10.78 seconds
Started Jul 21 05:04:31 PM PDT 24
Finished Jul 21 05:04:42 PM PDT 24
Peak memory 199660 kb
Host smart-ca0bd85c-a8cc-4b91-bf97-0b458ede1ba0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628089172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.628089172
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3095391774
Short name T575
Test name
Test status
Simulation time 15305430 ps
CPU time 0.75 seconds
Started Jul 21 05:04:33 PM PDT 24
Finished Jul 21 05:04:34 PM PDT 24
Peak memory 197732 kb
Host smart-fcf00fb6-509c-4634-b92b-4bea84b3aa0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095391774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3095391774
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1770536369
Short name T553
Test name
Test status
Simulation time 147356953 ps
CPU time 1.3 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:37 PM PDT 24
Peak memory 199660 kb
Host smart-0d888b7a-a4a4-47f9-a5ea-a677a54fd6d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770536369 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1770536369
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2533428914
Short name T582
Test name
Test status
Simulation time 71949030 ps
CPU time 0.88 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199492 kb
Host smart-ab85538d-c2f1-4809-889b-27003c013fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533428914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2533428914
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.264793661
Short name T543
Test name
Test status
Simulation time 14543989 ps
CPU time 0.58 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 193644 kb
Host smart-e445997e-555e-424a-a8bb-ad4a5a183bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264793661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.264793661
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1177489081
Short name T574
Test name
Test status
Simulation time 456176888 ps
CPU time 1.94 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199580 kb
Host smart-00dd7c98-3a2c-4a53-9e1d-b0c6aa413d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177489081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1177489081
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1109831594
Short name T611
Test name
Test status
Simulation time 23869823 ps
CPU time 1.25 seconds
Started Jul 21 05:04:26 PM PDT 24
Finished Jul 21 05:04:28 PM PDT 24
Peak memory 199652 kb
Host smart-8a4e7b68-85ed-49a3-8efb-e6684bca4b93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109831594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1109831594
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1802241851
Short name T612
Test name
Test status
Simulation time 509757124 ps
CPU time 4.55 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:04:42 PM PDT 24
Peak memory 199700 kb
Host smart-f68c8149-232e-4c89-8fa0-4a53f5b1e38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802241851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1802241851
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2601821201
Short name T523
Test name
Test status
Simulation time 40177698 ps
CPU time 0.6 seconds
Started Jul 21 05:04:53 PM PDT 24
Finished Jul 21 05:04:54 PM PDT 24
Peak memory 194424 kb
Host smart-981e48f7-63d3-4915-ac74-0be7340e290f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601821201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2601821201
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2677294444
Short name T527
Test name
Test status
Simulation time 21211982 ps
CPU time 0.63 seconds
Started Jul 21 05:04:54 PM PDT 24
Finished Jul 21 05:04:56 PM PDT 24
Peak memory 194752 kb
Host smart-073a5a5f-b9e2-4290-b33a-f57614103048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677294444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2677294444
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3472052046
Short name T593
Test name
Test status
Simulation time 142944642 ps
CPU time 0.6 seconds
Started Jul 21 05:04:54 PM PDT 24
Finished Jul 21 05:04:55 PM PDT 24
Peak memory 194652 kb
Host smart-ddbc8045-568a-44e6-af46-c0977f31be4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472052046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3472052046
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1460767336
Short name T627
Test name
Test status
Simulation time 23755718 ps
CPU time 0.58 seconds
Started Jul 21 05:04:50 PM PDT 24
Finished Jul 21 05:04:52 PM PDT 24
Peak memory 194536 kb
Host smart-02dfbf04-ccea-4265-8e8e-c06d3200f817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460767336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1460767336
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1393360481
Short name T603
Test name
Test status
Simulation time 17732719 ps
CPU time 0.64 seconds
Started Jul 21 05:04:59 PM PDT 24
Finished Jul 21 05:05:00 PM PDT 24
Peak memory 194656 kb
Host smart-20e033fa-0cc9-4070-b2e3-ce9540baf605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393360481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1393360481
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1477395412
Short name T534
Test name
Test status
Simulation time 13636882 ps
CPU time 0.6 seconds
Started Jul 21 05:04:57 PM PDT 24
Finished Jul 21 05:04:58 PM PDT 24
Peak memory 194664 kb
Host smart-12816e6a-bba1-4bcc-a86e-4fe875741225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477395412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1477395412
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.491658688
Short name T644
Test name
Test status
Simulation time 34046899 ps
CPU time 0.63 seconds
Started Jul 21 05:05:01 PM PDT 24
Finished Jul 21 05:05:02 PM PDT 24
Peak memory 194464 kb
Host smart-ac7788a7-83f4-46fc-9ef1-be9f1fd4df14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491658688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.491658688
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.705177062
Short name T583
Test name
Test status
Simulation time 11944617 ps
CPU time 0.59 seconds
Started Jul 21 05:04:57 PM PDT 24
Finished Jul 21 05:04:59 PM PDT 24
Peak memory 194500 kb
Host smart-8b74dd6e-6358-4c98-9026-ec542d2737a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705177062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.705177062
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.169098872
Short name T545
Test name
Test status
Simulation time 37828235 ps
CPU time 0.66 seconds
Started Jul 21 05:05:01 PM PDT 24
Finished Jul 21 05:05:02 PM PDT 24
Peak memory 194556 kb
Host smart-109f599e-5e35-42b2-80d9-c13730443900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169098872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.169098872
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4094043027
Short name T598
Test name
Test status
Simulation time 29136292 ps
CPU time 0.59 seconds
Started Jul 21 05:04:56 PM PDT 24
Finished Jul 21 05:04:57 PM PDT 24
Peak memory 194572 kb
Host smart-48638fc1-8e3a-4047-80b0-a6532e5a72f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094043027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4094043027
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3177078280
Short name T609
Test name
Test status
Simulation time 54974945 ps
CPU time 3.83 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:37 PM PDT 24
Peak memory 216096 kb
Host smart-ff6bdbc3-5f54-43f3-b266-60f3136b8917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177078280 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3177078280
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3880911948
Short name T645
Test name
Test status
Simulation time 255941691 ps
CPU time 0.85 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 199300 kb
Host smart-38c28916-ac38-4f66-87fd-bf7d0a19601a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880911948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3880911948
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3021999219
Short name T619
Test name
Test status
Simulation time 11828945 ps
CPU time 0.61 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:32 PM PDT 24
Peak memory 194568 kb
Host smart-c31f2cb5-7348-4c64-be61-020073f85843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021999219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3021999219
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2541897720
Short name T655
Test name
Test status
Simulation time 82960178 ps
CPU time 1.11 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:31 PM PDT 24
Peak memory 199480 kb
Host smart-763cb903-f680-4d85-9aa5-cbb418a99c50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541897720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2541897720
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1795175029
Short name T599
Test name
Test status
Simulation time 58135448 ps
CPU time 3.17 seconds
Started Jul 21 05:04:31 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199756 kb
Host smart-cabe4a60-7c11-470e-9928-efb2e0b4c0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795175029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1795175029
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.467937185
Short name T52
Test name
Test status
Simulation time 448296585 ps
CPU time 4.58 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:37 PM PDT 24
Peak memory 199680 kb
Host smart-98ab0aaa-8597-4d0e-b6f4-c494ef3081dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467937185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.467937185
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3232243429
Short name T526
Test name
Test status
Simulation time 89070962 ps
CPU time 2.4 seconds
Started Jul 21 05:04:33 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 199740 kb
Host smart-5c8ea6e6-6afa-40c5-8aa7-f151a4492951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232243429 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3232243429
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3509806131
Short name T91
Test name
Test status
Simulation time 27984731 ps
CPU time 0.87 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:31 PM PDT 24
Peak memory 199416 kb
Host smart-b0c384f6-ed21-4e1a-8db7-f52eaf72b71c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509806131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3509806131
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3830375125
Short name T647
Test name
Test status
Simulation time 58172093 ps
CPU time 0.59 seconds
Started Jul 21 05:04:33 PM PDT 24
Finished Jul 21 05:04:34 PM PDT 24
Peak memory 194420 kb
Host smart-6592d915-e7de-491b-9d6e-24f601a69b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830375125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3830375125
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2947687810
Short name T595
Test name
Test status
Simulation time 66186013 ps
CPU time 1.08 seconds
Started Jul 21 05:04:35 PM PDT 24
Finished Jul 21 05:04:37 PM PDT 24
Peak memory 199656 kb
Host smart-7724b051-5f4a-45d1-976e-2e60cb538fff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947687810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2947687810
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1832114845
Short name T562
Test name
Test status
Simulation time 112900240 ps
CPU time 3.17 seconds
Started Jul 21 05:04:37 PM PDT 24
Finished Jul 21 05:04:41 PM PDT 24
Peak memory 199680 kb
Host smart-2c2c8fe4-2b63-4658-8ccc-f4e7d43ee1df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832114845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1832114845
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.635701366
Short name T623
Test name
Test status
Simulation time 247766140 ps
CPU time 3.98 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199676 kb
Host smart-0153c3b1-f86e-402b-9c99-8d7fa94f7747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635701366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.635701366
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3911367322
Short name T549
Test name
Test status
Simulation time 42906175 ps
CPU time 1.35 seconds
Started Jul 21 05:04:31 PM PDT 24
Finished Jul 21 05:04:33 PM PDT 24
Peak memory 199744 kb
Host smart-d2425bd1-f996-4c29-af8e-ccb3ca24dd80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911367322 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3911367322
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1540001131
Short name T89
Test name
Test status
Simulation time 23931962 ps
CPU time 0.83 seconds
Started Jul 21 05:04:35 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 199288 kb
Host smart-f07f36b8-dd70-4500-8c41-cb49da224246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540001131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1540001131
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1214022901
Short name T552
Test name
Test status
Simulation time 33145351 ps
CPU time 0.64 seconds
Started Jul 21 05:04:31 PM PDT 24
Finished Jul 21 05:04:32 PM PDT 24
Peak memory 194620 kb
Host smart-c281026b-1ce3-4be3-99f7-c53ec2cbd6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214022901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1214022901
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1418752192
Short name T577
Test name
Test status
Simulation time 46992602 ps
CPU time 2.16 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:33 PM PDT 24
Peak memory 199724 kb
Host smart-55481057-cee4-4ed6-a7e5-b250c09c5e95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418752192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1418752192
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2297998390
Short name T652
Test name
Test status
Simulation time 73028458 ps
CPU time 3.76 seconds
Started Jul 21 05:04:29 PM PDT 24
Finished Jul 21 05:04:34 PM PDT 24
Peak memory 199604 kb
Host smart-5bd7326e-817a-413f-a16b-b1b843133dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297998390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2297998390
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.575981743
Short name T567
Test name
Test status
Simulation time 870514471 ps
CPU time 4.34 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:38 PM PDT 24
Peak memory 199652 kb
Host smart-f17f1a95-bffd-479d-a064-264ec39131e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575981743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.575981743
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3529804506
Short name T600
Test name
Test status
Simulation time 38583382 ps
CPU time 2.34 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:33 PM PDT 24
Peak memory 207980 kb
Host smart-c60c8af7-eb71-4bc9-9156-0ea1fcc297bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529804506 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3529804506
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.694737385
Short name T636
Test name
Test status
Simulation time 53175002 ps
CPU time 0.69 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 197160 kb
Host smart-f648ba70-4537-4d25-ac1c-67a941b28f74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694737385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.694737385
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3685507071
Short name T639
Test name
Test status
Simulation time 16161715 ps
CPU time 0.6 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 194500 kb
Host smart-0d1a5648-847c-4bd6-af0d-245e7ba625aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685507071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3685507071
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.65124057
Short name T564
Test name
Test status
Simulation time 34048637 ps
CPU time 1.67 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199680 kb
Host smart-9d2f8da6-f7af-466e-b82a-42493b903b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65124057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_o
utstanding.65124057
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2478834232
Short name T657
Test name
Test status
Simulation time 195456108 ps
CPU time 1.28 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:32 PM PDT 24
Peak memory 199612 kb
Host smart-376db99b-cd8e-47c2-bab7-7e4efe27591a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478834232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2478834232
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3968366140
Short name T602
Test name
Test status
Simulation time 587363483 ps
CPU time 3.96 seconds
Started Jul 21 05:04:34 PM PDT 24
Finished Jul 21 05:04:39 PM PDT 24
Peak memory 198636 kb
Host smart-4283d397-fa1b-4a9a-8c7b-9da62275ba20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968366140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3968366140
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.762266738
Short name T542
Test name
Test status
Simulation time 41663319 ps
CPU time 2.57 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199804 kb
Host smart-c12bf079-241c-43de-bf1a-cfced1372205
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762266738 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.762266738
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2342155635
Short name T629
Test name
Test status
Simulation time 38379349 ps
CPU time 0.8 seconds
Started Jul 21 05:04:31 PM PDT 24
Finished Jul 21 05:04:32 PM PDT 24
Peak memory 199036 kb
Host smart-d702ba65-d563-4576-9bb1-d8a8b6992949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342155635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2342155635
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.656010164
Short name T559
Test name
Test status
Simulation time 27290916 ps
CPU time 0.62 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:33 PM PDT 24
Peak memory 194436 kb
Host smart-4851912e-12be-402f-a780-fc90a46292c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656010164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.656010164
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3968944959
Short name T576
Test name
Test status
Simulation time 64189937 ps
CPU time 1.72 seconds
Started Jul 21 05:04:30 PM PDT 24
Finished Jul 21 05:04:32 PM PDT 24
Peak memory 199388 kb
Host smart-1d815582-a926-41d1-a9d4-e3b2a7459a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968944959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3968944959
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1553427965
Short name T571
Test name
Test status
Simulation time 266112114 ps
CPU time 1.47 seconds
Started Jul 21 05:04:32 PM PDT 24
Finished Jul 21 05:04:35 PM PDT 24
Peak memory 199616 kb
Host smart-4e82974f-f779-4747-93a8-e6af7a4394aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553427965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1553427965
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1839186043
Short name T658
Test name
Test status
Simulation time 620851374 ps
CPU time 2.97 seconds
Started Jul 21 05:04:33 PM PDT 24
Finished Jul 21 05:04:36 PM PDT 24
Peak memory 199676 kb
Host smart-efdb84e9-c5dc-4cf2-8680-a6a76b36e9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839186043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1839186043
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3112486272
Short name T303
Test name
Test status
Simulation time 8147687918 ps
CPU time 72.3 seconds
Started Jul 21 05:22:32 PM PDT 24
Finished Jul 21 05:23:45 PM PDT 24
Peak memory 200288 kb
Host smart-f822dd3e-66dc-4e46-8005-e9d5eaa2485f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112486272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3112486272
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.772191980
Short name T217
Test name
Test status
Simulation time 2997384369 ps
CPU time 581.74 seconds
Started Jul 21 05:22:31 PM PDT 24
Finished Jul 21 05:32:13 PM PDT 24
Peak memory 698544 kb
Host smart-6b611bd3-c93a-463d-9e29-5d2483e0f99f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772191980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.772191980
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.4177120067
Short name T65
Test name
Test status
Simulation time 12662649316 ps
CPU time 78.46 seconds
Started Jul 21 05:22:31 PM PDT 24
Finished Jul 21 05:23:50 PM PDT 24
Peak memory 200252 kb
Host smart-075ce153-1544-4ae7-a725-21164bb9aaf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177120067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4177120067
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3853376566
Short name T494
Test name
Test status
Simulation time 525079315 ps
CPU time 31.37 seconds
Started Jul 21 05:22:27 PM PDT 24
Finished Jul 21 05:22:59 PM PDT 24
Peak memory 200200 kb
Host smart-ec2f3a22-af92-45ad-92b0-321ac4fc9780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853376566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3853376566
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1531390773
Short name T163
Test name
Test status
Simulation time 65098357 ps
CPU time 2.78 seconds
Started Jul 21 05:22:25 PM PDT 24
Finished Jul 21 05:22:28 PM PDT 24
Peak memory 200196 kb
Host smart-4fba03c6-8e9b-4928-89bc-8c0ff2381742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531390773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1531390773
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2168485352
Short name T236
Test name
Test status
Simulation time 6315497737 ps
CPU time 559.37 seconds
Started Jul 21 05:22:35 PM PDT 24
Finished Jul 21 05:31:54 PM PDT 24
Peak memory 413612 kb
Host smart-eb39a741-12f1-4eef-981a-ecc1341d01c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168485352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2168485352
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.487665810
Short name T14
Test name
Test status
Simulation time 1082609886946 ps
CPU time 6631.59 seconds
Started Jul 21 05:22:36 PM PDT 24
Finished Jul 21 07:13:08 PM PDT 24
Peak memory 898216 kb
Host smart-30a08382-7bd5-452f-97dd-995408d9f026
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487665810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.487665810
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3064472640
Short name T279
Test name
Test status
Simulation time 17243436358 ps
CPU time 75.16 seconds
Started Jul 21 05:22:31 PM PDT 24
Finished Jul 21 05:23:47 PM PDT 24
Peak memory 200524 kb
Host smart-e9e4d2f9-820c-4b4c-bc5b-d05bfa114816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3064472640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3064472640
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1600851860
Short name T436
Test name
Test status
Simulation time 7988661920 ps
CPU time 92.91 seconds
Started Jul 21 05:22:36 PM PDT 24
Finished Jul 21 05:24:09 PM PDT 24
Peak memory 200100 kb
Host smart-048766cd-1d51-45b1-bfa6-42a452101efa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1600851860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1600851860
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1869733693
Short name T262
Test name
Test status
Simulation time 10293698837 ps
CPU time 63.22 seconds
Started Jul 21 05:22:37 PM PDT 24
Finished Jul 21 05:23:40 PM PDT 24
Peak memory 200100 kb
Host smart-284669fe-02a4-4330-867e-8b7abc1b79db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1869733693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1869733693
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1425908300
Short name T126
Test name
Test status
Simulation time 35208353676 ps
CPU time 2060.2 seconds
Started Jul 21 05:22:31 PM PDT 24
Finished Jul 21 05:56:52 PM PDT 24
Peak memory 215728 kb
Host smart-0279b9b0-293c-4f60-b0fb-189c776e7322
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1425908300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1425908300
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2861295087
Short name T253
Test name
Test status
Simulation time 57627897237 ps
CPU time 56.55 seconds
Started Jul 21 05:22:31 PM PDT 24
Finished Jul 21 05:23:28 PM PDT 24
Peak memory 200260 kb
Host smart-5dd5d2da-8850-48b8-860d-5bbeb9a9e1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861295087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2861295087
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1264247319
Short name T299
Test name
Test status
Simulation time 53340065 ps
CPU time 0.59 seconds
Started Jul 21 05:23:11 PM PDT 24
Finished Jul 21 05:23:12 PM PDT 24
Peak memory 196020 kb
Host smart-42eec65e-9e4f-4729-813b-1b412eb7631d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264247319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1264247319
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4036627571
Short name T324
Test name
Test status
Simulation time 10531518026 ps
CPU time 61.38 seconds
Started Jul 21 05:22:48 PM PDT 24
Finished Jul 21 05:23:50 PM PDT 24
Peak memory 215620 kb
Host smart-034cef5f-cc89-4a5b-8817-6921a70c0aa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036627571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4036627571
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.576653848
Short name T170
Test name
Test status
Simulation time 34047126594 ps
CPU time 1670.54 seconds
Started Jul 21 05:22:48 PM PDT 24
Finished Jul 21 05:50:39 PM PDT 24
Peak memory 725580 kb
Host smart-94ef5d66-8b3e-4d78-a11c-6e6eac2b68aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576653848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.576653848
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3088667805
Short name T50
Test name
Test status
Simulation time 171263655 ps
CPU time 9.98 seconds
Started Jul 21 05:22:47 PM PDT 24
Finished Jul 21 05:22:57 PM PDT 24
Peak memory 200060 kb
Host smart-34309c12-3654-442f-937f-443df78b6407
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088667805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3088667805
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.306373995
Short name T229
Test name
Test status
Simulation time 25013786216 ps
CPU time 126.79 seconds
Started Jul 21 05:22:39 PM PDT 24
Finished Jul 21 05:24:46 PM PDT 24
Peak memory 200300 kb
Host smart-0862e3e2-ba6e-48bc-8d84-c4e8e58cdfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306373995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.306373995
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3691876841
Short name T39
Test name
Test status
Simulation time 78516685 ps
CPU time 0.84 seconds
Started Jul 21 05:23:12 PM PDT 24
Finished Jul 21 05:23:13 PM PDT 24
Peak memory 218496 kb
Host smart-d6fb1b1c-ff60-4991-a1bf-d8daf75369d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691876841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3691876841
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2734388589
Short name T418
Test name
Test status
Simulation time 143179400865 ps
CPU time 1322.11 seconds
Started Jul 21 05:23:03 PM PDT 24
Finished Jul 21 05:45:06 PM PDT 24
Peak memory 660284 kb
Host smart-d70ac954-0446-4b39-8ad3-48108f4ce56b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734388589 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2734388589
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.1364841277
Short name T55
Test name
Test status
Simulation time 468375015035 ps
CPU time 3123.85 seconds
Started Jul 21 05:23:10 PM PDT 24
Finished Jul 21 06:15:15 PM PDT 24
Peak memory 807196 kb
Host smart-341fc2c9-58a7-4911-8f55-7db0f1483b7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364841277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.1364841277
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.293920088
Short name T469
Test name
Test status
Simulation time 3044722999 ps
CPU time 49.09 seconds
Started Jul 21 05:23:07 PM PDT 24
Finished Jul 21 05:23:56 PM PDT 24
Peak memory 200252 kb
Host smart-54cae26e-8ed3-47a5-b520-33562cbe4e3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=293920088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.293920088
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.4026260036
Short name T214
Test name
Test status
Simulation time 6523547164 ps
CPU time 107.97 seconds
Started Jul 21 05:23:05 PM PDT 24
Finished Jul 21 05:24:53 PM PDT 24
Peak memory 200260 kb
Host smart-2419f67c-038c-48ca-8ef0-f9beb067ffd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4026260036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.4026260036
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2930163691
Short name T466
Test name
Test status
Simulation time 2850862159 ps
CPU time 108.71 seconds
Started Jul 21 05:23:04 PM PDT 24
Finished Jul 21 05:24:53 PM PDT 24
Peak memory 200248 kb
Host smart-b93dfb2b-7898-44b8-ad17-335096e920ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2930163691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2930163691
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2552488654
Short name T434
Test name
Test status
Simulation time 40104564336 ps
CPU time 645.17 seconds
Started Jul 21 05:22:56 PM PDT 24
Finished Jul 21 05:33:42 PM PDT 24
Peak memory 200252 kb
Host smart-0042ecc6-b9e4-4bbe-a99a-6bc87f7214f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2552488654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2552488654
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3035531578
Short name T319
Test name
Test status
Simulation time 86994552788 ps
CPU time 2321.1 seconds
Started Jul 21 05:23:04 PM PDT 24
Finished Jul 21 06:01:46 PM PDT 24
Peak memory 215812 kb
Host smart-5d262c34-7515-43e9-8b1c-3331189a989c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3035531578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3035531578
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4290462938
Short name T420
Test name
Test status
Simulation time 706110698453 ps
CPU time 2574.7 seconds
Started Jul 21 05:23:05 PM PDT 24
Finished Jul 21 06:06:00 PM PDT 24
Peak memory 216636 kb
Host smart-7bbf5e5c-b2c7-4a36-89b0-c50f10395d99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4290462938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4290462938
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4212394168
Short name T333
Test name
Test status
Simulation time 3733198609 ps
CPU time 72.16 seconds
Started Jul 21 05:22:46 PM PDT 24
Finished Jul 21 05:23:59 PM PDT 24
Peak memory 200208 kb
Host smart-9e68c54c-b643-4bb1-b950-ec159b86fbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212394168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4212394168
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3569180245
Short name T508
Test name
Test status
Simulation time 53469604 ps
CPU time 0.6 seconds
Started Jul 21 05:25:22 PM PDT 24
Finished Jul 21 05:25:23 PM PDT 24
Peak memory 196704 kb
Host smart-fb899536-b271-4c00-b5ec-0bf4d968a6e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569180245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3569180245
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1056228801
Short name T13
Test name
Test status
Simulation time 9245552292 ps
CPU time 81.03 seconds
Started Jul 21 05:25:22 PM PDT 24
Finished Jul 21 05:26:43 PM PDT 24
Peak memory 200136 kb
Host smart-56317ee0-7e4e-4389-aa0c-8b9f38631210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056228801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1056228801
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.331079791
Short name T506
Test name
Test status
Simulation time 1567311865 ps
CPU time 26.58 seconds
Started Jul 21 05:25:24 PM PDT 24
Finished Jul 21 05:25:51 PM PDT 24
Peak memory 200412 kb
Host smart-08734021-6e1f-4d13-a1a6-a0f98e6752de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331079791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.331079791
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1452104328
Short name T148
Test name
Test status
Simulation time 7317987217 ps
CPU time 341.71 seconds
Started Jul 21 05:25:23 PM PDT 24
Finished Jul 21 05:31:05 PM PDT 24
Peak memory 683348 kb
Host smart-8cb646e4-f6a1-44ef-884b-095d38b17b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452104328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1452104328
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.915634580
Short name T381
Test name
Test status
Simulation time 8637564394 ps
CPU time 110.39 seconds
Started Jul 21 05:25:23 PM PDT 24
Finished Jul 21 05:27:13 PM PDT 24
Peak memory 200140 kb
Host smart-b1acd9a2-f419-48a9-aeb7-4c42f5aeaceb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915634580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.915634580
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2024185361
Short name T404
Test name
Test status
Simulation time 21018267424 ps
CPU time 58.55 seconds
Started Jul 21 05:25:17 PM PDT 24
Finished Jul 21 05:26:16 PM PDT 24
Peak memory 200324 kb
Host smart-04c8c8cd-9022-4a82-8a17-c0e2483b4697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024185361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2024185361
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2681253638
Short name T240
Test name
Test status
Simulation time 491359185 ps
CPU time 10.44 seconds
Started Jul 21 05:25:19 PM PDT 24
Finished Jul 21 05:25:30 PM PDT 24
Peak memory 200116 kb
Host smart-b3ac0e74-10ea-40cf-abbe-35a6ee648b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681253638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2681253638
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.4256155071
Short name T328
Test name
Test status
Simulation time 76423513518 ps
CPU time 211.3 seconds
Started Jul 21 05:25:22 PM PDT 24
Finished Jul 21 05:28:54 PM PDT 24
Peak memory 200304 kb
Host smart-9b9d6a2a-dcaa-4570-8553-25c0177d0b62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256155071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.4256155071
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.800708496
Short name T239
Test name
Test status
Simulation time 7578823164 ps
CPU time 132.23 seconds
Started Jul 21 05:25:24 PM PDT 24
Finished Jul 21 05:27:36 PM PDT 24
Peak memory 200316 kb
Host smart-5231bd37-2255-40f2-86e2-f0567d0d6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800708496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.800708496
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.944278758
Short name T237
Test name
Test status
Simulation time 35194120 ps
CPU time 0.57 seconds
Started Jul 21 05:25:34 PM PDT 24
Finished Jul 21 05:25:35 PM PDT 24
Peak memory 195100 kb
Host smart-bcbedd3b-5c06-447a-a0fa-24940c408570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944278758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.944278758
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3880682987
Short name T471
Test name
Test status
Simulation time 114299592 ps
CPU time 6.6 seconds
Started Jul 21 05:25:30 PM PDT 24
Finished Jul 21 05:25:36 PM PDT 24
Peak memory 200092 kb
Host smart-3b491d4d-8ad5-4b29-a0d7-89c0c6c8833c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880682987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3880682987
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.808820721
Short name T261
Test name
Test status
Simulation time 540659476 ps
CPU time 8.03 seconds
Started Jul 21 05:25:28 PM PDT 24
Finished Jul 21 05:25:36 PM PDT 24
Peak memory 200176 kb
Host smart-8e516c6b-d10c-4d19-81c0-ba1246d432b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808820721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.808820721
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4125834091
Short name T468
Test name
Test status
Simulation time 14511221506 ps
CPU time 556.88 seconds
Started Jul 21 05:25:28 PM PDT 24
Finished Jul 21 05:34:45 PM PDT 24
Peak memory 693900 kb
Host smart-7244e15c-7a48-4442-87c1-f94e15023983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125834091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4125834091
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2868082621
Short name T473
Test name
Test status
Simulation time 1744994447 ps
CPU time 31.85 seconds
Started Jul 21 05:25:34 PM PDT 24
Finished Jul 21 05:26:06 PM PDT 24
Peak memory 200212 kb
Host smart-167ab1ea-46b3-419b-a8d7-ffc3945b845b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868082621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2868082621
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1125165807
Short name T317
Test name
Test status
Simulation time 37288928133 ps
CPU time 196.68 seconds
Started Jul 21 05:25:28 PM PDT 24
Finished Jul 21 05:28:45 PM PDT 24
Peak memory 208512 kb
Host smart-02c30a43-ee31-4d4c-9d32-984310167d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125165807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1125165807
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.744134768
Short name T302
Test name
Test status
Simulation time 36752696 ps
CPU time 1.74 seconds
Started Jul 21 05:25:28 PM PDT 24
Finished Jul 21 05:25:30 PM PDT 24
Peak memory 200176 kb
Host smart-1692ace8-2134-4210-94a1-441b95917c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744134768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.744134768
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1549342126
Short name T296
Test name
Test status
Simulation time 92533615513 ps
CPU time 3115.33 seconds
Started Jul 21 05:25:34 PM PDT 24
Finished Jul 21 06:17:30 PM PDT 24
Peak memory 778616 kb
Host smart-390abb3f-0f7b-4409-b198-a7f36759d5c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549342126 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1549342126
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3418289935
Short name T344
Test name
Test status
Simulation time 5325099868 ps
CPU time 68.45 seconds
Started Jul 21 05:25:34 PM PDT 24
Finished Jul 21 05:26:43 PM PDT 24
Peak memory 200284 kb
Host smart-4fdabed0-5df2-4cbd-92a6-b0914d0224b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418289935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3418289935
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1002393716
Short name T462
Test name
Test status
Simulation time 13158402 ps
CPU time 0.57 seconds
Started Jul 21 05:25:36 PM PDT 24
Finished Jul 21 05:25:37 PM PDT 24
Peak memory 196080 kb
Host smart-9c8c58d6-4e18-46c6-a5aa-8340b19bf6d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002393716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1002393716
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3267405515
Short name T516
Test name
Test status
Simulation time 538072418 ps
CPU time 27.66 seconds
Started Jul 21 05:25:37 PM PDT 24
Finished Jul 21 05:26:05 PM PDT 24
Peak memory 200116 kb
Host smart-f8c26f95-aa80-41e2-b9ec-414bccd377e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267405515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3267405515
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2792088416
Short name T129
Test name
Test status
Simulation time 3119486713 ps
CPU time 41.15 seconds
Started Jul 21 05:25:39 PM PDT 24
Finished Jul 21 05:26:21 PM PDT 24
Peak memory 200156 kb
Host smart-ebdffffa-5bb2-4193-ae50-5b98241735ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792088416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2792088416
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2701588351
Short name T208
Test name
Test status
Simulation time 5152818820 ps
CPU time 1042.13 seconds
Started Jul 21 05:25:39 PM PDT 24
Finished Jul 21 05:43:02 PM PDT 24
Peak memory 770492 kb
Host smart-e97f189f-0c73-4e65-9541-a0302225f432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701588351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2701588351
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.659884892
Short name T320
Test name
Test status
Simulation time 9426877070 ps
CPU time 148.68 seconds
Started Jul 21 05:25:39 PM PDT 24
Finished Jul 21 05:28:08 PM PDT 24
Peak memory 200176 kb
Host smart-2c50fc69-c671-4fa9-b800-82fcf54cc6dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659884892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.659884892
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1724244458
Short name T115
Test name
Test status
Simulation time 2463480340 ps
CPU time 30.98 seconds
Started Jul 21 05:25:41 PM PDT 24
Finished Jul 21 05:26:13 PM PDT 24
Peak memory 200460 kb
Host smart-00a89cbe-ff29-4589-a7a0-1ef3c69d34fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724244458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1724244458
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.325330776
Short name T297
Test name
Test status
Simulation time 73335677 ps
CPU time 1.37 seconds
Started Jul 21 05:25:33 PM PDT 24
Finished Jul 21 05:25:34 PM PDT 24
Peak memory 200192 kb
Host smart-8848b5ff-8b5b-473c-95aa-a184bfaf25b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325330776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.325330776
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1719700986
Short name T61
Test name
Test status
Simulation time 22242274151 ps
CPU time 71.25 seconds
Started Jul 21 05:25:37 PM PDT 24
Finished Jul 21 05:26:49 PM PDT 24
Peak memory 200240 kb
Host smart-b1b884f6-8dc6-4fd2-9600-1b5a932b7cf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719700986 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1719700986
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3788002365
Short name T187
Test name
Test status
Simulation time 4550253760 ps
CPU time 55.93 seconds
Started Jul 21 05:25:39 PM PDT 24
Finished Jul 21 05:26:35 PM PDT 24
Peak memory 200260 kb
Host smart-f424bfed-16c3-4146-af50-33ca02b78e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788002365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3788002365
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3138808304
Short name T323
Test name
Test status
Simulation time 51707277 ps
CPU time 0.59 seconds
Started Jul 21 05:25:51 PM PDT 24
Finished Jul 21 05:25:52 PM PDT 24
Peak memory 196120 kb
Host smart-20f2f05e-882d-4488-9b64-24ad36c71849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138808304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3138808304
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2046444675
Short name T421
Test name
Test status
Simulation time 1009358453 ps
CPU time 62.66 seconds
Started Jul 21 05:25:44 PM PDT 24
Finished Jul 21 05:26:47 PM PDT 24
Peak memory 200168 kb
Host smart-a7feff62-db93-455d-93a1-8fa615f2cd61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046444675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2046444675
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.262835759
Short name T392
Test name
Test status
Simulation time 11063694073 ps
CPU time 34.15 seconds
Started Jul 21 05:25:45 PM PDT 24
Finished Jul 21 05:26:19 PM PDT 24
Peak memory 200272 kb
Host smart-95181c08-1d9c-44b1-b65b-90f0b02ce214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262835759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.262835759
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1537275134
Short name T399
Test name
Test status
Simulation time 1510221792 ps
CPU time 126.5 seconds
Started Jul 21 05:25:45 PM PDT 24
Finished Jul 21 05:27:51 PM PDT 24
Peak memory 567228 kb
Host smart-f0484111-c0bb-4cf9-ac07-1f9887e2fdbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1537275134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1537275134
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3957338556
Short name T380
Test name
Test status
Simulation time 10946959581 ps
CPU time 158.15 seconds
Started Jul 21 05:25:44 PM PDT 24
Finished Jul 21 05:28:22 PM PDT 24
Peak memory 200232 kb
Host smart-2d229cf5-cf5c-43fc-b6e7-08f772fbe3f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957338556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3957338556
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1390016683
Short name T312
Test name
Test status
Simulation time 10760388192 ps
CPU time 121.04 seconds
Started Jul 21 05:25:44 PM PDT 24
Finished Jul 21 05:27:45 PM PDT 24
Peak memory 200308 kb
Host smart-0bbdf2a3-a8ad-4a71-985c-a54aeb6483cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390016683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1390016683
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1889754441
Short name T150
Test name
Test status
Simulation time 418021230 ps
CPU time 1.76 seconds
Started Jul 21 05:25:38 PM PDT 24
Finished Jul 21 05:25:40 PM PDT 24
Peak memory 200200 kb
Host smart-94481ddc-2a29-41f0-a872-7cdd78d3b844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889754441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1889754441
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1803966773
Short name T307
Test name
Test status
Simulation time 18151165200 ps
CPU time 308.27 seconds
Started Jul 21 05:25:51 PM PDT 24
Finished Jul 21 05:31:00 PM PDT 24
Peak memory 200260 kb
Host smart-d6d45506-7906-4d2f-91d5-404a37d663cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803966773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1803966773
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1088716615
Short name T113
Test name
Test status
Simulation time 9563951462 ps
CPU time 84.93 seconds
Started Jul 21 05:25:52 PM PDT 24
Finished Jul 21 05:27:17 PM PDT 24
Peak memory 200212 kb
Host smart-3bb9cc6d-22c4-4cbd-bf56-797f9e43d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088716615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1088716615
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2698459979
Short name T416
Test name
Test status
Simulation time 40873072 ps
CPU time 0.58 seconds
Started Jul 21 05:25:55 PM PDT 24
Finished Jul 21 05:25:56 PM PDT 24
Peak memory 196056 kb
Host smart-cea8cf98-e99c-4b6d-a83c-dbb1ec8ac496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698459979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2698459979
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1780953233
Short name T481
Test name
Test status
Simulation time 1024436881 ps
CPU time 63.01 seconds
Started Jul 21 05:25:49 PM PDT 24
Finished Jul 21 05:26:53 PM PDT 24
Peak memory 200244 kb
Host smart-82e170f1-1465-40ee-a781-79b98279e208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780953233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1780953233
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.145988613
Short name T136
Test name
Test status
Simulation time 859359405 ps
CPU time 24.13 seconds
Started Jul 21 05:25:56 PM PDT 24
Finished Jul 21 05:26:21 PM PDT 24
Peak memory 200180 kb
Host smart-92b039a2-b836-4cda-a7f6-59bf79ffca74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145988613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.145988613
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_error.1352652531
Short name T45
Test name
Test status
Simulation time 5907936236 ps
CPU time 157.05 seconds
Started Jul 21 05:25:55 PM PDT 24
Finished Jul 21 05:28:33 PM PDT 24
Peak memory 200272 kb
Host smart-68a0ef64-2341-46e5-83ff-a8b06fb5d012
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352652531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1352652531
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1397999491
Short name T16
Test name
Test status
Simulation time 6947945665 ps
CPU time 124.8 seconds
Started Jul 21 05:25:50 PM PDT 24
Finished Jul 21 05:27:55 PM PDT 24
Peak memory 200252 kb
Host smart-b760629e-b38d-4783-b7aa-678e1957de74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397999491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1397999491
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2965326782
Short name T59
Test name
Test status
Simulation time 1011783166 ps
CPU time 9 seconds
Started Jul 21 05:25:50 PM PDT 24
Finished Jul 21 05:26:00 PM PDT 24
Peak memory 200076 kb
Host smart-d9fda3d1-df0f-411b-8007-904be6e0d2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965326782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2965326782
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.631232833
Short name T325
Test name
Test status
Simulation time 56785682979 ps
CPU time 460.67 seconds
Started Jul 21 05:25:55 PM PDT 24
Finished Jul 21 05:33:36 PM PDT 24
Peak memory 474344 kb
Host smart-c1df5eba-a82b-4a43-96a7-faa1bcc939c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631232833 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.631232833
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4165325875
Short name T112
Test name
Test status
Simulation time 14252350156 ps
CPU time 39 seconds
Started Jul 21 05:25:55 PM PDT 24
Finished Jul 21 05:26:34 PM PDT 24
Peak memory 200164 kb
Host smart-f8e20369-aafc-461c-b236-deb8e0fa143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165325875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4165325875
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1036967
Short name T352
Test name
Test status
Simulation time 38365190 ps
CPU time 0.59 seconds
Started Jul 21 05:26:14 PM PDT 24
Finished Jul 21 05:26:15 PM PDT 24
Peak memory 196132 kb
Host smart-460bb91a-1161-494f-af39-efbcce2f71e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1036967
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1282324112
Short name T213
Test name
Test status
Simulation time 2750168718 ps
CPU time 42.19 seconds
Started Jul 21 05:26:09 PM PDT 24
Finished Jul 21 05:26:52 PM PDT 24
Peak memory 200240 kb
Host smart-ab2e7216-ebf9-43c4-866e-871043dca25d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1282324112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1282324112
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3784634755
Short name T314
Test name
Test status
Simulation time 1044420087 ps
CPU time 9.62 seconds
Started Jul 21 05:26:09 PM PDT 24
Finished Jul 21 05:26:19 PM PDT 24
Peak memory 200232 kb
Host smart-542bbc49-3276-410a-a490-4ec3efe5c8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784634755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3784634755
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1004073235
Short name T300
Test name
Test status
Simulation time 6533243902 ps
CPU time 1231.59 seconds
Started Jul 21 05:26:09 PM PDT 24
Finished Jul 21 05:46:41 PM PDT 24
Peak memory 781532 kb
Host smart-fce753df-7ddc-4cbb-b60c-f617d86f226e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004073235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1004073235
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.268991420
Short name T388
Test name
Test status
Simulation time 16260328847 ps
CPU time 50.98 seconds
Started Jul 21 05:26:09 PM PDT 24
Finished Jul 21 05:27:00 PM PDT 24
Peak memory 200036 kb
Host smart-b5acf1ae-b6a0-4a5f-a7c4-6cbff11e7064
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268991420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.268991420
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4144494321
Short name T367
Test name
Test status
Simulation time 2234834110 ps
CPU time 135.23 seconds
Started Jul 21 05:26:08 PM PDT 24
Finished Jul 21 05:28:23 PM PDT 24
Peak memory 200232 kb
Host smart-9755cd5d-e7af-44e1-8617-7212fdf98e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144494321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4144494321
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.467531112
Short name T432
Test name
Test status
Simulation time 1000860228 ps
CPU time 11.19 seconds
Started Jul 21 05:25:55 PM PDT 24
Finished Jul 21 05:26:06 PM PDT 24
Peak memory 200184 kb
Host smart-466d1559-9467-4eee-ba78-6fc468edd04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467531112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.467531112
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3054731569
Short name T321
Test name
Test status
Simulation time 4982034843 ps
CPU time 82.8 seconds
Started Jul 21 05:26:08 PM PDT 24
Finished Jul 21 05:27:31 PM PDT 24
Peak memory 200224 kb
Host smart-b0980cc4-9ca3-4d0a-9883-8434da2700c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054731569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3054731569
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2980853439
Short name T258
Test name
Test status
Simulation time 16812792 ps
CPU time 0.58 seconds
Started Jul 21 05:26:13 PM PDT 24
Finished Jul 21 05:26:14 PM PDT 24
Peak memory 196700 kb
Host smart-47032f4e-066a-473b-9a75-efd014b9958f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980853439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2980853439
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1267160957
Short name T265
Test name
Test status
Simulation time 2797112260 ps
CPU time 45 seconds
Started Jul 21 05:26:13 PM PDT 24
Finished Jul 21 05:26:59 PM PDT 24
Peak memory 200304 kb
Host smart-7dab8f21-a5e6-4961-9228-590b176b7a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267160957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1267160957
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1262926992
Short name T233
Test name
Test status
Simulation time 7135797718 ps
CPU time 50.85 seconds
Started Jul 21 05:26:15 PM PDT 24
Finished Jul 21 05:27:06 PM PDT 24
Peak memory 200236 kb
Host smart-5ef44b73-d1f8-49d0-bd87-169765d4f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262926992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1262926992
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3283880508
Short name T197
Test name
Test status
Simulation time 21173948624 ps
CPU time 788.04 seconds
Started Jul 21 05:26:18 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 723628 kb
Host smart-9c7c18c2-407e-49d6-a814-0559fda276de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283880508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3283880508
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.115713016
Short name T427
Test name
Test status
Simulation time 7956498620 ps
CPU time 53.89 seconds
Started Jul 21 05:26:13 PM PDT 24
Finished Jul 21 05:27:07 PM PDT 24
Peak memory 200224 kb
Host smart-835f53aa-efe1-4ea7-8a50-a906b5239cb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115713016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.115713016
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.4013963251
Short name T423
Test name
Test status
Simulation time 4590323660 ps
CPU time 137.12 seconds
Started Jul 21 05:26:13 PM PDT 24
Finished Jul 21 05:28:30 PM PDT 24
Peak memory 200304 kb
Host smart-1172be17-05f6-440e-868f-1db800ea7fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013963251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.4013963251
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.66597090
Short name T180
Test name
Test status
Simulation time 240336984 ps
CPU time 3.64 seconds
Started Jul 21 05:26:14 PM PDT 24
Finished Jul 21 05:26:19 PM PDT 24
Peak memory 200120 kb
Host smart-ae5cc539-71ce-4f56-9e40-1665d10b735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66597090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.66597090
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.897916638
Short name T139
Test name
Test status
Simulation time 66758853638 ps
CPU time 1446.16 seconds
Started Jul 21 05:26:16 PM PDT 24
Finished Jul 21 05:50:23 PM PDT 24
Peak memory 716296 kb
Host smart-53f712fe-4737-4dc5-94d7-311c3f0521c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897916638 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.897916638
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3725202692
Short name T306
Test name
Test status
Simulation time 5847395920 ps
CPU time 57.55 seconds
Started Jul 21 05:26:15 PM PDT 24
Finished Jul 21 05:27:13 PM PDT 24
Peak memory 200300 kb
Host smart-913ac46a-cf8e-4647-9199-5f4b75b5bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725202692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3725202692
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.545314220
Short name T327
Test name
Test status
Simulation time 10969939 ps
CPU time 0.59 seconds
Started Jul 21 05:26:20 PM PDT 24
Finished Jul 21 05:26:21 PM PDT 24
Peak memory 195072 kb
Host smart-1744dcd7-2539-4878-8808-6480f8bd1c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545314220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.545314220
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.163715961
Short name T334
Test name
Test status
Simulation time 2015878796 ps
CPU time 59.49 seconds
Started Jul 21 05:26:14 PM PDT 24
Finished Jul 21 05:27:14 PM PDT 24
Peak memory 200164 kb
Host smart-71c56c25-d31f-4120-8b1a-7e9a55505300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163715961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.163715961
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1009437895
Short name T132
Test name
Test status
Simulation time 530410494 ps
CPU time 30.89 seconds
Started Jul 21 05:26:20 PM PDT 24
Finished Jul 21 05:26:52 PM PDT 24
Peak memory 200120 kb
Host smart-c8e51d0c-175e-4ee9-8941-feaa0d28d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009437895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1009437895
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2418839453
Short name T441
Test name
Test status
Simulation time 20006429212 ps
CPU time 1132.01 seconds
Started Jul 21 05:26:13 PM PDT 24
Finished Jul 21 05:45:06 PM PDT 24
Peak memory 770680 kb
Host smart-9dffdbf0-a459-47e9-8ae0-2683913a8fa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418839453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2418839453
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1587605471
Short name T203
Test name
Test status
Simulation time 5334906907 ps
CPU time 88.17 seconds
Started Jul 21 05:26:20 PM PDT 24
Finished Jul 21 05:27:48 PM PDT 24
Peak memory 200140 kb
Host smart-0a4d7f53-a92b-419e-8a01-8ba8543b18d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587605471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1587605471
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1585338159
Short name T480
Test name
Test status
Simulation time 39066234298 ps
CPU time 204.6 seconds
Started Jul 21 05:26:14 PM PDT 24
Finished Jul 21 05:29:39 PM PDT 24
Peak memory 200196 kb
Host smart-41b26530-86e7-4fb6-a6fa-e8d7a793a82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585338159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1585338159
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.136553121
Short name T369
Test name
Test status
Simulation time 2267371958 ps
CPU time 8.98 seconds
Started Jul 21 05:26:15 PM PDT 24
Finished Jul 21 05:26:24 PM PDT 24
Peak memory 200244 kb
Host smart-529168f3-5b54-44e1-aa41-76142bd78e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136553121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.136553121
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.745071936
Short name T153
Test name
Test status
Simulation time 4449580175 ps
CPU time 11.28 seconds
Started Jul 21 05:26:20 PM PDT 24
Finished Jul 21 05:26:32 PM PDT 24
Peak memory 200304 kb
Host smart-8639c347-6751-4b7b-9592-ba9412d467e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745071936 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.745071936
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4282418648
Short name T507
Test name
Test status
Simulation time 11432738770 ps
CPU time 136.8 seconds
Started Jul 21 05:26:19 PM PDT 24
Finished Jul 21 05:28:37 PM PDT 24
Peak memory 200308 kb
Host smart-5e2ee826-bd1e-44c2-bfeb-fdf71d6f8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282418648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4282418648
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3451572865
Short name T144
Test name
Test status
Simulation time 14412299 ps
CPU time 0.59 seconds
Started Jul 21 05:26:28 PM PDT 24
Finished Jul 21 05:26:30 PM PDT 24
Peak memory 195888 kb
Host smart-af27d133-7f98-418c-b676-a79ab8cb6cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451572865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3451572865
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.4161415037
Short name T365
Test name
Test status
Simulation time 876272919 ps
CPU time 52.54 seconds
Started Jul 21 05:26:25 PM PDT 24
Finished Jul 21 05:27:18 PM PDT 24
Peak memory 200056 kb
Host smart-a1b7d1fd-5204-4364-b4e1-91abf871531f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161415037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4161415037
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4031430102
Short name T339
Test name
Test status
Simulation time 452952771 ps
CPU time 5.74 seconds
Started Jul 21 05:26:27 PM PDT 24
Finished Jul 21 05:26:34 PM PDT 24
Peak memory 200164 kb
Host smart-0fbc0906-5b39-4372-893d-001664a45074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031430102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4031430102
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.227408302
Short name T280
Test name
Test status
Simulation time 4525576327 ps
CPU time 227.75 seconds
Started Jul 21 05:26:27 PM PDT 24
Finished Jul 21 05:30:15 PM PDT 24
Peak memory 458792 kb
Host smart-eed21937-10c9-445d-933f-08a2ddf07ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227408302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.227408302
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1704438578
Short name T332
Test name
Test status
Simulation time 4937191749 ps
CPU time 94.5 seconds
Started Jul 21 05:26:30 PM PDT 24
Finished Jul 21 05:28:07 PM PDT 24
Peak memory 200452 kb
Host smart-b41dab7f-6493-4f44-84e9-5a6460b73b8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704438578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1704438578
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1188176873
Short name T224
Test name
Test status
Simulation time 8321122798 ps
CPU time 144.76 seconds
Started Jul 21 05:26:26 PM PDT 24
Finished Jul 21 05:28:51 PM PDT 24
Peak memory 200248 kb
Host smart-83879d5e-989c-4fd7-8f64-33231e9a9cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188176873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1188176873
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2670586460
Short name T505
Test name
Test status
Simulation time 1821683037 ps
CPU time 2.48 seconds
Started Jul 21 05:26:27 PM PDT 24
Finished Jul 21 05:26:30 PM PDT 24
Peak memory 200176 kb
Host smart-1822a3b8-d1d3-40e1-beea-304d74e31f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670586460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2670586460
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2661036167
Short name T482
Test name
Test status
Simulation time 390135664476 ps
CPU time 2417.17 seconds
Started Jul 21 05:26:28 PM PDT 24
Finished Jul 21 06:06:47 PM PDT 24
Peak memory 794300 kb
Host smart-bb71e9cf-42b3-41bd-a91c-dee5b60b9308
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661036167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2661036167
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4156786313
Short name T254
Test name
Test status
Simulation time 1362321683 ps
CPU time 6.8 seconds
Started Jul 21 05:26:26 PM PDT 24
Finished Jul 21 05:26:33 PM PDT 24
Peak memory 200132 kb
Host smart-e0b83ad6-d3be-485d-88b0-5601b3fbfc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156786313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4156786313
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3297175026
Short name T391
Test name
Test status
Simulation time 14769298 ps
CPU time 0.59 seconds
Started Jul 21 05:26:38 PM PDT 24
Finished Jul 21 05:26:40 PM PDT 24
Peak memory 196004 kb
Host smart-e595de96-3918-4a6e-bde8-39bc0462c443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297175026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3297175026
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1916151501
Short name T7
Test name
Test status
Simulation time 277534902 ps
CPU time 13.02 seconds
Started Jul 21 05:26:33 PM PDT 24
Finished Jul 21 05:26:47 PM PDT 24
Peak memory 200232 kb
Host smart-0ca9cabf-dd80-4565-b4c7-f18e06875a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916151501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1916151501
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3503963453
Short name T167
Test name
Test status
Simulation time 9834189369 ps
CPU time 35.91 seconds
Started Jul 21 05:26:33 PM PDT 24
Finished Jul 21 05:27:10 PM PDT 24
Peak memory 200244 kb
Host smart-71289559-82f2-4c34-9827-41fb9095ed05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503963453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3503963453
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1543370754
Short name T410
Test name
Test status
Simulation time 3063226812 ps
CPU time 133.46 seconds
Started Jul 21 05:26:32 PM PDT 24
Finished Jul 21 05:28:46 PM PDT 24
Peak memory 571476 kb
Host smart-4dfa4ef6-34e8-4284-8d79-e368cdd35054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543370754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1543370754
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4218865434
Short name T498
Test name
Test status
Simulation time 17036697223 ps
CPU time 102 seconds
Started Jul 21 05:26:39 PM PDT 24
Finished Jul 21 05:28:22 PM PDT 24
Peak memory 200036 kb
Host smart-9dd0c4fd-1dda-49ab-a788-27c9cd97fc30
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218865434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4218865434
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1799657604
Short name T499
Test name
Test status
Simulation time 22940933126 ps
CPU time 141.82 seconds
Started Jul 21 05:26:30 PM PDT 24
Finished Jul 21 05:28:54 PM PDT 24
Peak memory 200512 kb
Host smart-e44f1d29-0d72-4fef-8530-c5c0f02ac135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799657604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1799657604
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.249778262
Short name T354
Test name
Test status
Simulation time 19426092 ps
CPU time 0.85 seconds
Started Jul 21 05:26:27 PM PDT 24
Finished Jul 21 05:26:28 PM PDT 24
Peak memory 198896 kb
Host smart-b9bfde6e-383c-4a1e-90ee-45005c7e42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249778262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.249778262
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.767257365
Short name T75
Test name
Test status
Simulation time 86692926860 ps
CPU time 807.86 seconds
Started Jul 21 05:26:36 PM PDT 24
Finished Jul 21 05:40:06 PM PDT 24
Peak memory 208352 kb
Host smart-0d835b13-4dfb-4215-baa4-d0fab9d1592a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767257365 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.767257365
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3947399404
Short name T461
Test name
Test status
Simulation time 1185269850 ps
CPU time 20.13 seconds
Started Jul 21 05:26:36 PM PDT 24
Finished Jul 21 05:26:58 PM PDT 24
Peak memory 200104 kb
Host smart-2b592316-e898-4c21-b7dd-e712931507eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947399404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3947399404
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3954577970
Short name T206
Test name
Test status
Simulation time 36256268 ps
CPU time 0.59 seconds
Started Jul 21 05:23:32 PM PDT 24
Finished Jul 21 05:23:33 PM PDT 24
Peak memory 196112 kb
Host smart-ed162c52-e401-43a6-a11a-6409c12c9de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954577970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3954577970
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3987125782
Short name T447
Test name
Test status
Simulation time 1357630880 ps
CPU time 40.18 seconds
Started Jul 21 05:23:16 PM PDT 24
Finished Jul 21 05:23:56 PM PDT 24
Peak memory 200060 kb
Host smart-a0d4a517-0cd4-4128-9c17-ff1aca79cadd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987125782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3987125782
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2457461873
Short name T353
Test name
Test status
Simulation time 6960173753 ps
CPU time 44.2 seconds
Started Jul 21 05:23:16 PM PDT 24
Finished Jul 21 05:24:01 PM PDT 24
Peak memory 200260 kb
Host smart-49dd9318-4d71-472d-ba9e-66237016d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457461873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2457461873
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1556501232
Short name T322
Test name
Test status
Simulation time 5643900951 ps
CPU time 294.74 seconds
Started Jul 21 05:23:14 PM PDT 24
Finished Jul 21 05:28:09 PM PDT 24
Peak memory 653968 kb
Host smart-194577c3-d511-4cdd-a0ae-856aec36dace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556501232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1556501232
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2480356202
Short name T190
Test name
Test status
Simulation time 3932347523 ps
CPU time 234.89 seconds
Started Jul 21 05:23:19 PM PDT 24
Finished Jul 21 05:27:15 PM PDT 24
Peak memory 200300 kb
Host smart-b09b1898-0111-4523-a573-8c7f455df0df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480356202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2480356202
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1167205244
Short name T152
Test name
Test status
Simulation time 16632028285 ps
CPU time 30.92 seconds
Started Jul 21 05:23:14 PM PDT 24
Finished Jul 21 05:23:45 PM PDT 24
Peak memory 200136 kb
Host smart-7ee25518-3e94-46cd-aeba-3381a7e9b5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167205244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1167205244
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4235418619
Short name T42
Test name
Test status
Simulation time 237739093 ps
CPU time 0.9 seconds
Started Jul 21 05:23:32 PM PDT 24
Finished Jul 21 05:23:33 PM PDT 24
Peak memory 218600 kb
Host smart-169e11a3-be96-48b6-8813-5089c35d62d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235418619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4235418619
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1378957819
Short name T241
Test name
Test status
Simulation time 323147936 ps
CPU time 3.33 seconds
Started Jul 21 05:23:17 PM PDT 24
Finished Jul 21 05:23:21 PM PDT 24
Peak memory 200236 kb
Host smart-729f02f5-6bfa-461f-af4b-78d7d898a256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378957819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1378957819
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3551069174
Short name T69
Test name
Test status
Simulation time 348030792993 ps
CPU time 1009.68 seconds
Started Jul 21 05:23:32 PM PDT 24
Finished Jul 21 05:40:22 PM PDT 24
Peak memory 216152 kb
Host smart-18c3bd89-26f8-486e-9299-8ddfac164364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551069174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3551069174
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1889658437
Short name T8
Test name
Test status
Simulation time 334886302730 ps
CPU time 1289.04 seconds
Started Jul 21 05:23:32 PM PDT 24
Finished Jul 21 05:45:02 PM PDT 24
Peak memory 761192 kb
Host smart-5181eee2-dada-43ea-a07a-34bfe561f301
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889658437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1889658437
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3348302540
Short name T189
Test name
Test status
Simulation time 15019529437 ps
CPU time 71.7 seconds
Started Jul 21 05:23:27 PM PDT 24
Finished Jul 21 05:24:39 PM PDT 24
Peak memory 200256 kb
Host smart-e536344e-189c-4030-8fe0-f38e11eee14b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3348302540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3348302540
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3259446025
Short name T273
Test name
Test status
Simulation time 4746806788 ps
CPU time 57.24 seconds
Started Jul 21 05:23:29 PM PDT 24
Finished Jul 21 05:24:27 PM PDT 24
Peak memory 200236 kb
Host smart-a80e531a-db8d-4a47-a965-33bf7501f569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3259446025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3259446025
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.400616532
Short name T504
Test name
Test status
Simulation time 6358480780 ps
CPU time 122.72 seconds
Started Jul 21 05:23:33 PM PDT 24
Finished Jul 21 05:25:36 PM PDT 24
Peak memory 200144 kb
Host smart-60a68c23-afa6-415c-92f9-8beef1219a57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=400616532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.400616532
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.692156316
Short name T502
Test name
Test status
Simulation time 53302067317 ps
CPU time 674.72 seconds
Started Jul 21 05:23:27 PM PDT 24
Finished Jul 21 05:34:42 PM PDT 24
Peak memory 200196 kb
Host smart-92ca04ce-10de-4a49-bc6a-f366b31243b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=692156316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.692156316
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2064366926
Short name T394
Test name
Test status
Simulation time 40144422625 ps
CPU time 2250.07 seconds
Started Jul 21 05:23:29 PM PDT 24
Finished Jul 21 06:01:00 PM PDT 24
Peak memory 215760 kb
Host smart-aa1e8d58-5bc7-4ac2-9f3f-994fba931926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2064366926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2064366926
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1125752161
Short name T356
Test name
Test status
Simulation time 136831806217 ps
CPU time 2327.5 seconds
Started Jul 21 05:23:26 PM PDT 24
Finished Jul 21 06:02:15 PM PDT 24
Peak memory 216264 kb
Host smart-0296b759-ab06-4ce4-8fd4-0e6132b6e0e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1125752161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1125752161
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1345847915
Short name T495
Test name
Test status
Simulation time 4328723420 ps
CPU time 20.69 seconds
Started Jul 21 05:23:20 PM PDT 24
Finished Jul 21 05:23:41 PM PDT 24
Peak memory 200256 kb
Host smart-8e2d6ced-f9ec-4d7d-a170-7304c9e04c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345847915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1345847915
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1909484339
Short name T226
Test name
Test status
Simulation time 11503111 ps
CPU time 0.57 seconds
Started Jul 21 05:26:52 PM PDT 24
Finished Jul 21 05:26:53 PM PDT 24
Peak memory 195992 kb
Host smart-4d198a2d-cb11-4a90-888e-0bc88c64d0d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909484339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1909484339
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1422431036
Short name T263
Test name
Test status
Simulation time 3268608279 ps
CPU time 48.19 seconds
Started Jul 21 05:26:43 PM PDT 24
Finished Jul 21 05:27:31 PM PDT 24
Peak memory 200272 kb
Host smart-5760620d-fab1-40da-b45b-0f3029b72ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422431036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1422431036
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1304912943
Short name T290
Test name
Test status
Simulation time 1591633129 ps
CPU time 43.45 seconds
Started Jul 21 05:26:42 PM PDT 24
Finished Jul 21 05:27:25 PM PDT 24
Peak memory 200136 kb
Host smart-d351846d-74af-4c8a-9cb2-63f87050c2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304912943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1304912943
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2311651979
Short name T330
Test name
Test status
Simulation time 6991636657 ps
CPU time 410.06 seconds
Started Jul 21 05:26:43 PM PDT 24
Finished Jul 21 05:33:34 PM PDT 24
Peak memory 696324 kb
Host smart-592ef460-2e54-4cb6-8ccf-83d3344901ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311651979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2311651979
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2740892757
Short name T491
Test name
Test status
Simulation time 4489305778 ps
CPU time 59.24 seconds
Started Jul 21 05:26:43 PM PDT 24
Finished Jul 21 05:27:43 PM PDT 24
Peak memory 200136 kb
Host smart-2d2cf9e3-27b8-4971-a02b-3747564a1e1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740892757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2740892757
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2864122973
Short name T517
Test name
Test status
Simulation time 1139683082 ps
CPU time 7.67 seconds
Started Jul 21 05:26:37 PM PDT 24
Finished Jul 21 05:26:46 PM PDT 24
Peak memory 200164 kb
Host smart-b500ce9c-0464-4a2f-8fce-e40b96e279e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864122973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2864122973
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3290434288
Short name T123
Test name
Test status
Simulation time 659767814 ps
CPU time 6.57 seconds
Started Jul 21 05:26:37 PM PDT 24
Finished Jul 21 05:26:45 PM PDT 24
Peak memory 200188 kb
Host smart-7a58f83d-dc05-4898-b7fe-8c617da7d530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290434288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3290434288
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.779590308
Short name T234
Test name
Test status
Simulation time 219921182934 ps
CPU time 775.92 seconds
Started Jul 21 05:26:50 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 216636 kb
Host smart-a462bff3-253e-4ab3-8b7e-375d63dec360
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779590308 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.779590308
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1194591862
Short name T422
Test name
Test status
Simulation time 1373048366 ps
CPU time 5.59 seconds
Started Jul 21 05:26:52 PM PDT 24
Finished Jul 21 05:26:58 PM PDT 24
Peak memory 200184 kb
Host smart-e32afa7f-cfa4-44c8-8960-a555897586dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194591862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1194591862
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2847959253
Short name T232
Test name
Test status
Simulation time 28152301 ps
CPU time 0.61 seconds
Started Jul 21 05:26:55 PM PDT 24
Finished Jul 21 05:26:56 PM PDT 24
Peak memory 196140 kb
Host smart-65ab6e30-8015-4089-9f9c-ff7f04b0682d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847959253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2847959253
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1463197016
Short name T212
Test name
Test status
Simulation time 320971381 ps
CPU time 9.06 seconds
Started Jul 21 05:26:56 PM PDT 24
Finished Jul 21 05:27:06 PM PDT 24
Peak memory 200256 kb
Host smart-9da30321-e4ee-44b8-80be-41106405f44f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463197016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1463197016
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1552425766
Short name T157
Test name
Test status
Simulation time 681892760 ps
CPU time 3.72 seconds
Started Jul 21 05:26:55 PM PDT 24
Finished Jul 21 05:26:59 PM PDT 24
Peak memory 200180 kb
Host smart-7a3d79bb-929c-4065-9d5c-7d8867829924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552425766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1552425766
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2716429528
Short name T522
Test name
Test status
Simulation time 6271373758 ps
CPU time 1029.58 seconds
Started Jul 21 05:26:55 PM PDT 24
Finished Jul 21 05:44:05 PM PDT 24
Peak memory 669180 kb
Host smart-0f93a8b3-8bc9-464d-899b-ef3e57429a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716429528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2716429528
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2820174529
Short name T336
Test name
Test status
Simulation time 648407845 ps
CPU time 33.3 seconds
Started Jul 21 05:26:56 PM PDT 24
Finished Jul 21 05:27:29 PM PDT 24
Peak memory 200188 kb
Host smart-c944350d-22d6-436d-a76b-406e97898cbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820174529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2820174529
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3412575412
Short name T347
Test name
Test status
Simulation time 22695255085 ps
CPU time 145.91 seconds
Started Jul 21 05:26:57 PM PDT 24
Finished Jul 21 05:29:23 PM PDT 24
Peak memory 216488 kb
Host smart-4672168d-1b06-4de5-97b8-2e5165689f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412575412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3412575412
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3575769824
Short name T484
Test name
Test status
Simulation time 1010564991 ps
CPU time 13.83 seconds
Started Jul 21 05:26:50 PM PDT 24
Finished Jul 21 05:27:04 PM PDT 24
Peak memory 200056 kb
Host smart-6280afa6-42c9-44e4-8a0f-4c8feeefa2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575769824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3575769824
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.488045374
Short name T207
Test name
Test status
Simulation time 518998451901 ps
CPU time 565.43 seconds
Started Jul 21 05:26:55 PM PDT 24
Finished Jul 21 05:36:21 PM PDT 24
Peak memory 660084 kb
Host smart-6b16b925-755f-4006-8de0-deff87e9d98a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488045374 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.488045374
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3361045679
Short name T204
Test name
Test status
Simulation time 7416784543 ps
CPU time 90.42 seconds
Started Jul 21 05:26:55 PM PDT 24
Finished Jul 21 05:28:25 PM PDT 24
Peak memory 200184 kb
Host smart-72ea44d3-f534-40a3-a6b1-12c1bbe4003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361045679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3361045679
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.4150536458
Short name T350
Test name
Test status
Simulation time 22573825 ps
CPU time 0.58 seconds
Started Jul 21 05:27:07 PM PDT 24
Finished Jul 21 05:27:08 PM PDT 24
Peak memory 196136 kb
Host smart-0e53414a-9ad6-4c63-b46d-c60be0892766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150536458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.4150536458
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1378706732
Short name T340
Test name
Test status
Simulation time 5987414411 ps
CPU time 62.44 seconds
Started Jul 21 05:27:04 PM PDT 24
Finished Jul 21 05:28:07 PM PDT 24
Peak memory 200204 kb
Host smart-01f385ad-d65d-4501-b50e-dd8917f32b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378706732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1378706732
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1249726009
Short name T131
Test name
Test status
Simulation time 7755158410 ps
CPU time 79.96 seconds
Started Jul 21 05:27:07 PM PDT 24
Finished Jul 21 05:28:27 PM PDT 24
Peak memory 200276 kb
Host smart-f1b3e859-ccaa-49de-92c1-0f0685bf5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249726009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1249726009
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1279443587
Short name T311
Test name
Test status
Simulation time 8717254659 ps
CPU time 816.87 seconds
Started Jul 21 05:27:01 PM PDT 24
Finished Jul 21 05:40:38 PM PDT 24
Peak memory 515756 kb
Host smart-a3a31b32-3d4d-4d66-9413-5f45d30b36af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279443587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1279443587
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4230798856
Short name T210
Test name
Test status
Simulation time 15750065529 ps
CPU time 200.2 seconds
Started Jul 21 05:27:07 PM PDT 24
Finished Jul 21 05:30:28 PM PDT 24
Peak memory 200120 kb
Host smart-c81a0f00-80e0-4ed2-8a81-1ec0ba941e81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230798856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4230798856
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1061307133
Short name T405
Test name
Test status
Simulation time 1305952482 ps
CPU time 67.63 seconds
Started Jul 21 05:26:55 PM PDT 24
Finished Jul 21 05:28:03 PM PDT 24
Peak memory 200128 kb
Host smart-e8b571d4-a500-40f6-82d8-2fdf8e8f7231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061307133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1061307133
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4001563241
Short name T390
Test name
Test status
Simulation time 242707127 ps
CPU time 4.71 seconds
Started Jul 21 05:26:57 PM PDT 24
Finished Jul 21 05:27:02 PM PDT 24
Peak memory 200144 kb
Host smart-ff3e5cd0-a704-4c26-a8ad-4bfd4e49ba64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001563241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4001563241
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1651203352
Short name T235
Test name
Test status
Simulation time 3945173878 ps
CPU time 31.2 seconds
Started Jul 21 05:27:07 PM PDT 24
Finished Jul 21 05:27:39 PM PDT 24
Peak memory 200160 kb
Host smart-41e4edf0-a159-4fb9-9a26-4d6fa571b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651203352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1651203352
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2152052008
Short name T393
Test name
Test status
Simulation time 14837130 ps
CPU time 0.59 seconds
Started Jul 21 05:27:14 PM PDT 24
Finished Jul 21 05:27:15 PM PDT 24
Peak memory 196816 kb
Host smart-c0ddee04-d0f8-432c-976e-d676dd1cc068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152052008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2152052008
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2673569843
Short name T515
Test name
Test status
Simulation time 1941325590 ps
CPU time 58.27 seconds
Started Jul 21 05:27:10 PM PDT 24
Finished Jul 21 05:28:08 PM PDT 24
Peak memory 200220 kb
Host smart-99645daa-2c7b-4cb7-a44c-0fdcbbd2031b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2673569843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2673569843
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1258748994
Short name T286
Test name
Test status
Simulation time 11918049345 ps
CPU time 40.17 seconds
Started Jul 21 05:27:14 PM PDT 24
Finished Jul 21 05:27:55 PM PDT 24
Peak memory 200200 kb
Host smart-1bfa1ab9-258a-4f84-9983-9e6b6c0efa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258748994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1258748994
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3268345253
Short name T161
Test name
Test status
Simulation time 1120400180 ps
CPU time 169.01 seconds
Started Jul 21 05:27:14 PM PDT 24
Finished Jul 21 05:30:03 PM PDT 24
Peak memory 468760 kb
Host smart-21b914b4-a9ab-40e7-b314-f3229fed0fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268345253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3268345253
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1763470107
Short name T32
Test name
Test status
Simulation time 5362980573 ps
CPU time 145.15 seconds
Started Jul 21 05:27:13 PM PDT 24
Finished Jul 21 05:29:39 PM PDT 24
Peak memory 200300 kb
Host smart-b78aed0e-b3c3-4ece-ba07-3e5fa5967e02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763470107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1763470107
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4255983887
Short name T283
Test name
Test status
Simulation time 9300929092 ps
CPU time 131.48 seconds
Started Jul 21 05:27:08 PM PDT 24
Finished Jul 21 05:29:20 PM PDT 24
Peak memory 200268 kb
Host smart-24a8565a-948d-4e90-9216-93386bba2b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255983887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4255983887
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.4221164578
Short name T456
Test name
Test status
Simulation time 4311569360 ps
CPU time 13.59 seconds
Started Jul 21 05:27:08 PM PDT 24
Finished Jul 21 05:27:22 PM PDT 24
Peak memory 200232 kb
Host smart-57d45902-d7e4-4233-89c4-86ebb19c3db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221164578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.4221164578
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.377877900
Short name T431
Test name
Test status
Simulation time 109369470863 ps
CPU time 1713.77 seconds
Started Jul 21 05:27:14 PM PDT 24
Finished Jul 21 05:55:48 PM PDT 24
Peak memory 753552 kb
Host smart-00125dbb-6e94-4061-b751-cd061e7239fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377877900 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.377877900
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1777851218
Short name T274
Test name
Test status
Simulation time 3581430468 ps
CPU time 91.01 seconds
Started Jul 21 05:27:14 PM PDT 24
Finished Jul 21 05:28:45 PM PDT 24
Peak memory 200276 kb
Host smart-ded6b67d-10c5-40d2-9813-b480022ed456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777851218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1777851218
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1985104473
Short name T512
Test name
Test status
Simulation time 76091595 ps
CPU time 0.55 seconds
Started Jul 21 05:27:20 PM PDT 24
Finished Jul 21 05:27:20 PM PDT 24
Peak memory 195764 kb
Host smart-fae74d7f-3ee5-44cf-b5e6-73049dbb1731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985104473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1985104473
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3582216346
Short name T368
Test name
Test status
Simulation time 5061565745 ps
CPU time 21.42 seconds
Started Jul 21 05:27:21 PM PDT 24
Finished Jul 21 05:27:42 PM PDT 24
Peak memory 200232 kb
Host smart-092f6071-3d3a-4ea8-bb21-907d2c3f02d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582216346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3582216346
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3413079660
Short name T266
Test name
Test status
Simulation time 37522112109 ps
CPU time 34.08 seconds
Started Jul 21 05:27:21 PM PDT 24
Finished Jul 21 05:27:56 PM PDT 24
Peak memory 200132 kb
Host smart-c1ef5bd6-b456-43aa-81d7-286867888dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413079660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3413079660
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.903782458
Short name T385
Test name
Test status
Simulation time 4892499122 ps
CPU time 906.13 seconds
Started Jul 21 05:27:21 PM PDT 24
Finished Jul 21 05:42:28 PM PDT 24
Peak memory 730348 kb
Host smart-f18f2108-4515-4ef4-b528-b4c5781ab165
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903782458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.903782458
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2159627178
Short name T440
Test name
Test status
Simulation time 1855816198 ps
CPU time 99.14 seconds
Started Jul 21 05:27:21 PM PDT 24
Finished Jul 21 05:29:01 PM PDT 24
Peak memory 200160 kb
Host smart-3400bec2-9ff2-4606-9569-3d4ef964de22
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159627178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2159627178
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.24294205
Short name T376
Test name
Test status
Simulation time 10255818866 ps
CPU time 169.8 seconds
Started Jul 21 05:27:25 PM PDT 24
Finished Jul 21 05:30:15 PM PDT 24
Peak memory 200264 kb
Host smart-9429885b-504a-452d-823c-cdc838c307df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24294205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.24294205
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.471775560
Short name T292
Test name
Test status
Simulation time 440266334 ps
CPU time 7.87 seconds
Started Jul 21 05:27:14 PM PDT 24
Finished Jul 21 05:27:22 PM PDT 24
Peak memory 200192 kb
Host smart-a3910c3b-221e-43d0-89f7-855269aeb1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471775560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.471775560
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1280023528
Short name T22
Test name
Test status
Simulation time 38202389269 ps
CPU time 516.48 seconds
Started Jul 21 05:27:21 PM PDT 24
Finished Jul 21 05:35:58 PM PDT 24
Peak memory 208408 kb
Host smart-bd9f8899-c722-4635-bfe8-26d50538828a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280023528 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1280023528
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2214933495
Short name T108
Test name
Test status
Simulation time 1821797835 ps
CPU time 93.64 seconds
Started Jul 21 05:27:21 PM PDT 24
Finished Jul 21 05:28:55 PM PDT 24
Peak memory 200120 kb
Host smart-b8a6999e-c56d-43fe-b928-3eed0cf36972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214933495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2214933495
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1886986592
Short name T428
Test name
Test status
Simulation time 47022213 ps
CPU time 0.63 seconds
Started Jul 21 05:27:27 PM PDT 24
Finished Jul 21 05:27:27 PM PDT 24
Peak memory 196144 kb
Host smart-bfe2f0d6-56b8-4c7b-b846-fa646318baa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886986592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1886986592
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3017443423
Short name T387
Test name
Test status
Simulation time 4060997078 ps
CPU time 61.57 seconds
Started Jul 21 05:27:27 PM PDT 24
Finished Jul 21 05:28:29 PM PDT 24
Peak memory 216388 kb
Host smart-a869a49b-ddc1-46ee-bac8-e325334f2837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017443423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3017443423
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.665311252
Short name T288
Test name
Test status
Simulation time 8640487508 ps
CPU time 61.61 seconds
Started Jul 21 05:27:27 PM PDT 24
Finished Jul 21 05:28:29 PM PDT 24
Peak memory 200204 kb
Host smart-72905a88-1d2f-4e06-84ab-79c98963b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665311252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.665311252
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.883650178
Short name T143
Test name
Test status
Simulation time 4080928248 ps
CPU time 829.1 seconds
Started Jul 21 05:27:26 PM PDT 24
Finished Jul 21 05:41:15 PM PDT 24
Peak memory 679492 kb
Host smart-d43e5201-4ac2-4d58-8e1a-1a03cab9a1b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883650178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.883650178
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.862824678
Short name T477
Test name
Test status
Simulation time 4538823600 ps
CPU time 47.06 seconds
Started Jul 21 05:27:26 PM PDT 24
Finished Jul 21 05:28:13 PM PDT 24
Peak memory 200132 kb
Host smart-fe561c66-b3e6-47c6-b8ec-7a1776f0ef5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862824678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.862824678
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1549711648
Short name T259
Test name
Test status
Simulation time 304776907 ps
CPU time 7.6 seconds
Started Jul 21 05:27:26 PM PDT 24
Finished Jul 21 05:27:34 PM PDT 24
Peak memory 200184 kb
Host smart-e85c0a3e-5c73-4d0c-b889-ca5b9e117264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549711648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1549711648
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.70831957
Short name T444
Test name
Test status
Simulation time 1521183240 ps
CPU time 6.01 seconds
Started Jul 21 05:27:28 PM PDT 24
Finished Jul 21 05:27:34 PM PDT 24
Peak memory 200164 kb
Host smart-42894765-e897-40c7-967a-f8585239a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70831957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.70831957
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2047182407
Short name T472
Test name
Test status
Simulation time 60369776139 ps
CPU time 1794.85 seconds
Started Jul 21 05:27:25 PM PDT 24
Finished Jul 21 05:57:21 PM PDT 24
Peak memory 707608 kb
Host smart-7b50d5f3-e0a8-4706-8ef3-41b91e0c5610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047182407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2047182407
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1214776445
Short name T142
Test name
Test status
Simulation time 315733623 ps
CPU time 4.33 seconds
Started Jul 21 05:27:26 PM PDT 24
Finished Jul 21 05:27:31 PM PDT 24
Peak memory 200204 kb
Host smart-f2d2eecb-c365-42d7-8f0c-dcde9a339b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214776445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1214776445
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4281194183
Short name T194
Test name
Test status
Simulation time 105872379 ps
CPU time 0.59 seconds
Started Jul 21 05:27:34 PM PDT 24
Finished Jul 21 05:27:35 PM PDT 24
Peak memory 195056 kb
Host smart-cb4bba79-ff5b-4701-8def-8611a6bd43ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281194183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4281194183
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2593043406
Short name T467
Test name
Test status
Simulation time 1120638282 ps
CPU time 33.98 seconds
Started Jul 21 05:27:31 PM PDT 24
Finished Jul 21 05:28:06 PM PDT 24
Peak memory 200208 kb
Host smart-2314474c-e69c-4ef5-baac-12c0c658ab9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593043406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2593043406
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3349961153
Short name T238
Test name
Test status
Simulation time 712558173 ps
CPU time 3.8 seconds
Started Jul 21 05:27:32 PM PDT 24
Finished Jul 21 05:27:37 PM PDT 24
Peak memory 200168 kb
Host smart-8ae3f255-cf03-43e7-b7f3-0cb8376ea618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349961153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3349961153
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1842349460
Short name T198
Test name
Test status
Simulation time 8334517702 ps
CPU time 483.01 seconds
Started Jul 21 05:27:33 PM PDT 24
Finished Jul 21 05:35:36 PM PDT 24
Peak memory 679544 kb
Host smart-4a1abd62-f146-4146-a10c-795ae6a557bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1842349460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1842349460
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1497576302
Short name T15
Test name
Test status
Simulation time 10499635487 ps
CPU time 28.64 seconds
Started Jul 21 05:27:33 PM PDT 24
Finished Jul 21 05:28:02 PM PDT 24
Peak memory 200128 kb
Host smart-a94fb3d6-68d5-488a-9827-4dda134611e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497576302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1497576302
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.504916932
Short name T445
Test name
Test status
Simulation time 1338481658 ps
CPU time 9.56 seconds
Started Jul 21 05:27:32 PM PDT 24
Finished Jul 21 05:27:42 PM PDT 24
Peak memory 200000 kb
Host smart-f9d7e32b-d2bc-4da4-a7c2-083a3abca957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504916932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.504916932
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2508787728
Short name T186
Test name
Test status
Simulation time 2664186492 ps
CPU time 8.5 seconds
Started Jul 21 05:27:25 PM PDT 24
Finished Jul 21 05:27:34 PM PDT 24
Peak memory 200248 kb
Host smart-572b1dfb-e5f9-4de0-9d4f-153fe765151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508787728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2508787728
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1104365334
Short name T68
Test name
Test status
Simulation time 151033298706 ps
CPU time 2079.54 seconds
Started Jul 21 05:27:32 PM PDT 24
Finished Jul 21 06:02:12 PM PDT 24
Peak memory 793800 kb
Host smart-cbdda086-0a40-4a38-a450-98b4a5691a28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104365334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1104365334
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2341260474
Short name T268
Test name
Test status
Simulation time 2663648428 ps
CPU time 92.76 seconds
Started Jul 21 05:27:33 PM PDT 24
Finished Jul 21 05:29:07 PM PDT 24
Peak memory 200516 kb
Host smart-55ec4410-27ce-48df-af8c-68f40b4040af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341260474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2341260474
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1576403114
Short name T452
Test name
Test status
Simulation time 116928932 ps
CPU time 0.58 seconds
Started Jul 21 05:27:40 PM PDT 24
Finished Jul 21 05:27:40 PM PDT 24
Peak memory 195756 kb
Host smart-aaa3f2b9-f8c3-4dc5-8bf5-93f79626d3cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576403114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1576403114
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3940900633
Short name T412
Test name
Test status
Simulation time 5491934858 ps
CPU time 78.19 seconds
Started Jul 21 05:27:40 PM PDT 24
Finished Jul 21 05:28:59 PM PDT 24
Peak memory 208332 kb
Host smart-cf727211-b459-4865-8aa1-a33c6eb84a2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940900633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3940900633
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.631601714
Short name T411
Test name
Test status
Simulation time 2163555991 ps
CPU time 55.77 seconds
Started Jul 21 05:27:40 PM PDT 24
Finished Jul 21 05:28:36 PM PDT 24
Peak memory 200264 kb
Host smart-d1a91ae0-ff59-4628-a161-3f53f905491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631601714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.631601714
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.4294801179
Short name T500
Test name
Test status
Simulation time 5467333839 ps
CPU time 600.08 seconds
Started Jul 21 05:27:39 PM PDT 24
Finished Jul 21 05:37:40 PM PDT 24
Peak memory 650132 kb
Host smart-a5812ced-5c45-4b22-826a-e0fc4ee3788c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294801179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.4294801179
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1563879165
Short name T425
Test name
Test status
Simulation time 2459011099 ps
CPU time 101.86 seconds
Started Jul 21 05:27:43 PM PDT 24
Finished Jul 21 05:29:26 PM PDT 24
Peak memory 200448 kb
Host smart-dd832412-5f20-4c55-b37e-e25adc748d51
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563879165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1563879165
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2265139381
Short name T196
Test name
Test status
Simulation time 11077636841 ps
CPU time 174.38 seconds
Started Jul 21 05:27:39 PM PDT 24
Finished Jul 21 05:30:34 PM PDT 24
Peak memory 200208 kb
Host smart-96c78672-22f1-41a3-897f-a30e04869c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265139381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2265139381
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.665931324
Short name T166
Test name
Test status
Simulation time 968769808 ps
CPU time 11.35 seconds
Started Jul 21 05:27:38 PM PDT 24
Finished Jul 21 05:27:50 PM PDT 24
Peak memory 200140 kb
Host smart-6f3ae76d-fd6a-4d05-8f13-ab93c61452ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665931324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.665931324
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3819352344
Short name T406
Test name
Test status
Simulation time 145613783605 ps
CPU time 2145.14 seconds
Started Jul 21 05:27:39 PM PDT 24
Finished Jul 21 06:03:24 PM PDT 24
Peak memory 738456 kb
Host smart-1f49b650-f586-414f-98bc-48895aba6dbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819352344 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3819352344
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3379531287
Short name T80
Test name
Test status
Simulation time 8632136119 ps
CPU time 62.13 seconds
Started Jul 21 05:27:40 PM PDT 24
Finished Jul 21 05:28:42 PM PDT 24
Peak memory 200244 kb
Host smart-6a63c812-925a-4b5e-ab2c-1e4fdc89da60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379531287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3379531287
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.749778693
Short name T173
Test name
Test status
Simulation time 14262191 ps
CPU time 0.57 seconds
Started Jul 21 05:27:45 PM PDT 24
Finished Jul 21 05:27:46 PM PDT 24
Peak memory 194980 kb
Host smart-dce6ccfd-055c-4f03-a14c-9dfc471edf47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749778693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.749778693
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2426341433
Short name T159
Test name
Test status
Simulation time 5907747179 ps
CPU time 91.66 seconds
Started Jul 21 05:27:45 PM PDT 24
Finished Jul 21 05:29:17 PM PDT 24
Peak memory 215884 kb
Host smart-d92945fb-183f-488e-8c4e-4cbc543a2698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426341433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2426341433
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3265297093
Short name T492
Test name
Test status
Simulation time 19433803 ps
CPU time 0.71 seconds
Started Jul 21 05:27:47 PM PDT 24
Finished Jul 21 05:27:48 PM PDT 24
Peak memory 196768 kb
Host smart-45bea177-1349-47cc-a8b2-6856ebcdaf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265297093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3265297093
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2404534449
Short name T511
Test name
Test status
Simulation time 6504719423 ps
CPU time 528.4 seconds
Started Jul 21 05:27:47 PM PDT 24
Finished Jul 21 05:36:36 PM PDT 24
Peak memory 666032 kb
Host smart-80045f9f-57b7-465c-afa8-f2afe73575b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404534449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2404534449
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3967997269
Short name T183
Test name
Test status
Simulation time 6756017710 ps
CPU time 116.37 seconds
Started Jul 21 05:27:45 PM PDT 24
Finished Jul 21 05:29:41 PM PDT 24
Peak memory 200280 kb
Host smart-51ee1ef9-cff7-4279-8f9f-6eb7e647859c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967997269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3967997269
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1978777378
Short name T195
Test name
Test status
Simulation time 3527666448 ps
CPU time 105.11 seconds
Started Jul 21 05:27:40 PM PDT 24
Finished Jul 21 05:29:26 PM PDT 24
Peak memory 200284 kb
Host smart-cfb9054e-f64d-40e6-953d-251e78118eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978777378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1978777378
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1521249554
Short name T433
Test name
Test status
Simulation time 702837376 ps
CPU time 6.88 seconds
Started Jul 21 05:27:40 PM PDT 24
Finished Jul 21 05:27:47 PM PDT 24
Peak memory 200204 kb
Host smart-58ba53c8-d48b-42bf-a023-a79232e4244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521249554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1521249554
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.919957993
Short name T348
Test name
Test status
Simulation time 148496444025 ps
CPU time 2579.44 seconds
Started Jul 21 05:27:44 PM PDT 24
Finished Jul 21 06:10:44 PM PDT 24
Peak memory 741504 kb
Host smart-5edcbdd1-1cb0-47c3-a775-74deeb52b000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919957993 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.919957993
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2821424075
Short name T149
Test name
Test status
Simulation time 3481509685 ps
CPU time 20.96 seconds
Started Jul 21 05:27:45 PM PDT 24
Finished Jul 21 05:28:06 PM PDT 24
Peak memory 200256 kb
Host smart-dcf64c84-900d-47fc-8568-d2bf8ab130fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821424075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2821424075
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3355842957
Short name T398
Test name
Test status
Simulation time 11100724 ps
CPU time 0.58 seconds
Started Jul 21 05:27:50 PM PDT 24
Finished Jul 21 05:27:52 PM PDT 24
Peak memory 195096 kb
Host smart-7dd2ab1c-ef6c-46e5-9830-71270fec8f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355842957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3355842957
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2313403103
Short name T364
Test name
Test status
Simulation time 3207848146 ps
CPU time 100.75 seconds
Started Jul 21 05:27:51 PM PDT 24
Finished Jul 21 05:29:32 PM PDT 24
Peak memory 216544 kb
Host smart-9005c3ca-b805-49c8-89b1-2f057ecdcc72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313403103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2313403103
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2663975201
Short name T374
Test name
Test status
Simulation time 4850668232 ps
CPU time 69.78 seconds
Started Jul 21 05:27:52 PM PDT 24
Finished Jul 21 05:29:03 PM PDT 24
Peak memory 200276 kb
Host smart-af91b0a4-dcf0-400a-b691-9cb573ea09b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663975201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2663975201
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3615934118
Short name T178
Test name
Test status
Simulation time 298290357 ps
CPU time 49.51 seconds
Started Jul 21 05:27:51 PM PDT 24
Finished Jul 21 05:28:41 PM PDT 24
Peak memory 318428 kb
Host smart-3606a2b3-9e8e-4659-9e26-559cbef6701e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615934118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3615934118
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3028059295
Short name T228
Test name
Test status
Simulation time 7293287915 ps
CPU time 64.73 seconds
Started Jul 21 05:27:53 PM PDT 24
Finished Jul 21 05:28:58 PM PDT 24
Peak memory 200200 kb
Host smart-7bca64cd-40c8-487f-9cb8-d263407b7be4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028059295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3028059295
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1966230772
Short name T220
Test name
Test status
Simulation time 3445102623 ps
CPU time 50.71 seconds
Started Jul 21 05:27:51 PM PDT 24
Finished Jul 21 05:28:42 PM PDT 24
Peak memory 200260 kb
Host smart-af43eb4f-1fd0-4541-ae8a-debe99399595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966230772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1966230772
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2409349125
Short name T242
Test name
Test status
Simulation time 149385951 ps
CPU time 1.72 seconds
Started Jul 21 05:27:50 PM PDT 24
Finished Jul 21 05:27:52 PM PDT 24
Peak memory 200168 kb
Host smart-a81d6831-7ffa-40f8-9ebd-b08527fdaec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409349125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2409349125
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4131377224
Short name T133
Test name
Test status
Simulation time 6964850621 ps
CPU time 403.83 seconds
Started Jul 21 05:27:52 PM PDT 24
Finished Jul 21 05:34:36 PM PDT 24
Peak memory 216624 kb
Host smart-720c905c-32f9-4208-b9d9-6424e88c2be1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131377224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4131377224
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3659628819
Short name T164
Test name
Test status
Simulation time 3521931059 ps
CPU time 12.69 seconds
Started Jul 21 05:27:50 PM PDT 24
Finished Jul 21 05:28:03 PM PDT 24
Peak memory 200212 kb
Host smart-c8f2da51-5439-4dba-85a8-8ffe71e55189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659628819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3659628819
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3512680843
Short name T188
Test name
Test status
Simulation time 36389355 ps
CPU time 0.56 seconds
Started Jul 21 05:24:00 PM PDT 24
Finished Jul 21 05:24:01 PM PDT 24
Peak memory 195788 kb
Host smart-4d6ff590-921c-4f2b-b93c-322915164997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512680843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3512680843
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.605930710
Short name T501
Test name
Test status
Simulation time 1088973051 ps
CPU time 59.65 seconds
Started Jul 21 05:23:31 PM PDT 24
Finished Jul 21 05:24:31 PM PDT 24
Peak memory 200160 kb
Host smart-fff163f7-01d5-4d9b-973f-7cba98eef1ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=605930710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.605930710
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3224708348
Short name T193
Test name
Test status
Simulation time 17903387146 ps
CPU time 74.34 seconds
Started Jul 21 05:23:41 PM PDT 24
Finished Jul 21 05:24:55 PM PDT 24
Peak memory 200304 kb
Host smart-12ef0e48-2995-4092-b36f-a987773f46a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224708348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3224708348
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3958208366
Short name T414
Test name
Test status
Simulation time 9682443308 ps
CPU time 386.78 seconds
Started Jul 21 05:23:37 PM PDT 24
Finished Jul 21 05:30:05 PM PDT 24
Peak memory 482240 kb
Host smart-0dff5ebe-b991-41cd-b875-bd178e7f6d46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958208366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3958208366
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2430030364
Short name T181
Test name
Test status
Simulation time 11228794952 ps
CPU time 50.31 seconds
Started Jul 21 05:23:44 PM PDT 24
Finished Jul 21 05:24:35 PM PDT 24
Peak memory 200100 kb
Host smart-eea1e193-d034-4dcc-ac91-fbdfdcce13e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430030364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2430030364
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1632855976
Short name T155
Test name
Test status
Simulation time 23762751309 ps
CPU time 188.57 seconds
Started Jul 21 05:23:33 PM PDT 24
Finished Jul 21 05:26:42 PM PDT 24
Peak memory 208408 kb
Host smart-c4424476-c917-4534-904f-5e2c144d7d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632855976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1632855976
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1613412767
Short name T41
Test name
Test status
Simulation time 219512524 ps
CPU time 0.93 seconds
Started Jul 21 05:24:00 PM PDT 24
Finished Jul 21 05:24:01 PM PDT 24
Peak memory 218512 kb
Host smart-a1d2d29c-cb80-4b04-a996-bcad99a32eec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613412767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1613412767
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1314427909
Short name T168
Test name
Test status
Simulation time 1202107009 ps
CPU time 7.37 seconds
Started Jul 21 05:23:33 PM PDT 24
Finished Jul 21 05:23:41 PM PDT 24
Peak memory 200080 kb
Host smart-38d1d756-443a-4a7a-b4a2-c2b86023b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314427909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1314427909
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1246555312
Short name T81
Test name
Test status
Simulation time 18980331522 ps
CPU time 2331.03 seconds
Started Jul 21 05:23:55 PM PDT 24
Finished Jul 21 06:02:47 PM PDT 24
Peak memory 772472 kb
Host smart-6457ecb7-20e5-4595-b8e1-33538600f472
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246555312 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1246555312
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3231167149
Short name T34
Test name
Test status
Simulation time 108322485405 ps
CPU time 1942.92 seconds
Started Jul 21 05:23:55 PM PDT 24
Finished Jul 21 05:56:18 PM PDT 24
Peak memory 706768 kb
Host smart-fb06a221-05d9-4f69-82e2-ef6268873f70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231167149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3231167149
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1602051622
Short name T140
Test name
Test status
Simulation time 8703480779 ps
CPU time 53.42 seconds
Started Jul 21 05:23:48 PM PDT 24
Finished Jul 21 05:24:42 PM PDT 24
Peak memory 200260 kb
Host smart-d682c8ee-e0f7-4d9a-a0e9-bceff24f65c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1602051622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1602051622
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.284822068
Short name T451
Test name
Test status
Simulation time 9708389759 ps
CPU time 87 seconds
Started Jul 21 05:23:49 PM PDT 24
Finished Jul 21 05:25:17 PM PDT 24
Peak memory 200316 kb
Host smart-de8c15ac-5925-4fa1-926a-dfbd7f9a3b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=284822068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.284822068
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.71785695
Short name T86
Test name
Test status
Simulation time 26154012020 ps
CPU time 78.94 seconds
Started Jul 21 05:23:54 PM PDT 24
Finished Jul 21 05:25:13 PM PDT 24
Peak memory 200144 kb
Host smart-513b3440-974f-409d-ab42-924ca71a0094
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=71785695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.71785695
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1518058473
Short name T125
Test name
Test status
Simulation time 49637591445 ps
CPU time 529.16 seconds
Started Jul 21 05:23:49 PM PDT 24
Finished Jul 21 05:32:39 PM PDT 24
Peak memory 200256 kb
Host smart-ab125c1f-a967-4d97-bf79-718cc50b6aaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1518058473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1518058473
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3236760217
Short name T291
Test name
Test status
Simulation time 739374855876 ps
CPU time 2416.96 seconds
Started Jul 21 05:23:47 PM PDT 24
Finished Jul 21 06:04:05 PM PDT 24
Peak memory 215736 kb
Host smart-4d42794e-f24f-4bc6-a5f5-f7f9215e0509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3236760217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3236760217
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.602309738
Short name T309
Test name
Test status
Simulation time 498953819007 ps
CPU time 2372.62 seconds
Started Jul 21 05:23:49 PM PDT 24
Finished Jul 21 06:03:22 PM PDT 24
Peak memory 216684 kb
Host smart-ff24f480-9e46-4444-ae33-12b77483487f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=602309738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.602309738
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3155036436
Short name T44
Test name
Test status
Simulation time 48410383322 ps
CPU time 118.79 seconds
Started Jul 21 05:23:42 PM PDT 24
Finished Jul 21 05:25:41 PM PDT 24
Peak memory 200256 kb
Host smart-4874b726-e5f7-4ecf-97c8-b03aab89c64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155036436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3155036436
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.4221960605
Short name T459
Test name
Test status
Simulation time 47696582 ps
CPU time 0.6 seconds
Started Jul 21 05:28:03 PM PDT 24
Finished Jul 21 05:28:04 PM PDT 24
Peak memory 196796 kb
Host smart-d4e486f2-3435-4a50-af37-4687d417eddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221960605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4221960605
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3240832268
Short name T460
Test name
Test status
Simulation time 473037205 ps
CPU time 12.75 seconds
Started Jul 21 05:27:57 PM PDT 24
Finished Jul 21 05:28:10 PM PDT 24
Peak memory 200056 kb
Host smart-3d50f749-a5b0-4c75-95fd-f7b070aee8b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240832268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3240832268
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1701526011
Short name T35
Test name
Test status
Simulation time 3791385702 ps
CPU time 33.83 seconds
Started Jul 21 05:27:58 PM PDT 24
Finished Jul 21 05:28:32 PM PDT 24
Peak memory 200132 kb
Host smart-055b45e4-d8ba-4718-a672-d8d75804119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701526011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1701526011
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1977741446
Short name T316
Test name
Test status
Simulation time 9433544312 ps
CPU time 429.67 seconds
Started Jul 21 05:27:58 PM PDT 24
Finished Jul 21 05:35:08 PM PDT 24
Peak memory 654216 kb
Host smart-29d528e7-d4f1-43c2-a9d6-053ddf4a828f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977741446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1977741446
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3770705306
Short name T174
Test name
Test status
Simulation time 5156175136 ps
CPU time 119.19 seconds
Started Jul 21 05:28:00 PM PDT 24
Finished Jul 21 05:30:00 PM PDT 24
Peak memory 200496 kb
Host smart-35880092-b71a-40d9-901f-a734142126b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770705306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3770705306
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2352071633
Short name T63
Test name
Test status
Simulation time 181456336422 ps
CPU time 174.26 seconds
Started Jul 21 05:27:57 PM PDT 24
Finished Jul 21 05:30:51 PM PDT 24
Peak memory 200208 kb
Host smart-5d1fbbfc-7581-40a9-9c2a-c65a837e914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352071633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2352071633
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2029532466
Short name T493
Test name
Test status
Simulation time 796891767 ps
CPU time 10.71 seconds
Started Jul 21 05:27:57 PM PDT 24
Finished Jul 21 05:28:08 PM PDT 24
Peak memory 200144 kb
Host smart-ca135af9-a81e-44ee-8fb0-aa2f2c553d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029532466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2029532466
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1567198156
Short name T209
Test name
Test status
Simulation time 32572258563 ps
CPU time 356.1 seconds
Started Jul 21 05:28:03 PM PDT 24
Finished Jul 21 05:34:00 PM PDT 24
Peak memory 662148 kb
Host smart-0facab20-8a7d-4b69-bafb-66c187859e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567198156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1567198156
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3483961450
Short name T479
Test name
Test status
Simulation time 99000993 ps
CPU time 3.83 seconds
Started Jul 21 05:27:59 PM PDT 24
Finished Jul 21 05:28:03 PM PDT 24
Peak memory 200188 kb
Host smart-25c5b1e0-c050-4f67-b36f-fe219f4212bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483961450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3483961450
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4184258903
Short name T277
Test name
Test status
Simulation time 44367487 ps
CPU time 0.6 seconds
Started Jul 21 05:28:10 PM PDT 24
Finished Jul 21 05:28:11 PM PDT 24
Peak memory 195704 kb
Host smart-ba1faaa9-031e-4da3-8725-51aebb50b126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184258903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4184258903
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3190075111
Short name T343
Test name
Test status
Simulation time 698663850 ps
CPU time 39.98 seconds
Started Jul 21 05:28:05 PM PDT 24
Finished Jul 21 05:28:45 PM PDT 24
Peak memory 200140 kb
Host smart-acbaae71-6b2f-4a48-b8e4-351e5f205949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190075111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3190075111
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3546877372
Short name T285
Test name
Test status
Simulation time 2274594944 ps
CPU time 34.17 seconds
Started Jul 21 05:28:12 PM PDT 24
Finished Jul 21 05:28:47 PM PDT 24
Peak memory 200284 kb
Host smart-567b2ccd-4952-4b1b-aef8-ac707091683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546877372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3546877372
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3434174918
Short name T463
Test name
Test status
Simulation time 106404517061 ps
CPU time 1120.67 seconds
Started Jul 21 05:28:12 PM PDT 24
Finished Jul 21 05:46:53 PM PDT 24
Peak memory 759776 kb
Host smart-886153fc-b74b-4fa6-adeb-08f355b3063b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434174918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3434174918
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1480962336
Short name T401
Test name
Test status
Simulation time 18556380 ps
CPU time 0.7 seconds
Started Jul 21 05:28:12 PM PDT 24
Finished Jul 21 05:28:13 PM PDT 24
Peak memory 196648 kb
Host smart-b1aaa545-1c60-423a-9b4a-c8a8e1692084
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480962336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1480962336
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2185362831
Short name T329
Test name
Test status
Simulation time 776018709 ps
CPU time 13.9 seconds
Started Jul 21 05:28:03 PM PDT 24
Finished Jul 21 05:28:17 PM PDT 24
Peak memory 200188 kb
Host smart-d6ee73f5-75ee-4e9f-aee8-6c594ed5cd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185362831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2185362831
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3344549469
Short name T175
Test name
Test status
Simulation time 1559385875 ps
CPU time 5.22 seconds
Started Jul 21 05:28:03 PM PDT 24
Finished Jul 21 05:28:09 PM PDT 24
Peak memory 200136 kb
Host smart-0fadb561-56bd-479d-94a0-a0d554d9ca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344549469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3344549469
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2639840265
Short name T442
Test name
Test status
Simulation time 263331211428 ps
CPU time 2122.14 seconds
Started Jul 21 05:28:12 PM PDT 24
Finished Jul 21 06:03:35 PM PDT 24
Peak memory 750616 kb
Host smart-b19bd0ce-432a-4fbf-a43c-30e52f89b933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639840265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2639840265
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3634993345
Short name T429
Test name
Test status
Simulation time 1286351937 ps
CPU time 17.16 seconds
Started Jul 21 05:28:10 PM PDT 24
Finished Jul 21 05:28:27 PM PDT 24
Peak memory 200212 kb
Host smart-e6a85ac4-6816-4b92-b0da-41fa00021a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634993345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3634993345
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3439228784
Short name T244
Test name
Test status
Simulation time 25916792 ps
CPU time 0.6 seconds
Started Jul 21 05:28:15 PM PDT 24
Finished Jul 21 05:28:16 PM PDT 24
Peak memory 196104 kb
Host smart-4ae6c0be-ca5b-4752-90a6-d8bc33263711
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439228784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3439228784
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.4078268856
Short name T225
Test name
Test status
Simulation time 1400717153 ps
CPU time 88.51 seconds
Started Jul 21 05:28:12 PM PDT 24
Finished Jul 21 05:29:41 PM PDT 24
Peak memory 200188 kb
Host smart-59bbc50b-d713-4257-b491-e002162d934d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078268856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4078268856
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3315494401
Short name T134
Test name
Test status
Simulation time 980093728 ps
CPU time 13.21 seconds
Started Jul 21 05:28:17 PM PDT 24
Finished Jul 21 05:28:31 PM PDT 24
Peak memory 200112 kb
Host smart-539d9e5e-3cf3-4b87-9592-8c8f8c872470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315494401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3315494401
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1139754105
Short name T269
Test name
Test status
Simulation time 21713242962 ps
CPU time 459.5 seconds
Started Jul 21 05:28:10 PM PDT 24
Finished Jul 21 05:35:50 PM PDT 24
Peak memory 644620 kb
Host smart-6e7e742a-d874-4941-a9eb-ba15b26d78e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139754105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1139754105
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3725196497
Short name T192
Test name
Test status
Simulation time 17417284963 ps
CPU time 181.94 seconds
Started Jul 21 05:28:14 PM PDT 24
Finished Jul 21 05:31:16 PM PDT 24
Peak memory 200248 kb
Host smart-1efcae67-4044-4913-8ed5-12f919bc2a79
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725196497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3725196497
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3685241702
Short name T278
Test name
Test status
Simulation time 11954996164 ps
CPU time 150.31 seconds
Started Jul 21 05:28:09 PM PDT 24
Finished Jul 21 05:30:40 PM PDT 24
Peak memory 200152 kb
Host smart-678c9c57-67db-4c14-a491-bf4add337dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685241702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3685241702
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4040718566
Short name T151
Test name
Test status
Simulation time 99045300 ps
CPU time 4.35 seconds
Started Jul 21 05:28:08 PM PDT 24
Finished Jul 21 05:28:13 PM PDT 24
Peak memory 200136 kb
Host smart-d7d8bf2f-4911-4b20-a721-a1ff7792cca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040718566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4040718566
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2077230438
Short name T24
Test name
Test status
Simulation time 20990203801 ps
CPU time 1603.96 seconds
Started Jul 21 05:28:16 PM PDT 24
Finished Jul 21 05:55:00 PM PDT 24
Peak memory 691200 kb
Host smart-7b17edec-d189-44b9-bcb9-2c320d198ada
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077230438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2077230438
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1352552100
Short name T318
Test name
Test status
Simulation time 13643700896 ps
CPU time 121.3 seconds
Started Jul 21 05:28:14 PM PDT 24
Finished Jul 21 05:30:15 PM PDT 24
Peak memory 200248 kb
Host smart-fb8ffa9a-c22f-4ae9-9dc8-7cf06f8dd894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352552100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1352552100
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2086891347
Short name T29
Test name
Test status
Simulation time 91096614 ps
CPU time 0.58 seconds
Started Jul 21 05:28:22 PM PDT 24
Finished Jul 21 05:28:23 PM PDT 24
Peak memory 196040 kb
Host smart-15576a4f-a474-4448-9fd4-b715d5419015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086891347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2086891347
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.614241712
Short name T245
Test name
Test status
Simulation time 2373357125 ps
CPU time 37.78 seconds
Started Jul 21 05:28:20 PM PDT 24
Finished Jul 21 05:28:58 PM PDT 24
Peak memory 200136 kb
Host smart-7358d96b-1d14-48fa-8aac-ca110909af78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614241712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.614241712
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3111929203
Short name T282
Test name
Test status
Simulation time 2681466299 ps
CPU time 12.77 seconds
Started Jul 21 05:28:22 PM PDT 24
Finished Jul 21 05:28:35 PM PDT 24
Peak memory 200252 kb
Host smart-f8ef926d-ad44-41e3-a6a2-e3fe492d7789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111929203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3111929203
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.611940363
Short name T371
Test name
Test status
Simulation time 16207515204 ps
CPU time 801.78 seconds
Started Jul 21 05:28:21 PM PDT 24
Finished Jul 21 05:41:43 PM PDT 24
Peak memory 726492 kb
Host smart-d6f7bc11-49c1-4d80-ab6f-7d8550fba976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611940363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.611940363
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2976386576
Short name T48
Test name
Test status
Simulation time 18978783804 ps
CPU time 64.44 seconds
Started Jul 21 05:28:21 PM PDT 24
Finished Jul 21 05:29:26 PM PDT 24
Peak memory 200228 kb
Host smart-1d820e89-6b07-4746-a461-bd767dacc319
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976386576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2976386576
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2859010656
Short name T313
Test name
Test status
Simulation time 11969134067 ps
CPU time 161.81 seconds
Started Jul 21 05:28:22 PM PDT 24
Finished Jul 21 05:31:04 PM PDT 24
Peak memory 216628 kb
Host smart-5d329051-fd48-4622-a930-c7c5a3d832f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859010656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2859010656
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1378000499
Short name T169
Test name
Test status
Simulation time 8883130843 ps
CPU time 14.9 seconds
Started Jul 21 05:28:14 PM PDT 24
Finished Jul 21 05:28:29 PM PDT 24
Peak memory 200312 kb
Host smart-7e72b34e-56fe-4840-b2bc-2e8178dbbb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378000499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1378000499
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1473936121
Short name T216
Test name
Test status
Simulation time 37403448631 ps
CPU time 286.14 seconds
Started Jul 21 05:28:22 PM PDT 24
Finished Jul 21 05:33:08 PM PDT 24
Peak memory 208396 kb
Host smart-f7fe503b-b69e-4f73-b29e-fcb4e0f6fa56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473936121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1473936121
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1256190021
Short name T294
Test name
Test status
Simulation time 9192189972 ps
CPU time 99.67 seconds
Started Jul 21 05:28:21 PM PDT 24
Finished Jul 21 05:30:01 PM PDT 24
Peak memory 200304 kb
Host smart-9ae80e50-769e-42fb-8dcf-fb7d92f7c07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256190021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1256190021
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3069948406
Short name T389
Test name
Test status
Simulation time 12745550 ps
CPU time 0.6 seconds
Started Jul 21 05:28:25 PM PDT 24
Finished Jul 21 05:28:26 PM PDT 24
Peak memory 196028 kb
Host smart-b8b45795-07a3-47ab-b81d-24c5c2241412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069948406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3069948406
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.23958417
Short name T246
Test name
Test status
Simulation time 187364822 ps
CPU time 10.39 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:28:37 PM PDT 24
Peak memory 200232 kb
Host smart-21f049e1-e990-402b-a66b-2071dba714b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23958417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.23958417
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1847454224
Short name T145
Test name
Test status
Simulation time 22395727759 ps
CPU time 51.42 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:29:18 PM PDT 24
Peak memory 200196 kb
Host smart-4fbe079f-dff9-434d-a921-3184cd45a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847454224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1847454224
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4106093284
Short name T475
Test name
Test status
Simulation time 62991165 ps
CPU time 1.29 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:28:27 PM PDT 24
Peak memory 216556 kb
Host smart-4c97b69c-a889-4411-8bff-c1c88a387476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106093284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4106093284
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3715127843
Short name T298
Test name
Test status
Simulation time 81214624250 ps
CPU time 132.02 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:30:38 PM PDT 24
Peak memory 200240 kb
Host smart-65d7c7f2-1808-49e3-85c9-963c03d97add
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715127843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3715127843
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.956903049
Short name T219
Test name
Test status
Simulation time 3318814357 ps
CPU time 147.87 seconds
Started Jul 21 05:28:25 PM PDT 24
Finished Jul 21 05:30:53 PM PDT 24
Peak memory 200200 kb
Host smart-fd469bf5-0a8a-4470-aa00-18d3b49fd880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956903049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.956903049
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.532789082
Short name T341
Test name
Test status
Simulation time 1656063903 ps
CPU time 8.12 seconds
Started Jul 21 05:28:20 PM PDT 24
Finished Jul 21 05:28:29 PM PDT 24
Peak memory 200232 kb
Host smart-f7d9470f-84f7-4dbf-8969-94a5bb0562ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532789082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.532789082
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.16653584
Short name T137
Test name
Test status
Simulation time 7377993306 ps
CPU time 934.11 seconds
Started Jul 21 05:28:27 PM PDT 24
Finished Jul 21 05:44:01 PM PDT 24
Peak memory 669728 kb
Host smart-f793ef46-57c0-47fe-b883-945f1fdd6d79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16653584 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.16653584
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1948541676
Short name T338
Test name
Test status
Simulation time 1305607884 ps
CPU time 71.15 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:29:38 PM PDT 24
Peak memory 200180 kb
Host smart-c57e891c-baa3-4079-8b93-e20f44d825a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948541676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1948541676
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3275986734
Short name T37
Test name
Test status
Simulation time 29224033 ps
CPU time 0.6 seconds
Started Jul 21 05:28:37 PM PDT 24
Finished Jul 21 05:28:38 PM PDT 24
Peak memory 195684 kb
Host smart-a6d57f92-e9dc-4323-ac3c-ed0520d6bd83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275986734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3275986734
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3511063241
Short name T293
Test name
Test status
Simulation time 499380239 ps
CPU time 28.65 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:28:55 PM PDT 24
Peak memory 200136 kb
Host smart-7a9fb9fb-e7eb-4ed1-bdcb-55ac9735d360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511063241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3511063241
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1520266175
Short name T49
Test name
Test status
Simulation time 20790053848 ps
CPU time 1323.63 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:50:30 PM PDT 24
Peak memory 766372 kb
Host smart-8c4182da-793a-4304-9502-ca96413f2dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520266175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1520266175
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1799964278
Short name T487
Test name
Test status
Simulation time 34385200895 ps
CPU time 152.09 seconds
Started Jul 21 05:28:33 PM PDT 24
Finished Jul 21 05:31:05 PM PDT 24
Peak memory 200228 kb
Host smart-1c7eef6b-6315-4247-8ad9-f2f886e251f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799964278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1799964278
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.289499004
Short name T509
Test name
Test status
Simulation time 6498183159 ps
CPU time 104.42 seconds
Started Jul 21 05:28:31 PM PDT 24
Finished Jul 21 05:30:15 PM PDT 24
Peak memory 208276 kb
Host smart-00d5dd58-c8b0-4d14-b5af-931e46561a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289499004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.289499004
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.798208386
Short name T370
Test name
Test status
Simulation time 15131079435 ps
CPU time 12.76 seconds
Started Jul 21 05:28:26 PM PDT 24
Finished Jul 21 05:28:39 PM PDT 24
Peak memory 200204 kb
Host smart-def00023-5911-4a15-9ecc-e9c9087ce824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798208386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.798208386
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.323317746
Short name T337
Test name
Test status
Simulation time 92755989599 ps
CPU time 1638.66 seconds
Started Jul 21 05:28:32 PM PDT 24
Finished Jul 21 05:55:51 PM PDT 24
Peak memory 736656 kb
Host smart-687d953a-a214-4fa5-a4cc-ac988d7bc1c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323317746 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.323317746
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.55834377
Short name T382
Test name
Test status
Simulation time 9808688861 ps
CPU time 87.53 seconds
Started Jul 21 05:28:33 PM PDT 24
Finished Jul 21 05:30:01 PM PDT 24
Peak memory 200304 kb
Host smart-6e3132c3-0113-402a-b73c-0b248c347eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55834377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.55834377
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2700891098
Short name T305
Test name
Test status
Simulation time 11585836 ps
CPU time 0.57 seconds
Started Jul 21 05:28:44 PM PDT 24
Finished Jul 21 05:28:45 PM PDT 24
Peak memory 196796 kb
Host smart-ac1adc03-909c-46b6-a415-0ada18b1961a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700891098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2700891098
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3418154783
Short name T20
Test name
Test status
Simulation time 4699780265 ps
CPU time 64.75 seconds
Started Jul 21 05:28:38 PM PDT 24
Finished Jul 21 05:29:43 PM PDT 24
Peak memory 200128 kb
Host smart-3cac644b-efe1-4e75-b607-122318e0ae28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3418154783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3418154783
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2358757442
Short name T19
Test name
Test status
Simulation time 1247397490 ps
CPU time 23.37 seconds
Started Jul 21 05:28:38 PM PDT 24
Finished Jul 21 05:29:02 PM PDT 24
Peak memory 200048 kb
Host smart-51ec3168-cdb1-4b53-9e9e-3c2b1065f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358757442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2358757442
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2405418080
Short name T184
Test name
Test status
Simulation time 1427762320 ps
CPU time 210.46 seconds
Started Jul 21 05:28:37 PM PDT 24
Finished Jul 21 05:32:08 PM PDT 24
Peak memory 467332 kb
Host smart-3ec74560-0e28-4736-a14b-9082c3480204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405418080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2405418080
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1339724703
Short name T264
Test name
Test status
Simulation time 5625123687 ps
CPU time 64.27 seconds
Started Jul 21 05:28:38 PM PDT 24
Finished Jul 21 05:29:43 PM PDT 24
Peak memory 200212 kb
Host smart-70b2e74c-7629-4018-a288-2065929be11a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339724703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1339724703
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.182335459
Short name T400
Test name
Test status
Simulation time 2903184319 ps
CPU time 37.27 seconds
Started Jul 21 05:28:38 PM PDT 24
Finished Jul 21 05:29:15 PM PDT 24
Peak memory 200248 kb
Host smart-6c8a48b3-f754-473b-a8b3-14d7492b5faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182335459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.182335459
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2449362250
Short name T438
Test name
Test status
Simulation time 230711702 ps
CPU time 3.57 seconds
Started Jul 21 05:28:37 PM PDT 24
Finished Jul 21 05:28:41 PM PDT 24
Peak memory 200184 kb
Host smart-9b3eb797-18b0-44b6-a6f8-d38a4bbf253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449362250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2449362250
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4084810500
Short name T109
Test name
Test status
Simulation time 23582364891 ps
CPU time 1752.29 seconds
Started Jul 21 05:28:37 PM PDT 24
Finished Jul 21 05:57:50 PM PDT 24
Peak memory 682056 kb
Host smart-91570183-d2c8-4bd2-8568-8c662e522a25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084810500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4084810500
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4068066680
Short name T110
Test name
Test status
Simulation time 4227648482 ps
CPU time 19.9 seconds
Started Jul 21 05:28:38 PM PDT 24
Finished Jul 21 05:28:59 PM PDT 24
Peak memory 200252 kb
Host smart-3e9d6170-c191-4c95-a9b2-df76edb50931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068066680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4068066680
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.697477791
Short name T396
Test name
Test status
Simulation time 45271344 ps
CPU time 0.57 seconds
Started Jul 21 05:28:45 PM PDT 24
Finished Jul 21 05:28:46 PM PDT 24
Peak memory 195752 kb
Host smart-60413b9a-ae00-4402-9ee3-a563da12fca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697477791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.697477791
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3211653633
Short name T33
Test name
Test status
Simulation time 9850372549 ps
CPU time 76.01 seconds
Started Jul 21 05:28:44 PM PDT 24
Finished Jul 21 05:30:00 PM PDT 24
Peak memory 200260 kb
Host smart-f214d37d-e5ae-48e9-8416-5e98bab1b024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211653633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3211653633
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.344909821
Short name T476
Test name
Test status
Simulation time 370052931 ps
CPU time 19.96 seconds
Started Jul 21 05:28:43 PM PDT 24
Finished Jul 21 05:29:04 PM PDT 24
Peak memory 200184 kb
Host smart-3c78edad-5600-452a-b853-801364f9bc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344909821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.344909821
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1937162296
Short name T77
Test name
Test status
Simulation time 7639001729 ps
CPU time 336.06 seconds
Started Jul 21 05:28:43 PM PDT 24
Finished Jul 21 05:34:20 PM PDT 24
Peak memory 634528 kb
Host smart-a4eb31ae-94d6-4bbc-8dd3-a39d36112a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937162296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1937162296
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1120596311
Short name T377
Test name
Test status
Simulation time 30910917952 ps
CPU time 216.75 seconds
Started Jul 21 05:28:45 PM PDT 24
Finished Jul 21 05:32:22 PM PDT 24
Peak memory 200284 kb
Host smart-7fb2de2f-4889-46d7-8fce-4619951f911f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120596311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1120596311
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.37734297
Short name T4
Test name
Test status
Simulation time 47718422661 ps
CPU time 155.43 seconds
Started Jul 21 05:28:46 PM PDT 24
Finished Jul 21 05:31:21 PM PDT 24
Peak memory 200488 kb
Host smart-d54c0046-8721-4c3e-ac5e-a83857bf0b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37734297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.37734297
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3969792414
Short name T156
Test name
Test status
Simulation time 1576206407 ps
CPU time 5.69 seconds
Started Jul 21 05:28:43 PM PDT 24
Finished Jul 21 05:28:50 PM PDT 24
Peak memory 200080 kb
Host smart-d8d7477f-2d87-4a6f-856d-0ce21e26dd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969792414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3969792414
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.219606720
Short name T70
Test name
Test status
Simulation time 8871987903 ps
CPU time 116.56 seconds
Started Jul 21 05:28:44 PM PDT 24
Finished Jul 21 05:30:41 PM PDT 24
Peak memory 216520 kb
Host smart-4294a13d-0425-4ec1-b3c5-51010b93adc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219606720 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.219606720
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2779913239
Short name T82
Test name
Test status
Simulation time 5937368080 ps
CPU time 83.16 seconds
Started Jul 21 05:28:46 PM PDT 24
Finished Jul 21 05:30:09 PM PDT 24
Peak memory 200196 kb
Host smart-c815ee09-3be5-4cc5-812b-d411fa8723a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779913239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2779913239
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3215072580
Short name T403
Test name
Test status
Simulation time 31176775 ps
CPU time 0.6 seconds
Started Jul 21 05:28:51 PM PDT 24
Finished Jul 21 05:28:52 PM PDT 24
Peak memory 196140 kb
Host smart-c212ba1c-5459-4c24-a798-e6be5f52e156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215072580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3215072580
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.96266245
Short name T448
Test name
Test status
Simulation time 637848949 ps
CPU time 9.31 seconds
Started Jul 21 05:28:48 PM PDT 24
Finished Jul 21 05:28:58 PM PDT 24
Peak memory 200144 kb
Host smart-c25aca3b-fda0-47c8-83e5-38f12f9478fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96266245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.96266245
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.915239699
Short name T128
Test name
Test status
Simulation time 409970694 ps
CPU time 12.05 seconds
Started Jul 21 05:28:49 PM PDT 24
Finished Jul 21 05:29:02 PM PDT 24
Peak memory 200084 kb
Host smart-d4647da2-b524-4307-8835-8638640bfec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915239699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.915239699
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.931691884
Short name T409
Test name
Test status
Simulation time 16247592509 ps
CPU time 649.97 seconds
Started Jul 21 05:28:50 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 678324 kb
Host smart-99944e97-e0f9-4492-9302-f455941b78f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931691884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.931691884
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.329846201
Short name T419
Test name
Test status
Simulation time 3463129802 ps
CPU time 47.33 seconds
Started Jul 21 05:28:48 PM PDT 24
Finished Jul 21 05:29:36 PM PDT 24
Peak memory 200260 kb
Host smart-33e6a7db-8c3c-4ac5-b148-839ff8c28000
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329846201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.329846201
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.636866584
Short name T446
Test name
Test status
Simulation time 75126332267 ps
CPU time 87.26 seconds
Started Jul 21 05:28:50 PM PDT 24
Finished Jul 21 05:30:17 PM PDT 24
Peak memory 200264 kb
Host smart-525858a5-e0b0-45e1-8752-3f4ec0d59c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636866584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.636866584
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3076237895
Short name T257
Test name
Test status
Simulation time 1908591990 ps
CPU time 12.32 seconds
Started Jul 21 05:28:43 PM PDT 24
Finished Jul 21 05:28:56 PM PDT 24
Peak memory 200072 kb
Host smart-14b6a163-6eb8-46fc-92a2-7ba30ea8a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076237895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3076237895
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.809818983
Short name T66
Test name
Test status
Simulation time 4806984082 ps
CPU time 337.99 seconds
Started Jul 21 05:28:50 PM PDT 24
Finished Jul 21 05:34:28 PM PDT 24
Peak memory 471292 kb
Host smart-80f0532c-b8a6-4948-a299-67b2e65d05cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809818983 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.809818983
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1285154767
Short name T83
Test name
Test status
Simulation time 19712041553 ps
CPU time 134.07 seconds
Started Jul 21 05:28:49 PM PDT 24
Finished Jul 21 05:31:04 PM PDT 24
Peak memory 200156 kb
Host smart-34efe077-4e08-4527-bfe3-4fb6fdac8313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285154767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1285154767
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2629028746
Short name T160
Test name
Test status
Simulation time 46463318 ps
CPU time 0.67 seconds
Started Jul 21 05:29:02 PM PDT 24
Finished Jul 21 05:29:03 PM PDT 24
Peak memory 195112 kb
Host smart-2a40c2dd-f2d1-45f1-82c3-f4b6b29caa96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629028746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2629028746
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.731712533
Short name T191
Test name
Test status
Simulation time 541139988 ps
CPU time 34.35 seconds
Started Jul 21 05:28:55 PM PDT 24
Finished Jul 21 05:29:30 PM PDT 24
Peak memory 200152 kb
Host smart-e9c6c390-beee-4223-bc3f-5079de5fd62d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731712533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.731712533
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2548092429
Short name T79
Test name
Test status
Simulation time 3571435209 ps
CPU time 11.36 seconds
Started Jul 21 05:29:01 PM PDT 24
Finished Jul 21 05:29:13 PM PDT 24
Peak memory 200224 kb
Host smart-69401a87-9d37-40eb-945d-81b6307edf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548092429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2548092429
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.973305627
Short name T503
Test name
Test status
Simulation time 18448895764 ps
CPU time 737.98 seconds
Started Jul 21 05:28:55 PM PDT 24
Finished Jul 21 05:41:13 PM PDT 24
Peak memory 700960 kb
Host smart-9d6a19e5-05ca-4d94-9236-175ae2a5f092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973305627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.973305627
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1964717112
Short name T205
Test name
Test status
Simulation time 13338373 ps
CPU time 0.68 seconds
Started Jul 21 05:29:01 PM PDT 24
Finished Jul 21 05:29:02 PM PDT 24
Peak memory 196572 kb
Host smart-62d663c3-8dba-42d2-a8b9-2b7c07d93da8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964717112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1964717112
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.877960873
Short name T470
Test name
Test status
Simulation time 6504992956 ps
CPU time 125.96 seconds
Started Jul 21 05:28:55 PM PDT 24
Finished Jul 21 05:31:01 PM PDT 24
Peak memory 216620 kb
Host smart-04f774d8-d47a-43bc-bd17-b9c3b57ab1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877960873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.877960873
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3911822812
Short name T158
Test name
Test status
Simulation time 357345277 ps
CPU time 4.62 seconds
Started Jul 21 05:28:48 PM PDT 24
Finished Jul 21 05:28:53 PM PDT 24
Peak memory 200228 kb
Host smart-2e28e1d0-0101-44ed-a362-fb234ff33868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911822812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3911822812
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3613043324
Short name T335
Test name
Test status
Simulation time 50966885146 ps
CPU time 1335.84 seconds
Started Jul 21 05:29:00 PM PDT 24
Finished Jul 21 05:51:17 PM PDT 24
Peak memory 750428 kb
Host smart-3783b0a4-3b14-4428-bb03-47c80935dfea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613043324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3613043324
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3562272247
Short name T275
Test name
Test status
Simulation time 6658016761 ps
CPU time 65.75 seconds
Started Jul 21 05:29:00 PM PDT 24
Finished Jul 21 05:30:06 PM PDT 24
Peak memory 200256 kb
Host smart-32e8c006-2279-4193-b06b-767d7f190b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562272247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3562272247
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3199155064
Short name T308
Test name
Test status
Simulation time 13092980 ps
CPU time 0.58 seconds
Started Jul 21 05:24:24 PM PDT 24
Finished Jul 21 05:24:25 PM PDT 24
Peak memory 195692 kb
Host smart-82f15661-bd63-490b-98ee-7463b6921998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199155064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3199155064
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2257142722
Short name T25
Test name
Test status
Simulation time 1747769560 ps
CPU time 101.92 seconds
Started Jul 21 05:24:07 PM PDT 24
Finished Jul 21 05:25:49 PM PDT 24
Peak memory 200180 kb
Host smart-66ebf63a-1076-42b8-a60f-cbbc794b5d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257142722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2257142722
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3289683437
Short name T179
Test name
Test status
Simulation time 7920966289 ps
CPU time 56.7 seconds
Started Jul 21 05:24:14 PM PDT 24
Finished Jul 21 05:25:11 PM PDT 24
Peak memory 200256 kb
Host smart-0c3676a5-f029-4b65-9570-d7bf7189588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289683437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3289683437
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2948586089
Short name T439
Test name
Test status
Simulation time 31213790551 ps
CPU time 1482.24 seconds
Started Jul 21 05:24:06 PM PDT 24
Finished Jul 21 05:48:49 PM PDT 24
Peak memory 761192 kb
Host smart-16f845bb-2879-4fd1-8e49-f032ffca6997
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948586089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2948586089
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.784841422
Short name T295
Test name
Test status
Simulation time 13859285429 ps
CPU time 51.51 seconds
Started Jul 21 05:24:13 PM PDT 24
Finished Jul 21 05:25:04 PM PDT 24
Peak memory 200276 kb
Host smart-7260583a-fc41-4fa3-94d0-3b97bdbf096c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784841422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.784841422
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2483192871
Short name T60
Test name
Test status
Simulation time 1531870167 ps
CPU time 21.61 seconds
Started Jul 21 05:24:07 PM PDT 24
Finished Jul 21 05:24:29 PM PDT 24
Peak memory 200104 kb
Host smart-b5b49260-f1f1-4bf4-9850-76af06cca9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483192871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2483192871
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2539219821
Short name T38
Test name
Test status
Simulation time 61784482 ps
CPU time 0.85 seconds
Started Jul 21 05:24:23 PM PDT 24
Finished Jul 21 05:24:25 PM PDT 24
Peak memory 218536 kb
Host smart-0f259727-ce04-4a83-82fe-5a5e05d8f748
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539219821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2539219821
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3937075638
Short name T172
Test name
Test status
Simulation time 114708375 ps
CPU time 5.35 seconds
Started Jul 21 05:24:00 PM PDT 24
Finished Jul 21 05:24:06 PM PDT 24
Peak memory 200184 kb
Host smart-96741f12-f0e3-4018-bd63-a90fdfed716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937075638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3937075638
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.438546701
Short name T426
Test name
Test status
Simulation time 31649581544 ps
CPU time 2497.05 seconds
Started Jul 21 05:24:23 PM PDT 24
Finished Jul 21 06:06:01 PM PDT 24
Peak memory 798272 kb
Host smart-c685b619-4bee-4c93-bedf-9bab18a513ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438546701 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.438546701
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3067642279
Short name T57
Test name
Test status
Simulation time 43346577064 ps
CPU time 914.3 seconds
Started Jul 21 05:24:23 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 632424 kb
Host smart-59a3c68d-570a-4f15-a459-c9ca897a673f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067642279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3067642279
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2181028054
Short name T430
Test name
Test status
Simulation time 4343602866 ps
CPU time 57.79 seconds
Started Jul 21 05:24:19 PM PDT 24
Finished Jul 21 05:25:17 PM PDT 24
Peak memory 200236 kb
Host smart-6af1ad09-912c-45ae-8783-08eb78e58f8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2181028054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2181028054
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3203167046
Short name T27
Test name
Test status
Simulation time 13162980521 ps
CPU time 89.25 seconds
Started Jul 21 05:24:17 PM PDT 24
Finished Jul 21 05:25:47 PM PDT 24
Peak memory 200236 kb
Host smart-68522a92-0bc4-4249-8b0e-91be44c48c8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3203167046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3203167046
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3591204492
Short name T223
Test name
Test status
Simulation time 6338704984 ps
CPU time 118.86 seconds
Started Jul 21 05:24:17 PM PDT 24
Finished Jul 21 05:26:16 PM PDT 24
Peak memory 200252 kb
Host smart-c3a768ae-7c75-475c-b291-7315fe626679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3591204492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3591204492
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.753727073
Short name T488
Test name
Test status
Simulation time 47868015030 ps
CPU time 605.9 seconds
Started Jul 21 05:24:19 PM PDT 24
Finished Jul 21 05:34:25 PM PDT 24
Peak memory 200204 kb
Host smart-a59873ea-d2f3-4358-a71b-6b7588680ceb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=753727073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.753727073
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.476305361
Short name T372
Test name
Test status
Simulation time 572117195086 ps
CPU time 2371.03 seconds
Started Jul 21 05:24:17 PM PDT 24
Finished Jul 21 06:03:49 PM PDT 24
Peak memory 215708 kb
Host smart-8d152569-654e-4a91-8952-f49946623ceb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=476305361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.476305361
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3453673319
Short name T489
Test name
Test status
Simulation time 440892472948 ps
CPU time 2607.86 seconds
Started Jul 21 05:24:16 PM PDT 24
Finished Jul 21 06:07:45 PM PDT 24
Peak memory 215676 kb
Host smart-de78cf85-244c-4c73-bce4-3a093b40f603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3453673319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3453673319
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3066289667
Short name T417
Test name
Test status
Simulation time 2965920532 ps
CPU time 55.45 seconds
Started Jul 21 05:24:13 PM PDT 24
Finished Jul 21 05:25:08 PM PDT 24
Peak memory 200252 kb
Host smart-2e7cd949-b32f-420c-8b58-fb35d661f071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066289667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3066289667
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3428613734
Short name T497
Test name
Test status
Simulation time 29215863 ps
CPU time 0.59 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:29:08 PM PDT 24
Peak memory 195092 kb
Host smart-eba4f254-1dce-481c-96f9-672ca9ddcf96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428613734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3428613734
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2645913325
Short name T357
Test name
Test status
Simulation time 1576882025 ps
CPU time 91.94 seconds
Started Jul 21 05:29:00 PM PDT 24
Finished Jul 21 05:30:32 PM PDT 24
Peak memory 200144 kb
Host smart-964c3ba7-a703-4700-a96e-9dd4bdd3c49c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645913325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2645913325
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2245155744
Short name T490
Test name
Test status
Simulation time 1673904032 ps
CPU time 22.01 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:29:29 PM PDT 24
Peak memory 200172 kb
Host smart-350b96ed-1f05-4558-8cfd-fe3151dec442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245155744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2245155744
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2131938870
Short name T361
Test name
Test status
Simulation time 9869542283 ps
CPU time 385.3 seconds
Started Jul 21 05:28:58 PM PDT 24
Finished Jul 21 05:35:24 PM PDT 24
Peak memory 430924 kb
Host smart-e268a350-d6b3-48be-ba0e-3748a30a8303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2131938870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2131938870
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4253454283
Short name T378
Test name
Test status
Simulation time 19975836503 ps
CPU time 71.97 seconds
Started Jul 21 05:29:06 PM PDT 24
Finished Jul 21 05:30:19 PM PDT 24
Peak memory 200244 kb
Host smart-416762fa-6db8-468c-9802-d091f4f31016
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253454283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4253454283
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1794913194
Short name T47
Test name
Test status
Simulation time 11052989669 ps
CPU time 144.2 seconds
Started Jul 21 05:29:01 PM PDT 24
Finished Jul 21 05:31:25 PM PDT 24
Peak memory 200172 kb
Host smart-2733e3a5-114c-46af-8bdd-b8d32275c045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794913194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1794913194
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3754420764
Short name T76
Test name
Test status
Simulation time 206020564 ps
CPU time 4.18 seconds
Started Jul 21 05:29:00 PM PDT 24
Finished Jul 21 05:29:04 PM PDT 24
Peak memory 200188 kb
Host smart-958a3e2c-f96d-4be2-aa51-eeefc36df373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754420764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3754420764
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2713708418
Short name T304
Test name
Test status
Simulation time 28669077580 ps
CPU time 279.25 seconds
Started Jul 21 05:29:10 PM PDT 24
Finished Jul 21 05:33:49 PM PDT 24
Peak memory 200256 kb
Host smart-8fe9d026-2515-4bdc-86eb-375d4e68f02e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713708418 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2713708418
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1120850580
Short name T386
Test name
Test status
Simulation time 3090942705 ps
CPU time 39.08 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:29:46 PM PDT 24
Peak memory 200292 kb
Host smart-43a039e3-1c7f-42f0-a3e6-63abbfc37916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120850580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1120850580
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1852828282
Short name T351
Test name
Test status
Simulation time 33036126 ps
CPU time 0.58 seconds
Started Jul 21 05:29:10 PM PDT 24
Finished Jul 21 05:29:11 PM PDT 24
Peak memory 195112 kb
Host smart-48380767-be89-4cd2-90fb-0b670ce14d8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852828282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1852828282
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4142520451
Short name T458
Test name
Test status
Simulation time 85241160 ps
CPU time 4.94 seconds
Started Jul 21 05:29:06 PM PDT 24
Finished Jul 21 05:29:12 PM PDT 24
Peak memory 200096 kb
Host smart-8d905762-3ec1-4561-84c9-4c28fec7be90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142520451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4142520451
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.532241325
Short name T256
Test name
Test status
Simulation time 907448486 ps
CPU time 17 seconds
Started Jul 21 05:29:06 PM PDT 24
Finished Jul 21 05:29:24 PM PDT 24
Peak memory 200180 kb
Host smart-fe9c9f9f-055b-4d09-9418-c46e59fc33ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532241325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.532241325
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3759154179
Short name T326
Test name
Test status
Simulation time 3103255244 ps
CPU time 636.17 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:39:44 PM PDT 24
Peak memory 685120 kb
Host smart-d502264d-93b7-4acc-94ee-006c7cd027f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759154179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3759154179
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1076888617
Short name T43
Test name
Test status
Simulation time 1687216359 ps
CPU time 29.76 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:29:37 PM PDT 24
Peak memory 200216 kb
Host smart-a29c70d7-e5f7-40c6-b4ad-78f0f6adcbec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076888617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1076888617
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2721247352
Short name T222
Test name
Test status
Simulation time 9629560592 ps
CPU time 179.61 seconds
Started Jul 21 05:29:05 PM PDT 24
Finished Jul 21 05:32:05 PM PDT 24
Peak memory 216468 kb
Host smart-bbaf83d7-ff30-4ba5-8e63-ac669f8faad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721247352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2721247352
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3435962189
Short name T464
Test name
Test status
Simulation time 249825531 ps
CPU time 12.62 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:29:20 PM PDT 24
Peak memory 200164 kb
Host smart-2b93eef1-d53e-431d-9b00-84c82b5a4169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435962189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3435962189
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.793895890
Short name T72
Test name
Test status
Simulation time 138022307412 ps
CPU time 3347.34 seconds
Started Jul 21 05:29:10 PM PDT 24
Finished Jul 21 06:24:58 PM PDT 24
Peak memory 835468 kb
Host smart-864db255-363c-4d25-a9a9-dd60db5130c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793895890 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.793895890
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.4160999114
Short name T199
Test name
Test status
Simulation time 1969563927 ps
CPU time 36.54 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:29:44 PM PDT 24
Peak memory 200160 kb
Host smart-045429e6-4ac8-4b99-8a1e-dd4acdc97ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160999114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4160999114
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2511010967
Short name T514
Test name
Test status
Simulation time 27115074 ps
CPU time 0.62 seconds
Started Jul 21 05:29:13 PM PDT 24
Finished Jul 21 05:29:14 PM PDT 24
Peak memory 195796 kb
Host smart-757fd207-0491-4764-9a6c-bef9a5f89a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511010967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2511010967
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3822685207
Short name T455
Test name
Test status
Simulation time 5201096627 ps
CPU time 69.27 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:30:17 PM PDT 24
Peak memory 200228 kb
Host smart-c02bd909-658d-439e-ac45-8112f1cb7bf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822685207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3822685207
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.251821841
Short name T301
Test name
Test status
Simulation time 14923873355 ps
CPU time 45.27 seconds
Started Jul 21 05:29:13 PM PDT 24
Finished Jul 21 05:29:58 PM PDT 24
Peak memory 200256 kb
Host smart-ccf4e975-04ed-4c78-8cc9-44fa51a3421e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251821841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.251821841
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.724564423
Short name T243
Test name
Test status
Simulation time 7020173747 ps
CPU time 1432.98 seconds
Started Jul 21 05:29:13 PM PDT 24
Finished Jul 21 05:53:06 PM PDT 24
Peak memory 784504 kb
Host smart-7b1b7b21-26f1-451b-8fc6-66b4789feb01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724564423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.724564423
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.348579305
Short name T251
Test name
Test status
Simulation time 19157541074 ps
CPU time 125.75 seconds
Started Jul 21 05:29:13 PM PDT 24
Finished Jul 21 05:31:19 PM PDT 24
Peak memory 200160 kb
Host smart-8cb6f575-424b-45eb-9ec4-ed22cece8068
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348579305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.348579305
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1098171863
Short name T520
Test name
Test status
Simulation time 10275022292 ps
CPU time 42.55 seconds
Started Jul 21 05:29:07 PM PDT 24
Finished Jul 21 05:29:50 PM PDT 24
Peak memory 200144 kb
Host smart-b18fc293-d938-44e5-bf3f-7c14903c92d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098171863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1098171863
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2428317063
Short name T345
Test name
Test status
Simulation time 725133578 ps
CPU time 12.17 seconds
Started Jul 21 05:29:09 PM PDT 24
Finished Jul 21 05:29:21 PM PDT 24
Peak memory 200172 kb
Host smart-be34e913-5259-49b3-8ce2-8493aee58ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428317063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2428317063
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3191154626
Short name T331
Test name
Test status
Simulation time 2580254986 ps
CPU time 59.05 seconds
Started Jul 21 05:29:13 PM PDT 24
Finished Jul 21 05:30:12 PM PDT 24
Peak memory 200304 kb
Host smart-1463ce3d-7b08-4941-a6fb-f43e886c658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191154626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3191154626
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2214134314
Short name T252
Test name
Test status
Simulation time 91177913 ps
CPU time 0.65 seconds
Started Jul 21 05:29:18 PM PDT 24
Finished Jul 21 05:29:19 PM PDT 24
Peak memory 196080 kb
Host smart-8f23a78d-cac5-4a9c-b3f2-8348c9f21940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214134314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2214134314
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1221025527
Short name T276
Test name
Test status
Simulation time 587532529 ps
CPU time 10.38 seconds
Started Jul 21 05:29:12 PM PDT 24
Finished Jul 21 05:29:23 PM PDT 24
Peak memory 200240 kb
Host smart-507b463d-a323-4f77-95d3-00cbf6092535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221025527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1221025527
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3126443251
Short name T202
Test name
Test status
Simulation time 67255404 ps
CPU time 2.97 seconds
Started Jul 21 05:29:17 PM PDT 24
Finished Jul 21 05:29:20 PM PDT 24
Peak memory 200192 kb
Host smart-c40a7e48-d32b-4da2-8671-82290db7385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126443251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3126443251
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2672907152
Short name T177
Test name
Test status
Simulation time 10975348026 ps
CPU time 931.66 seconds
Started Jul 21 05:29:14 PM PDT 24
Finished Jul 21 05:44:46 PM PDT 24
Peak memory 744788 kb
Host smart-a5e721f4-9a49-4ac5-9c3b-be6d0233118f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672907152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2672907152
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.590347450
Short name T450
Test name
Test status
Simulation time 1968870749 ps
CPU time 118.13 seconds
Started Jul 21 05:29:21 PM PDT 24
Finished Jul 21 05:31:19 PM PDT 24
Peak memory 200236 kb
Host smart-233b998d-3266-41e7-908d-2dc61fb37c94
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590347450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.590347450
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2068574868
Short name T485
Test name
Test status
Simulation time 5265824329 ps
CPU time 75.6 seconds
Started Jul 21 05:29:13 PM PDT 24
Finished Jul 21 05:30:29 PM PDT 24
Peak memory 200412 kb
Host smart-6dff330f-6b45-4251-a017-2e3da351055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068574868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2068574868
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2139158175
Short name T185
Test name
Test status
Simulation time 352914380 ps
CPU time 7.88 seconds
Started Jul 21 05:29:11 PM PDT 24
Finished Jul 21 05:29:19 PM PDT 24
Peak memory 200232 kb
Host smart-44e452d6-7f92-4d57-9543-ee28b5f059b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139158175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2139158175
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2147297194
Short name T23
Test name
Test status
Simulation time 13746330751 ps
CPU time 778.24 seconds
Started Jul 21 05:29:18 PM PDT 24
Finished Jul 21 05:42:16 PM PDT 24
Peak memory 208480 kb
Host smart-0c93bcae-8e86-451f-b3c8-f23bae88c531
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147297194 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2147297194
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3485636163
Short name T6
Test name
Test status
Simulation time 8084401684 ps
CPU time 92.34 seconds
Started Jul 21 05:29:20 PM PDT 24
Finished Jul 21 05:30:52 PM PDT 24
Peak memory 200152 kb
Host smart-1f218d16-2120-4250-b41b-8b115e4aee88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485636163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3485636163
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.134782833
Short name T270
Test name
Test status
Simulation time 11763817 ps
CPU time 0.59 seconds
Started Jul 21 05:29:27 PM PDT 24
Finished Jul 21 05:29:28 PM PDT 24
Peak memory 195776 kb
Host smart-0ba58fab-1d2f-4e83-a16e-b0a2687dab1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134782833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.134782833
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.720107473
Short name T346
Test name
Test status
Simulation time 2598623980 ps
CPU time 27.71 seconds
Started Jul 21 05:29:26 PM PDT 24
Finished Jul 21 05:29:54 PM PDT 24
Peak memory 200204 kb
Host smart-21981dad-96e4-402a-8585-36523520a052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=720107473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.720107473
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1357571226
Short name T200
Test name
Test status
Simulation time 15912127753 ps
CPU time 55.74 seconds
Started Jul 21 05:29:26 PM PDT 24
Finished Jul 21 05:30:22 PM PDT 24
Peak memory 216592 kb
Host smart-b299b02b-983d-4699-a97f-89d266ad2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357571226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1357571226
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1125807723
Short name T176
Test name
Test status
Simulation time 7201481560 ps
CPU time 624.9 seconds
Started Jul 21 05:29:25 PM PDT 24
Finished Jul 21 05:39:51 PM PDT 24
Peak memory 668296 kb
Host smart-b0e7bb71-2281-4780-a598-a8ad4c21112b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125807723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1125807723
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.144185617
Short name T231
Test name
Test status
Simulation time 27127003780 ps
CPU time 126.49 seconds
Started Jul 21 05:29:28 PM PDT 24
Finished Jul 21 05:31:35 PM PDT 24
Peak memory 200212 kb
Host smart-90d60a5f-399c-4dae-8e9a-ce9a3c7fda99
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144185617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.144185617
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3012854133
Short name T366
Test name
Test status
Simulation time 15623119582 ps
CPU time 43.24 seconds
Started Jul 21 05:29:18 PM PDT 24
Finished Jul 21 05:30:01 PM PDT 24
Peak memory 200264 kb
Host smart-09e8eac8-726c-430b-b48a-6b64bb9d94c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012854133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3012854133
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1347819649
Short name T85
Test name
Test status
Simulation time 618475445 ps
CPU time 4.11 seconds
Started Jul 21 05:29:17 PM PDT 24
Finished Jul 21 05:29:21 PM PDT 24
Peak memory 200104 kb
Host smart-df617d94-99ec-4658-a8f9-adc6c20e229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347819649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1347819649
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3568291224
Short name T355
Test name
Test status
Simulation time 11535754840 ps
CPU time 2326.02 seconds
Started Jul 21 05:29:27 PM PDT 24
Finished Jul 21 06:08:13 PM PDT 24
Peak memory 820268 kb
Host smart-6ec64cb8-6a84-435c-8553-832563317e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568291224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3568291224
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2883403756
Short name T349
Test name
Test status
Simulation time 2892433810 ps
CPU time 13.77 seconds
Started Jul 21 05:29:27 PM PDT 24
Finished Jul 21 05:29:41 PM PDT 24
Peak memory 200248 kb
Host smart-b0bfb1a6-245a-4513-b99b-71bdcecccdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883403756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2883403756
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1331099728
Short name T260
Test name
Test status
Simulation time 38065048 ps
CPU time 0.56 seconds
Started Jul 21 05:29:34 PM PDT 24
Finished Jul 21 05:29:35 PM PDT 24
Peak memory 195016 kb
Host smart-5bfe70de-2849-495e-a305-eb7f0b53d634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331099728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1331099728
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1164166045
Short name T64
Test name
Test status
Simulation time 351611747 ps
CPU time 18.45 seconds
Started Jul 21 05:29:35 PM PDT 24
Finished Jul 21 05:29:54 PM PDT 24
Peak memory 200212 kb
Host smart-817aefaa-73f9-48dd-bba1-197b4c83ea08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164166045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1164166045
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1380028245
Short name T73
Test name
Test status
Simulation time 111637513 ps
CPU time 5.77 seconds
Started Jul 21 05:29:30 PM PDT 24
Finished Jul 21 05:29:36 PM PDT 24
Peak memory 200092 kb
Host smart-623b9ae0-dfa4-4a48-bbf4-fceb64821bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380028245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1380028245
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3713361166
Short name T384
Test name
Test status
Simulation time 739609115 ps
CPU time 114.76 seconds
Started Jul 21 05:29:34 PM PDT 24
Finished Jul 21 05:31:29 PM PDT 24
Peak memory 419064 kb
Host smart-d08be033-286f-4689-8693-9397dddeed66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713361166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3713361166
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.807144652
Short name T267
Test name
Test status
Simulation time 230211128 ps
CPU time 12.81 seconds
Started Jul 21 05:29:34 PM PDT 24
Finished Jul 21 05:29:48 PM PDT 24
Peak memory 200300 kb
Host smart-c771b31b-e9cd-4174-8c72-5e201ce0a66c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807144652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.807144652
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1184854435
Short name T486
Test name
Test status
Simulation time 2851420838 ps
CPU time 12.27 seconds
Started Jul 21 05:29:26 PM PDT 24
Finished Jul 21 05:29:38 PM PDT 24
Peak memory 200200 kb
Host smart-85f60292-7113-43fd-8503-73dcf52b2faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184854435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1184854435
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.790282774
Short name T62
Test name
Test status
Simulation time 1881976635 ps
CPU time 7.89 seconds
Started Jul 21 05:29:27 PM PDT 24
Finished Jul 21 05:29:35 PM PDT 24
Peak memory 200180 kb
Host smart-7cd8b70b-4bac-492b-a591-019a072cb5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790282774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.790282774
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.507990397
Short name T71
Test name
Test status
Simulation time 583907825603 ps
CPU time 2177.91 seconds
Started Jul 21 05:29:33 PM PDT 24
Finished Jul 21 06:05:52 PM PDT 24
Peak memory 717916 kb
Host smart-98a409b6-9598-44e5-9946-cc30ef39b49b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507990397 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.507990397
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1184566424
Short name T250
Test name
Test status
Simulation time 4216779728 ps
CPU time 67.83 seconds
Started Jul 21 05:29:36 PM PDT 24
Finished Jul 21 05:30:44 PM PDT 24
Peak memory 200296 kb
Host smart-93bdce5c-48b5-4ea8-b305-9742636df2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184566424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1184566424
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3467460540
Short name T58
Test name
Test status
Simulation time 39210871 ps
CPU time 0.59 seconds
Started Jul 21 05:29:39 PM PDT 24
Finished Jul 21 05:29:40 PM PDT 24
Peak memory 195100 kb
Host smart-66ebbf70-46b5-4671-ab07-187b15e62428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467460540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3467460540
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1733881484
Short name T363
Test name
Test status
Simulation time 84907020 ps
CPU time 4.95 seconds
Started Jul 21 05:29:34 PM PDT 24
Finished Jul 21 05:29:40 PM PDT 24
Peak memory 200208 kb
Host smart-f6ed961a-5461-4b05-b6b5-2c74dae2b131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733881484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1733881484
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1332794097
Short name T397
Test name
Test status
Simulation time 22634829656 ps
CPU time 748.33 seconds
Started Jul 21 05:29:33 PM PDT 24
Finished Jul 21 05:42:02 PM PDT 24
Peak memory 693708 kb
Host smart-9738fdd6-27cc-4760-be74-ff608143b4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332794097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1332794097
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.242938201
Short name T518
Test name
Test status
Simulation time 4891419594 ps
CPU time 93.04 seconds
Started Jul 21 05:29:35 PM PDT 24
Finished Jul 21 05:31:08 PM PDT 24
Peak memory 200272 kb
Host smart-ece34b55-9321-4004-964b-18f7aab30005
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242938201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.242938201
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2716331906
Short name T147
Test name
Test status
Simulation time 3743989387 ps
CPU time 70.89 seconds
Started Jul 21 05:29:33 PM PDT 24
Finished Jul 21 05:30:44 PM PDT 24
Peak memory 200144 kb
Host smart-1b64d78d-a83f-4b66-9164-bd6f456bb2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716331906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2716331906
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1952805239
Short name T359
Test name
Test status
Simulation time 178791346 ps
CPU time 4.34 seconds
Started Jul 21 05:29:31 PM PDT 24
Finished Jul 21 05:29:36 PM PDT 24
Peak memory 200164 kb
Host smart-45bdf846-4c88-461f-9daf-c38ccb19e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952805239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1952805239
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3189057063
Short name T67
Test name
Test status
Simulation time 195724522787 ps
CPU time 1616.59 seconds
Started Jul 21 05:29:47 PM PDT 24
Finished Jul 21 05:56:44 PM PDT 24
Peak memory 763564 kb
Host smart-09a6c2f2-391a-4ffc-9d0d-4137ee44ac04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189057063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3189057063
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.958141403
Short name T449
Test name
Test status
Simulation time 6016408438 ps
CPU time 61.39 seconds
Started Jul 21 05:29:34 PM PDT 24
Finished Jul 21 05:30:36 PM PDT 24
Peak memory 200436 kb
Host smart-5324c419-878c-4dd8-a335-3d50fd0eda82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958141403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.958141403
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1483157760
Short name T247
Test name
Test status
Simulation time 12679420 ps
CPU time 0.59 seconds
Started Jul 21 05:29:39 PM PDT 24
Finished Jul 21 05:29:40 PM PDT 24
Peak memory 195072 kb
Host smart-06e4e8ad-2793-424b-921c-bb1696f7d49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483157760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1483157760
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1985807831
Short name T483
Test name
Test status
Simulation time 1021154694 ps
CPU time 19.12 seconds
Started Jul 21 05:29:38 PM PDT 24
Finished Jul 21 05:29:58 PM PDT 24
Peak memory 200176 kb
Host smart-7292a76d-0940-45e2-a7d2-8b207644b99d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985807831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1985807831
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4246538585
Short name T28
Test name
Test status
Simulation time 4608750417 ps
CPU time 67.57 seconds
Started Jul 21 05:29:40 PM PDT 24
Finished Jul 21 05:30:48 PM PDT 24
Peak memory 208672 kb
Host smart-ff1b08d8-4e45-4ff0-a3c1-5c0830770058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246538585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4246538585
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.209522285
Short name T402
Test name
Test status
Simulation time 30860025943 ps
CPU time 702.48 seconds
Started Jul 21 05:29:37 PM PDT 24
Finished Jul 21 05:41:20 PM PDT 24
Peak memory 667928 kb
Host smart-062ef373-d58e-423c-9b6b-811e112df187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209522285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.209522285
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1115270307
Short name T454
Test name
Test status
Simulation time 3410198849 ps
CPU time 64.44 seconds
Started Jul 21 05:29:39 PM PDT 24
Finished Jul 21 05:30:44 PM PDT 24
Peak memory 200100 kb
Host smart-1647bb30-d5f4-470a-b573-55cfa86a9fbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115270307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1115270307
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1775331973
Short name T221
Test name
Test status
Simulation time 33456942540 ps
CPU time 140.42 seconds
Started Jul 21 05:29:40 PM PDT 24
Finished Jul 21 05:32:00 PM PDT 24
Peak memory 200136 kb
Host smart-6e23a25f-2e44-43ef-8230-896eb9980ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775331973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1775331973
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.959165496
Short name T362
Test name
Test status
Simulation time 567674099 ps
CPU time 6.93 seconds
Started Jul 21 05:29:38 PM PDT 24
Finished Jul 21 05:29:45 PM PDT 24
Peak memory 200132 kb
Host smart-8c35825d-354c-47a1-8ed6-1d0aea721e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959165496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.959165496
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3569687634
Short name T510
Test name
Test status
Simulation time 114793101024 ps
CPU time 2712.14 seconds
Started Jul 21 05:29:38 PM PDT 24
Finished Jul 21 06:14:51 PM PDT 24
Peak memory 758628 kb
Host smart-967902a1-edb1-450a-98ce-8168b80335c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569687634 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3569687634
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1851400207
Short name T74
Test name
Test status
Simulation time 1960419401 ps
CPU time 94.97 seconds
Started Jul 21 05:29:38 PM PDT 24
Finished Jul 21 05:31:13 PM PDT 24
Peak memory 200236 kb
Host smart-589dece1-e262-4b8b-84b6-f242f064e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851400207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1851400207
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.153223246
Short name T342
Test name
Test status
Simulation time 93637091 ps
CPU time 0.6 seconds
Started Jul 21 05:29:51 PM PDT 24
Finished Jul 21 05:29:52 PM PDT 24
Peak memory 196128 kb
Host smart-3fbb3a7b-ef3a-4bb2-8c4e-0987655fb4ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153223246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.153223246
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4125959856
Short name T141
Test name
Test status
Simulation time 3814671567 ps
CPU time 52.97 seconds
Started Jul 21 05:29:43 PM PDT 24
Finished Jul 21 05:30:36 PM PDT 24
Peak memory 200284 kb
Host smart-4c579ea9-1243-4377-b7a0-328059cad0b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125959856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4125959856
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3279205958
Short name T154
Test name
Test status
Simulation time 229992998 ps
CPU time 4.1 seconds
Started Jul 21 05:29:44 PM PDT 24
Finished Jul 21 05:29:49 PM PDT 24
Peak memory 200188 kb
Host smart-99240144-8050-443a-9085-b5cdf2afff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279205958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3279205958
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3168858299
Short name T457
Test name
Test status
Simulation time 18156622897 ps
CPU time 848.09 seconds
Started Jul 21 05:29:50 PM PDT 24
Finished Jul 21 05:43:58 PM PDT 24
Peak memory 697116 kb
Host smart-518edce9-b67f-4106-ba90-2958980a83d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168858299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3168858299
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.635156561
Short name T287
Test name
Test status
Simulation time 416989414 ps
CPU time 3.38 seconds
Started Jul 21 05:29:44 PM PDT 24
Finished Jul 21 05:29:48 PM PDT 24
Peak memory 200148 kb
Host smart-2a10c389-c471-4b55-b4ef-0dab00d4326f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635156561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.635156561
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3809270311
Short name T284
Test name
Test status
Simulation time 15153136536 ps
CPU time 208.53 seconds
Started Jul 21 05:29:45 PM PDT 24
Finished Jul 21 05:33:14 PM PDT 24
Peak memory 216628 kb
Host smart-a243625e-8bc8-4dbb-a65e-18cc8a208d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809270311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3809270311
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1266168
Short name T315
Test name
Test status
Simulation time 458535483 ps
CPU time 6.74 seconds
Started Jul 21 05:29:38 PM PDT 24
Finished Jul 21 05:29:45 PM PDT 24
Peak memory 200180 kb
Host smart-234eab6b-216c-445d-8ebd-792a149cff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1266168
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.145091819
Short name T437
Test name
Test status
Simulation time 869639288 ps
CPU time 47.04 seconds
Started Jul 21 05:29:57 PM PDT 24
Finished Jul 21 05:30:44 PM PDT 24
Peak memory 200084 kb
Host smart-8cd37e3f-57e8-4add-a7bd-869ecfa9effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145091819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.145091819
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3439034340
Short name T360
Test name
Test status
Simulation time 56150550 ps
CPU time 0.59 seconds
Started Jul 21 05:29:56 PM PDT 24
Finished Jul 21 05:29:57 PM PDT 24
Peak memory 196024 kb
Host smart-08a4b3f3-eadd-4815-9e53-b25848ec9d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439034340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3439034340
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2869183316
Short name T215
Test name
Test status
Simulation time 950774295 ps
CPU time 30.11 seconds
Started Jul 21 05:29:49 PM PDT 24
Finished Jul 21 05:30:20 PM PDT 24
Peak memory 200168 kb
Host smart-880fe698-fdd3-4cb1-8edc-432b5866b1c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869183316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2869183316
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4225923328
Short name T31
Test name
Test status
Simulation time 4622921574 ps
CPU time 61.83 seconds
Started Jul 21 05:30:04 PM PDT 24
Finished Jul 21 05:31:06 PM PDT 24
Peak memory 200160 kb
Host smart-c6535fb9-b4c8-444c-82b5-9fd3e04d2740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225923328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4225923328
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2792523643
Short name T310
Test name
Test status
Simulation time 1211052059 ps
CPU time 27.59 seconds
Started Jul 21 05:29:57 PM PDT 24
Finished Jul 21 05:30:25 PM PDT 24
Peak memory 207796 kb
Host smart-94b2df6d-5ce6-4f7a-a455-f3c0e2e7a84a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792523643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2792523643
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4109499825
Short name T281
Test name
Test status
Simulation time 1437453823 ps
CPU time 6.44 seconds
Started Jul 21 05:29:58 PM PDT 24
Finished Jul 21 05:30:05 PM PDT 24
Peak memory 200076 kb
Host smart-fb345130-9260-42d0-8d05-a3e6c1f384ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109499825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4109499825
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4097020294
Short name T127
Test name
Test status
Simulation time 6941602285 ps
CPU time 123.77 seconds
Started Jul 21 05:29:51 PM PDT 24
Finished Jul 21 05:31:55 PM PDT 24
Peak memory 208476 kb
Host smart-fe86f642-c40d-4104-b149-9e1907bca448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097020294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4097020294
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2608690560
Short name T87
Test name
Test status
Simulation time 1427943415 ps
CPU time 3.4 seconds
Started Jul 21 05:29:50 PM PDT 24
Finished Jul 21 05:29:54 PM PDT 24
Peak memory 200216 kb
Host smart-85690d76-bc8f-4cac-a1f7-e962b568dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608690560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2608690560
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2596138349
Short name T211
Test name
Test status
Simulation time 6019306662 ps
CPU time 106.8 seconds
Started Jul 21 05:29:58 PM PDT 24
Finished Jul 21 05:31:45 PM PDT 24
Peak memory 200260 kb
Host smart-6072a673-12cf-4b86-bab0-f7e64c9e6753
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596138349 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2596138349
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2493649836
Short name T474
Test name
Test status
Simulation time 10072974639 ps
CPU time 117.26 seconds
Started Jul 21 05:29:57 PM PDT 24
Finished Jul 21 05:31:54 PM PDT 24
Peak memory 200172 kb
Host smart-9a3d232b-7573-4d6a-9854-b0a022276e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493649836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2493649836
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.641291795
Short name T227
Test name
Test status
Simulation time 47339062 ps
CPU time 0.59 seconds
Started Jul 21 05:24:35 PM PDT 24
Finished Jul 21 05:24:36 PM PDT 24
Peak memory 196192 kb
Host smart-e2162e3b-b611-4181-a690-edc33ff0795b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641291795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.641291795
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3971331288
Short name T373
Test name
Test status
Simulation time 7663253006 ps
CPU time 106.62 seconds
Started Jul 21 05:24:29 PM PDT 24
Finished Jul 21 05:26:16 PM PDT 24
Peak memory 215684 kb
Host smart-1903a1ad-0cd7-4a99-b308-19dd376c8f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971331288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3971331288
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1946132071
Short name T78
Test name
Test status
Simulation time 18942705576 ps
CPU time 51.71 seconds
Started Jul 21 05:24:28 PM PDT 24
Finished Jul 21 05:25:20 PM PDT 24
Peak memory 200312 kb
Host smart-69fb29d0-86a3-48d9-9d02-f1f3ec50bcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946132071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1946132071
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2103967020
Short name T415
Test name
Test status
Simulation time 8486187991 ps
CPU time 550.52 seconds
Started Jul 21 05:24:29 PM PDT 24
Finished Jul 21 05:33:40 PM PDT 24
Peak memory 629420 kb
Host smart-d355c1cc-9aef-4011-a7fe-630a95d23f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103967020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2103967020
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1365860257
Short name T271
Test name
Test status
Simulation time 5844499369 ps
CPU time 17.73 seconds
Started Jul 21 05:24:27 PM PDT 24
Finished Jul 21 05:24:45 PM PDT 24
Peak memory 200188 kb
Host smart-13b748cc-4080-4400-94c4-6d260ff3c195
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365860257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1365860257
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2631433432
Short name T255
Test name
Test status
Simulation time 4042472776 ps
CPU time 57.95 seconds
Started Jul 21 05:24:24 PM PDT 24
Finished Jul 21 05:25:22 PM PDT 24
Peak memory 200232 kb
Host smart-084d2eec-4b30-4dfd-8fb2-c797905b42c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631433432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2631433432
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3397418585
Short name T519
Test name
Test status
Simulation time 686206068 ps
CPU time 13.22 seconds
Started Jul 21 05:24:23 PM PDT 24
Finished Jul 21 05:24:36 PM PDT 24
Peak memory 200204 kb
Host smart-67b6f6eb-505b-42c8-9118-ab2ecf652fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397418585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3397418585
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2183085587
Short name T379
Test name
Test status
Simulation time 3983707981 ps
CPU time 75.18 seconds
Started Jul 21 05:24:36 PM PDT 24
Finished Jul 21 05:25:51 PM PDT 24
Peak memory 200236 kb
Host smart-b31e4f4a-cf7f-4ee4-afe4-d7377ad777e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183085587 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2183085587
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2470403806
Short name T54
Test name
Test status
Simulation time 32286288563 ps
CPU time 812.82 seconds
Started Jul 21 05:24:35 PM PDT 24
Finished Jul 21 05:38:08 PM PDT 24
Peak memory 674856 kb
Host smart-cda122fd-b446-4170-9216-b5f0b32b189d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470403806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2470403806
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1693020030
Short name T289
Test name
Test status
Simulation time 6095855856 ps
CPU time 75.77 seconds
Started Jul 21 05:24:31 PM PDT 24
Finished Jul 21 05:25:47 PM PDT 24
Peak memory 200416 kb
Host smart-c6c36897-52ac-4271-a5ae-afd4ac40e469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693020030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1693020030
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4055846525
Short name T17
Test name
Test status
Simulation time 13183943 ps
CPU time 0.56 seconds
Started Jul 21 05:24:39 PM PDT 24
Finished Jul 21 05:24:40 PM PDT 24
Peak memory 195024 kb
Host smart-34011d3d-30ad-4e8c-af0b-336c584aa2eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055846525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4055846525
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2869132312
Short name T513
Test name
Test status
Simulation time 501150136 ps
CPU time 13.96 seconds
Started Jul 21 05:24:35 PM PDT 24
Finished Jul 21 05:24:49 PM PDT 24
Peak memory 200192 kb
Host smart-9eabb945-e8b9-45ac-9d35-b85fe8261375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869132312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2869132312
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.381806759
Short name T130
Test name
Test status
Simulation time 731126200 ps
CPU time 39.56 seconds
Started Jul 21 05:24:37 PM PDT 24
Finished Jul 21 05:25:17 PM PDT 24
Peak memory 200156 kb
Host smart-8d9fedb1-a48e-48ac-918f-54b90ce66dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381806759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.381806759
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1294939317
Short name T521
Test name
Test status
Simulation time 11221057875 ps
CPU time 1037.46 seconds
Started Jul 21 05:24:34 PM PDT 24
Finished Jul 21 05:41:52 PM PDT 24
Peak memory 767404 kb
Host smart-f6021bb6-8186-4793-b4a2-e159cb75a536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294939317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1294939317
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1919395565
Short name T443
Test name
Test status
Simulation time 24698050283 ps
CPU time 153.41 seconds
Started Jul 21 05:24:36 PM PDT 24
Finished Jul 21 05:27:09 PM PDT 24
Peak memory 200176 kb
Host smart-14a8ccc4-ace3-4a9f-b622-4a98184950d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919395565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1919395565
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.767433096
Short name T383
Test name
Test status
Simulation time 35513138932 ps
CPU time 168.95 seconds
Started Jul 21 05:24:36 PM PDT 24
Finished Jul 21 05:27:25 PM PDT 24
Peak memory 200248 kb
Host smart-bfec6c7e-cf87-4449-b01f-64f576da2949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767433096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.767433096
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4225934880
Short name T171
Test name
Test status
Simulation time 136882983 ps
CPU time 5.89 seconds
Started Jul 21 05:24:35 PM PDT 24
Finished Jul 21 05:24:41 PM PDT 24
Peak memory 200116 kb
Host smart-de209296-49b4-48fc-9583-eae53f7ccb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225934880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4225934880
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2998662528
Short name T111
Test name
Test status
Simulation time 43444606026 ps
CPU time 1661.73 seconds
Started Jul 21 05:24:36 PM PDT 24
Finished Jul 21 05:52:18 PM PDT 24
Peak memory 739668 kb
Host smart-2c41e45d-2efb-4465-ba43-5aeaeb0818a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998662528 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2998662528
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2602345588
Short name T10
Test name
Test status
Simulation time 1738838104939 ps
CPU time 3299.76 seconds
Started Jul 21 05:24:41 PM PDT 24
Finished Jul 21 06:19:41 PM PDT 24
Peak memory 790508 kb
Host smart-cd41c9c2-af1a-4be2-8c43-4db9ef824476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602345588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2602345588
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3503395369
Short name T18
Test name
Test status
Simulation time 1660438208 ps
CPU time 5.61 seconds
Started Jul 21 05:24:38 PM PDT 24
Finished Jul 21 05:24:44 PM PDT 24
Peak memory 200332 kb
Host smart-67a04409-ef43-49d4-b438-5d521bb7c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503395369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3503395369
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3303957274
Short name T182
Test name
Test status
Simulation time 25352820 ps
CPU time 0.58 seconds
Started Jul 21 05:24:59 PM PDT 24
Finished Jul 21 05:25:00 PM PDT 24
Peak memory 195684 kb
Host smart-f9034997-e713-4b23-b027-a9eaa2705337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303957274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3303957274
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2335030459
Short name T408
Test name
Test status
Simulation time 437073714 ps
CPU time 11.89 seconds
Started Jul 21 05:24:46 PM PDT 24
Finished Jul 21 05:24:58 PM PDT 24
Peak memory 200076 kb
Host smart-3a3c5b8b-2b82-47ae-9c50-e51b5962eb82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335030459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2335030459
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3966835983
Short name T138
Test name
Test status
Simulation time 1015262411 ps
CPU time 14.23 seconds
Started Jul 21 05:24:47 PM PDT 24
Finished Jul 21 05:25:02 PM PDT 24
Peak memory 200068 kb
Host smart-61165f52-19c7-46ed-9b96-acd4fc7304b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966835983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3966835983
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2219745522
Short name T395
Test name
Test status
Simulation time 3475672294 ps
CPU time 552.06 seconds
Started Jul 21 05:24:48 PM PDT 24
Finished Jul 21 05:34:00 PM PDT 24
Peak memory 498780 kb
Host smart-b4a03384-321c-42ea-a526-7866ecf92063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219745522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2219745522
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1678242351
Short name T201
Test name
Test status
Simulation time 12940031515 ps
CPU time 188.58 seconds
Started Jul 21 05:24:52 PM PDT 24
Finished Jul 21 05:28:01 PM PDT 24
Peak memory 200124 kb
Host smart-2ccf0950-c83e-42dc-8f4c-57ea70b9feff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678242351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1678242351
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2336135183
Short name T165
Test name
Test status
Simulation time 18326736694 ps
CPU time 58.84 seconds
Started Jul 21 05:24:48 PM PDT 24
Finished Jul 21 05:25:47 PM PDT 24
Peak memory 200228 kb
Host smart-478da856-1339-43e5-a8d4-85ec31ced377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336135183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2336135183
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1415941750
Short name T218
Test name
Test status
Simulation time 3711188735 ps
CPU time 11.29 seconds
Started Jul 21 05:24:40 PM PDT 24
Finished Jul 21 05:24:52 PM PDT 24
Peak memory 200180 kb
Host smart-b2ba2109-5ea9-4b18-8579-9317de71e2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415941750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1415941750
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1440687483
Short name T478
Test name
Test status
Simulation time 18737648402 ps
CPU time 530.87 seconds
Started Jul 21 05:25:00 PM PDT 24
Finished Jul 21 05:33:52 PM PDT 24
Peak memory 461396 kb
Host smart-ad506ad7-69ce-4685-807a-f227e415fffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440687483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1440687483
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2977594337
Short name T435
Test name
Test status
Simulation time 1168615088 ps
CPU time 50.28 seconds
Started Jul 21 05:24:52 PM PDT 24
Finished Jul 21 05:25:43 PM PDT 24
Peak memory 200160 kb
Host smart-f2cc9651-e6f3-4052-818f-0cbafdf90c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977594337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2977594337
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2181495788
Short name T88
Test name
Test status
Simulation time 12178746 ps
CPU time 0.58 seconds
Started Jul 21 05:25:06 PM PDT 24
Finished Jul 21 05:25:07 PM PDT 24
Peak memory 196140 kb
Host smart-90fa0bb6-b1fb-40ca-b24b-9e758cc0cc54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181495788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2181495788
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.481538241
Short name T358
Test name
Test status
Simulation time 2207862196 ps
CPU time 39.14 seconds
Started Jul 21 05:24:59 PM PDT 24
Finished Jul 21 05:25:38 PM PDT 24
Peak memory 200292 kb
Host smart-0183896a-8487-4f0a-9a66-6093f4f78b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481538241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.481538241
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3025766809
Short name T413
Test name
Test status
Simulation time 3011523221 ps
CPU time 56.64 seconds
Started Jul 21 05:24:59 PM PDT 24
Finished Jul 21 05:25:56 PM PDT 24
Peak memory 200160 kb
Host smart-1649bb6f-bfeb-4054-a580-906caefd7a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025766809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3025766809
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4183816423
Short name T162
Test name
Test status
Simulation time 7588402395 ps
CPU time 608.57 seconds
Started Jul 21 05:25:00 PM PDT 24
Finished Jul 21 05:35:09 PM PDT 24
Peak memory 729184 kb
Host smart-dcb06cc3-eef5-4578-b59e-ae65802d7608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183816423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4183816423
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.284007100
Short name T248
Test name
Test status
Simulation time 383735263 ps
CPU time 3.88 seconds
Started Jul 21 05:25:00 PM PDT 24
Finished Jul 21 05:25:04 PM PDT 24
Peak memory 200112 kb
Host smart-a5625e30-fbde-4307-9dd2-c7eb6f02e29d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284007100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.284007100
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3099291747
Short name T496
Test name
Test status
Simulation time 2804611582 ps
CPU time 40.02 seconds
Started Jul 21 05:24:59 PM PDT 24
Finished Jul 21 05:25:40 PM PDT 24
Peak memory 200220 kb
Host smart-5a0bbd92-4d29-4774-8b73-1816cc9be489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099291747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3099291747
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.224991144
Short name T146
Test name
Test status
Simulation time 1227169912 ps
CPU time 7.06 seconds
Started Jul 21 05:24:58 PM PDT 24
Finished Jul 21 05:25:05 PM PDT 24
Peak memory 200212 kb
Host smart-850df533-3fbc-470e-b5f3-5eb448dfb351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224991144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.224991144
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3233834785
Short name T230
Test name
Test status
Simulation time 37147622583 ps
CPU time 183.64 seconds
Started Jul 21 05:25:04 PM PDT 24
Finished Jul 21 05:28:08 PM PDT 24
Peak memory 208452 kb
Host smart-65291011-1341-418f-9dd5-8540b528316e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233834785 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3233834785
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1832584578
Short name T56
Test name
Test status
Simulation time 91194978011 ps
CPU time 2108.98 seconds
Started Jul 21 05:25:04 PM PDT 24
Finished Jul 21 06:00:14 PM PDT 24
Peak memory 777740 kb
Host smart-f213c406-dc28-4cc9-81c1-9359e6e5cd85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832584578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1832584578
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1639227499
Short name T2
Test name
Test status
Simulation time 6581155327 ps
CPU time 85.28 seconds
Started Jul 21 05:25:03 PM PDT 24
Finished Jul 21 05:26:28 PM PDT 24
Peak memory 200232 kb
Host smart-b77f6c46-e38d-4006-bb5a-5f5cd1eeec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639227499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1639227499
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1127142338
Short name T453
Test name
Test status
Simulation time 14683192 ps
CPU time 0.61 seconds
Started Jul 21 05:25:17 PM PDT 24
Finished Jul 21 05:25:18 PM PDT 24
Peak memory 196808 kb
Host smart-4ccc4d5a-4e7a-45ee-9aac-b8b365f7d17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127142338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1127142338
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.960140509
Short name T30
Test name
Test status
Simulation time 17944295516 ps
CPU time 53.16 seconds
Started Jul 21 05:25:11 PM PDT 24
Finished Jul 21 05:26:04 PM PDT 24
Peak memory 200188 kb
Host smart-c78e045e-14b3-4e06-b403-2d783293fe30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960140509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.960140509
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2481705180
Short name T114
Test name
Test status
Simulation time 9706337119 ps
CPU time 27.33 seconds
Started Jul 21 05:25:11 PM PDT 24
Finished Jul 21 05:25:39 PM PDT 24
Peak memory 200240 kb
Host smart-6b5861ca-aeb0-4a65-b5c4-565e812c5be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481705180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2481705180
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3467432704
Short name T424
Test name
Test status
Simulation time 5121620077 ps
CPU time 936.8 seconds
Started Jul 21 05:25:10 PM PDT 24
Finished Jul 21 05:40:48 PM PDT 24
Peak memory 718420 kb
Host smart-42443a43-91f5-4e6a-a844-4948cfe15fe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467432704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3467432704
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1927242058
Short name T465
Test name
Test status
Simulation time 7451883150 ps
CPU time 105.7 seconds
Started Jul 21 05:25:10 PM PDT 24
Finished Jul 21 05:26:56 PM PDT 24
Peak memory 200048 kb
Host smart-c02785e9-66ca-4f6d-8000-c5a79b3f3762
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927242058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1927242058
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3108486082
Short name T249
Test name
Test status
Simulation time 6812606793 ps
CPU time 196.07 seconds
Started Jul 21 05:25:11 PM PDT 24
Finished Jul 21 05:28:28 PM PDT 24
Peak memory 216512 kb
Host smart-60be45bb-5406-4f3d-8a60-79d733ee3346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108486082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3108486082
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.139496408
Short name T46
Test name
Test status
Simulation time 22599164 ps
CPU time 1.2 seconds
Started Jul 21 05:25:05 PM PDT 24
Finished Jul 21 05:25:06 PM PDT 24
Peak memory 200188 kb
Host smart-afa9194f-cd05-4ec9-825b-24c44af3f51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139496408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.139496408
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2830750339
Short name T375
Test name
Test status
Simulation time 64419642022 ps
CPU time 419.25 seconds
Started Jul 21 05:25:16 PM PDT 24
Finished Jul 21 05:32:16 PM PDT 24
Peak memory 208360 kb
Host smart-d26c8bf8-8d88-4b9f-abca-04865d33db75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830750339 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2830750339
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.818079246
Short name T407
Test name
Test status
Simulation time 18327603282 ps
CPU time 126.33 seconds
Started Jul 21 05:25:13 PM PDT 24
Finished Jul 21 05:27:19 PM PDT 24
Peak memory 200252 kb
Host smart-e2ca8faf-2f0d-40e6-b168-ce6e62b882dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818079246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.818079246
Directory /workspace/9.hmac_wipe_secret/latest
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