Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19961109	1			T2	404935		T3	8546		T6	6845
all_values[1]	19961109	1			T2	404935		T3	8546		T6	6845
all_values[2]	19961109	1			T2	404935		T3	8546		T6	6845

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252684

1

T2

645

T3

2

T7

27

auto[1]

59630643

1

T2

121416

T3

25636

T6

20535

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50897916

1

T2

104387

T3

17744

T6

16680

auto[1]

8985411

1

T2

170927

T3

7894

T6

3855

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92932	1			T2	503		T7	25		T16	163
all_values[0]	auto[0]	auto[1]	431	1			T2	14		T7	2		T16	8
all_values[0]	auto[1]	auto[0]	19846518	1			T2	404048		T3	8544		T6	6844
all_values[0]	auto[1]	auto[1]	21228	1			T2	370		T3	2		T6	1
all_values[1]	auto[0]	auto[0]	80073	1			T2	60		T16	177		T26	257
all_values[1]	auto[0]	auto[1]	245	1			T2	8		T16	6		T24	2
all_values[1]	auto[1]	auto[0]	19880404	1			T2	404850		T3	8546		T6	6845
all_values[1]	auto[1]	auto[1]	387	1			T2	17		T16	18		T24	6
all_values[2]	auto[0]	auto[0]	43034	1			T2	29		T3	1		T16	335
all_values[2]	auto[0]	auto[1]	35969	1			T2	31		T3	1		T16	1473
all_values[2]	auto[1]	auto[0]	10954955	1			T2	234388		T3	653		T6	2991
all_values[2]	auto[1]	auto[1]	8927151	1			T2	170487		T3	7891		T6	3854