Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163427

1

T2

1665

T3

26

T6

10

auto[1]

141352

1

T2

2762

T3

14

T6

8

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	119390	1			T2	1676		T3	8		T6	3
len_1026_2046	7904	1			T2	304		T3	2		T7	2
len_514_1022	4024	1			T2	53		T7	2		T16	53
len_2_510	4933	1			T2	27		T15	4		T16	37
len_2056	178	1			T2	1		T7	4		T24	6
len_2048	431	1			T2	13		T7	1		T16	12
len_2040	204	1			T2	4		T7	1		T16	5
len_1032	184	1			T2	1		T16	6		T24	3
len_1024	1813	1			T2	9		T14	93		T4	1
len_1016	163	1			T2	8		T7	2		T16	1
len_520	179	1			T2	3		T7	2		T24	2
len_512	395	1			T2	7		T7	3		T16	3
len_504	231	1			T2	8		T16	2		T103	1
len_8	1398	1			T2	35		T4	10		T24	12
len_0	10963	1			T2	65		T3	10		T6	6

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

109

1

T23

2

T18

6

T37

3

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	67769	1			T2	669		T3	5		T15	19
auto[0]	len_1026_2046	3539	1			T2	70		T15	3		T16	50
auto[0]	len_514_1022	2260	1			T2	12		T7	1		T16	30
auto[0]	len_2_510	2618	1			T2	17		T15	2		T16	21
auto[0]	len_2056	90	1			T2	1		T7	1		T24	1
auto[0]	len_2048	251	1			T2	7		T7	1		T16	9
auto[0]	len_2040	128	1			T16	2		T103	1		T24	1
auto[0]	len_1032	116	1			T2	1		T16	4		T24	3
auto[0]	len_1024	251	1			T2	4		T16	4		T23	1
auto[0]	len_1016	94	1			T2	3		T16	1		T24	5
auto[0]	len_520	104	1			T2	2		T7	2		T24	1
auto[0]	len_512	234	1			T2	2		T7	2		T16	2
auto[0]	len_504	119	1			T2	6		T103	1		T24	7
auto[0]	len_8	30	1			T18	1		T74	1		T116	2
auto[0]	len_0	4111	1			T2	39		T3	8		T6	5
auto[1]	len_2050_plus	51621	1			T2	1007		T3	3		T6	3
auto[1]	len_1026_2046	4365	1			T2	234		T3	2		T7	2
auto[1]	len_514_1022	1764	1			T2	41		T7	1		T16	23
auto[1]	len_2_510	2315	1			T2	10		T15	2		T16	16
auto[1]	len_2056	88	1			T7	3		T24	5		T72	1
auto[1]	len_2048	180	1			T2	6		T16	3		T23	2
auto[1]	len_2040	76	1			T2	4		T7	1		T16	3
auto[1]	len_1032	68	1			T16	2		T18	2		T61	2
auto[1]	len_1024	1562	1			T2	5		T14	93		T4	1
auto[1]	len_1016	69	1			T2	5		T7	2		T24	1
auto[1]	len_520	75	1			T2	1		T24	1		T18	1
auto[1]	len_512	161	1			T2	5		T7	1		T16	1
auto[1]	len_504	112	1			T2	2		T16	2		T24	2
auto[1]	len_8	1368	1			T2	35		T4	10		T24	12
auto[1]	len_0	6852	1			T2	26		T3	2		T6	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

61

1

T18

6

T117

2

T47

2

auto[1]

len_upper

48

1

T23

2

T37

3

T118

1