Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4962746

1

T2

86402

T3

52

T6

1397

auto[1]

3289377

1

T2

89640

T3

288

T6

349

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3221148

1

T2

97008

T3

329

T6

595

auto[1]

5030975

1

T2

79034

T3

11

T6

1151

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3599008

1

T2

69824

T3

15

T6

350

auto[1]

4653115

1

T2

106218

T3

325

T6

1396

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5050887

1

T2

93078

T3

55

T6

1150

auto[1]

3201236

1

T2

82964

T3

285

T6

596

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7495315	1			T2	150805		T3	332		T6	1713
fifo_depth[1]	124811	1			T2	3787		T3	8		T6	28
fifo_depth[2]	93735	1			T2	3608		T6	5		T7	15
fifo_depth[3]	73265	1			T2	3203		T7	17		T14	123
fifo_depth[4]	67434	1			T2	2873		T7	12		T14	96
fifo_depth[5]	53045	1			T2	2334		T7	10		T14	45
fifo_depth[6]	43094	1			T2	1825		T7	12		T14	16
fifo_depth[7]	28705	1			T2	1199		T7	6		T14	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

756808

1

T2

25237

T3

8

T6

33

auto[1]

7495315

1

T2

150805

T3

332

T6

1713

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8238512

1

T2

175792

T3

340

T6

1746

auto[1]

13611

1

T2

250

T16

1289

T24

392

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

34817

1

T2

1382

T16

3120

T26

73

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29389

1

T2

985

T7

8

T15

259

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

37482

1

T2

1147

T7

3

T15

227

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

38658

1

T2

1072

T15

35

T16

2979

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

139595

1

T2

1190

T15

29

T16

7608

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

46092

1

T2

1496

T16

1106

T23

20

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44292

1

T2

2049

T7

12

T16

1593

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

39976

1

T2

1991

T15

140

T16

2600

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46180

1

T2

2643

T3

2

T7

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43230

1

T2

1793

T16

739

T23

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41031

1

T2

2310

T4

285

T16

535

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

44665

1

T2

1192

T3

6

T7

35

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43315

1

T2

1774

T6

33

T7

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35288

1

T2

691

T7

6

T15

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

49710

1

T2

2273

T4

748

T16

481

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43088

1

T2

1249

T7

9

T15

67

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

196872

1

T2

5378

T3

2

T15

486

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

202965

1

T2

7883

T3

1

T7

127

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

199203

1

T2

7144

T3

3

T7

33

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

201259

1

T2

6248

T3

1

T6

347

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1794823

1

T2

7831

T3

1

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

201394

1

T2

5832

T3

2

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

193401

1

T2

7739

T3

3

T7

97

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

198790

1

T2

10457

T3

2

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

521475

1

T2

15692

T3

39

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

512398

1

T2

13827

T3

3

T6

247

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

515724

1

T2

17434

T3

2

T7

58

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

555800

1

T2

10878

T3

270

T7

117

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

616589

1

T2

9035

T3

2

T6

1114

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

498324

1

T2

8970

T7

23

T4

379

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

576378

1

T2

8057

T3

1

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

509920

1

T2

8400

T7

5

T4

3492

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

231118

1

T2

6760

T3

2

T15

486

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

231920

1

T2

8868

T3

1

T7

135

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

235137

1

T2

8291

T3

3

T7

36

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

238164

1

T2

7320

T3

1

T6

347

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1933732

1

T2

8962

T3

1

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

245100

1

T2

7298

T3

2

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

235905

1

T2

9778

T3

3

T7

109

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

237640

1

T2

12448

T3

2

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

567432

1

T2

18335

T3

41

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

555357

1

T2

15616

T3

3

T6

247

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

555642

1

T2

19744

T3

2

T7

58

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

600144

1

T2

12070

T3

276

T7

152

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

659713

1

T2

10780

T3

2

T6

1147

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

533142

1

T2

9584

T7

29

T4

379

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

625924

1

T2

10319

T3

1

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

552442

1

T2

9619

T7

14

T4

3492

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

571

1

T16

125

T24

2

T106

15

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

434

1

T16

32

T106

21

T122

45

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1548

1

T16

87

T18

1

T19

80

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1753

1

T16

496

T19

4

T106

65

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

686

1

T2

59

T16

107

T18

32

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2386

1

T2

30

T16

1

T24

127

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1788

1

T2

10

T16

4

T24

137

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1126

1

T16

100

T18

7

T106

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

223

1

T16

3

T19

55

T35

47

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

271

1

T2

4

T16

1

T18

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1113

1

T16

6

T106

163

T122

54

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

321

1

T16

239

T19

7

T35

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

191

1

T2

29

T24

66

T122

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

470

1

T2

77

T16

2

T18

14

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

164

1

T2

11

T16

7

T24

24

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

566

1

T2

30

T16

79

T24

36

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

196872

1

T2

5378

T3

2

T15

486

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

202965

1

T2

7883

T3

1

T7

127

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

199203

1

T2

7144

T3

3

T7

33

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

201259

1

T2

6248

T3

1

T6

347

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1794823

1

T2

7831

T3

1

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

201394

1

T2

5832

T3

2

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

193401

1

T2

7739

T3

3

T7

97

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

198790

1

T2

10457

T3

2

T6

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

521475

1

T2

15692

T3

39

T6

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

512398

1

T2

13827

T3

3

T6

247

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

515724

1

T2

17434

T3

2

T7

58

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

555800

1

T2

10878

T3

270

T7

117

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

616589

1

T2

9035

T3

2

T6

1114

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

498324

1

T2

8970

T7

23

T4

379

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

576378

1

T2

8057

T3

1

T6

1

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

509920

1

T2

8400

T7

5

T4

3492

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3735

1

T2

280

T16

44

T26

12

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3629

1

T2

170

T15

47

T16

13

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3969

1

T2

257

T7

1

T15

86

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4155

1

T2

181

T15

10

T16

12

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

38139

1

T2

181

T15

9

T16

185

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4141

1

T2

143

T16

112

T23

7

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3998

1

T2

252

T7

2

T16

79

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3678

1

T2

272

T15

27

T16

47

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

7643

1

T2

501

T3

2

T7

2

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6851

1

T2

156

T16

113

T23

6

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

7250

1

T2

444

T4

37

T16

18

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

7662

1

T2

262

T3

6

T7

5

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9060

1

T2

262

T6

28

T7

1

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5743

1

T2

47

T7

1

T16

17

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

8126

1

T2

238

T4

121

T16

16

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

7032

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13

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204

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4

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20

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38

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22

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17

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192

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37

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115

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93

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T2

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27

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49

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T2

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T16

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T2

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42

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T2

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65

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T2

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62

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101

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132

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T2

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T2

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T2

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T2

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fifo_depth[5]

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T2

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16

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109

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16

fifo_depth[6]

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T2

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T2

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fifo_depth[6]

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T2

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60

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26

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fifo_depth[6]

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203

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33

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22

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T2

84

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61

fifo_depth[6]

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T2

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7

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T2

86

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6

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T2

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16

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T2

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119

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fifo_depth[7]

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T2

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16

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6

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T2

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T16

120

T26

11

fifo_depth[7]

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T2

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64

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9

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1

T2

44

T7

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T16

73

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1

T2

128

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4

T16

44

fifo_depth[7]

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1

T2

172

T7

1

T4

11

fifo_depth[7]

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1

T2

78

T16

21

T26

1

fifo_depth[7]

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1

T2

118

T4

27

T16

17

fifo_depth[7]

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1

T2

51

T7

1

T16

35

fifo_depth[7]

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1

T2

91

T7

1

T14

3

fifo_depth[7]

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1

T2

9

T16

21

T103

1

fifo_depth[7]

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1

T2

97

T4

63

T16

16

fifo_depth[7]

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1

T2

66

T7

1

T16

10