Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19961109	1			T2	404935		T3	8546		T6	6845
all_pins[1]	19961109	1			T2	404935		T3	8546		T6	6845
all_pins[2]	19961109	1			T2	404935		T3	8546		T6	6845

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50933669	1			T2	104391		T3	17745		T6	16680
values[0x1]	8949658	1			T2	170889		T3	7893		T6	3855
transitions[0x0=>0x1]	8949454	1			T2	170883		T3	7893		T6	3855
transitions[0x1=>0x0]	8949464	1			T2	170883		T3	7893		T6	3855

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19939014	1			T2	404550		T3	8544		T6	6844
all_pins[0]	values[0x1]	22095	1			T2	385		T3	2		T6	1
all_pins[0]	transitions[0x0=>0x1]	22025	1			T2	384		T3	2		T6	1
all_pins[0]	transitions[0x1=>0x0]	8927091	1			T2	170486		T3	7891		T6	3854
all_pins[1]	values[0x0]	19960697	1			T2	404918		T3	8546		T6	6845
all_pins[1]	values[0x1]	412	1			T2	17		T16	21		T24	7
all_pins[1]	transitions[0x0=>0x1]	346	1			T2	14		T16	21		T24	6
all_pins[1]	transitions[0x1=>0x0]	22029	1			T2	382		T3	2		T6	1
all_pins[2]	values[0x0]	11033958	1			T2	234448		T3	655		T6	2991
all_pins[2]	values[0x1]	8927151	1			T2	170487		T3	7891		T6	3854
all_pins[2]	transitions[0x0=>0x1]	8927083	1			T2	170485		T3	7891		T6	3854
all_pins[2]	transitions[0x1=>0x0]	344	1			T2	15		T16	21		T24	6