Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1175 1 T2 49 T16 18 T24 17
all_values[1] 1175 1 T2 49 T16 18 T24 17
all_values[2] 1175 1 T2 49 T16 18 T24 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1783 1 T2 85 T16 38 T24 17
auto[1] 1742 1 T2 62 T16 16 T24 34


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1225 1 T2 46 T16 19 T24 13
auto[1] 2300 1 T2 101 T16 35 T24 38


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2003 1 T2 84 T16 30 T24 26
auto[1] 1522 1 T2 63 T16 24 T24 25


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 240 1 T2 9 T16 6 T24 1
all_values[0] auto[0] auto[0] auto[1] 110 1 T2 6 T16 2 T24 1
all_values[0] auto[0] auto[1] auto[0] 199 1 T2 4 T16 3 T24 1
all_values[0] auto[0] auto[1] auto[1] 112 1 T2 4 T16 1 T24 3
all_values[0] auto[1] auto[0] auto[1] 267 1 T2 16 T16 6 T24 3
all_values[0] auto[1] auto[1] auto[1] 247 1 T2 10 T24 8 T18 3
all_values[1] auto[0] auto[0] auto[0] 197 1 T2 8 T16 3 T24 4
all_values[1] auto[0] auto[0] auto[1] 146 1 T2 14 T16 4 T18 2
all_values[1] auto[0] auto[1] auto[0] 192 1 T2 1 T16 2 T24 3
all_values[1] auto[0] auto[1] auto[1] 140 1 T2 3 T24 3 T18 3
all_values[1] auto[1] auto[0] auto[1] 250 1 T2 8 T16 6 T24 4
all_values[1] auto[1] auto[1] auto[1] 250 1 T2 15 T16 3 T24 3
all_values[2] auto[0] auto[0] auto[0] 188 1 T2 12 T16 3 T18 1
all_values[2] auto[0] auto[0] auto[1] 126 1 T2 5 T16 3 T24 2
all_values[2] auto[0] auto[1] auto[0] 209 1 T2 12 T16 2 T24 4
all_values[2] auto[0] auto[1] auto[1] 144 1 T2 6 T16 1 T24 4
all_values[2] auto[1] auto[0] auto[1] 259 1 T2 7 T16 5 T24 2
all_values[2] auto[1] auto[1] auto[1] 249 1 T2 7 T16 4 T24 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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