Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4823	1			T2	133		T3	4		T7	4
sha2_none	4838	1			T2	123		T3	3		T6	1
sha2_512	8253	1			T2	136		T3	1		T6	2
sha2_384	7780	1			T2	133		T3	4		T6	3
sha2_256	6845	1			T2	141		T3	5		T7	9

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20153

1

T2

333

T3

9

T6

4

auto[1]

12819

1

T2

341

T3

8

T6

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12603

1

T2

356

T3

11

T6

2

auto[1]

20369

1

T2

318

T3

6

T6

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17167

1

T2

376

T3

9

T6

3

disabled

15805

1

T2

298

T3

8

T6

3

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5350	1			T2	137		T3	4		T6	2
key_none	8160	1			T2	109		T3	5		T7	6
key_1024	4659	1			T2	84		T3	1		T7	7
key_512	4122	1			T2	77		T3	3		T6	1
key_384	3827	1			T2	84		T3	1		T7	9
key_256	3464	1			T2	92		T3	2		T7	3
key_128	3291	1			T2	89		T3	1		T6	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20412

1

T2

350

T3

11

T6

3

auto[1]

12560

1

T2

324

T3

6

T6

3

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32759

1

T2

670

T3

16

T6

6

disabled

213

1

T2

4

T3

1

T15

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1845

1

T2

50

T3

1

T7

3

enabled

auto[0]

auto[0]

auto[1]

1697

1

T2

45

T3

2

T6

1

enabled

auto[0]

auto[1]

auto[0]

1740

1

T2

52

T3

1

T7

2

enabled

auto[0]

auto[1]

auto[1]

1884

1

T2

58

T3

2

T7

5

enabled

auto[1]

auto[0]

auto[0]

4533

1

T2

51

T3

2

T6

1

enabled

auto[1]

auto[0]

auto[1]

1720

1

T2

37

T7

2

T4

1

enabled

auto[1]

auto[1]

auto[0]

1943

1

T2

46

T3

1

T6

1

enabled

auto[1]

auto[1]

auto[1]

1805

1

T2

37

T7

1

T4

4

disabled

auto[0]

auto[0]

auto[0]

1338

1

T2

35

T3

3

T15

1

disabled

auto[0]

auto[0]

auto[1]

1367

1

T2

38

T7

6

T15

5

disabled

auto[0]

auto[1]

auto[0]

1387

1

T2

45

T3

1

T7

3

disabled

auto[0]

auto[1]

auto[1]

1345

1

T2

33

T3

1

T6

1

disabled

auto[1]

auto[0]

auto[0]

6233

1

T2

40

T3

1

T6

1

disabled

auto[1]

auto[0]

auto[1]

1420

1

T2

37

T6

1

T7

4

disabled

auto[1]

auto[1]

auto[0]

1393

1

T2

31

T3

1

T7

4

disabled

auto[1]

auto[1]

auto[1]

1322

1

T2

39

T3

1

T15

5

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17087

1

T2

374

T3

9

T6

3

enabled

disabled

80

1

T2

2

T16

1

T104

2

disabled

disabled

133

1

T2

2

T3

1

T15

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15672

1

T2

296

T3

7

T6

3

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1274	1			T2	33		T3	3		T7	2
key_invalid	sha2_none	1029	1			T2	30		T6	1		T7	3
key_invalid	sha2_512	1008	1			T2	25		T6	1		T7	2
key_invalid	sha2_384	931	1			T2	24		T4	1		T15	1
key_invalid	sha2_256	988	1			T2	24		T3	1		T7	1
key_none	sha2_invalid	601	1			T2	18		T3	1		T7	1
key_none	sha2_none	673	1			T2	26		T3	2		T7	2
key_none	sha2_512	2586	1			T2	21		T4	3		T15	1
key_none	sha2_384	2582	1			T2	16		T3	1		T7	3
key_none	sha2_256	1670	1			T2	28		T3	1		T4	1
key_1024	sha2_invalid	572	1			T2	19		T4	1		T16	8
key_1024	sha2_none	597	1			T2	11		T7	2		T4	1
key_1024	sha2_512	1799	1			T2	22		T7	1		T4	4
key_1024	sha2_384	983	1			T2	17		T7	2		T14	60
key_512	sha2_invalid	582	1			T2	9		T15	1		T16	4
key_512	sha2_none	612	1			T2	14		T7	2		T4	1
key_512	sha2_512	670	1			T2	19		T15	4		T16	8
key_512	sha2_384	1292	1			T2	14		T3	2		T6	1
key_512	sha2_256	917	1			T2	21		T3	1		T7	1
key_384	sha2_invalid	585	1			T2	14		T4	1		T15	2
key_384	sha2_none	620	1			T2	12		T7	2		T4	2
key_384	sha2_512	738	1			T2	20		T7	1		T4	1
key_384	sha2_384	699	1			T2	21		T7	2		T4	1
key_384	sha2_256	1129	1			T2	16		T3	1		T7	4
key_256	sha2_invalid	581	1			T2	16		T4	1		T16	6
key_256	sha2_none	661	1			T2	18		T3	1		T7	2
key_256	sha2_512	733	1			T2	13		T15	2		T16	9
key_256	sha2_384	645	1			T2	21		T3	1		T7	1
key_256	sha2_256	796	1			T2	22		T4	1		T15	1
key_128	sha2_invalid	605	1			T2	24		T7	1		T16	7
key_128	sha2_none	625	1			T2	12		T4	2		T16	4
key_128	sha2_512	699	1			T2	16		T3	1		T6	1
key_128	sha2_384	635	1			T2	19		T6	2		T16	8
key_128	sha2_256	671	1			T2	16		T7	1		T16	6

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

652

1

T2

13

T3

1

T7

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1274	1			T2	33		T3	3		T7	2
key_invalid	sha2_none	1029	1			T2	30		T6	1		T7	3
key_invalid	sha2_512	1008	1			T2	25		T6	1		T7	2
key_invalid	sha2_384	931	1			T2	24		T4	1		T15	1
key_invalid	sha2_256	988	1			T2	24		T3	1		T7	1
key_none	sha2_invalid	601	1			T2	18		T3	1		T7	1
key_none	sha2_none	673	1			T2	26		T3	2		T7	2
key_none	sha2_512	2586	1			T2	21		T4	3		T15	1
key_none	sha2_384	2582	1			T2	16		T3	1		T7	3
key_none	sha2_256	1670	1			T2	28		T3	1		T4	1
key_1024	sha2_invalid	572	1			T2	19		T4	1		T16	8
key_1024	sha2_none	597	1			T2	11		T7	2		T4	1
key_1024	sha2_512	1799	1			T2	22		T7	1		T4	4
key_1024	sha2_384	983	1			T2	17		T7	2		T14	60
key_1024	sha2_256	652	1			T2	13		T3	1		T7	2
key_512	sha2_invalid	582	1			T2	9		T15	1		T16	4
key_512	sha2_none	612	1			T2	14		T7	2		T4	1
key_512	sha2_512	670	1			T2	19		T15	4		T16	8
key_512	sha2_384	1292	1			T2	14		T3	2		T6	1
key_512	sha2_256	917	1			T2	21		T3	1		T7	1
key_384	sha2_invalid	585	1			T2	14		T4	1		T15	2
key_384	sha2_none	620	1			T2	12		T7	2		T4	2
key_384	sha2_512	738	1			T2	20		T7	1		T4	1
key_384	sha2_384	699	1			T2	21		T7	2		T4	1
key_384	sha2_256	1129	1			T2	16		T3	1		T7	4
key_256	sha2_invalid	581	1			T2	16		T4	1		T16	6
key_256	sha2_none	661	1			T2	18		T3	1		T7	2
key_256	sha2_512	733	1			T2	13		T15	2		T16	9
key_256	sha2_384	645	1			T2	21		T3	1		T7	1
key_256	sha2_256	796	1			T2	22		T4	1		T15	1
key_128	sha2_invalid	605	1			T2	24		T7	1		T16	7
key_128	sha2_none	625	1			T2	12		T4	2		T16	4
key_128	sha2_512	699	1			T2	16		T3	1		T6	1
key_128	sha2_384	635	1			T2	19		T6	2		T16	8
key_128	sha2_256	671	1			T2	16		T7	1		T16	6