Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.06 95.40 97.33 100.00 97.06 98.27 98.48 99.85


Total test records in report: 660
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T98 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1377228886 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:50 PM PDT 24 312300331 ps
T534 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.187225146 Jul 25 06:07:01 PM PDT 24 Jul 25 06:07:04 PM PDT 24 169762250 ps
T53 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3630364994 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:53 PM PDT 24 332811416 ps
T91 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2250990945 Jul 25 06:06:51 PM PDT 24 Jul 25 06:07:06 PM PDT 24 6080588665 ps
T54 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.20399503 Jul 25 06:06:58 PM PDT 24 Jul 25 06:07:00 PM PDT 24 800031488 ps
T535 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2303830061 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:51 PM PDT 24 153615565 ps
T536 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.311419870 Jul 25 06:06:42 PM PDT 24 Jul 25 06:06:43 PM PDT 24 21167604 ps
T537 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3788631692 Jul 25 06:07:03 PM PDT 24 Jul 25 06:07:04 PM PDT 24 44560351 ps
T538 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2646003551 Jul 25 06:06:53 PM PDT 24 Jul 25 06:06:55 PM PDT 24 48667001 ps
T539 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2139847232 Jul 25 06:07:01 PM PDT 24 Jul 25 06:07:01 PM PDT 24 46288071 ps
T82 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3709088794 Jul 25 06:06:36 PM PDT 24 Jul 25 06:06:45 PM PDT 24 595991168 ps
T540 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1128782464 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 12915971 ps
T541 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1789968957 Jul 25 06:06:56 PM PDT 24 Jul 25 06:06:57 PM PDT 24 171633724 ps
T542 /workspace/coverage/cover_reg_top/15.hmac_intr_test.789943770 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 45564553 ps
T543 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1620971928 Jul 25 06:06:37 PM PDT 24 Jul 25 06:06:53 PM PDT 24 3265604924 ps
T544 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3039622479 Jul 25 06:06:58 PM PDT 24 Jul 25 06:06:58 PM PDT 24 14817571 ps
T545 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2993991469 Jul 25 06:06:40 PM PDT 24 Jul 25 06:06:41 PM PDT 24 12715800 ps
T546 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3177443515 Jul 25 06:06:38 PM PDT 24 Jul 25 06:06:41 PM PDT 24 60488397 ps
T99 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.736823489 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:50 PM PDT 24 63607947 ps
T547 /workspace/coverage/cover_reg_top/43.hmac_intr_test.4097620552 Jul 25 06:06:57 PM PDT 24 Jul 25 06:06:58 PM PDT 24 43553880 ps
T548 /workspace/coverage/cover_reg_top/19.hmac_intr_test.513914917 Jul 25 06:07:05 PM PDT 24 Jul 25 06:07:05 PM PDT 24 15506614 ps
T83 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.273619353 Jul 25 06:07:22 PM PDT 24 Jul 25 06:07:28 PM PDT 24 593752742 ps
T549 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1313766069 Jul 25 06:06:46 PM PDT 24 Jul 25 06:06:46 PM PDT 24 18297907 ps
T550 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2959472380 Jul 25 06:07:01 PM PDT 24 Jul 25 06:07:02 PM PDT 24 44935227 ps
T551 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1641190992 Jul 25 06:06:58 PM PDT 24 Jul 25 06:06:59 PM PDT 24 112939742 ps
T84 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3292483145 Jul 25 06:06:46 PM PDT 24 Jul 25 06:06:47 PM PDT 24 15594790 ps
T552 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1830558836 Jul 25 06:06:56 PM PDT 24 Jul 25 06:13:59 PM PDT 24 43598204501 ps
T85 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1905359631 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 28012740 ps
T553 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.985248591 Jul 25 06:06:43 PM PDT 24 Jul 25 06:06:46 PM PDT 24 325573262 ps
T100 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3560093954 Jul 25 06:06:48 PM PDT 24 Jul 25 06:06:51 PM PDT 24 84779641 ps
T554 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1891118147 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 31965124 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2651896176 Jul 25 06:06:42 PM PDT 24 Jul 25 06:06:43 PM PDT 24 127690901 ps
T555 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2433641007 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 38911308 ps
T556 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4157726715 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 46897301 ps
T557 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1639736285 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 32700398 ps
T55 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1504272503 Jul 25 06:06:41 PM PDT 24 Jul 25 06:06:44 PM PDT 24 86522000 ps
T558 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1585940498 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:57 PM PDT 24 52329449 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2162292637 Jul 25 06:06:46 PM PDT 24 Jul 25 06:06:47 PM PDT 24 304613418 ps
T559 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1294559676 Jul 25 06:06:43 PM PDT 24 Jul 25 06:06:44 PM PDT 24 16999208 ps
T560 /workspace/coverage/cover_reg_top/1.hmac_intr_test.228388606 Jul 25 06:06:40 PM PDT 24 Jul 25 06:06:41 PM PDT 24 13500115 ps
T561 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1826508459 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:51 PM PDT 24 103687672 ps
T562 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2973214857 Jul 25 06:06:46 PM PDT 24 Jul 25 06:29:53 PM PDT 24 142325740825 ps
T563 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1184711875 Jul 25 06:06:38 PM PDT 24 Jul 25 06:06:40 PM PDT 24 155217128 ps
T564 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1828910583 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 165611092 ps
T56 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2475624905 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:56 PM PDT 24 267976699 ps
T86 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3741107926 Jul 25 06:06:53 PM PDT 24 Jul 25 06:06:54 PM PDT 24 22292287 ps
T111 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3938017693 Jul 25 06:07:03 PM PDT 24 Jul 25 06:07:07 PM PDT 24 544488402 ps
T565 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1871697501 Jul 25 06:07:00 PM PDT 24 Jul 25 06:07:01 PM PDT 24 23860926 ps
T566 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3945162160 Jul 25 06:06:43 PM PDT 24 Jul 25 06:06:45 PM PDT 24 426410443 ps
T567 /workspace/coverage/cover_reg_top/6.hmac_intr_test.408896737 Jul 25 06:06:48 PM PDT 24 Jul 25 06:06:49 PM PDT 24 20336202 ps
T568 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2685202389 Jul 25 06:07:01 PM PDT 24 Jul 25 06:07:01 PM PDT 24 19015170 ps
T569 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2065143745 Jul 25 06:07:03 PM PDT 24 Jul 25 06:07:04 PM PDT 24 12346108 ps
T570 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4287076110 Jul 25 06:06:52 PM PDT 24 Jul 25 06:06:53 PM PDT 24 16471052 ps
T571 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3828255485 Jul 25 06:06:42 PM PDT 24 Jul 25 06:06:46 PM PDT 24 219670714 ps
T572 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1207716127 Jul 25 06:06:56 PM PDT 24 Jul 25 06:12:13 PM PDT 24 30673455673 ps
T87 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1633353294 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 60189727 ps
T573 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2666209735 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:57 PM PDT 24 49482260 ps
T574 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3219704160 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:52 PM PDT 24 45787697 ps
T575 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1376107716 Jul 25 06:06:53 PM PDT 24 Jul 25 06:06:55 PM PDT 24 267484925 ps
T113 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3316857286 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:52 PM PDT 24 160988596 ps
T576 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.502601554 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 58818674 ps
T577 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1733166995 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 86077274 ps
T578 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1685096864 Jul 25 06:06:57 PM PDT 24 Jul 25 06:06:58 PM PDT 24 97951926 ps
T88 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4256083301 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 59254335 ps
T579 /workspace/coverage/cover_reg_top/39.hmac_intr_test.481087417 Jul 25 06:06:57 PM PDT 24 Jul 25 06:06:58 PM PDT 24 24943515 ps
T109 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3603636757 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:53 PM PDT 24 91462855 ps
T580 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2337981833 Jul 25 06:06:47 PM PDT 24 Jul 25 06:16:11 PM PDT 24 39228128295 ps
T581 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3820074111 Jul 25 06:06:57 PM PDT 24 Jul 25 06:06:58 PM PDT 24 18559251 ps
T582 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2098283141 Jul 25 06:06:42 PM PDT 24 Jul 25 06:06:47 PM PDT 24 461231541 ps
T583 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1747431634 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 21948435 ps
T584 /workspace/coverage/cover_reg_top/28.hmac_intr_test.130418266 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 30752968 ps
T585 /workspace/coverage/cover_reg_top/20.hmac_intr_test.4081621668 Jul 25 06:06:56 PM PDT 24 Jul 25 06:06:56 PM PDT 24 31883517 ps
T89 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2224627364 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:50 PM PDT 24 59227265 ps
T586 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2180007702 Jul 25 06:06:52 PM PDT 24 Jul 25 06:06:54 PM PDT 24 431410283 ps
T90 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.286112121 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 118204169 ps
T92 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.926606793 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 68651569 ps
T587 /workspace/coverage/cover_reg_top/45.hmac_intr_test.103711512 Jul 25 06:06:58 PM PDT 24 Jul 25 06:06:58 PM PDT 24 12676649 ps
T588 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.408482158 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 231279236 ps
T110 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2229609438 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:54 PM PDT 24 840243567 ps
T589 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3730570022 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:52 PM PDT 24 466749659 ps
T590 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2520045531 Jul 25 06:07:05 PM PDT 24 Jul 25 06:07:05 PM PDT 24 25712097 ps
T93 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.126500368 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:53 PM PDT 24 121301843 ps
T591 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2768269794 Jul 25 06:06:56 PM PDT 24 Jul 25 06:06:58 PM PDT 24 815679681 ps
T592 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3215413499 Jul 25 06:06:54 PM PDT 24 Jul 25 06:06:58 PM PDT 24 195962161 ps
T593 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2378701787 Jul 25 06:06:58 PM PDT 24 Jul 25 06:06:59 PM PDT 24 15493202 ps
T115 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.571801359 Jul 25 06:06:52 PM PDT 24 Jul 25 06:06:54 PM PDT 24 491569958 ps
T114 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1543944015 Jul 25 06:06:40 PM PDT 24 Jul 25 06:06:45 PM PDT 24 2506378124 ps
T594 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1633549041 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 28094786 ps
T595 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.323700524 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:53 PM PDT 24 106697671 ps
T596 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3235510875 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:53 PM PDT 24 939102322 ps
T58 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3553216159 Jul 25 06:06:52 PM PDT 24 Jul 25 06:06:55 PM PDT 24 176691530 ps
T597 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.619935828 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:55 PM PDT 24 139058418 ps
T112 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4201958990 Jul 25 06:06:52 PM PDT 24 Jul 25 06:06:55 PM PDT 24 91075646 ps
T598 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1692795225 Jul 25 06:06:50 PM PDT 24 Jul 25 06:08:32 PM PDT 24 11094965515 ps
T599 /workspace/coverage/cover_reg_top/8.hmac_intr_test.135462243 Jul 25 06:06:52 PM PDT 24 Jul 25 06:06:52 PM PDT 24 30927577 ps
T600 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2189363618 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:53 PM PDT 24 2688619038 ps
T601 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1807221054 Jul 25 06:06:40 PM PDT 24 Jul 25 06:06:58 PM PDT 24 3265489033 ps
T602 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3918942248 Jul 25 06:07:00 PM PDT 24 Jul 25 06:07:00 PM PDT 24 27402903 ps
T603 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1859376151 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 55778974 ps
T604 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4235751374 Jul 25 06:06:54 PM PDT 24 Jul 25 06:06:56 PM PDT 24 363068137 ps
T605 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.761620981 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:53 PM PDT 24 79129575 ps
T606 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.187044649 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:53 PM PDT 24 168639249 ps
T607 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.288133319 Jul 25 06:06:59 PM PDT 24 Jul 25 06:07:00 PM PDT 24 32400076 ps
T608 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1131317801 Jul 25 06:07:02 PM PDT 24 Jul 25 06:07:02 PM PDT 24 43785550 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2815248295 Jul 25 06:06:48 PM PDT 24 Jul 25 06:06:57 PM PDT 24 931019728 ps
T609 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.926794993 Jul 25 06:06:43 PM PDT 24 Jul 25 06:06:44 PM PDT 24 52381970 ps
T610 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3897683870 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:50 PM PDT 24 86300446 ps
T611 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3183141257 Jul 25 06:06:36 PM PDT 24 Jul 25 06:06:37 PM PDT 24 16896135 ps
T612 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3407839380 Jul 25 06:06:45 PM PDT 24 Jul 25 06:06:55 PM PDT 24 216363499 ps
T613 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1517380650 Jul 25 06:06:42 PM PDT 24 Jul 25 06:06:45 PM PDT 24 689161570 ps
T614 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.354312535 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:54 PM PDT 24 128232950 ps
T615 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4203168438 Jul 25 06:06:41 PM PDT 24 Jul 25 06:06:42 PM PDT 24 198712617 ps
T616 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1491095632 Jul 25 06:06:45 PM PDT 24 Jul 25 06:06:46 PM PDT 24 42465957 ps
T617 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1461350613 Jul 25 06:06:58 PM PDT 24 Jul 25 06:07:02 PM PDT 24 689484591 ps
T618 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3491485931 Jul 25 06:06:41 PM PDT 24 Jul 25 06:06:42 PM PDT 24 51035098 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3475193192 Jul 25 06:06:42 PM PDT 24 Jul 25 06:06:44 PM PDT 24 25581578 ps
T620 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2455520404 Jul 25 06:06:59 PM PDT 24 Jul 25 06:07:01 PM PDT 24 77393992 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2704176409 Jul 25 06:06:56 PM PDT 24 Jul 25 06:06:59 PM PDT 24 111547693 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.270694106 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:58 PM PDT 24 49868432 ps
T623 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2060963293 Jul 25 06:06:40 PM PDT 24 Jul 25 06:06:41 PM PDT 24 241318745 ps
T624 /workspace/coverage/cover_reg_top/31.hmac_intr_test.899379047 Jul 25 06:07:01 PM PDT 24 Jul 25 06:07:02 PM PDT 24 16134213 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.240809799 Jul 25 06:06:47 PM PDT 24 Jul 25 06:06:48 PM PDT 24 26130990 ps
T626 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1935212119 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 457893933 ps
T627 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2938517495 Jul 25 06:06:53 PM PDT 24 Jul 25 06:06:54 PM PDT 24 148280905 ps
T628 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2293043823 Jul 25 06:06:58 PM PDT 24 Jul 25 06:07:01 PM PDT 24 1173043762 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3965001094 Jul 25 06:06:43 PM PDT 24 Jul 25 06:06:44 PM PDT 24 326756909 ps
T629 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2093006555 Jul 25 06:07:03 PM PDT 24 Jul 25 06:07:04 PM PDT 24 14086304 ps
T630 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3904101843 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:53 PM PDT 24 79179908 ps
T96 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2286438388 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 183094057 ps
T631 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1792617456 Jul 25 06:06:35 PM PDT 24 Jul 25 06:06:36 PM PDT 24 28715321 ps
T632 /workspace/coverage/cover_reg_top/35.hmac_intr_test.614310401 Jul 25 06:06:57 PM PDT 24 Jul 25 06:06:58 PM PDT 24 32604872 ps
T633 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.394210523 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 107948470 ps
T634 /workspace/coverage/cover_reg_top/37.hmac_intr_test.4145560124 Jul 25 06:06:58 PM PDT 24 Jul 25 06:06:59 PM PDT 24 16366256 ps
T635 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1635483154 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:50 PM PDT 24 16511544 ps
T636 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1118357127 Jul 25 06:07:02 PM PDT 24 Jul 25 06:07:02 PM PDT 24 43874710 ps
T637 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2009682055 Jul 25 06:06:59 PM PDT 24 Jul 25 06:07:02 PM PDT 24 603937319 ps
T638 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2323492130 Jul 25 06:06:43 PM PDT 24 Jul 25 06:06:44 PM PDT 24 31111346 ps
T639 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3442286922 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 100270094 ps
T640 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1715029034 Jul 25 06:06:58 PM PDT 24 Jul 25 06:06:58 PM PDT 24 27328230 ps
T641 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.646202155 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:52 PM PDT 24 52024632 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1000937957 Jul 25 06:06:42 PM PDT 24 Jul 25 06:06:48 PM PDT 24 671531825 ps
T643 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2896522242 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:53 PM PDT 24 990420292 ps
T644 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1942853225 Jul 25 06:06:41 PM PDT 24 Jul 25 06:14:50 PM PDT 24 132520314989 ps
T645 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1037199307 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:51 PM PDT 24 19075095 ps
T646 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4282399081 Jul 25 06:06:56 PM PDT 24 Jul 25 06:06:57 PM PDT 24 20047192 ps
T647 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2649756386 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:53 PM PDT 24 205777296 ps
T648 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.647182908 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:52 PM PDT 24 23353128 ps
T649 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3298110396 Jul 25 06:07:01 PM PDT 24 Jul 25 06:07:02 PM PDT 24 17128268 ps
T650 /workspace/coverage/cover_reg_top/34.hmac_intr_test.158511675 Jul 25 06:06:54 PM PDT 24 Jul 25 06:06:55 PM PDT 24 12946579 ps
T651 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3112569225 Jul 25 06:06:55 PM PDT 24 Jul 25 06:06:56 PM PDT 24 38611904 ps
T652 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2145466150 Jul 25 06:06:53 PM PDT 24 Jul 25 06:06:55 PM PDT 24 249112542 ps
T653 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1203736109 Jul 25 06:07:01 PM PDT 24 Jul 25 06:07:04 PM PDT 24 38978855 ps
T654 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.798785501 Jul 25 06:06:51 PM PDT 24 Jul 25 06:06:53 PM PDT 24 28611670 ps
T655 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.337750566 Jul 25 06:06:49 PM PDT 24 Jul 25 06:06:50 PM PDT 24 66252325 ps
T656 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.461659416 Jul 25 06:06:53 PM PDT 24 Jul 25 06:06:57 PM PDT 24 1059030173 ps
T57 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2851549098 Jul 25 06:06:41 PM PDT 24 Jul 25 06:06:45 PM PDT 24 232057874 ps
T657 /workspace/coverage/cover_reg_top/26.hmac_intr_test.511294123 Jul 25 06:06:57 PM PDT 24 Jul 25 06:06:57 PM PDT 24 22276141 ps
T658 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.367047946 Jul 25 06:06:58 PM PDT 24 Jul 25 06:07:00 PM PDT 24 87570332 ps
T659 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.726769566 Jul 25 06:06:57 PM PDT 24 Jul 25 06:06:59 PM PDT 24 76975361 ps
T660 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.604698994 Jul 25 06:06:50 PM PDT 24 Jul 25 06:06:52 PM PDT 24 93668891 ps

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2350285755
Short name T2
Test name
Test status
Simulation time 97360571535 ps
CPU time 3804.97 seconds
Started Jul 25 06:14:51 PM PDT 24
Finished Jul 25 07:18:17 PM PDT 24
Peak memory 738736 kb
Host smart-964acf18-2c60-4f1d-9393-a33c46cdfb49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350285755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2350285755
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_stress_all.832974648
Short name T24
Test name
Test status
Simulation time 19494368238 ps
CPU time 1758 seconds
Started Jul 25 06:17:24 PM PDT 24
Finished Jul 25 06:46:42 PM PDT 24
Peak memory 683188 kb
Host smart-4d3bb3d3-67a9-4198-90a3-40b0ade1edd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832974648 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.832974648
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.4276915663
Short name T20
Test name
Test status
Simulation time 277128044045 ps
CPU time 4231.87 seconds
Started Jul 25 06:14:23 PM PDT 24
Finished Jul 25 07:24:56 PM PDT 24
Peak memory 683328 kb
Host smart-f26e8da7-21ce-44e7-85e4-93b60bd7bf93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4276915663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.4276915663
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1504272503
Short name T55
Test name
Test status
Simulation time 86522000 ps
CPU time 2.96 seconds
Started Jul 25 06:06:41 PM PDT 24
Finished Jul 25 06:06:44 PM PDT 24
Peak memory 199896 kb
Host smart-a5cb0d23-8509-4515-9b82-9b33c5e51f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504272503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1504272503
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3083683707
Short name T1
Test name
Test status
Simulation time 43782865 ps
CPU time 0.6 seconds
Started Jul 25 06:18:43 PM PDT 24
Finished Jul 25 06:18:44 PM PDT 24
Peak memory 194564 kb
Host smart-a9f266e3-5ef9-4363-887f-bb1ab6b46bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083683707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3083683707
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1296656030
Short name T18
Test name
Test status
Simulation time 26053651130 ps
CPU time 3406.53 seconds
Started Jul 25 06:15:32 PM PDT 24
Finished Jul 25 07:12:19 PM PDT 24
Peak memory 773220 kb
Host smart-35d92f47-d88b-4db2-882e-e91ebd0b4e20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296656030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1296656030
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.534373199
Short name T81
Test name
Test status
Simulation time 218937850 ps
CPU time 0.93 seconds
Started Jul 25 06:06:34 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 199416 kb
Host smart-5296daf1-8ce1-4903-86b9-f53b48775157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534373199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.534373199
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3497957468
Short name T42
Test name
Test status
Simulation time 321570269 ps
CPU time 0.99 seconds
Started Jul 25 06:13:44 PM PDT 24
Finished Jul 25 06:13:45 PM PDT 24
Peak memory 219464 kb
Host smart-98fe200d-a194-4496-bccb-c561933c025b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497957468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3497957468
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4081213390
Short name T62
Test name
Test status
Simulation time 132726598049 ps
CPU time 811.84 seconds
Started Jul 25 06:14:52 PM PDT 24
Finished Jul 25 06:28:24 PM PDT 24
Peak memory 216200 kb
Host smart-dd4d4f64-aea8-4671-9759-c9c268c6da75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081213390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4081213390
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1543944015
Short name T114
Test name
Test status
Simulation time 2506378124 ps
CPU time 4.5 seconds
Started Jul 25 06:06:40 PM PDT 24
Finished Jul 25 06:06:45 PM PDT 24
Peak memory 200000 kb
Host smart-f7f7f64d-c0ca-46bc-a2f0-4ed26c2845c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543944015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1543944015
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2851549098
Short name T57
Test name
Test status
Simulation time 232057874 ps
CPU time 4.46 seconds
Started Jul 25 06:06:41 PM PDT 24
Finished Jul 25 06:06:45 PM PDT 24
Peak memory 199892 kb
Host smart-13111c99-b369-4bd6-a0df-a99565549da1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851549098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2851549098
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3215029313
Short name T119
Test name
Test status
Simulation time 3612136613 ps
CPU time 45.84 seconds
Started Jul 25 06:15:39 PM PDT 24
Finished Jul 25 06:16:25 PM PDT 24
Peak memory 199784 kb
Host smart-faf6c655-03af-4caf-a45c-64818d21a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215029313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3215029313
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3157250386
Short name T8
Test name
Test status
Simulation time 23363590852 ps
CPU time 3087 seconds
Started Jul 25 06:13:58 PM PDT 24
Finished Jul 25 07:05:25 PM PDT 24
Peak memory 795796 kb
Host smart-73bc1903-d13f-4db9-aa5f-5c643244ab4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157250386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3157250386
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2475624905
Short name T56
Test name
Test status
Simulation time 267976699 ps
CPU time 4.61 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 199896 kb
Host smart-28c6374f-a8e0-4045-9780-5fabfb378de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475624905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2475624905
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3553216159
Short name T58
Test name
Test status
Simulation time 176691530 ps
CPU time 2.93 seconds
Started Jul 25 06:06:52 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 199840 kb
Host smart-95032946-56db-4c11-8d58-17cf0aa6180b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553216159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3553216159
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2119877192
Short name T60
Test name
Test status
Simulation time 34575916787 ps
CPU time 256.37 seconds
Started Jul 25 06:14:08 PM PDT 24
Finished Jul 25 06:18:25 PM PDT 24
Peak memory 216332 kb
Host smart-1dca9fb4-dcca-4fed-9413-d4a1102e90b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119877192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2119877192
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3709088794
Short name T82
Test name
Test status
Simulation time 595991168 ps
CPU time 8.1 seconds
Started Jul 25 06:06:36 PM PDT 24
Finished Jul 25 06:06:45 PM PDT 24
Peak memory 199688 kb
Host smart-cb564669-4f9b-41ff-b885-f7011b12dd70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709088794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3709088794
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1620971928
Short name T543
Test name
Test status
Simulation time 3265604924 ps
CPU time 15.83 seconds
Started Jul 25 06:06:37 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199992 kb
Host smart-5c2d2f19-61bc-449b-933d-6e9003b0745e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620971928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1620971928
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3183141257
Short name T611
Test name
Test status
Simulation time 16896135 ps
CPU time 0.74 seconds
Started Jul 25 06:06:36 PM PDT 24
Finished Jul 25 06:06:37 PM PDT 24
Peak memory 198120 kb
Host smart-e64346cc-d534-423a-8d1f-35777f87a02f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183141257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3183141257
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1942853225
Short name T644
Test name
Test status
Simulation time 132520314989 ps
CPU time 488.39 seconds
Started Jul 25 06:06:41 PM PDT 24
Finished Jul 25 06:14:50 PM PDT 24
Peak memory 208252 kb
Host smart-c81f0f2c-7a56-4bde-8337-4e3f0be703b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942853225 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1942853225
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1792617456
Short name T631
Test name
Test status
Simulation time 28715321 ps
CPU time 0.57 seconds
Started Jul 25 06:06:35 PM PDT 24
Finished Jul 25 06:06:36 PM PDT 24
Peak memory 194768 kb
Host smart-6dbaead5-3c3b-4407-9989-c787bff7894f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792617456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1792617456
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2651896176
Short name T101
Test name
Test status
Simulation time 127690901 ps
CPU time 1.2 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:43 PM PDT 24
Peak memory 199620 kb
Host smart-6415fab8-402f-46a8-a5e4-131b22041bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651896176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2651896176
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1184711875
Short name T563
Test name
Test status
Simulation time 155217128 ps
CPU time 2.02 seconds
Started Jul 25 06:06:38 PM PDT 24
Finished Jul 25 06:06:40 PM PDT 24
Peak memory 199848 kb
Host smart-474371fa-508b-4537-bc2c-079bf0cc7361
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184711875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1184711875
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2098283141
Short name T582
Test name
Test status
Simulation time 461231541 ps
CPU time 4.54 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:47 PM PDT 24
Peak memory 199864 kb
Host smart-423bbdb1-f81f-494a-9267-c455c7cecfba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098283141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2098283141
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3177443515
Short name T546
Test name
Test status
Simulation time 60488397 ps
CPU time 2.79 seconds
Started Jul 25 06:06:38 PM PDT 24
Finished Jul 25 06:06:41 PM PDT 24
Peak memory 199568 kb
Host smart-9df89084-4362-4e9d-8d9a-167e79b6c6bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177443515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3177443515
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1807221054
Short name T601
Test name
Test status
Simulation time 3265489033 ps
CPU time 17.28 seconds
Started Jul 25 06:06:40 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 199304 kb
Host smart-222c5928-2829-4046-9b0f-c1e884bbc261
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807221054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1807221054
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4203168438
Short name T615
Test name
Test status
Simulation time 198712617 ps
CPU time 1.01 seconds
Started Jul 25 06:06:41 PM PDT 24
Finished Jul 25 06:06:42 PM PDT 24
Peak memory 199676 kb
Host smart-64202267-3f7c-4e85-a895-0d9502ee08f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203168438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4203168438
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2060963293
Short name T623
Test name
Test status
Simulation time 241318745 ps
CPU time 1.17 seconds
Started Jul 25 06:06:40 PM PDT 24
Finished Jul 25 06:06:41 PM PDT 24
Peak memory 199672 kb
Host smart-2290b4af-42d2-4891-9448-67fcc7d6be6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060963293 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2060963293
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3491485931
Short name T618
Test name
Test status
Simulation time 51035098 ps
CPU time 1.01 seconds
Started Jul 25 06:06:41 PM PDT 24
Finished Jul 25 06:06:42 PM PDT 24
Peak memory 199632 kb
Host smart-4bdae38f-b690-48d7-b5f6-356b9b6ad03a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491485931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3491485931
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.228388606
Short name T560
Test name
Test status
Simulation time 13500115 ps
CPU time 0.59 seconds
Started Jul 25 06:06:40 PM PDT 24
Finished Jul 25 06:06:41 PM PDT 24
Peak memory 194788 kb
Host smart-b95dc83e-efd7-46f1-a053-c1b475fb758c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228388606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.228388606
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.926794993
Short name T609
Test name
Test status
Simulation time 52381970 ps
CPU time 1.03 seconds
Started Jul 25 06:06:43 PM PDT 24
Finished Jul 25 06:06:44 PM PDT 24
Peak memory 199616 kb
Host smart-b7198f69-f679-4ff6-aef0-dfc29ce9d805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926794993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.926794993
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3945162160
Short name T566
Test name
Test status
Simulation time 426410443 ps
CPU time 2.54 seconds
Started Jul 25 06:06:43 PM PDT 24
Finished Jul 25 06:06:45 PM PDT 24
Peak memory 199908 kb
Host smart-4022c671-5c5e-49a7-a788-3f29580b86ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945162160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3945162160
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.798785501
Short name T654
Test name
Test status
Simulation time 28611670 ps
CPU time 1.64 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199856 kb
Host smart-efb3898a-6ce0-411c-b54b-ce060c9f4059
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798785501 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.798785501
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3292483145
Short name T84
Test name
Test status
Simulation time 15594790 ps
CPU time 0.67 seconds
Started Jul 25 06:06:46 PM PDT 24
Finished Jul 25 06:06:47 PM PDT 24
Peak memory 197908 kb
Host smart-356eb763-3256-4767-a177-80efcc67abc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292483145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3292483145
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1828910583
Short name T564
Test name
Test status
Simulation time 165611092 ps
CPU time 0.61 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 194708 kb
Host smart-3db3f51b-276b-4f5e-a423-753a91061ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828910583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1828910583
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.604698994
Short name T660
Test name
Test status
Simulation time 93668891 ps
CPU time 1.71 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199764 kb
Host smart-a6560aef-7786-4cee-b851-4b67822f1de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604698994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.604698994
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3730570022
Short name T589
Test name
Test status
Simulation time 466749659 ps
CPU time 1.56 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199908 kb
Host smart-3b2e27d1-add7-47b0-b103-4d6498c48542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730570022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3730570022
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.646202155
Short name T641
Test name
Test status
Simulation time 52024632 ps
CPU time 1.75 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199940 kb
Host smart-ace94c7f-311f-4e54-b1ab-202557a02d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646202155 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.646202155
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.337750566
Short name T655
Test name
Test status
Simulation time 66252325 ps
CPU time 0.97 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:50 PM PDT 24
Peak memory 199620 kb
Host smart-38c52cd0-4d10-4648-ab9c-bac7da7f9dce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337750566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.337750566
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1037199307
Short name T645
Test name
Test status
Simulation time 19075095 ps
CPU time 0.58 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 194856 kb
Host smart-f83db0de-48c5-4510-8de9-49baa76d2af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037199307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1037199307
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2455520404
Short name T620
Test name
Test status
Simulation time 77393992 ps
CPU time 1.79 seconds
Started Jul 25 06:06:59 PM PDT 24
Finished Jul 25 06:07:01 PM PDT 24
Peak memory 199812 kb
Host smart-59e13cc8-445a-48bf-91eb-9b14f8a8111c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455520404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2455520404
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1733166995
Short name T577
Test name
Test status
Simulation time 86077274 ps
CPU time 1.29 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 199884 kb
Host smart-751ce101-caed-4cf6-a6ea-fd0fb70f862b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733166995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1733166995
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4157726715
Short name T556
Test name
Test status
Simulation time 46897301 ps
CPU time 1.08 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199784 kb
Host smart-e79047f5-6aed-4de2-9657-d32492325a36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157726715 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4157726715
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3741107926
Short name T86
Test name
Test status
Simulation time 22292287 ps
CPU time 0.8 seconds
Started Jul 25 06:06:53 PM PDT 24
Finished Jul 25 06:06:54 PM PDT 24
Peak memory 199184 kb
Host smart-1692b00a-52e9-4b87-b39e-28e8ac63d2b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741107926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3741107926
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2433641007
Short name T555
Test name
Test status
Simulation time 38911308 ps
CPU time 0.63 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 194884 kb
Host smart-7f5f98e6-cbed-49a0-948b-bf1343e7c4af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433641007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2433641007
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2180007702
Short name T586
Test name
Test status
Simulation time 431410283 ps
CPU time 1.78 seconds
Started Jul 25 06:06:52 PM PDT 24
Finished Jul 25 06:06:54 PM PDT 24
Peak memory 199904 kb
Host smart-d37d4739-5d92-45c1-b132-532d64d755be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180007702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2180007702
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3215413499
Short name T592
Test name
Test status
Simulation time 195962161 ps
CPU time 4.09 seconds
Started Jul 25 06:06:54 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 199880 kb
Host smart-47caac72-5ce4-4dbb-a26e-f1489f477302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215413499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3215413499
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3603636757
Short name T109
Test name
Test status
Simulation time 91462855 ps
CPU time 1.88 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199980 kb
Host smart-6c3b4161-cb65-4598-85f5-8296e8f1b335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603636757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3603636757
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1747431634
Short name T583
Test name
Test status
Simulation time 21948435 ps
CPU time 1.44 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199852 kb
Host smart-a0e91d2b-9236-4f22-9184-150b85faee33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747431634 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1747431634
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1905359631
Short name T85
Test name
Test status
Simulation time 28012740 ps
CPU time 0.89 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199704 kb
Host smart-2fa185ea-9dfb-4ab3-89e0-35cc288f84c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905359631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1905359631
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1639736285
Short name T557
Test name
Test status
Simulation time 32700398 ps
CPU time 0.61 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 194940 kb
Host smart-ee381dde-8f0b-4a81-a859-bdfd80caf7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639736285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1639736285
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1376107716
Short name T575
Test name
Test status
Simulation time 267484925 ps
CPU time 1.61 seconds
Started Jul 25 06:06:53 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 199884 kb
Host smart-b8fbe5f2-d7e8-4ef3-849a-8fe6d9324585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376107716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1376107716
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2145466150
Short name T652
Test name
Test status
Simulation time 249112542 ps
CPU time 1.46 seconds
Started Jul 25 06:06:53 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 199892 kb
Host smart-67a0aaaa-fc2f-4e33-b097-45c50f91729d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145466150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2145466150
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.571801359
Short name T115
Test name
Test status
Simulation time 491569958 ps
CPU time 1.81 seconds
Started Jul 25 06:06:52 PM PDT 24
Finished Jul 25 06:06:54 PM PDT 24
Peak memory 199928 kb
Host smart-103e1c02-a97f-4d77-a2b7-f6161a3ac431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571801359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.571801359
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2938517495
Short name T627
Test name
Test status
Simulation time 148280905 ps
CPU time 1.14 seconds
Started Jul 25 06:06:53 PM PDT 24
Finished Jul 25 06:06:54 PM PDT 24
Peak memory 199712 kb
Host smart-f21097e9-c958-409a-95ed-05683c4e9319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938517495 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2938517495
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4256083301
Short name T88
Test name
Test status
Simulation time 59254335 ps
CPU time 0.67 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 197572 kb
Host smart-12419dd3-b525-4167-bb85-ecad63c79fba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256083301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4256083301
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4287076110
Short name T570
Test name
Test status
Simulation time 16471052 ps
CPU time 0.6 seconds
Started Jul 25 06:06:52 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 194844 kb
Host smart-08ec8156-ad7a-428c-adff-2bfaf7eb8169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287076110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4287076110
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.761620981
Short name T605
Test name
Test status
Simulation time 79129575 ps
CPU time 1.74 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199748 kb
Host smart-13db382c-ee83-4841-a930-ad17f2fd2508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761620981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.761620981
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.619935828
Short name T597
Test name
Test status
Simulation time 139058418 ps
CPU time 3.54 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 199872 kb
Host smart-8a7ff3f6-3f66-4026-b000-5fded32464c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619935828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.619935828
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3316857286
Short name T113
Test name
Test status
Simulation time 160988596 ps
CPU time 3.2 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199968 kb
Host smart-6f6a3d8c-be29-4e6a-b60f-f0389c5c039f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316857286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3316857286
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1207716127
Short name T572
Test name
Test status
Simulation time 30673455673 ps
CPU time 317.04 seconds
Started Jul 25 06:06:56 PM PDT 24
Finished Jul 25 06:12:13 PM PDT 24
Peak memory 216400 kb
Host smart-5ef56600-128c-4cca-b361-28a7d066b665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207716127 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1207716127
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.736823489
Short name T99
Test name
Test status
Simulation time 63607947 ps
CPU time 0.94 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:50 PM PDT 24
Peak memory 199632 kb
Host smart-8910286b-4809-4845-a7a6-bb4cb7efeec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736823489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.736823489
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.789943770
Short name T542
Test name
Test status
Simulation time 45564553 ps
CPU time 0.67 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 194856 kb
Host smart-3ce99bd0-fad3-4368-9345-29af480b344e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789943770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.789943770
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3897683870
Short name T610
Test name
Test status
Simulation time 86300446 ps
CPU time 1.15 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:50 PM PDT 24
Peak memory 198376 kb
Host smart-b2d3f708-879a-4fbf-8504-c826f6ccb6c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897683870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3897683870
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2646003551
Short name T538
Test name
Test status
Simulation time 48667001 ps
CPU time 2.57 seconds
Started Jul 25 06:06:53 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 199896 kb
Host smart-ac4ac70c-4d80-482d-85c7-6503f850f2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646003551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2646003551
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.323700524
Short name T595
Test name
Test status
Simulation time 106697671 ps
CPU time 1.89 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199868 kb
Host smart-4078286c-c2e7-4e42-9dee-bb7a63b6502e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323700524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.323700524
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1585940498
Short name T558
Test name
Test status
Simulation time 52329449 ps
CPU time 1.78 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:57 PM PDT 24
Peak memory 199916 kb
Host smart-691e6714-fba6-4787-af59-89439bec916e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585940498 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1585940498
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1859376151
Short name T603
Test name
Test status
Simulation time 55778974 ps
CPU time 0.88 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 199264 kb
Host smart-ce11fd53-0bc0-4f99-b080-66e17491399c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859376151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1859376151
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1789968957
Short name T541
Test name
Test status
Simulation time 171633724 ps
CPU time 0.61 seconds
Started Jul 25 06:06:56 PM PDT 24
Finished Jul 25 06:06:57 PM PDT 24
Peak memory 194832 kb
Host smart-1da5482e-f149-4dab-9fb4-7bf5f215d05d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789968957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1789968957
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.325545234
Short name T97
Test name
Test status
Simulation time 44404437 ps
CPU time 1.17 seconds
Started Jul 25 06:06:54 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 198256 kb
Host smart-7ed8b5f6-4e85-4a26-9675-e00c2cd60b66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325545234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.325545234
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2009682055
Short name T637
Test name
Test status
Simulation time 603937319 ps
CPU time 2.88 seconds
Started Jul 25 06:06:59 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 199856 kb
Host smart-b325f8dd-9c9c-43e1-aa24-5c67b42c3d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009682055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2009682055
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.20399503
Short name T54
Test name
Test status
Simulation time 800031488 ps
CPU time 1.83 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:07:00 PM PDT 24
Peak memory 199804 kb
Host smart-86f8a7d1-d550-48b4-a506-365162d4e92e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20399503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.20399503
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.726769566
Short name T659
Test name
Test status
Simulation time 76975361 ps
CPU time 1.14 seconds
Started Jul 25 06:06:57 PM PDT 24
Finished Jul 25 06:06:59 PM PDT 24
Peak memory 199720 kb
Host smart-8f014510-f921-413c-92f8-520a5bf61e46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726769566 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.726769566
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.288133319
Short name T607
Test name
Test status
Simulation time 32400076 ps
CPU time 0.68 seconds
Started Jul 25 06:06:59 PM PDT 24
Finished Jul 25 06:07:00 PM PDT 24
Peak memory 197300 kb
Host smart-80d216e4-83ed-40d8-a9a3-17074eb92b7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288133319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.288133319
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1871697501
Short name T565
Test name
Test status
Simulation time 23860926 ps
CPU time 0.6 seconds
Started Jul 25 06:07:00 PM PDT 24
Finished Jul 25 06:07:01 PM PDT 24
Peak memory 194916 kb
Host smart-8075e4ec-d1cf-4397-92aa-98748ca9c260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871697501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1871697501
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2704176409
Short name T621
Test name
Test status
Simulation time 111547693 ps
CPU time 2.35 seconds
Started Jul 25 06:06:56 PM PDT 24
Finished Jul 25 06:06:59 PM PDT 24
Peak memory 199864 kb
Host smart-40b04102-7d5e-4513-80fb-b55461d25001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704176409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2704176409
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1203736109
Short name T653
Test name
Test status
Simulation time 38978855 ps
CPU time 1.99 seconds
Started Jul 25 06:07:01 PM PDT 24
Finished Jul 25 06:07:04 PM PDT 24
Peak memory 199812 kb
Host smart-8bcd057d-ebc8-4529-a0cf-f7109351020f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203736109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1203736109
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3938017693
Short name T111
Test name
Test status
Simulation time 544488402 ps
CPU time 4.1 seconds
Started Jul 25 06:07:03 PM PDT 24
Finished Jul 25 06:07:07 PM PDT 24
Peak memory 199860 kb
Host smart-5e39e7ea-323f-4dd3-b498-09ecfc74a0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938017693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3938017693
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2625673596
Short name T531
Test name
Test status
Simulation time 290640305 ps
CPU time 1.74 seconds
Started Jul 25 06:06:59 PM PDT 24
Finished Jul 25 06:07:01 PM PDT 24
Peak memory 199856 kb
Host smart-7e6744d5-c73f-46cf-a627-534cd3058f73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625673596 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2625673596
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1641190992
Short name T551
Test name
Test status
Simulation time 112939742 ps
CPU time 0.91 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:06:59 PM PDT 24
Peak memory 199456 kb
Host smart-219ac8b9-47fa-4b3a-a4c4-052580bb0c70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641190992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1641190992
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1715029034
Short name T640
Test name
Test status
Simulation time 27328230 ps
CPU time 0.64 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194804 kb
Host smart-4fcb64e0-9fae-47a1-b975-81b637d91970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715029034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1715029034
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2293043823
Short name T628
Test name
Test status
Simulation time 1173043762 ps
CPU time 2.32 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:07:01 PM PDT 24
Peak memory 199804 kb
Host smart-f1d9e574-f9bb-4863-b47a-b42211bf41c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293043823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2293043823
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2666209735
Short name T573
Test name
Test status
Simulation time 49482260 ps
CPU time 2.44 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:57 PM PDT 24
Peak memory 199856 kb
Host smart-9acaf1cd-75cc-441f-8c5b-07c9a369318e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666209735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2666209735
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.367047946
Short name T658
Test name
Test status
Simulation time 87570332 ps
CPU time 1.83 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:07:00 PM PDT 24
Peak memory 199872 kb
Host smart-53ff60e3-596d-4a31-a577-79379db344c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367047946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.367047946
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1830558836
Short name T552
Test name
Test status
Simulation time 43598204501 ps
CPU time 423.65 seconds
Started Jul 25 06:06:56 PM PDT 24
Finished Jul 25 06:13:59 PM PDT 24
Peak memory 216392 kb
Host smart-c9f2a902-809b-4ae4-a6e8-8fe7f083e815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830558836 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1830558836
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.394210523
Short name T633
Test name
Test status
Simulation time 107948470 ps
CPU time 0.8 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 199096 kb
Host smart-fe5e4b31-4987-444e-a78b-273d80fd49d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394210523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.394210523
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.513914917
Short name T548
Test name
Test status
Simulation time 15506614 ps
CPU time 0.61 seconds
Started Jul 25 06:07:05 PM PDT 24
Finished Jul 25 06:07:05 PM PDT 24
Peak memory 194716 kb
Host smart-2d2b497c-da17-4fcd-b3f3-192c45b5d181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513914917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.513914917
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2768269794
Short name T591
Test name
Test status
Simulation time 815679681 ps
CPU time 2.21 seconds
Started Jul 25 06:06:56 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 199788 kb
Host smart-305da05c-3538-4bfc-bbe0-7fbe79a25303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768269794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2768269794
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.187225146
Short name T534
Test name
Test status
Simulation time 169762250 ps
CPU time 3.32 seconds
Started Jul 25 06:07:01 PM PDT 24
Finished Jul 25 06:07:04 PM PDT 24
Peak memory 199932 kb
Host smart-9e37e6f2-ce7c-4714-9798-d9aaeb8e7291
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187225146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.187225146
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1461350613
Short name T617
Test name
Test status
Simulation time 689484591 ps
CPU time 3.18 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 199864 kb
Host smart-3376841f-a313-46b1-8b87-7d954618f780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461350613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1461350613
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1517380650
Short name T613
Test name
Test status
Simulation time 689161570 ps
CPU time 3.47 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:45 PM PDT 24
Peak memory 199880 kb
Host smart-c9ae63a8-fed7-4823-b019-a5588d021e7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517380650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1517380650
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1000937957
Short name T642
Test name
Test status
Simulation time 671531825 ps
CPU time 5.06 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:48 PM PDT 24
Peak memory 198828 kb
Host smart-964dbd33-a702-410f-9c7f-1f35002b5aae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000937957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1000937957
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.311419870
Short name T536
Test name
Test status
Simulation time 21167604 ps
CPU time 0.75 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:43 PM PDT 24
Peak memory 197528 kb
Host smart-4cb6a3b2-d6fa-4148-be21-197b484763a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311419870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.311419870
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.985248591
Short name T553
Test name
Test status
Simulation time 325573262 ps
CPU time 2.33 seconds
Started Jul 25 06:06:43 PM PDT 24
Finished Jul 25 06:06:46 PM PDT 24
Peak memory 208176 kb
Host smart-ca6a81e1-7606-4fb4-bb02-a6092395ebd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985248591 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.985248591
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3965001094
Short name T95
Test name
Test status
Simulation time 326756909 ps
CPU time 0.97 seconds
Started Jul 25 06:06:43 PM PDT 24
Finished Jul 25 06:06:44 PM PDT 24
Peak memory 199704 kb
Host smart-8b7a4a38-28cc-4cb5-8856-aef86e04856a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965001094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3965001094
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1313766069
Short name T549
Test name
Test status
Simulation time 18297907 ps
CPU time 0.59 seconds
Started Jul 25 06:06:46 PM PDT 24
Finished Jul 25 06:06:46 PM PDT 24
Peak memory 194692 kb
Host smart-4fd14af3-528c-437c-aa30-940fe110dc1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313766069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1313766069
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1491095632
Short name T616
Test name
Test status
Simulation time 42465957 ps
CPU time 1.11 seconds
Started Jul 25 06:06:45 PM PDT 24
Finished Jul 25 06:06:46 PM PDT 24
Peak memory 199924 kb
Host smart-13bddf17-ea43-48ac-8c67-9d14c0beec54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491095632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1491095632
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3828255485
Short name T571
Test name
Test status
Simulation time 219670714 ps
CPU time 3.14 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:46 PM PDT 24
Peak memory 199844 kb
Host smart-e7a8fa16-54ec-45e2-9f62-97825cf43c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828255485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3828255485
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.4081621668
Short name T585
Test name
Test status
Simulation time 31883517 ps
CPU time 0.57 seconds
Started Jul 25 06:06:56 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 194836 kb
Host smart-5cb630b0-680b-4e72-ac72-62d79a63cbb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081621668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4081621668
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2959472380
Short name T550
Test name
Test status
Simulation time 44935227 ps
CPU time 0.6 seconds
Started Jul 25 06:07:01 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 194692 kb
Host smart-9128f58c-207b-4576-96c2-a0c04b18dd8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959472380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2959472380
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3788631692
Short name T537
Test name
Test status
Simulation time 44560351 ps
CPU time 0.6 seconds
Started Jul 25 06:07:03 PM PDT 24
Finished Jul 25 06:07:04 PM PDT 24
Peak memory 194736 kb
Host smart-938b77b6-c279-41e6-b867-c47babf26334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788631692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3788631692
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2378701787
Short name T593
Test name
Test status
Simulation time 15493202 ps
CPU time 0.58 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:06:59 PM PDT 24
Peak memory 194644 kb
Host smart-14fb8862-486a-4b70-86b0-57d8a4271d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378701787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2378701787
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3224407884
Short name T533
Test name
Test status
Simulation time 39332593 ps
CPU time 0.58 seconds
Started Jul 25 06:07:03 PM PDT 24
Finished Jul 25 06:07:04 PM PDT 24
Peak memory 194824 kb
Host smart-db4b3932-6891-4c63-8aa0-1b710a4707d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224407884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3224407884
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1685096864
Short name T578
Test name
Test status
Simulation time 97951926 ps
CPU time 0.63 seconds
Started Jul 25 06:06:57 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194784 kb
Host smart-87af8aa3-a3f8-487e-983f-1c19fe6b1ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685096864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1685096864
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.511294123
Short name T657
Test name
Test status
Simulation time 22276141 ps
CPU time 0.56 seconds
Started Jul 25 06:06:57 PM PDT 24
Finished Jul 25 06:06:57 PM PDT 24
Peak memory 194716 kb
Host smart-628104ac-9b77-40cf-a811-51994e61643d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511294123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.511294123
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3820074111
Short name T581
Test name
Test status
Simulation time 18559251 ps
CPU time 0.57 seconds
Started Jul 25 06:06:57 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194780 kb
Host smart-e7164a9e-ed50-4062-9167-a8f4ce54a104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820074111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3820074111
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.130418266
Short name T584
Test name
Test status
Simulation time 30752968 ps
CPU time 0.61 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 194832 kb
Host smart-eeffb69d-171b-4380-8ae0-736fdf020680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130418266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.130418266
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2093006555
Short name T629
Test name
Test status
Simulation time 14086304 ps
CPU time 0.61 seconds
Started Jul 25 06:07:03 PM PDT 24
Finished Jul 25 06:07:04 PM PDT 24
Peak memory 194736 kb
Host smart-74a2a534-c991-4f03-a129-f5c414faa7fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093006555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2093006555
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2815248295
Short name T94
Test name
Test status
Simulation time 931019728 ps
CPU time 9.04 seconds
Started Jul 25 06:06:48 PM PDT 24
Finished Jul 25 06:06:57 PM PDT 24
Peak memory 199932 kb
Host smart-613fc0fc-4c2b-4310-bf74-4fa5d79d86e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815248295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2815248295
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3407839380
Short name T612
Test name
Test status
Simulation time 216363499 ps
CPU time 9.77 seconds
Started Jul 25 06:06:45 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 199924 kb
Host smart-8d0fc250-5afe-413d-b9d9-6533b2b0884d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407839380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3407839380
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2323492130
Short name T638
Test name
Test status
Simulation time 31111346 ps
CPU time 0.83 seconds
Started Jul 25 06:06:43 PM PDT 24
Finished Jul 25 06:06:44 PM PDT 24
Peak memory 198720 kb
Host smart-a22c1c14-5eac-4d01-86cb-9bd0888a06af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323492130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2323492130
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2337981833
Short name T580
Test name
Test status
Simulation time 39228128295 ps
CPU time 563.62 seconds
Started Jul 25 06:06:47 PM PDT 24
Finished Jul 25 06:16:11 PM PDT 24
Peak memory 215600 kb
Host smart-e97c78d7-693b-4ce4-9d78-82d3ea1171c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337981833 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2337981833
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1294559676
Short name T559
Test name
Test status
Simulation time 16999208 ps
CPU time 0.7 seconds
Started Jul 25 06:06:43 PM PDT 24
Finished Jul 25 06:06:44 PM PDT 24
Peak memory 197788 kb
Host smart-3cbac6f9-5a1a-4110-8f3d-e7aeceaf4fa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294559676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1294559676
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2993991469
Short name T545
Test name
Test status
Simulation time 12715800 ps
CPU time 0.6 seconds
Started Jul 25 06:06:40 PM PDT 24
Finished Jul 25 06:06:41 PM PDT 24
Peak memory 194888 kb
Host smart-68f736b7-d927-4dab-8134-44d00e6233d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993991469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2993991469
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2162292637
Short name T102
Test name
Test status
Simulation time 304613418 ps
CPU time 1.17 seconds
Started Jul 25 06:06:46 PM PDT 24
Finished Jul 25 06:06:47 PM PDT 24
Peak memory 199736 kb
Host smart-fe6a1158-ff45-45ea-b628-fc506cd58fe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162292637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2162292637
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3475193192
Short name T619
Test name
Test status
Simulation time 25581578 ps
CPU time 1.37 seconds
Started Jul 25 06:06:42 PM PDT 24
Finished Jul 25 06:06:44 PM PDT 24
Peak memory 199892 kb
Host smart-a3d7d893-7664-4fd3-be81-65df65127655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475193192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3475193192
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2139847232
Short name T539
Test name
Test status
Simulation time 46288071 ps
CPU time 0.61 seconds
Started Jul 25 06:07:01 PM PDT 24
Finished Jul 25 06:07:01 PM PDT 24
Peak memory 194756 kb
Host smart-995ed681-14fc-4554-a416-df5be0706362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139847232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2139847232
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.899379047
Short name T624
Test name
Test status
Simulation time 16134213 ps
CPU time 0.63 seconds
Started Jul 25 06:07:01 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 194700 kb
Host smart-1d305f85-2ecf-467d-a038-519c5a03c251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899379047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.899379047
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2520045531
Short name T590
Test name
Test status
Simulation time 25712097 ps
CPU time 0.61 seconds
Started Jul 25 06:07:05 PM PDT 24
Finished Jul 25 06:07:05 PM PDT 24
Peak memory 194844 kb
Host smart-4db146fc-54bf-46dc-b5d5-e500f011974b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520045531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2520045531
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3039622479
Short name T544
Test name
Test status
Simulation time 14817571 ps
CPU time 0.61 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194808 kb
Host smart-583ff619-9986-4e68-9736-5a894e5e7936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039622479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3039622479
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.158511675
Short name T650
Test name
Test status
Simulation time 12946579 ps
CPU time 0.61 seconds
Started Jul 25 06:06:54 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 194792 kb
Host smart-6c104185-00b6-4d17-923d-151d10ed547f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158511675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.158511675
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.614310401
Short name T632
Test name
Test status
Simulation time 32604872 ps
CPU time 0.57 seconds
Started Jul 25 06:06:57 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194860 kb
Host smart-baedced6-69fe-489c-8dfe-2fab40250a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614310401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.614310401
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1128782464
Short name T540
Test name
Test status
Simulation time 12915971 ps
CPU time 0.61 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 194880 kb
Host smart-95ad3f8c-f24f-4799-b8c0-becd031993ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128782464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1128782464
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.4145560124
Short name T634
Test name
Test status
Simulation time 16366256 ps
CPU time 0.59 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:06:59 PM PDT 24
Peak memory 194740 kb
Host smart-71eaa672-7927-4717-b335-bba171c9b19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145560124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.4145560124
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2685202389
Short name T568
Test name
Test status
Simulation time 19015170 ps
CPU time 0.6 seconds
Started Jul 25 06:07:01 PM PDT 24
Finished Jul 25 06:07:01 PM PDT 24
Peak memory 194892 kb
Host smart-fd136e06-19dc-4139-a347-942dbdfada35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685202389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2685202389
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.481087417
Short name T579
Test name
Test status
Simulation time 24943515 ps
CPU time 0.61 seconds
Started Jul 25 06:06:57 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194912 kb
Host smart-a929d745-4dcd-4733-86ec-e08258d4fb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481087417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.481087417
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.273619353
Short name T83
Test name
Test status
Simulation time 593752742 ps
CPU time 5.98 seconds
Started Jul 25 06:07:22 PM PDT 24
Finished Jul 25 06:07:28 PM PDT 24
Peak memory 199912 kb
Host smart-b103eab6-2cdd-4fb0-a032-1e06a6b0b17c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273619353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.273619353
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2250990945
Short name T91
Test name
Test status
Simulation time 6080588665 ps
CPU time 14.36 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:07:06 PM PDT 24
Peak memory 199908 kb
Host smart-f7eb8757-6ca5-4a7c-b67f-767a613f5a84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250990945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2250990945
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.286112121
Short name T90
Test name
Test status
Simulation time 118204169 ps
CPU time 0.91 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 199064 kb
Host smart-d8947402-5524-450b-93b1-ac2161cc8d68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286112121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.286112121
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1692795225
Short name T598
Test name
Test status
Simulation time 11094965515 ps
CPU time 101.76 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:08:32 PM PDT 24
Peak memory 215452 kb
Host smart-d463b9d5-dd5e-4002-8024-3f2cd99f5346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692795225 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1692795225
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.240809799
Short name T625
Test name
Test status
Simulation time 26130990 ps
CPU time 0.82 seconds
Started Jul 25 06:06:47 PM PDT 24
Finished Jul 25 06:06:48 PM PDT 24
Peak memory 199288 kb
Host smart-6b731105-4b32-43a4-ac67-69b747e039c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240809799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.240809799
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3591891041
Short name T532
Test name
Test status
Simulation time 13991412 ps
CPU time 0.64 seconds
Started Jul 25 06:06:52 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 194704 kb
Host smart-94389330-a2f8-4cb6-81c8-65adde1aa7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591891041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3591891041
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1377228886
Short name T98
Test name
Test status
Simulation time 312300331 ps
CPU time 1.15 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:50 PM PDT 24
Peak memory 198288 kb
Host smart-956d5868-281a-4150-9912-4b026b9ff319
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377228886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1377228886
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3235510875
Short name T596
Test name
Test status
Simulation time 939102322 ps
CPU time 3.04 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199844 kb
Host smart-0337d78c-02a3-4a1e-9b55-ea8f92ffbbd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235510875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3235510875
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2229609438
Short name T110
Test name
Test status
Simulation time 840243567 ps
CPU time 3.88 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:54 PM PDT 24
Peak memory 199932 kb
Host smart-1dc0bf0a-a7e8-4103-a8af-5507d91078fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229609438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2229609438
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1891118147
Short name T554
Test name
Test status
Simulation time 31965124 ps
CPU time 0.6 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 194784 kb
Host smart-e5bdc14c-13cf-4e07-b54b-3f6d619e13b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891118147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1891118147
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3918942248
Short name T602
Test name
Test status
Simulation time 27402903 ps
CPU time 0.59 seconds
Started Jul 25 06:07:00 PM PDT 24
Finished Jul 25 06:07:00 PM PDT 24
Peak memory 194796 kb
Host smart-ae7e9bcc-8f3b-4d44-8071-3b5d5e5b775d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918942248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3918942248
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3298110396
Short name T649
Test name
Test status
Simulation time 17128268 ps
CPU time 0.57 seconds
Started Jul 25 06:07:01 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 194900 kb
Host smart-515f2b10-cb84-4db6-968b-0fab881f1749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298110396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3298110396
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.4097620552
Short name T547
Test name
Test status
Simulation time 43553880 ps
CPU time 0.66 seconds
Started Jul 25 06:06:57 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194920 kb
Host smart-e37106ea-68cc-453f-a244-e6785787a4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097620552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4097620552
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2065143745
Short name T569
Test name
Test status
Simulation time 12346108 ps
CPU time 0.62 seconds
Started Jul 25 06:07:03 PM PDT 24
Finished Jul 25 06:07:04 PM PDT 24
Peak memory 194920 kb
Host smart-c978a886-92a2-4277-a87f-d8d73f6b89d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065143745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2065143745
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.103711512
Short name T587
Test name
Test status
Simulation time 12676649 ps
CPU time 0.6 seconds
Started Jul 25 06:06:58 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 194792 kb
Host smart-892a6dee-7571-439b-a0ad-4dc0144d9678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103711512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.103711512
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3442286922
Short name T639
Test name
Test status
Simulation time 100270094 ps
CPU time 0.55 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 194732 kb
Host smart-d0a5af3c-e17e-4ba3-a696-138cf597a02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442286922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3442286922
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1131317801
Short name T608
Test name
Test status
Simulation time 43785550 ps
CPU time 0.69 seconds
Started Jul 25 06:07:02 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 194732 kb
Host smart-d480c3e6-d838-4a8c-b819-8992d7b8ee41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131317801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1131317801
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1118357127
Short name T636
Test name
Test status
Simulation time 43874710 ps
CPU time 0.67 seconds
Started Jul 25 06:07:02 PM PDT 24
Finished Jul 25 06:07:02 PM PDT 24
Peak memory 194788 kb
Host smart-0ee1637b-8445-43e4-a5de-3df437260a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118357127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1118357127
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4282399081
Short name T646
Test name
Test status
Simulation time 20047192 ps
CPU time 0.66 seconds
Started Jul 25 06:06:56 PM PDT 24
Finished Jul 25 06:06:57 PM PDT 24
Peak memory 194784 kb
Host smart-f311ae30-1c12-4dcd-9f50-759de615ee1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282399081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4282399081
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.270694106
Short name T622
Test name
Test status
Simulation time 49868432 ps
CPU time 3.26 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:58 PM PDT 24
Peak memory 216312 kb
Host smart-f7fa6c41-3258-4177-be4f-d4d9dbf351c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270694106 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.270694106
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.126500368
Short name T93
Test name
Test status
Simulation time 121301843 ps
CPU time 0.98 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199712 kb
Host smart-c0e8782b-2c07-4a0b-b78d-93535c221d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126500368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.126500368
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1633549041
Short name T594
Test name
Test status
Simulation time 28094786 ps
CPU time 0.6 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 194752 kb
Host smart-412fadd7-127d-40ed-8814-4b54cdfe690f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633549041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1633549041
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1935212119
Short name T626
Test name
Test status
Simulation time 457893933 ps
CPU time 1.11 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 198472 kb
Host smart-5b00b75e-1a1b-40d9-afcd-6ceea1974d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935212119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1935212119
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.461659416
Short name T656
Test name
Test status
Simulation time 1059030173 ps
CPU time 4.08 seconds
Started Jul 25 06:06:53 PM PDT 24
Finished Jul 25 06:06:57 PM PDT 24
Peak memory 199892 kb
Host smart-d54ed14c-a45d-4137-b13e-aaf7f65c904c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461659416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.461659416
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.354312535
Short name T614
Test name
Test status
Simulation time 128232950 ps
CPU time 3.99 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:54 PM PDT 24
Peak memory 199896 kb
Host smart-1c4a961f-95e5-4de9-9b34-805d489b8643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354312535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.354312535
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3219704160
Short name T574
Test name
Test status
Simulation time 45787697 ps
CPU time 2.4 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199960 kb
Host smart-9c00f459-6bcd-4f5f-9292-bd2dc8a389eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219704160 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3219704160
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2224627364
Short name T89
Test name
Test status
Simulation time 59227265 ps
CPU time 0.85 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:50 PM PDT 24
Peak memory 199640 kb
Host smart-2da9d6ee-caaf-413b-b940-69a1996a5e52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224627364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2224627364
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.408896737
Short name T567
Test name
Test status
Simulation time 20336202 ps
CPU time 0.58 seconds
Started Jul 25 06:06:48 PM PDT 24
Finished Jul 25 06:06:49 PM PDT 24
Peak memory 194888 kb
Host smart-a2f50f66-fc4c-4e2d-8a74-f1676c7e61ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408896737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.408896737
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.647182908
Short name T648
Test name
Test status
Simulation time 23353128 ps
CPU time 1.16 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 198468 kb
Host smart-c2fdb21a-cf31-4bf4-a9a0-219920a46c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647182908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.647182908
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3904101843
Short name T630
Test name
Test status
Simulation time 79179908 ps
CPU time 1.79 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199888 kb
Host smart-f369bedf-7cd0-4266-a68e-bf5ddedd2e3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904101843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3904101843
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3630364994
Short name T53
Test name
Test status
Simulation time 332811416 ps
CPU time 1.87 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199876 kb
Host smart-2ef5870c-3147-45b9-8fa2-dd7942cfc49a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630364994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3630364994
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1826508459
Short name T561
Test name
Test status
Simulation time 103687672 ps
CPU time 1.55 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 199960 kb
Host smart-f67de499-ec0c-439e-b6c0-7138d198a6de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826508459 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1826508459
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1633353294
Short name T87
Test name
Test status
Simulation time 60189727 ps
CPU time 0.99 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 199716 kb
Host smart-dcfca718-def0-4def-b852-98cc9ef659a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633353294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1633353294
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3112569225
Short name T651
Test name
Test status
Simulation time 38611904 ps
CPU time 0.6 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 194932 kb
Host smart-2756b22b-7eff-4025-a5d9-bcf82e7d4260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112569225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3112569225
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4235751374
Short name T604
Test name
Test status
Simulation time 363068137 ps
CPU time 1.73 seconds
Started Jul 25 06:06:54 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 199880 kb
Host smart-f50f566b-2a5f-4433-86f4-1b119efe1d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235751374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.4235751374
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.187044649
Short name T606
Test name
Test status
Simulation time 168639249 ps
CPU time 3.82 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199884 kb
Host smart-46b95b59-1746-4509-b6ec-69d05aae1b53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187044649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.187044649
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4201958990
Short name T112
Test name
Test status
Simulation time 91075646 ps
CPU time 2.92 seconds
Started Jul 25 06:06:52 PM PDT 24
Finished Jul 25 06:06:55 PM PDT 24
Peak memory 199952 kb
Host smart-d312afcf-273a-439c-a727-7e70aed49c32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201958990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4201958990
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2973214857
Short name T562
Test name
Test status
Simulation time 142325740825 ps
CPU time 1386.81 seconds
Started Jul 25 06:06:46 PM PDT 24
Finished Jul 25 06:29:53 PM PDT 24
Peak memory 218716 kb
Host smart-12e70e31-0133-4bcc-88b2-bcb1232ea707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973214857 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2973214857
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2286438388
Short name T96
Test name
Test status
Simulation time 183094057 ps
CPU time 0.88 seconds
Started Jul 25 06:06:55 PM PDT 24
Finished Jul 25 06:06:56 PM PDT 24
Peak memory 199696 kb
Host smart-7cbcaf0e-e33b-4adf-a883-61514c2070a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286438388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2286438388
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.135462243
Short name T599
Test name
Test status
Simulation time 30927577 ps
CPU time 0.63 seconds
Started Jul 25 06:06:52 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 194824 kb
Host smart-5f0c373b-6ce5-4158-9170-b9ebae58a5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135462243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.135462243
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.408482158
Short name T588
Test name
Test status
Simulation time 231279236 ps
CPU time 1.25 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199852 kb
Host smart-fb16a580-cc96-493c-b9d3-6fc806d7bddb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408482158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.408482158
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.502601554
Short name T576
Test name
Test status
Simulation time 58818674 ps
CPU time 1.48 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199796 kb
Host smart-753265d9-439a-423f-bb53-3bb2c4ccef64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502601554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.502601554
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2896522242
Short name T643
Test name
Test status
Simulation time 990420292 ps
CPU time 3.2 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199884 kb
Host smart-aed405e0-f8ba-4bed-b4d7-63976b1f5cce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896522242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2896522242
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2303830061
Short name T535
Test name
Test status
Simulation time 153615565 ps
CPU time 1.14 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 199708 kb
Host smart-73b34123-797c-4ba2-9d47-e4ea2833073e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303830061 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2303830061
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.926606793
Short name T92
Test name
Test status
Simulation time 68651569 ps
CPU time 0.91 seconds
Started Jul 25 06:06:51 PM PDT 24
Finished Jul 25 06:06:52 PM PDT 24
Peak memory 199248 kb
Host smart-c659f823-0a4f-4e41-bad2-9cf3ca5d04c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926606793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.926606793
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1635483154
Short name T635
Test name
Test status
Simulation time 16511544 ps
CPU time 0.6 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:50 PM PDT 24
Peak memory 194804 kb
Host smart-60174590-3c48-4b0c-92d9-136aa2f51bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635483154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1635483154
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3560093954
Short name T100
Test name
Test status
Simulation time 84779641 ps
CPU time 2.05 seconds
Started Jul 25 06:06:48 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 199880 kb
Host smart-125133b4-5aba-4f50-b447-373d8f0c489d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560093954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3560093954
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2189363618
Short name T600
Test name
Test status
Simulation time 2688619038 ps
CPU time 3.25 seconds
Started Jul 25 06:06:50 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199968 kb
Host smart-61ca7283-48a5-4a70-8696-1c6c577a66ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189363618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2189363618
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2649756386
Short name T647
Test name
Test status
Simulation time 205777296 ps
CPU time 3.16 seconds
Started Jul 25 06:06:49 PM PDT 24
Finished Jul 25 06:06:53 PM PDT 24
Peak memory 199868 kb
Host smart-aa42a72b-c79c-4b9b-a5b1-a2802d7b4044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649756386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2649756386
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.446610254
Short name T516
Test name
Test status
Simulation time 13878582 ps
CPU time 0.61 seconds
Started Jul 25 06:13:45 PM PDT 24
Finished Jul 25 06:13:46 PM PDT 24
Peak memory 195724 kb
Host smart-d3b5465f-4b3d-423f-a149-080ea660c880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446610254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.446610254
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.911064729
Short name T330
Test name
Test status
Simulation time 2990295799 ps
CPU time 81.97 seconds
Started Jul 25 06:13:40 PM PDT 24
Finished Jul 25 06:15:03 PM PDT 24
Peak memory 199784 kb
Host smart-dffda5f4-b819-4135-a2c9-0b51f19df323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911064729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.911064729
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3121221580
Short name T399
Test name
Test status
Simulation time 28824276922 ps
CPU time 22.7 seconds
Started Jul 25 06:13:37 PM PDT 24
Finished Jul 25 06:14:00 PM PDT 24
Peak memory 199752 kb
Host smart-8fe155f3-c45e-4936-9f4b-f6b0dda13ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121221580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3121221580
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.696879652
Short name T257
Test name
Test status
Simulation time 441912855 ps
CPU time 10.49 seconds
Started Jul 25 06:13:40 PM PDT 24
Finished Jul 25 06:13:51 PM PDT 24
Peak memory 219460 kb
Host smart-19bf05b0-c8a4-458e-aaba-2eadceca795a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696879652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.696879652
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.255139042
Short name T376
Test name
Test status
Simulation time 10776106850 ps
CPU time 132.63 seconds
Started Jul 25 06:13:37 PM PDT 24
Finished Jul 25 06:15:50 PM PDT 24
Peak memory 199772 kb
Host smart-3c52b95b-9495-4c72-9476-b43ecbfdcb57
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255139042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.255139042
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1506802978
Short name T234
Test name
Test status
Simulation time 14564675063 ps
CPU time 185.69 seconds
Started Jul 25 06:13:41 PM PDT 24
Finished Jul 25 06:16:47 PM PDT 24
Peak memory 216140 kb
Host smart-e29396ed-79a3-47bb-a7aa-1aabee55e40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506802978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1506802978
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1004455337
Short name T220
Test name
Test status
Simulation time 205505249 ps
CPU time 4.71 seconds
Started Jul 25 06:13:41 PM PDT 24
Finished Jul 25 06:13:46 PM PDT 24
Peak memory 199676 kb
Host smart-06e912c1-322c-45f2-9bb8-3204396a6236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004455337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1004455337
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1994599502
Short name T348
Test name
Test status
Simulation time 243153542119 ps
CPU time 1660.81 seconds
Started Jul 25 06:13:36 PM PDT 24
Finished Jul 25 06:41:17 PM PDT 24
Peak memory 727520 kb
Host smart-c6220161-970b-4e25-8021-05e84c349da2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994599502 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1994599502
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1327146323
Short name T22
Test name
Test status
Simulation time 308302274784 ps
CPU time 7324.56 seconds
Started Jul 25 06:13:42 PM PDT 24
Finished Jul 25 08:15:48 PM PDT 24
Peak memory 877888 kb
Host smart-b1931883-7b5e-4dbd-9315-57e5b6896c27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327146323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1327146323
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3005638618
Short name T320
Test name
Test status
Simulation time 6537023311 ps
CPU time 81.37 seconds
Started Jul 25 06:13:41 PM PDT 24
Finished Jul 25 06:15:03 PM PDT 24
Peak memory 199728 kb
Host smart-ae630bda-28c9-4b6c-b2f5-7c8867c711ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3005638618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3005638618
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2374498929
Short name T461
Test name
Test status
Simulation time 18573513963 ps
CPU time 58.37 seconds
Started Jul 25 06:13:41 PM PDT 24
Finished Jul 25 06:14:40 PM PDT 24
Peak memory 199788 kb
Host smart-a36f758e-59a0-4c81-a013-cb3cf9d39ed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2374498929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2374498929
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2659143366
Short name T226
Test name
Test status
Simulation time 7973011060 ps
CPU time 123.44 seconds
Started Jul 25 06:13:40 PM PDT 24
Finished Jul 25 06:15:43 PM PDT 24
Peak memory 199748 kb
Host smart-3863f00a-7b50-41bb-970e-8310d3583501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2659143366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2659143366
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.168298003
Short name T163
Test name
Test status
Simulation time 51729784524 ps
CPU time 662.64 seconds
Started Jul 25 06:13:40 PM PDT 24
Finished Jul 25 06:24:43 PM PDT 24
Peak memory 199844 kb
Host smart-73d54bcd-c561-42f8-b485-5f51caf5a2a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=168298003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.168298003
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1726188612
Short name T256
Test name
Test status
Simulation time 85872392918 ps
CPU time 2124.23 seconds
Started Jul 25 06:13:37 PM PDT 24
Finished Jul 25 06:49:01 PM PDT 24
Peak memory 215772 kb
Host smart-084eb770-e1bc-4fdb-861d-93378a4a502b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1726188612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1726188612
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.213873207
Short name T214
Test name
Test status
Simulation time 275973490229 ps
CPU time 2562.03 seconds
Started Jul 25 06:13:39 PM PDT 24
Finished Jul 25 06:56:21 PM PDT 24
Peak memory 215356 kb
Host smart-2b555651-81a9-4b04-9bbb-756a6051013d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=213873207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.213873207
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2032144374
Short name T181
Test name
Test status
Simulation time 1735265319 ps
CPU time 63.83 seconds
Started Jul 25 06:13:37 PM PDT 24
Finished Jul 25 06:14:41 PM PDT 24
Peak memory 199740 kb
Host smart-4b341e0c-9d71-4fec-ab3f-7405cd1f91bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032144374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2032144374
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2978598928
Short name T307
Test name
Test status
Simulation time 43031049 ps
CPU time 0.6 seconds
Started Jul 25 06:13:57 PM PDT 24
Finished Jul 25 06:13:58 PM PDT 24
Peak memory 196408 kb
Host smart-ecce9834-52e4-46d4-8611-3804a33811e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978598928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2978598928
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2720000926
Short name T227
Test name
Test status
Simulation time 124510963 ps
CPU time 6.64 seconds
Started Jul 25 06:13:46 PM PDT 24
Finished Jul 25 06:13:53 PM PDT 24
Peak memory 199700 kb
Host smart-99942bfe-7674-4c2c-9a48-988b09f5df61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720000926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2720000926
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2018622271
Short name T484
Test name
Test status
Simulation time 36579395697 ps
CPU time 62.04 seconds
Started Jul 25 06:13:45 PM PDT 24
Finished Jul 25 06:14:47 PM PDT 24
Peak memory 199732 kb
Host smart-547fff1a-085c-4375-8a48-759434b902da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018622271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2018622271
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1647908056
Short name T329
Test name
Test status
Simulation time 1291362278 ps
CPU time 215.14 seconds
Started Jul 25 06:13:46 PM PDT 24
Finished Jul 25 06:17:21 PM PDT 24
Peak memory 595976 kb
Host smart-fb405cc7-278f-4a4e-b7c1-0fbc885b605b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647908056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1647908056
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.159283710
Short name T205
Test name
Test status
Simulation time 29662404540 ps
CPU time 127.82 seconds
Started Jul 25 06:13:47 PM PDT 24
Finished Jul 25 06:15:55 PM PDT 24
Peak memory 199816 kb
Host smart-a49162ab-d7cb-4337-88be-4f11af8f23b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159283710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.159283710
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2991824865
Short name T459
Test name
Test status
Simulation time 17114423537 ps
CPU time 116.92 seconds
Started Jul 25 06:13:45 PM PDT 24
Finished Jul 25 06:15:42 PM PDT 24
Peak memory 200140 kb
Host smart-1e316c6f-6ca4-431c-afda-d0b0ed2bde31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991824865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2991824865
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4091705196
Short name T44
Test name
Test status
Simulation time 173012942 ps
CPU time 0.98 seconds
Started Jul 25 06:13:54 PM PDT 24
Finished Jul 25 06:13:55 PM PDT 24
Peak memory 219412 kb
Host smart-014ac545-2e77-4f94-832c-ac450c639907
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091705196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4091705196
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3767224862
Short name T7
Test name
Test status
Simulation time 250240272 ps
CPU time 11.34 seconds
Started Jul 25 06:13:45 PM PDT 24
Finished Jul 25 06:13:57 PM PDT 24
Peak memory 199732 kb
Host smart-de1e2964-a1a8-4526-b52b-75b7f99375e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767224862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3767224862
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1928548756
Short name T121
Test name
Test status
Simulation time 62736863844 ps
CPU time 2426.66 seconds
Started Jul 25 06:13:56 PM PDT 24
Finished Jul 25 06:54:23 PM PDT 24
Peak memory 779720 kb
Host smart-46888202-af97-4cd9-9599-cd8b2b1aa3f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928548756 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1928548756
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.727061907
Short name T135
Test name
Test status
Simulation time 4355069998 ps
CPU time 56.91 seconds
Started Jul 25 06:13:45 PM PDT 24
Finished Jul 25 06:14:42 PM PDT 24
Peak memory 199780 kb
Host smart-d770e9d0-7b45-4c33-a46f-917758df051e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=727061907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.727061907
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1950446587
Short name T14
Test name
Test status
Simulation time 9580551064 ps
CPU time 97.72 seconds
Started Jul 25 06:13:48 PM PDT 24
Finished Jul 25 06:15:26 PM PDT 24
Peak memory 199792 kb
Host smart-12e2d5e3-7f4a-46d9-b3d5-1a522309966b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1950446587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1950446587
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2490710666
Short name T299
Test name
Test status
Simulation time 28299422477 ps
CPU time 124.9 seconds
Started Jul 25 06:13:57 PM PDT 24
Finished Jul 25 06:16:02 PM PDT 24
Peak memory 199796 kb
Host smart-e5a7bf89-3100-4949-ad71-67c33e991851
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2490710666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2490710666
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1563481704
Short name T145
Test name
Test status
Simulation time 56014324253 ps
CPU time 679.79 seconds
Started Jul 25 06:13:46 PM PDT 24
Finished Jul 25 06:25:06 PM PDT 24
Peak memory 199836 kb
Host smart-c8ac8c9f-7272-4e5d-81f3-3da18aa7f79d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1563481704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1563481704
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.756216897
Short name T304
Test name
Test status
Simulation time 419560247274 ps
CPU time 2529.94 seconds
Started Jul 25 06:13:48 PM PDT 24
Finished Jul 25 06:55:59 PM PDT 24
Peak memory 215440 kb
Host smart-b492d4d0-090d-455a-8893-188a8bcec622
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=756216897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.756216897
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.552589752
Short name T437
Test name
Test status
Simulation time 153908261623 ps
CPU time 2704.6 seconds
Started Jul 25 06:13:47 PM PDT 24
Finished Jul 25 06:58:52 PM PDT 24
Peak memory 215964 kb
Host smart-792fc4f1-3038-4120-9069-526986d25279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=552589752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.552589752
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1610941449
Short name T315
Test name
Test status
Simulation time 764107639 ps
CPU time 20.79 seconds
Started Jul 25 06:13:47 PM PDT 24
Finished Jul 25 06:14:08 PM PDT 24
Peak memory 199700 kb
Host smart-9c457898-e6fa-4359-b34a-546a36ad0716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610941449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1610941449
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.502907064
Short name T250
Test name
Test status
Simulation time 13874326 ps
CPU time 0.56 seconds
Started Jul 25 06:15:18 PM PDT 24
Finished Jul 25 06:15:19 PM PDT 24
Peak memory 194752 kb
Host smart-59548cc6-7236-45ba-99c5-ddbb38334f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502907064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.502907064
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.724176066
Short name T228
Test name
Test status
Simulation time 948684738 ps
CPU time 53.56 seconds
Started Jul 25 06:15:20 PM PDT 24
Finished Jul 25 06:16:14 PM PDT 24
Peak memory 199752 kb
Host smart-953fab4b-7bbb-4ea9-b6bf-81f509062012
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724176066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.724176066
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2404224967
Short name T236
Test name
Test status
Simulation time 2896905985 ps
CPU time 36.31 seconds
Started Jul 25 06:15:19 PM PDT 24
Finished Jul 25 06:15:56 PM PDT 24
Peak memory 199796 kb
Host smart-195696a3-a377-4c22-9d4c-c1d11655c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404224967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2404224967
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2881989370
Short name T521
Test name
Test status
Simulation time 2258133721 ps
CPU time 152.98 seconds
Started Jul 25 06:15:19 PM PDT 24
Finished Jul 25 06:17:52 PM PDT 24
Peak memory 454384 kb
Host smart-45de4f80-671d-44a5-9138-da5596efc336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881989370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2881989370
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.214987505
Short name T425
Test name
Test status
Simulation time 55963993663 ps
CPU time 241.96 seconds
Started Jul 25 06:15:18 PM PDT 24
Finished Jul 25 06:19:20 PM PDT 24
Peak memory 199792 kb
Host smart-7dfdaee2-9994-47d3-89d1-b8241cf07764
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214987505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.214987505
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.4019985157
Short name T517
Test name
Test status
Simulation time 4421239167 ps
CPU time 62.52 seconds
Started Jul 25 06:15:18 PM PDT 24
Finished Jul 25 06:16:21 PM PDT 24
Peak memory 199840 kb
Host smart-8dd00764-2db2-4304-b33d-3a7885a897a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019985157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4019985157
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3833176288
Short name T217
Test name
Test status
Simulation time 1214125590 ps
CPU time 10.36 seconds
Started Jul 25 06:15:17 PM PDT 24
Finished Jul 25 06:15:27 PM PDT 24
Peak memory 199724 kb
Host smart-9e35f8fe-3632-4173-99c5-c592eb18ab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833176288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3833176288
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.194039320
Short name T65
Test name
Test status
Simulation time 306281441985 ps
CPU time 452.9 seconds
Started Jul 25 06:15:18 PM PDT 24
Finished Jul 25 06:22:51 PM PDT 24
Peak memory 208036 kb
Host smart-49cb5963-3027-4ee7-a6c4-b2763ceb42cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194039320 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.194039320
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2454754090
Short name T263
Test name
Test status
Simulation time 190444314 ps
CPU time 2.02 seconds
Started Jul 25 06:15:17 PM PDT 24
Finished Jul 25 06:15:19 PM PDT 24
Peak memory 199784 kb
Host smart-06878640-7024-433b-a678-e65c76e34a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454754090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2454754090
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4253354602
Short name T431
Test name
Test status
Simulation time 13644806 ps
CPU time 0.6 seconds
Started Jul 25 06:15:32 PM PDT 24
Finished Jul 25 06:15:33 PM PDT 24
Peak memory 195732 kb
Host smart-8a6eac2a-6e5a-44f5-afb5-ba73d56ced0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253354602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4253354602
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1065270397
Short name T149
Test name
Test status
Simulation time 2504683185 ps
CPU time 33.64 seconds
Started Jul 25 06:15:26 PM PDT 24
Finished Jul 25 06:16:00 PM PDT 24
Peak memory 199764 kb
Host smart-9ddd2d00-fc03-40f0-92fd-949b6bf11a9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065270397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1065270397
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3031219563
Short name T274
Test name
Test status
Simulation time 8461010700 ps
CPU time 39.04 seconds
Started Jul 25 06:15:26 PM PDT 24
Finished Jul 25 06:16:05 PM PDT 24
Peak memory 215280 kb
Host smart-36405911-e5ab-42e8-8b66-970df073bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031219563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3031219563
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3635590794
Short name T136
Test name
Test status
Simulation time 315309792 ps
CPU time 44.1 seconds
Started Jul 25 06:15:24 PM PDT 24
Finished Jul 25 06:16:09 PM PDT 24
Peak memory 332868 kb
Host smart-02b6e1c9-3e7c-4f9c-b7ac-7d3ba5d4b35c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635590794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3635590794
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1834698192
Short name T133
Test name
Test status
Simulation time 13816913091 ps
CPU time 128.15 seconds
Started Jul 25 06:15:25 PM PDT 24
Finished Jul 25 06:17:33 PM PDT 24
Peak memory 199764 kb
Host smart-946c908e-3cf1-4b96-9441-27b323850345
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834698192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1834698192
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.4046092035
Short name T172
Test name
Test status
Simulation time 1860296175 ps
CPU time 51.7 seconds
Started Jul 25 06:15:23 PM PDT 24
Finished Jul 25 06:16:15 PM PDT 24
Peak memory 199752 kb
Host smart-3f49c3b9-1c8b-48dc-a96e-d3c789ac8dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046092035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.4046092035
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.300109784
Short name T525
Test name
Test status
Simulation time 2173218048 ps
CPU time 9.02 seconds
Started Jul 25 06:15:26 PM PDT 24
Finished Jul 25 06:15:35 PM PDT 24
Peak memory 199764 kb
Host smart-73a58c99-ec8a-4844-b846-952755568ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300109784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.300109784
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2809595506
Short name T514
Test name
Test status
Simulation time 11946985217 ps
CPU time 103.7 seconds
Started Jul 25 06:15:31 PM PDT 24
Finished Jul 25 06:17:15 PM PDT 24
Peak memory 199820 kb
Host smart-78a2956c-8995-45b3-afd4-4c850dbcb0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809595506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2809595506
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3877682490
Short name T176
Test name
Test status
Simulation time 25377235 ps
CPU time 0.59 seconds
Started Jul 25 06:15:41 PM PDT 24
Finished Jul 25 06:15:42 PM PDT 24
Peak memory 195736 kb
Host smart-fdbc818e-7e4d-47f7-9158-f9a75efcd02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877682490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3877682490
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3607712323
Short name T367
Test name
Test status
Simulation time 1034531973 ps
CPU time 25 seconds
Started Jul 25 06:15:32 PM PDT 24
Finished Jul 25 06:15:57 PM PDT 24
Peak memory 199628 kb
Host smart-6dce53f3-fc3a-4435-9ca1-0166dedd1448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607712323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3607712323
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2483591895
Short name T375
Test name
Test status
Simulation time 3825573969 ps
CPU time 26.42 seconds
Started Jul 25 06:15:40 PM PDT 24
Finished Jul 25 06:16:07 PM PDT 24
Peak memory 199760 kb
Host smart-06340ecd-0dfc-4176-b3fa-bb697ee24354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483591895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2483591895
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.237559843
Short name T4
Test name
Test status
Simulation time 5086722119 ps
CPU time 923.33 seconds
Started Jul 25 06:15:31 PM PDT 24
Finished Jul 25 06:30:55 PM PDT 24
Peak memory 701376 kb
Host smart-da3602e6-fa6c-4041-a0a8-66f307d599c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237559843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.237559843
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3224862230
Short name T342
Test name
Test status
Simulation time 2540142704 ps
CPU time 126.38 seconds
Started Jul 25 06:15:38 PM PDT 24
Finished Jul 25 06:17:44 PM PDT 24
Peak memory 199768 kb
Host smart-874c2003-4e07-49e0-bacc-1a2e408699fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224862230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3224862230
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3281636215
Short name T247
Test name
Test status
Simulation time 2612404299 ps
CPU time 37.83 seconds
Started Jul 25 06:15:35 PM PDT 24
Finished Jul 25 06:16:13 PM PDT 24
Peak memory 199764 kb
Host smart-14f66eea-e43b-4cab-b3dd-069f2786bc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281636215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3281636215
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1017316412
Short name T287
Test name
Test status
Simulation time 3754422024 ps
CPU time 11.17 seconds
Started Jul 25 06:15:33 PM PDT 24
Finished Jul 25 06:15:44 PM PDT 24
Peak memory 199832 kb
Host smart-daf10743-be03-41e7-a555-1191702ccbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017316412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1017316412
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1907230439
Short name T268
Test name
Test status
Simulation time 27367248865 ps
CPU time 881.32 seconds
Started Jul 25 06:15:38 PM PDT 24
Finished Jul 25 06:30:19 PM PDT 24
Peak memory 661692 kb
Host smart-98812953-6406-434e-b7d8-2e77a3c0d3a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907230439 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1907230439
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.542675066
Short name T469
Test name
Test status
Simulation time 2119365644 ps
CPU time 103.47 seconds
Started Jul 25 06:15:38 PM PDT 24
Finished Jul 25 06:17:21 PM PDT 24
Peak memory 199712 kb
Host smart-eac2a7dc-f2fe-4e23-9bb3-37dc9b44249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542675066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.542675066
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3700419933
Short name T365
Test name
Test status
Simulation time 15881289 ps
CPU time 0.56 seconds
Started Jul 25 06:15:36 PM PDT 24
Finished Jul 25 06:15:37 PM PDT 24
Peak memory 194700 kb
Host smart-2fe9c464-09a4-4a11-8f7d-0f639ec20ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700419933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3700419933
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1699940061
Short name T450
Test name
Test status
Simulation time 1659315337 ps
CPU time 85.67 seconds
Started Jul 25 06:15:37 PM PDT 24
Finished Jul 25 06:17:02 PM PDT 24
Peak memory 199748 kb
Host smart-8ee0ba91-10a5-4089-ac8a-cde1b277cf59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699940061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1699940061
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1425771835
Short name T143
Test name
Test status
Simulation time 8399910891 ps
CPU time 414.64 seconds
Started Jul 25 06:15:38 PM PDT 24
Finished Jul 25 06:22:33 PM PDT 24
Peak memory 670020 kb
Host smart-6bdb720a-7870-46c8-9b4b-764bb203432f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425771835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1425771835
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1968013889
Short name T279
Test name
Test status
Simulation time 15059665829 ps
CPU time 50.78 seconds
Started Jul 25 06:15:40 PM PDT 24
Finished Jul 25 06:16:31 PM PDT 24
Peak memory 199768 kb
Host smart-f52eec8c-9b9e-4b4d-bb63-6000e59e8fed
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968013889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1968013889
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2663604455
Short name T50
Test name
Test status
Simulation time 2253987381 ps
CPU time 33.27 seconds
Started Jul 25 06:15:36 PM PDT 24
Finished Jul 25 06:16:10 PM PDT 24
Peak memory 199808 kb
Host smart-5d87804e-35b0-437c-9139-6b4b74143bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663604455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2663604455
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3088342734
Short name T188
Test name
Test status
Simulation time 508097979 ps
CPU time 6.36 seconds
Started Jul 25 06:15:40 PM PDT 24
Finished Jul 25 06:15:47 PM PDT 24
Peak memory 199716 kb
Host smart-f08f127b-7ef0-4e1d-a4be-38cda491f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088342734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3088342734
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.941291686
Short name T364
Test name
Test status
Simulation time 162490657471 ps
CPU time 576.02 seconds
Started Jul 25 06:15:39 PM PDT 24
Finished Jul 25 06:25:15 PM PDT 24
Peak memory 199792 kb
Host smart-8ee6bdcf-680b-415c-81b5-3750e96d31af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941291686 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.941291686
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.287611002
Short name T355
Test name
Test status
Simulation time 78837831524 ps
CPU time 130.44 seconds
Started Jul 25 06:15:39 PM PDT 24
Finished Jul 25 06:17:50 PM PDT 24
Peak memory 199808 kb
Host smart-5266021a-1093-4156-a135-511be01a6dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287611002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.287611002
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2401755560
Short name T396
Test name
Test status
Simulation time 23754314 ps
CPU time 0.6 seconds
Started Jul 25 06:15:45 PM PDT 24
Finished Jul 25 06:15:46 PM PDT 24
Peak memory 195732 kb
Host smart-b372e908-ff17-4a36-813a-d2b04f5058cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401755560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2401755560
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2812288283
Short name T31
Test name
Test status
Simulation time 1551480553 ps
CPU time 90.36 seconds
Started Jul 25 06:15:39 PM PDT 24
Finished Jul 25 06:17:10 PM PDT 24
Peak memory 199708 kb
Host smart-3561ce20-a27c-413f-a7c5-be4597618bc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812288283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2812288283
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1820612273
Short name T502
Test name
Test status
Simulation time 5921872540 ps
CPU time 20.95 seconds
Started Jul 25 06:15:47 PM PDT 24
Finished Jul 25 06:16:08 PM PDT 24
Peak memory 199800 kb
Host smart-60387a35-aa52-44ac-a6da-5f80b10485d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820612273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1820612273
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4031530382
Short name T218
Test name
Test status
Simulation time 5605140840 ps
CPU time 996.5 seconds
Started Jul 25 06:15:38 PM PDT 24
Finished Jul 25 06:32:15 PM PDT 24
Peak memory 701180 kb
Host smart-690fc64d-ac3b-4636-9baa-de0e80d571bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031530382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4031530382
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1915388184
Short name T162
Test name
Test status
Simulation time 27435771124 ps
CPU time 164.59 seconds
Started Jul 25 06:15:46 PM PDT 24
Finished Jul 25 06:18:31 PM PDT 24
Peak memory 199784 kb
Host smart-2ca06836-2b0f-4e0c-9d12-fd7e9bd77908
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915388184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1915388184
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2759071293
Short name T453
Test name
Test status
Simulation time 19923359329 ps
CPU time 94.8 seconds
Started Jul 25 06:15:38 PM PDT 24
Finished Jul 25 06:17:13 PM PDT 24
Peak memory 199728 kb
Host smart-10f61752-58da-4675-ad8d-8dace0e3bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759071293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2759071293
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.263814140
Short name T310
Test name
Test status
Simulation time 217445502 ps
CPU time 3.87 seconds
Started Jul 25 06:15:39 PM PDT 24
Finished Jul 25 06:15:43 PM PDT 24
Peak memory 199660 kb
Host smart-a47eae54-8a0c-4b1f-8d93-662ddf7fcb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263814140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.263814140
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1917186031
Short name T384
Test name
Test status
Simulation time 275309177925 ps
CPU time 898.76 seconds
Started Jul 25 06:15:46 PM PDT 24
Finished Jul 25 06:30:46 PM PDT 24
Peak memory 199772 kb
Host smart-ebf86297-615f-4400-bdb5-875f76176461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917186031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1917186031
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4041810017
Short name T79
Test name
Test status
Simulation time 5820393787 ps
CPU time 77.6 seconds
Started Jul 25 06:15:43 PM PDT 24
Finished Jul 25 06:17:01 PM PDT 24
Peak memory 199768 kb
Host smart-d2064fa3-f622-47e6-bd34-3e0fdcf9cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041810017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4041810017
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.36275809
Short name T311
Test name
Test status
Simulation time 61955701 ps
CPU time 0.59 seconds
Started Jul 25 06:15:53 PM PDT 24
Finished Jul 25 06:15:54 PM PDT 24
Peak memory 195720 kb
Host smart-c0325cb3-da4e-436e-a0b2-477181f72c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36275809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.36275809
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3937175387
Short name T378
Test name
Test status
Simulation time 3120925020 ps
CPU time 68.03 seconds
Started Jul 25 06:15:53 PM PDT 24
Finished Jul 25 06:17:01 PM PDT 24
Peak memory 199828 kb
Host smart-bcca9343-79ad-4716-addb-0c06560eea86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3937175387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3937175387
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.197594229
Short name T232
Test name
Test status
Simulation time 2423029841 ps
CPU time 31.69 seconds
Started Jul 25 06:15:59 PM PDT 24
Finished Jul 25 06:16:31 PM PDT 24
Peak memory 199800 kb
Host smart-f5e4e325-abed-4eb5-9cb1-a6859a767523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197594229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.197594229
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1269479493
Short name T51
Test name
Test status
Simulation time 2000209778 ps
CPU time 322.67 seconds
Started Jul 25 06:15:59 PM PDT 24
Finished Jul 25 06:21:22 PM PDT 24
Peak memory 490904 kb
Host smart-c0b790e7-61ec-4cae-aeee-33420f749fab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269479493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1269479493
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.7939436
Short name T381
Test name
Test status
Simulation time 4928132802 ps
CPU time 67.14 seconds
Started Jul 25 06:15:54 PM PDT 24
Finished Jul 25 06:17:01 PM PDT 24
Peak memory 199812 kb
Host smart-3b347e31-2385-4569-99b9-96376305b40d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7939436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.7939436
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3459310821
Short name T171
Test name
Test status
Simulation time 3007611513 ps
CPU time 152.66 seconds
Started Jul 25 06:15:45 PM PDT 24
Finished Jul 25 06:18:18 PM PDT 24
Peak memory 199844 kb
Host smart-6f953489-38f2-4c17-9179-6fe9bcee2d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459310821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3459310821
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2613128708
Short name T404
Test name
Test status
Simulation time 190990162 ps
CPU time 2.74 seconds
Started Jul 25 06:15:43 PM PDT 24
Finished Jul 25 06:15:46 PM PDT 24
Peak memory 199748 kb
Host smart-78288fca-47af-4327-843d-891377b8f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613128708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2613128708
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.912036839
Short name T306
Test name
Test status
Simulation time 44107468813 ps
CPU time 816.95 seconds
Started Jul 25 06:15:59 PM PDT 24
Finished Jul 25 06:29:36 PM PDT 24
Peak memory 199776 kb
Host smart-33a66a04-87e8-4ec2-bfe8-ca1f125df7e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912036839 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.912036839
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1224324881
Short name T305
Test name
Test status
Simulation time 2795248792 ps
CPU time 26.68 seconds
Started Jul 25 06:15:53 PM PDT 24
Finished Jul 25 06:16:20 PM PDT 24
Peak memory 199720 kb
Host smart-99ea651b-7df1-4e91-80ef-acecc2b45f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224324881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1224324881
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3221911300
Short name T159
Test name
Test status
Simulation time 30162336 ps
CPU time 0.64 seconds
Started Jul 25 06:16:03 PM PDT 24
Finished Jul 25 06:16:04 PM PDT 24
Peak memory 195724 kb
Host smart-2d18c814-cbae-4ccb-858b-7ea1a7e28338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221911300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3221911300
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1499725405
Short name T522
Test name
Test status
Simulation time 1360684235 ps
CPU time 80.65 seconds
Started Jul 25 06:15:54 PM PDT 24
Finished Jul 25 06:17:15 PM PDT 24
Peak memory 199716 kb
Host smart-e6f6c2c9-097e-4176-be85-22f8f29961fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499725405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1499725405
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1272050988
Short name T246
Test name
Test status
Simulation time 1382804375 ps
CPU time 38.41 seconds
Started Jul 25 06:16:04 PM PDT 24
Finished Jul 25 06:16:43 PM PDT 24
Peak memory 199708 kb
Host smart-b815ae33-db0a-4e32-8750-1cd99c6a9eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272050988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1272050988
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4161100916
Short name T195
Test name
Test status
Simulation time 14504924975 ps
CPU time 567.45 seconds
Started Jul 25 06:15:51 PM PDT 24
Finished Jul 25 06:25:19 PM PDT 24
Peak memory 528712 kb
Host smart-8e339e85-1716-4d2b-a80f-9c120c622c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161100916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4161100916
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.386856616
Short name T239
Test name
Test status
Simulation time 13655024514 ps
CPU time 247 seconds
Started Jul 25 06:16:07 PM PDT 24
Finished Jul 25 06:20:14 PM PDT 24
Peak memory 199820 kb
Host smart-8bb16579-44d8-4032-9f88-2bab0a97b3da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386856616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.386856616
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2897961878
Short name T197
Test name
Test status
Simulation time 17601989419 ps
CPU time 66.55 seconds
Started Jul 25 06:15:53 PM PDT 24
Finished Jul 25 06:17:00 PM PDT 24
Peak memory 199800 kb
Host smart-e808998a-4937-48ac-bc39-c9ed88159e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897961878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2897961878
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4101268874
Short name T103
Test name
Test status
Simulation time 176118762 ps
CPU time 7.54 seconds
Started Jul 25 06:15:53 PM PDT 24
Finished Jul 25 06:16:01 PM PDT 24
Peak memory 199720 kb
Host smart-5adc11e6-dc4c-4909-b41d-4ddb3f84478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101268874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4101268874
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3954258647
Short name T314
Test name
Test status
Simulation time 82648486515 ps
CPU time 1733.82 seconds
Started Jul 25 06:16:03 PM PDT 24
Finished Jul 25 06:44:58 PM PDT 24
Peak memory 786804 kb
Host smart-2ff6a293-b76e-48fa-ac0e-2bed3061cb95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954258647 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3954258647
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3755262493
Short name T497
Test name
Test status
Simulation time 9231552836 ps
CPU time 119.47 seconds
Started Jul 25 06:16:03 PM PDT 24
Finished Jul 25 06:18:02 PM PDT 24
Peak memory 199792 kb
Host smart-a7e98ed7-e401-4f45-a348-f5b366c763d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755262493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3755262493
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1677607528
Short name T387
Test name
Test status
Simulation time 21924916 ps
CPU time 0.59 seconds
Started Jul 25 06:16:10 PM PDT 24
Finished Jul 25 06:16:10 PM PDT 24
Peak memory 196376 kb
Host smart-8f5e8475-ecb2-4c52-8ebf-2213daa72e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677607528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1677607528
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3058722981
Short name T137
Test name
Test status
Simulation time 5824536438 ps
CPU time 86.36 seconds
Started Jul 25 06:16:14 PM PDT 24
Finished Jul 25 06:17:41 PM PDT 24
Peak memory 199768 kb
Host smart-09c2d621-dcec-4f0d-b0ff-d3bacf1f725a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058722981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3058722981
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.945072617
Short name T337
Test name
Test status
Simulation time 11084488208 ps
CPU time 15.87 seconds
Started Jul 25 06:16:13 PM PDT 24
Finished Jul 25 06:16:29 PM PDT 24
Peak memory 199848 kb
Host smart-ec5e7261-ca19-4080-8612-8ba0643ec190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945072617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.945072617
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.365920350
Short name T193
Test name
Test status
Simulation time 14528179436 ps
CPU time 668.03 seconds
Started Jul 25 06:16:46 PM PDT 24
Finished Jul 25 06:27:54 PM PDT 24
Peak memory 662668 kb
Host smart-8680916d-fc27-4597-bef1-867fbe1d1486
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365920350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.365920350
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3800616966
Short name T476
Test name
Test status
Simulation time 13978346906 ps
CPU time 173.45 seconds
Started Jul 25 06:16:11 PM PDT 24
Finished Jul 25 06:19:05 PM PDT 24
Peak memory 199772 kb
Host smart-e040f34a-ea89-4366-b00f-5df7495b3ee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800616966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3800616966
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.661367137
Short name T345
Test name
Test status
Simulation time 14179915733 ps
CPU time 105.17 seconds
Started Jul 25 06:16:12 PM PDT 24
Finished Jul 25 06:17:57 PM PDT 24
Peak memory 199772 kb
Host smart-950b8a38-fcac-409d-9941-3cb3ede15c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661367137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.661367137
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2276340733
Short name T191
Test name
Test status
Simulation time 226470169 ps
CPU time 4.57 seconds
Started Jul 25 06:16:04 PM PDT 24
Finished Jul 25 06:16:08 PM PDT 24
Peak memory 199708 kb
Host smart-e5afdc3f-e51c-46db-995d-8cbe534214fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276340733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2276340733
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3508864286
Short name T395
Test name
Test status
Simulation time 15332590973 ps
CPU time 724.24 seconds
Started Jul 25 06:16:08 PM PDT 24
Finished Jul 25 06:28:12 PM PDT 24
Peak memory 674304 kb
Host smart-ab243974-4d5a-4d0f-9622-48a86fb54bbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508864286 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3508864286
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1706531501
Short name T363
Test name
Test status
Simulation time 8206808293 ps
CPU time 112.63 seconds
Started Jul 25 06:16:08 PM PDT 24
Finished Jul 25 06:18:01 PM PDT 24
Peak memory 199844 kb
Host smart-0d092055-b00c-45c6-a89d-3f5eb22e24a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706531501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1706531501
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3059239745
Short name T38
Test name
Test status
Simulation time 26656393 ps
CPU time 0.58 seconds
Started Jul 25 06:16:10 PM PDT 24
Finished Jul 25 06:16:11 PM PDT 24
Peak memory 195704 kb
Host smart-8f079c69-f5e0-4b2d-902a-7bfb6c10abd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059239745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3059239745
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1531458543
Short name T298
Test name
Test status
Simulation time 1531036342 ps
CPU time 40.32 seconds
Started Jul 25 06:16:13 PM PDT 24
Finished Jul 25 06:16:53 PM PDT 24
Peak memory 199716 kb
Host smart-d8a7c565-e686-476d-9d37-a5c4469f9419
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531458543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1531458543
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.260993726
Short name T466
Test name
Test status
Simulation time 4259732059 ps
CPU time 27.96 seconds
Started Jul 25 06:16:12 PM PDT 24
Finished Jul 25 06:16:40 PM PDT 24
Peak memory 199756 kb
Host smart-469566fd-0198-4ec3-99a0-fedfbad79793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260993726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.260993726
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2691441676
Short name T515
Test name
Test status
Simulation time 921994223 ps
CPU time 139.88 seconds
Started Jul 25 06:16:08 PM PDT 24
Finished Jul 25 06:18:28 PM PDT 24
Peak memory 395124 kb
Host smart-584fccba-590b-4ff3-bd7a-eb90d1694dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691441676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2691441676
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1966068283
Short name T73
Test name
Test status
Simulation time 8114234634 ps
CPU time 23.1 seconds
Started Jul 25 06:16:08 PM PDT 24
Finished Jul 25 06:16:31 PM PDT 24
Peak memory 199820 kb
Host smart-2787a63f-5548-4255-8fc4-c282d2f1d59e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966068283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1966068283
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1341464608
Short name T212
Test name
Test status
Simulation time 1490364324 ps
CPU time 46.53 seconds
Started Jul 25 06:16:08 PM PDT 24
Finished Jul 25 06:16:55 PM PDT 24
Peak memory 199812 kb
Host smart-7b31b3b2-9f56-43cf-8f51-868d0cad7da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341464608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1341464608
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1607950590
Short name T424
Test name
Test status
Simulation time 377780225 ps
CPU time 2.39 seconds
Started Jul 25 06:16:09 PM PDT 24
Finished Jul 25 06:16:12 PM PDT 24
Peak memory 199760 kb
Host smart-c5f4da62-0326-42ce-aac8-46eb95c6e430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607950590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1607950590
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3407983132
Short name T106
Test name
Test status
Simulation time 97702673567 ps
CPU time 2613.07 seconds
Started Jul 25 06:16:08 PM PDT 24
Finished Jul 25 06:59:42 PM PDT 24
Peak memory 826932 kb
Host smart-42f354ae-f692-4b8a-a2a3-a68744ec6efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407983132 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3407983132
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3353124098
Short name T289
Test name
Test status
Simulation time 8710692635 ps
CPU time 106.28 seconds
Started Jul 25 06:16:11 PM PDT 24
Finished Jul 25 06:17:57 PM PDT 24
Peak memory 199796 kb
Host smart-170351d1-f3f6-41cb-bab6-a49e67587d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353124098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3353124098
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2749876968
Short name T377
Test name
Test status
Simulation time 61661492 ps
CPU time 0.57 seconds
Started Jul 25 06:16:20 PM PDT 24
Finished Jul 25 06:16:20 PM PDT 24
Peak memory 194680 kb
Host smart-e45ccb43-9e31-432f-9a58-421e9c949566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749876968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2749876968
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3117454168
Short name T201
Test name
Test status
Simulation time 364857010 ps
CPU time 19.72 seconds
Started Jul 25 06:16:19 PM PDT 24
Finished Jul 25 06:16:39 PM PDT 24
Peak memory 199756 kb
Host smart-e1a06552-da2e-4f78-a5a0-f71b4b0ab0ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117454168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3117454168
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3176281901
Short name T511
Test name
Test status
Simulation time 10372009392 ps
CPU time 67.91 seconds
Started Jul 25 06:16:18 PM PDT 24
Finished Jul 25 06:17:26 PM PDT 24
Peak memory 215500 kb
Host smart-caf7831c-bd7a-43b6-8df0-afff2d7dcbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176281901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3176281901
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.496291696
Short name T260
Test name
Test status
Simulation time 3137189995 ps
CPU time 610.32 seconds
Started Jul 25 06:16:14 PM PDT 24
Finished Jul 25 06:26:25 PM PDT 24
Peak memory 722572 kb
Host smart-efe5116a-a26d-44a5-841e-76f479b74a22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496291696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.496291696
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.399564037
Short name T439
Test name
Test status
Simulation time 7666039733 ps
CPU time 67.74 seconds
Started Jul 25 06:16:14 PM PDT 24
Finished Jul 25 06:17:22 PM PDT 24
Peak memory 199788 kb
Host smart-6281405c-08c2-4683-a052-8dad24386907
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399564037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.399564037
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1023105735
Short name T335
Test name
Test status
Simulation time 14745931951 ps
CPU time 207.36 seconds
Started Jul 25 06:16:18 PM PDT 24
Finished Jul 25 06:19:45 PM PDT 24
Peak memory 199784 kb
Host smart-f9c297f2-529a-4cd4-8c79-f3255d326d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023105735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1023105735
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1355192341
Short name T428
Test name
Test status
Simulation time 598976051 ps
CPU time 10.62 seconds
Started Jul 25 06:16:19 PM PDT 24
Finished Jul 25 06:16:30 PM PDT 24
Peak memory 199708 kb
Host smart-c4d75acd-d94a-482b-a204-1b545a7f4f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355192341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1355192341
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.170371542
Short name T321
Test name
Test status
Simulation time 61707006181 ps
CPU time 493.36 seconds
Started Jul 25 06:16:23 PM PDT 24
Finished Jul 25 06:24:37 PM PDT 24
Peak memory 418240 kb
Host smart-bdb9e52b-2aa6-42c5-833a-79258fab2161
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170371542 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.170371542
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1242741063
Short name T506
Test name
Test status
Simulation time 11717032008 ps
CPU time 52.17 seconds
Started Jul 25 06:16:14 PM PDT 24
Finished Jul 25 06:17:06 PM PDT 24
Peak memory 199768 kb
Host smart-b14bb874-929b-4c23-8306-3d8510d7381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242741063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1242741063
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2233302267
Short name T269
Test name
Test status
Simulation time 16470372 ps
CPU time 0.61 seconds
Started Jul 25 06:14:10 PM PDT 24
Finished Jul 25 06:14:11 PM PDT 24
Peak memory 195716 kb
Host smart-bd7fabdf-393d-43c0-802d-3246194bcf70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233302267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2233302267
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3318951999
Short name T389
Test name
Test status
Simulation time 1560830320 ps
CPU time 90.58 seconds
Started Jul 25 06:13:56 PM PDT 24
Finished Jul 25 06:15:26 PM PDT 24
Peak memory 199708 kb
Host smart-ed60f9ef-b085-4195-b32d-23be594bd51d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318951999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3318951999
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.699774939
Short name T273
Test name
Test status
Simulation time 1656557864 ps
CPU time 23.63 seconds
Started Jul 25 06:14:03 PM PDT 24
Finished Jul 25 06:14:27 PM PDT 24
Peak memory 199736 kb
Host smart-2d64a2ae-1314-4066-8703-486c16739fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699774939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.699774939
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4064420025
Short name T368
Test name
Test status
Simulation time 30969040768 ps
CPU time 1129.69 seconds
Started Jul 25 06:14:03 PM PDT 24
Finished Jul 25 06:32:53 PM PDT 24
Peak memory 697788 kb
Host smart-73d25f64-e576-43ef-bc6b-1d59407b4d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064420025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4064420025
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2733020333
Short name T339
Test name
Test status
Simulation time 31790844053 ps
CPU time 92.97 seconds
Started Jul 25 06:14:01 PM PDT 24
Finished Jul 25 06:15:34 PM PDT 24
Peak memory 199772 kb
Host smart-60a4c24c-6203-49c8-a45e-37b736968765
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733020333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2733020333
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3781595703
Short name T413
Test name
Test status
Simulation time 98493040143 ps
CPU time 231.25 seconds
Started Jul 25 06:13:58 PM PDT 24
Finished Jul 25 06:17:49 PM PDT 24
Peak memory 199788 kb
Host smart-046c8c80-c1ba-411f-88b7-5666be5ac359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781595703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3781595703
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2393652628
Short name T41
Test name
Test status
Simulation time 1288169064 ps
CPU time 0.94 seconds
Started Jul 25 06:14:10 PM PDT 24
Finished Jul 25 06:14:12 PM PDT 24
Peak memory 219356 kb
Host smart-6880d08a-ad11-4ee7-b7e5-44731cc39c65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393652628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2393652628
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.982737423
Short name T140
Test name
Test status
Simulation time 1295661160 ps
CPU time 4.26 seconds
Started Jul 25 06:13:57 PM PDT 24
Finished Jul 25 06:14:01 PM PDT 24
Peak memory 199764 kb
Host smart-4a5b316f-fc4f-4eef-b549-f88bf76662a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982737423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.982737423
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2203877424
Short name T465
Test name
Test status
Simulation time 100839136797 ps
CPU time 5807.59 seconds
Started Jul 25 06:14:11 PM PDT 24
Finished Jul 25 07:50:59 PM PDT 24
Peak memory 883968 kb
Host smart-ea1e6954-3601-483f-8236-09859fff3ffd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203877424 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2203877424
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3628674389
Short name T412
Test name
Test status
Simulation time 4255360565 ps
CPU time 71.61 seconds
Started Jul 25 06:14:06 PM PDT 24
Finished Jul 25 06:15:18 PM PDT 24
Peak memory 199788 kb
Host smart-2c46f3e1-ea0a-43de-a0e1-d383e15587e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3628674389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3628674389
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3749083053
Short name T293
Test name
Test status
Simulation time 5401431387 ps
CPU time 62.36 seconds
Started Jul 25 06:14:03 PM PDT 24
Finished Jul 25 06:15:06 PM PDT 24
Peak memory 199816 kb
Host smart-cb55bfbb-cee5-47ea-be89-706d3f50ec82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3749083053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3749083053
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1632900030
Short name T129
Test name
Test status
Simulation time 17282306840 ps
CPU time 78.03 seconds
Started Jul 25 06:14:11 PM PDT 24
Finished Jul 25 06:15:29 PM PDT 24
Peak memory 199748 kb
Host smart-b8da47e6-3e95-435f-af41-e520bdb64c94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1632900030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1632900030
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3496504700
Short name T213
Test name
Test status
Simulation time 372917083752 ps
CPU time 705.63 seconds
Started Jul 25 06:14:01 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 199780 kb
Host smart-fa5cb8c2-2e82-45a1-9679-732fb7e860e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3496504700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3496504700
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3677046580
Short name T74
Test name
Test status
Simulation time 229002504654 ps
CPU time 2714.89 seconds
Started Jul 25 06:14:04 PM PDT 24
Finished Jul 25 06:59:19 PM PDT 24
Peak memory 215260 kb
Host smart-15f9065b-f3b8-4d57-ba8c-a6e7f778f4b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3677046580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3677046580
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.281354126
Short name T309
Test name
Test status
Simulation time 126721525851 ps
CPU time 2088.86 seconds
Started Jul 25 06:14:03 PM PDT 24
Finished Jul 25 06:48:52 PM PDT 24
Peak memory 215600 kb
Host smart-05327657-400e-4ded-9269-f79b464191fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=281354126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.281354126
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1292034054
Short name T242
Test name
Test status
Simulation time 40311921648 ps
CPU time 106.78 seconds
Started Jul 25 06:14:03 PM PDT 24
Finished Jul 25 06:15:50 PM PDT 24
Peak memory 199788 kb
Host smart-be1e48ab-ecbd-4c63-ba9f-0314e7ea6286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292034054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1292034054
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.71883888
Short name T370
Test name
Test status
Simulation time 47466319 ps
CPU time 0.61 seconds
Started Jul 25 06:16:22 PM PDT 24
Finished Jul 25 06:16:22 PM PDT 24
Peak memory 196404 kb
Host smart-777cfb5f-a424-4c61-802a-480516996b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71883888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.71883888
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1965403632
Short name T498
Test name
Test status
Simulation time 2964428218 ps
CPU time 86.56 seconds
Started Jul 25 06:16:21 PM PDT 24
Finished Jul 25 06:17:47 PM PDT 24
Peak memory 199728 kb
Host smart-01243301-a2c8-4af7-aee3-36fea7614598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965403632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1965403632
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2748293652
Short name T479
Test name
Test status
Simulation time 517829694 ps
CPU time 6.57 seconds
Started Jul 25 06:16:23 PM PDT 24
Finished Jul 25 06:16:29 PM PDT 24
Peak memory 199700 kb
Host smart-8e9789d8-8014-47b3-a773-0b9ec93221e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748293652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2748293652
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.4276619790
Short name T126
Test name
Test status
Simulation time 17211284290 ps
CPU time 827.98 seconds
Started Jul 25 06:16:24 PM PDT 24
Finished Jul 25 06:30:13 PM PDT 24
Peak memory 531436 kb
Host smart-71af41d0-a147-401f-950f-7044c15071ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4276619790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.4276619790
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3922984700
Short name T264
Test name
Test status
Simulation time 15201387770 ps
CPU time 175.18 seconds
Started Jul 25 06:16:22 PM PDT 24
Finished Jul 25 06:19:18 PM PDT 24
Peak memory 199764 kb
Host smart-cd9580e4-63ab-43e3-89ed-6986a414bdd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922984700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3922984700
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1955163508
Short name T508
Test name
Test status
Simulation time 20157612545 ps
CPU time 231.44 seconds
Started Jul 25 06:16:23 PM PDT 24
Finished Jul 25 06:20:15 PM PDT 24
Peak memory 199772 kb
Host smart-c21d018c-9386-4da6-afcc-099cbfdb2b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955163508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1955163508
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2554915125
Short name T183
Test name
Test status
Simulation time 2408844985 ps
CPU time 14.29 seconds
Started Jul 25 06:16:24 PM PDT 24
Finished Jul 25 06:16:39 PM PDT 24
Peak memory 199780 kb
Host smart-2f6faa7d-c673-4313-8cfa-75018397c846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554915125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2554915125
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1930539979
Short name T434
Test name
Test status
Simulation time 96822642515 ps
CPU time 422.85 seconds
Started Jul 25 06:16:24 PM PDT 24
Finished Jul 25 06:23:27 PM PDT 24
Peak memory 199844 kb
Host smart-785cc681-9d96-4501-bae3-0a89704d327e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930539979 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1930539979
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4175492861
Short name T78
Test name
Test status
Simulation time 11974953994 ps
CPU time 107.18 seconds
Started Jul 25 06:16:23 PM PDT 24
Finished Jul 25 06:18:11 PM PDT 24
Peak memory 199836 kb
Host smart-3759d57d-0c3c-4856-94dc-f5f7b6bac3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175492861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4175492861
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.4179690506
Short name T369
Test name
Test status
Simulation time 116036512 ps
CPU time 0.61 seconds
Started Jul 25 06:16:27 PM PDT 24
Finished Jul 25 06:16:28 PM PDT 24
Peak memory 195724 kb
Host smart-17e3b9ce-6263-49d5-b40c-53ceb00d2845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179690506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.4179690506
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3864949548
Short name T350
Test name
Test status
Simulation time 6890121569 ps
CPU time 96.85 seconds
Started Jul 25 06:16:29 PM PDT 24
Finished Jul 25 06:18:06 PM PDT 24
Peak memory 199832 kb
Host smart-5462bf5d-2f71-40d1-b9e3-914bf658e4b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864949548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3864949548
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.120963122
Short name T336
Test name
Test status
Simulation time 6706728242 ps
CPU time 42.43 seconds
Started Jul 25 06:16:28 PM PDT 24
Finished Jul 25 06:17:10 PM PDT 24
Peak memory 199832 kb
Host smart-a60d1941-f7f5-4ec8-9032-c260e50d06cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120963122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.120963122
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1672270760
Short name T211
Test name
Test status
Simulation time 8824120111 ps
CPU time 780.18 seconds
Started Jul 25 06:16:28 PM PDT 24
Finished Jul 25 06:29:29 PM PDT 24
Peak memory 704336 kb
Host smart-acb051b1-30a6-484e-9c20-f92ae7eeb3b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672270760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1672270760
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3192639783
Short name T277
Test name
Test status
Simulation time 5823918822 ps
CPU time 51.51 seconds
Started Jul 25 06:16:29 PM PDT 24
Finished Jul 25 06:17:20 PM PDT 24
Peak memory 199816 kb
Host smart-b0190571-cc13-4909-9038-bfd2c6ba5cd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192639783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3192639783
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1224619668
Short name T5
Test name
Test status
Simulation time 2942525246 ps
CPU time 52.5 seconds
Started Jul 25 06:16:23 PM PDT 24
Finished Jul 25 06:17:16 PM PDT 24
Peak memory 199768 kb
Host smart-86a868cf-e152-4cb1-aa6d-5ba920d0b207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224619668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1224619668
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.197046161
Short name T464
Test name
Test status
Simulation time 929520256 ps
CPU time 3.22 seconds
Started Jul 25 06:16:20 PM PDT 24
Finished Jul 25 06:16:23 PM PDT 24
Peak memory 199800 kb
Host smart-7201fc9b-7348-4794-b0ed-7a9131b35591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197046161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.197046161
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1329333896
Short name T235
Test name
Test status
Simulation time 172745092167 ps
CPU time 2568.89 seconds
Started Jul 25 06:16:27 PM PDT 24
Finished Jul 25 06:59:16 PM PDT 24
Peak memory 764268 kb
Host smart-a6e29550-24a1-4d49-9f7c-be2f0ed2465d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329333896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1329333896
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3375535874
Short name T108
Test name
Test status
Simulation time 2221781949 ps
CPU time 110.43 seconds
Started Jul 25 06:16:26 PM PDT 24
Finished Jul 25 06:18:17 PM PDT 24
Peak memory 199796 kb
Host smart-25fc2655-2c74-4268-943e-2b7c7782530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375535874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3375535874
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3162423909
Short name T407
Test name
Test status
Simulation time 16247082 ps
CPU time 0.6 seconds
Started Jul 25 06:16:35 PM PDT 24
Finished Jul 25 06:16:36 PM PDT 24
Peak memory 195780 kb
Host smart-c738578e-c582-4e3c-8b59-3d2266285466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162423909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3162423909
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3272125025
Short name T117
Test name
Test status
Simulation time 1286518991 ps
CPU time 69.58 seconds
Started Jul 25 06:16:36 PM PDT 24
Finished Jul 25 06:17:46 PM PDT 24
Peak memory 199724 kb
Host smart-fdc65707-2d3c-457e-8fbd-67ee28774c79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272125025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3272125025
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2710737086
Short name T194
Test name
Test status
Simulation time 20102754718 ps
CPU time 30.7 seconds
Started Jul 25 06:16:35 PM PDT 24
Finished Jul 25 06:17:05 PM PDT 24
Peak memory 199844 kb
Host smart-787080aa-e6ea-4c6c-a0c1-21f10bab7a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710737086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2710737086
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.35838920
Short name T414
Test name
Test status
Simulation time 10685422704 ps
CPU time 571.06 seconds
Started Jul 25 06:16:37 PM PDT 24
Finished Jul 25 06:26:08 PM PDT 24
Peak memory 697812 kb
Host smart-02daa703-6734-415d-8705-f43da596c019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35838920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.35838920
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2134942733
Short name T454
Test name
Test status
Simulation time 1483530228 ps
CPU time 21.66 seconds
Started Jul 25 06:16:39 PM PDT 24
Finished Jul 25 06:17:01 PM PDT 24
Peak memory 199680 kb
Host smart-2b35eac9-150a-4888-9faf-50a3fabda83c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134942733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2134942733
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3135433584
Short name T303
Test name
Test status
Simulation time 1951142140 ps
CPU time 110.96 seconds
Started Jul 25 06:16:29 PM PDT 24
Finished Jul 25 06:18:20 PM PDT 24
Peak memory 199700 kb
Host smart-6bb3b98a-2c0b-41f6-a10a-0811576fb58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135433584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3135433584
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3108222702
Short name T313
Test name
Test status
Simulation time 1564718305 ps
CPU time 2.19 seconds
Started Jul 25 06:16:28 PM PDT 24
Finished Jul 25 06:16:30 PM PDT 24
Peak memory 199732 kb
Host smart-42eed613-abbc-458f-a927-7ddc1905b030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108222702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3108222702
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3018389041
Short name T64
Test name
Test status
Simulation time 6944021620 ps
CPU time 97.78 seconds
Started Jul 25 06:16:36 PM PDT 24
Finished Jul 25 06:18:14 PM PDT 24
Peak memory 207996 kb
Host smart-fc8fb931-b260-4b07-83aa-19c1a5dd121d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018389041 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3018389041
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3932999361
Short name T492
Test name
Test status
Simulation time 3903107475 ps
CPU time 57.78 seconds
Started Jul 25 06:16:34 PM PDT 24
Finished Jul 25 06:17:32 PM PDT 24
Peak memory 199776 kb
Host smart-d02c246f-77d3-4b8f-a565-ac99d268571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932999361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3932999361
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2002891168
Short name T184
Test name
Test status
Simulation time 120080854 ps
CPU time 0.59 seconds
Started Jul 25 06:16:45 PM PDT 24
Finished Jul 25 06:16:46 PM PDT 24
Peak memory 195732 kb
Host smart-6876a250-5e6a-4279-a285-10a507133ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002891168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2002891168
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1580615933
Short name T141
Test name
Test status
Simulation time 3100960211 ps
CPU time 89.42 seconds
Started Jul 25 06:16:35 PM PDT 24
Finished Jul 25 06:18:04 PM PDT 24
Peak memory 215896 kb
Host smart-7cfc4bed-d4f7-4209-8b30-8e32eb2787a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580615933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1580615933
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1393648044
Short name T312
Test name
Test status
Simulation time 663440845 ps
CPU time 11.7 seconds
Started Jul 25 06:16:43 PM PDT 24
Finished Jul 25 06:16:55 PM PDT 24
Peak memory 199724 kb
Host smart-c93629ff-962a-4d44-a317-1bad1dd48035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393648044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1393648044
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.763150926
Short name T25
Test name
Test status
Simulation time 2880635714 ps
CPU time 310.94 seconds
Started Jul 25 06:16:38 PM PDT 24
Finished Jul 25 06:21:49 PM PDT 24
Peak memory 591004 kb
Host smart-e884b763-17ef-4941-8cec-5ad817493f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763150926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.763150926
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3164122852
Short name T391
Test name
Test status
Simulation time 9805634048 ps
CPU time 100.49 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:18:29 PM PDT 24
Peak memory 199712 kb
Host smart-6d32d062-8c00-4f2a-be72-01e452615722
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164122852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3164122852
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1905428464
Short name T513
Test name
Test status
Simulation time 339422184 ps
CPU time 6.08 seconds
Started Jul 25 06:16:37 PM PDT 24
Finished Jul 25 06:16:43 PM PDT 24
Peak memory 199696 kb
Host smart-8197fc79-9115-4d41-a5fd-de1c6b8c81df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905428464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1905428464
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1768787723
Short name T441
Test name
Test status
Simulation time 2943305400 ps
CPU time 10.17 seconds
Started Jul 25 06:16:33 PM PDT 24
Finished Jul 25 06:16:43 PM PDT 24
Peak memory 199784 kb
Host smart-4e49b3ad-ca08-4cfe-a8c2-46e33097bdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768787723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1768787723
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3227964017
Short name T372
Test name
Test status
Simulation time 686974998282 ps
CPU time 2079.22 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:51:28 PM PDT 24
Peak memory 551816 kb
Host smart-ca4da0a3-d5cd-4d43-8a75-1d96b315c693
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227964017 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3227964017
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1986825076
Short name T334
Test name
Test status
Simulation time 16400438916 ps
CPU time 41.97 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:17:31 PM PDT 24
Peak memory 199740 kb
Host smart-e91249d3-e287-429d-8dcd-7cce87b13bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986825076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1986825076
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1436130845
Short name T185
Test name
Test status
Simulation time 18966671 ps
CPU time 0.58 seconds
Started Jul 25 06:16:42 PM PDT 24
Finished Jul 25 06:16:42 PM PDT 24
Peak memory 194752 kb
Host smart-d86e9987-9afb-46c2-9e3f-01b763191fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436130845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1436130845
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1659853623
Short name T449
Test name
Test status
Simulation time 5018441434 ps
CPU time 67.69 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:17:56 PM PDT 24
Peak memory 199868 kb
Host smart-846988eb-2b22-4451-a488-a402f542aef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659853623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1659853623
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.375461737
Short name T448
Test name
Test status
Simulation time 1159822298 ps
CPU time 8.75 seconds
Started Jul 25 06:16:42 PM PDT 24
Finished Jul 25 06:16:51 PM PDT 24
Peak memory 199640 kb
Host smart-0d7ce1c5-c87a-4464-a132-cb56706708ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375461737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.375461737
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1002449066
Short name T473
Test name
Test status
Simulation time 5688551606 ps
CPU time 1135.15 seconds
Started Jul 25 06:16:43 PM PDT 24
Finished Jul 25 06:35:38 PM PDT 24
Peak memory 739404 kb
Host smart-df582c8a-4ccb-4651-bd4b-c52b98704ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002449066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1002449066
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3568155297
Short name T130
Test name
Test status
Simulation time 6841963406 ps
CPU time 190.87 seconds
Started Jul 25 06:16:43 PM PDT 24
Finished Jul 25 06:19:54 PM PDT 24
Peak memory 199768 kb
Host smart-dbfe82dc-2e63-4f8b-9848-5ec3a14ae9a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568155297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3568155297
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1630848110
Short name T346
Test name
Test status
Simulation time 1564176891 ps
CPU time 96.73 seconds
Started Jul 25 06:16:40 PM PDT 24
Finished Jul 25 06:18:17 PM PDT 24
Peak memory 199700 kb
Host smart-f58155fd-461c-47f9-b7bd-b218b9eb9568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630848110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1630848110
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1625006632
Short name T72
Test name
Test status
Simulation time 354098932 ps
CPU time 8.05 seconds
Started Jul 25 06:16:42 PM PDT 24
Finished Jul 25 06:16:51 PM PDT 24
Peak memory 199712 kb
Host smart-36f34fc9-9336-44f1-8c8c-e9c6b551d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625006632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1625006632
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3929320874
Short name T224
Test name
Test status
Simulation time 93357679757 ps
CPU time 1027.36 seconds
Started Jul 25 06:16:44 PM PDT 24
Finished Jul 25 06:33:52 PM PDT 24
Peak memory 208148 kb
Host smart-0ce84761-6279-485b-ad03-45e0976ea452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929320874 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3929320874
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3675262981
Short name T253
Test name
Test status
Simulation time 2100873274 ps
CPU time 53.19 seconds
Started Jul 25 06:16:44 PM PDT 24
Finished Jul 25 06:17:38 PM PDT 24
Peak memory 199704 kb
Host smart-3e61e520-2350-413f-9734-b7cefccc8934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675262981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3675262981
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2293162235
Short name T210
Test name
Test status
Simulation time 21113189 ps
CPU time 0.6 seconds
Started Jul 25 06:16:52 PM PDT 24
Finished Jul 25 06:16:52 PM PDT 24
Peak memory 195660 kb
Host smart-2f77c048-3b03-43f3-afd3-69d1d4f5d795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293162235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2293162235
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2092657162
Short name T32
Test name
Test status
Simulation time 709895350 ps
CPU time 39.1 seconds
Started Jul 25 06:16:49 PM PDT 24
Finished Jul 25 06:17:29 PM PDT 24
Peak memory 199696 kb
Host smart-667c1af1-9983-4dea-8ce4-06db492c7bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092657162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2092657162
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3131411652
Short name T122
Test name
Test status
Simulation time 1907018962 ps
CPU time 51.09 seconds
Started Jul 25 06:16:50 PM PDT 24
Finished Jul 25 06:17:41 PM PDT 24
Peak memory 199748 kb
Host smart-9c55bdfd-87d9-4efd-a3f6-508ffb440131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131411652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3131411652
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.540334480
Short name T324
Test name
Test status
Simulation time 5373743987 ps
CPU time 1036.57 seconds
Started Jul 25 06:16:51 PM PDT 24
Finished Jul 25 06:34:08 PM PDT 24
Peak memory 752116 kb
Host smart-64df3c9c-0d50-48d1-b367-227f17134ad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540334480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.540334480
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3052036688
Short name T499
Test name
Test status
Simulation time 5317722891 ps
CPU time 87.97 seconds
Started Jul 25 06:16:50 PM PDT 24
Finished Jul 25 06:18:18 PM PDT 24
Peak memory 199788 kb
Host smart-ef407f74-bb5c-4da9-b8e5-46e64e3ce392
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052036688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3052036688
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1828775477
Short name T467
Test name
Test status
Simulation time 9199377829 ps
CPU time 60.05 seconds
Started Jul 25 06:16:47 PM PDT 24
Finished Jul 25 06:17:47 PM PDT 24
Peak memory 199804 kb
Host smart-f18da860-0b5f-455c-8f12-c92fc07e6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828775477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1828775477
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1039579497
Short name T153
Test name
Test status
Simulation time 289647025 ps
CPU time 6.09 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:16:54 PM PDT 24
Peak memory 199664 kb
Host smart-34fbbe0f-990e-498b-a0e7-dcc3f110fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039579497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1039579497
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.4246286604
Short name T61
Test name
Test status
Simulation time 65003872800 ps
CPU time 842.86 seconds
Started Jul 25 06:16:50 PM PDT 24
Finished Jul 25 06:30:53 PM PDT 24
Peak memory 199796 kb
Host smart-e2a4e399-bf24-48cb-aed2-7b8e87d9d5b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246286604 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4246286604
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3097938098
Short name T500
Test name
Test status
Simulation time 217522238 ps
CPU time 6.11 seconds
Started Jul 25 06:16:50 PM PDT 24
Finished Jul 25 06:16:56 PM PDT 24
Peak memory 199712 kb
Host smart-01b27472-2bb9-49a3-a8ff-af60fadad88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097938098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3097938098
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3625922713
Short name T290
Test name
Test status
Simulation time 10838597 ps
CPU time 0.6 seconds
Started Jul 25 06:16:55 PM PDT 24
Finished Jul 25 06:16:56 PM PDT 24
Peak memory 194688 kb
Host smart-74081c79-c09a-45ec-80c7-fe6cd21fd458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625922713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3625922713
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1434106596
Short name T358
Test name
Test status
Simulation time 2081367541 ps
CPU time 21.8 seconds
Started Jul 25 06:16:50 PM PDT 24
Finished Jul 25 06:17:12 PM PDT 24
Peak memory 199656 kb
Host smart-8f76a441-ce98-4d5d-84e4-410e4f14319a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434106596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1434106596
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3443425298
Short name T259
Test name
Test status
Simulation time 5603042953 ps
CPU time 26.92 seconds
Started Jul 25 06:16:47 PM PDT 24
Finished Jul 25 06:17:14 PM PDT 24
Peak memory 199832 kb
Host smart-5e3786bc-00ea-44dc-a1dc-57b029860722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443425298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3443425298
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3293486449
Short name T440
Test name
Test status
Simulation time 20874709107 ps
CPU time 956.67 seconds
Started Jul 25 06:16:51 PM PDT 24
Finished Jul 25 06:32:49 PM PDT 24
Peak memory 705488 kb
Host smart-e543d777-d344-4940-9e19-7e837a236aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3293486449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3293486449
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2197326132
Short name T249
Test name
Test status
Simulation time 5550819763 ps
CPU time 95.65 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:18:23 PM PDT 24
Peak memory 199776 kb
Host smart-066d69c3-2a31-48aa-ab62-2470fa7a5355
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197326132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2197326132
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1465073444
Short name T328
Test name
Test status
Simulation time 5918120286 ps
CPU time 76.54 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:18:05 PM PDT 24
Peak memory 199808 kb
Host smart-b95442cb-16be-49d8-bc43-ff36ca452c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465073444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1465073444
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.16586458
Short name T519
Test name
Test status
Simulation time 2302073731 ps
CPU time 14.98 seconds
Started Jul 25 06:16:47 PM PDT 24
Finished Jul 25 06:17:02 PM PDT 24
Peak memory 199796 kb
Host smart-a5d4acd2-7653-4b72-baab-06c1c62ede2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16586458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.16586458
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1010719054
Short name T503
Test name
Test status
Simulation time 101162721796 ps
CPU time 2079.16 seconds
Started Jul 25 06:16:48 PM PDT 24
Finished Jul 25 06:51:28 PM PDT 24
Peak memory 780572 kb
Host smart-4a3762f1-feef-435c-8285-f424e3e053f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010719054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1010719054
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.901966227
Short name T316
Test name
Test status
Simulation time 2989590977 ps
CPU time 11.5 seconds
Started Jul 25 06:16:47 PM PDT 24
Finished Jul 25 06:16:59 PM PDT 24
Peak memory 199828 kb
Host smart-d2bd85ab-dbf7-4061-9c8d-9dd4b7bc915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901966227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.901966227
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4126199852
Short name T240
Test name
Test status
Simulation time 15037326 ps
CPU time 0.6 seconds
Started Jul 25 06:16:58 PM PDT 24
Finished Jul 25 06:16:58 PM PDT 24
Peak memory 196400 kb
Host smart-2bfb393c-8cce-49bd-b784-5d048d09ea14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126199852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4126199852
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3134025337
Short name T219
Test name
Test status
Simulation time 812453254 ps
CPU time 42.96 seconds
Started Jul 25 06:16:59 PM PDT 24
Finished Jul 25 06:17:42 PM PDT 24
Peak memory 199760 kb
Host smart-4c9277e1-a273-47d9-abb2-0334ec98eb47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134025337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3134025337
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.810645765
Short name T341
Test name
Test status
Simulation time 17540609970 ps
CPU time 66.23 seconds
Started Jul 25 06:16:55 PM PDT 24
Finished Jul 25 06:18:01 PM PDT 24
Peak memory 208024 kb
Host smart-2637d8f7-422b-421f-8909-320c78755981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810645765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.810645765
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3469186578
Short name T283
Test name
Test status
Simulation time 6692823929 ps
CPU time 570.87 seconds
Started Jul 25 06:16:57 PM PDT 24
Finished Jul 25 06:26:28 PM PDT 24
Peak memory 723204 kb
Host smart-9fa91854-d747-400c-abfa-867ae878dad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469186578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3469186578
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3995062802
Short name T325
Test name
Test status
Simulation time 5027861162 ps
CPU time 42.99 seconds
Started Jul 25 06:16:54 PM PDT 24
Finished Jul 25 06:17:37 PM PDT 24
Peak memory 199840 kb
Host smart-62c3a5b9-3058-4d16-b93f-c1057fceb0c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995062802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3995062802
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3617642712
Short name T189
Test name
Test status
Simulation time 11478810832 ps
CPU time 91.37 seconds
Started Jul 25 06:16:54 PM PDT 24
Finished Jul 25 06:18:26 PM PDT 24
Peak memory 199796 kb
Host smart-da4267a3-6bcf-48d2-840b-0f20a436bd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617642712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3617642712
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1561820361
Short name T275
Test name
Test status
Simulation time 1274888653 ps
CPU time 14.78 seconds
Started Jul 25 06:16:56 PM PDT 24
Finished Jul 25 06:17:11 PM PDT 24
Peak memory 199644 kb
Host smart-4bc46fd2-f7b3-47af-9a7a-d7d36e500d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561820361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1561820361
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.4135553374
Short name T67
Test name
Test status
Simulation time 23735822 ps
CPU time 0.65 seconds
Started Jul 25 06:16:58 PM PDT 24
Finished Jul 25 06:16:59 PM PDT 24
Peak memory 195528 kb
Host smart-7d573f32-8c6c-4b09-b0b0-1ee4e4494c6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135553374 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.4135553374
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2164013732
Short name T390
Test name
Test status
Simulation time 16773307732 ps
CPU time 95.3 seconds
Started Jul 25 06:16:56 PM PDT 24
Finished Jul 25 06:18:32 PM PDT 24
Peak memory 199776 kb
Host smart-f0e2a4c0-d253-4d87-8fcd-8e4e32c115da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164013732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2164013732
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1910040239
Short name T406
Test name
Test status
Simulation time 12206092 ps
CPU time 0.59 seconds
Started Jul 25 06:17:03 PM PDT 24
Finished Jul 25 06:17:04 PM PDT 24
Peak memory 195732 kb
Host smart-a1758187-96de-4c7c-bcc7-cb6e081e5392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910040239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1910040239
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2324473311
Short name T475
Test name
Test status
Simulation time 1028838016 ps
CPU time 28.42 seconds
Started Jul 25 06:17:01 PM PDT 24
Finished Jul 25 06:17:29 PM PDT 24
Peak memory 199764 kb
Host smart-0e776f81-dee4-435c-bce9-8f2b17d44c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324473311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2324473311
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.636347025
Short name T154
Test name
Test status
Simulation time 2862447850 ps
CPU time 35.14 seconds
Started Jul 25 06:17:02 PM PDT 24
Finished Jul 25 06:17:38 PM PDT 24
Peak memory 199820 kb
Host smart-db798bca-6fa0-4bb3-afc8-660b9ead58b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636347025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.636347025
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2337775026
Short name T282
Test name
Test status
Simulation time 5241680554 ps
CPU time 1032.42 seconds
Started Jul 25 06:17:00 PM PDT 24
Finished Jul 25 06:34:12 PM PDT 24
Peak memory 687536 kb
Host smart-14bbe411-4c80-442e-8b94-894dc133b9a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2337775026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2337775026
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3132271988
Short name T331
Test name
Test status
Simulation time 11356173544 ps
CPU time 147.93 seconds
Started Jul 25 06:17:03 PM PDT 24
Finished Jul 25 06:19:31 PM PDT 24
Peak memory 199788 kb
Host smart-7abcf863-077f-47eb-b2f3-0615ee74b043
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132271988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3132271988
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1395898536
Short name T244
Test name
Test status
Simulation time 16508438510 ps
CPU time 214.78 seconds
Started Jul 25 06:16:54 PM PDT 24
Finished Jul 25 06:20:29 PM PDT 24
Peak memory 199744 kb
Host smart-086be5d4-808d-4d2b-bf85-074e9ea8857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395898536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1395898536
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1556461008
Short name T241
Test name
Test status
Simulation time 3903424543 ps
CPU time 16.85 seconds
Started Jul 25 06:16:54 PM PDT 24
Finished Jul 25 06:17:11 PM PDT 24
Peak memory 199860 kb
Host smart-6160b423-90c5-4fac-99fc-b0bb5cfa5e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556461008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1556461008
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1411838529
Short name T366
Test name
Test status
Simulation time 196291295946 ps
CPU time 4818.57 seconds
Started Jul 25 06:16:59 PM PDT 24
Finished Jul 25 07:37:18 PM PDT 24
Peak memory 867496 kb
Host smart-0b14db2d-7ed9-4e6b-afdd-4e102765f80b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411838529 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1411838529
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1480778027
Short name T77
Test name
Test status
Simulation time 2075944092 ps
CPU time 28.17 seconds
Started Jul 25 06:17:04 PM PDT 24
Finished Jul 25 06:17:32 PM PDT 24
Peak memory 199656 kb
Host smart-c5402c36-cd70-43f0-bc5c-2d37c20fc692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480778027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1480778027
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4043738574
Short name T398
Test name
Test status
Simulation time 12441506 ps
CPU time 0.57 seconds
Started Jul 25 06:17:07 PM PDT 24
Finished Jul 25 06:17:08 PM PDT 24
Peak memory 195340 kb
Host smart-7b7bb941-1544-4eb3-a1f3-c0aeaaa6de80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043738574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4043738574
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1140629324
Short name T504
Test name
Test status
Simulation time 2835667060 ps
CPU time 37.28 seconds
Started Jul 25 06:17:02 PM PDT 24
Finished Jul 25 06:17:39 PM PDT 24
Peak memory 199824 kb
Host smart-640f1495-a199-40bf-a2dd-5d7ec1a1b0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140629324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1140629324
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2049317049
Short name T452
Test name
Test status
Simulation time 15256071220 ps
CPU time 54.52 seconds
Started Jul 25 06:17:11 PM PDT 24
Finished Jul 25 06:18:06 PM PDT 24
Peak memory 199692 kb
Host smart-2c5a7aff-5957-40bf-96b5-cc570560ccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049317049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2049317049
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1268692657
Short name T262
Test name
Test status
Simulation time 1090673297 ps
CPU time 171.81 seconds
Started Jul 25 06:17:11 PM PDT 24
Finished Jul 25 06:20:03 PM PDT 24
Peak memory 464544 kb
Host smart-50c0794a-ba5a-4220-8ca2-133b710f90ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268692657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1268692657
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3691820673
Short name T270
Test name
Test status
Simulation time 456019639 ps
CPU time 25.75 seconds
Started Jul 25 06:17:08 PM PDT 24
Finished Jul 25 06:17:34 PM PDT 24
Peak memory 199688 kb
Host smart-689e4ec7-32a7-44bb-8077-5bb78aa4e711
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691820673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3691820673
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.879572089
Short name T474
Test name
Test status
Simulation time 2508210317 ps
CPU time 144.94 seconds
Started Jul 25 06:17:00 PM PDT 24
Finished Jul 25 06:19:25 PM PDT 24
Peak memory 199788 kb
Host smart-31cffc73-7a05-4873-9212-0d0b08860b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879572089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.879572089
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.852173390
Short name T510
Test name
Test status
Simulation time 2113016347 ps
CPU time 12.32 seconds
Started Jul 25 06:17:02 PM PDT 24
Finished Jul 25 06:17:15 PM PDT 24
Peak memory 199720 kb
Host smart-d7f93b16-6adc-46a5-b5aa-e9ef97f2d1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852173390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.852173390
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2089446143
Short name T16
Test name
Test status
Simulation time 9326513352 ps
CPU time 504.38 seconds
Started Jul 25 06:17:10 PM PDT 24
Finished Jul 25 06:25:35 PM PDT 24
Peak memory 199752 kb
Host smart-0a1434c3-833b-4519-aeb6-52725b83796e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089446143 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2089446143
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1670883568
Short name T70
Test name
Test status
Simulation time 7648456996 ps
CPU time 92.28 seconds
Started Jul 25 06:17:07 PM PDT 24
Finished Jul 25 06:18:40 PM PDT 24
Peak memory 199768 kb
Host smart-4d12b049-b801-41c7-a741-4f778e360a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670883568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1670883568
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.707015390
Short name T327
Test name
Test status
Simulation time 20594482 ps
CPU time 0.58 seconds
Started Jul 25 06:14:24 PM PDT 24
Finished Jul 25 06:14:24 PM PDT 24
Peak memory 195364 kb
Host smart-63a52338-1d02-4e59-a5cb-c089623261b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707015390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.707015390
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.692839177
Short name T266
Test name
Test status
Simulation time 1566815229 ps
CPU time 75.47 seconds
Started Jul 25 06:14:11 PM PDT 24
Finished Jul 25 06:15:27 PM PDT 24
Peak memory 199716 kb
Host smart-0fc3dfbc-f3e7-4d3b-ba48-c982b449d577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692839177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.692839177
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.689276615
Short name T356
Test name
Test status
Simulation time 4988356982 ps
CPU time 13.82 seconds
Started Jul 25 06:14:16 PM PDT 24
Finished Jul 25 06:14:30 PM PDT 24
Peak memory 199824 kb
Host smart-ef3fd16e-3255-4f4e-978a-0fb64d3cd976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689276615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.689276615
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3720306741
Short name T482
Test name
Test status
Simulation time 1027695007 ps
CPU time 142.97 seconds
Started Jul 25 06:14:09 PM PDT 24
Finished Jul 25 06:16:32 PM PDT 24
Peak memory 337756 kb
Host smart-f88fbbf3-ddc5-41b9-bc83-5d32eac38a64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720306741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3720306741
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.284224623
Short name T3
Test name
Test status
Simulation time 19689959952 ps
CPU time 46.83 seconds
Started Jul 25 06:14:14 PM PDT 24
Finished Jul 25 06:15:01 PM PDT 24
Peak memory 199800 kb
Host smart-063051fb-5e67-4072-8f1b-3f03a95151ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284224623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.284224623
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2131812238
Short name T438
Test name
Test status
Simulation time 7931628089 ps
CPU time 98.72 seconds
Started Jul 25 06:14:11 PM PDT 24
Finished Jul 25 06:15:50 PM PDT 24
Peak memory 199788 kb
Host smart-3b612c28-60cc-40f3-a9db-b38ba77094da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131812238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2131812238
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.4192022860
Short name T43
Test name
Test status
Simulation time 955191532 ps
CPU time 1.02 seconds
Started Jul 25 06:14:22 PM PDT 24
Finished Jul 25 06:14:23 PM PDT 24
Peak memory 219440 kb
Host smart-698db266-c753-406a-a4a2-27fd7c970d2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192022860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.4192022860
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3159015622
Short name T357
Test name
Test status
Simulation time 143910936 ps
CPU time 3.51 seconds
Started Jul 25 06:14:12 PM PDT 24
Finished Jul 25 06:14:16 PM PDT 24
Peak memory 199724 kb
Host smart-15054fa4-2de8-4410-92e8-243d78cf2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159015622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3159015622
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.481310250
Short name T382
Test name
Test status
Simulation time 100434166571 ps
CPU time 4719.05 seconds
Started Jul 25 06:14:21 PM PDT 24
Finished Jul 25 07:33:01 PM PDT 24
Peak memory 866896 kb
Host smart-76d0f2c8-924c-4f90-9b8a-35efa16c014c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481310250 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.481310250
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.224781711
Short name T271
Test name
Test status
Simulation time 16874542893 ps
CPU time 55.15 seconds
Started Jul 25 06:14:17 PM PDT 24
Finished Jul 25 06:15:13 PM PDT 24
Peak memory 199792 kb
Host smart-fb9e5f40-26bb-4e6e-b606-68b04f9d42c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=224781711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.224781711
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1589251350
Short name T444
Test name
Test status
Simulation time 5224004748 ps
CPU time 58.35 seconds
Started Jul 25 06:14:18 PM PDT 24
Finished Jul 25 06:15:16 PM PDT 24
Peak memory 199788 kb
Host smart-7f90a763-4a8d-48d2-9d52-d305de878eb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1589251350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1589251350
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1284872517
Short name T296
Test name
Test status
Simulation time 7760222344 ps
CPU time 123.02 seconds
Started Jul 25 06:14:16 PM PDT 24
Finished Jul 25 06:16:19 PM PDT 24
Peak memory 199788 kb
Host smart-534a4e6e-92b0-4752-8b97-0e1b3574260f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1284872517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1284872517
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1263444220
Short name T178
Test name
Test status
Simulation time 55068374873 ps
CPU time 686.17 seconds
Started Jul 25 06:14:17 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 199776 kb
Host smart-a1340e24-bc52-4494-8ed4-2b14a60182b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1263444220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1263444220
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2144346118
Short name T417
Test name
Test status
Simulation time 158722205657 ps
CPU time 2201.35 seconds
Started Jul 25 06:14:17 PM PDT 24
Finished Jul 25 06:50:59 PM PDT 24
Peak memory 216208 kb
Host smart-68f3f42c-ad30-4097-9f20-38bd6b4746a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2144346118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2144346118
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3288418285
Short name T186
Test name
Test status
Simulation time 141690167140 ps
CPU time 2397.81 seconds
Started Jul 25 06:14:16 PM PDT 24
Finished Jul 25 06:54:15 PM PDT 24
Peak memory 215632 kb
Host smart-df1d56fe-c89f-4f4b-879d-880249d628d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3288418285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3288418285
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3609090954
Short name T526
Test name
Test status
Simulation time 6731279037 ps
CPU time 95.47 seconds
Started Jul 25 06:14:19 PM PDT 24
Finished Jul 25 06:15:54 PM PDT 24
Peak memory 199848 kb
Host smart-08d567fc-965d-4f73-ab03-4af509cf1cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609090954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3609090954
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3209362950
Short name T170
Test name
Test status
Simulation time 14198608 ps
CPU time 0.59 seconds
Started Jul 25 06:17:15 PM PDT 24
Finished Jul 25 06:17:16 PM PDT 24
Peak memory 195584 kb
Host smart-ea446539-0209-4d7f-aa62-561f4c6f5b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209362950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3209362950
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.95089006
Short name T501
Test name
Test status
Simulation time 1261018777 ps
CPU time 36.44 seconds
Started Jul 25 06:17:09 PM PDT 24
Finished Jul 25 06:17:46 PM PDT 24
Peak memory 199676 kb
Host smart-39a16901-76a0-4b08-b5d7-5f1000cb8d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95089006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.95089006
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2161147960
Short name T402
Test name
Test status
Simulation time 391683304 ps
CPU time 1.71 seconds
Started Jul 25 06:17:15 PM PDT 24
Finished Jul 25 06:17:17 PM PDT 24
Peak memory 199700 kb
Host smart-76984fe9-fbed-4dd0-a2f3-f3c7a2c9bfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161147960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2161147960
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2211976816
Short name T393
Test name
Test status
Simulation time 1523763304 ps
CPU time 122.04 seconds
Started Jul 25 06:17:08 PM PDT 24
Finished Jul 25 06:19:10 PM PDT 24
Peak memory 437872 kb
Host smart-cdaeef51-93f9-479e-bc93-eca30d7a0e98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211976816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2211976816
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.258387981
Short name T318
Test name
Test status
Simulation time 142511240137 ps
CPU time 170.79 seconds
Started Jul 25 06:17:17 PM PDT 24
Finished Jul 25 06:20:08 PM PDT 24
Peak memory 199776 kb
Host smart-031584cc-bc7b-47c0-bf20-9f747679f6d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258387981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.258387981
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.350015871
Short name T233
Test name
Test status
Simulation time 260847998 ps
CPU time 4.33 seconds
Started Jul 25 06:17:09 PM PDT 24
Finished Jul 25 06:17:14 PM PDT 24
Peak memory 199704 kb
Host smart-49f7ac74-c471-427c-a911-a7d65fa7f4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350015871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.350015871
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2531809691
Short name T202
Test name
Test status
Simulation time 157877464 ps
CPU time 3.73 seconds
Started Jul 25 06:17:09 PM PDT 24
Finished Jul 25 06:17:13 PM PDT 24
Peak memory 199792 kb
Host smart-ef0d60c2-dc84-4321-aadd-c31649f5a27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531809691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2531809691
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2519591402
Short name T168
Test name
Test status
Simulation time 8490397612 ps
CPU time 135.79 seconds
Started Jul 25 06:17:14 PM PDT 24
Finished Jul 25 06:19:30 PM PDT 24
Peak memory 216200 kb
Host smart-b6b646a8-0179-4542-b551-e6012dfa8f3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519591402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2519591402
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3902747335
Short name T76
Test name
Test status
Simulation time 7745764782 ps
CPU time 93.07 seconds
Started Jul 25 06:17:14 PM PDT 24
Finished Jul 25 06:18:47 PM PDT 24
Peak memory 199820 kb
Host smart-c38d2b63-11b6-4361-b57e-3435ef101a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902747335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3902747335
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3520573886
Short name T182
Test name
Test status
Simulation time 111307129 ps
CPU time 0.55 seconds
Started Jul 25 06:17:23 PM PDT 24
Finished Jul 25 06:17:23 PM PDT 24
Peak memory 194676 kb
Host smart-a4880fc0-2093-4a15-bef8-89f8a476f697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520573886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3520573886
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1584198559
Short name T45
Test name
Test status
Simulation time 56457412 ps
CPU time 3 seconds
Started Jul 25 06:17:23 PM PDT 24
Finished Jul 25 06:17:26 PM PDT 24
Peak memory 199592 kb
Host smart-c285bfde-a388-4dc2-a6f3-a37e7b6c9599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1584198559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1584198559
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.437351257
Short name T418
Test name
Test status
Simulation time 8041086141 ps
CPU time 29 seconds
Started Jul 25 06:17:23 PM PDT 24
Finished Jul 25 06:17:52 PM PDT 24
Peak memory 199768 kb
Host smart-0a2f1c32-a0de-42b5-9180-8dffdf4eda95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437351257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.437351257
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3898118486
Short name T480
Test name
Test status
Simulation time 901157318 ps
CPU time 125.11 seconds
Started Jul 25 06:17:22 PM PDT 24
Finished Jul 25 06:19:27 PM PDT 24
Peak memory 353376 kb
Host smart-fd28f62e-e5b5-4af4-940f-e22290e326a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898118486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3898118486
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2864528099
Short name T284
Test name
Test status
Simulation time 6644970433 ps
CPU time 111.7 seconds
Started Jul 25 06:17:22 PM PDT 24
Finished Jul 25 06:19:14 PM PDT 24
Peak memory 199812 kb
Host smart-4193d7f5-9835-4069-849f-770d8af882a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864528099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2864528099
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2317123992
Short name T47
Test name
Test status
Simulation time 4328633329 ps
CPU time 120.39 seconds
Started Jul 25 06:17:32 PM PDT 24
Finished Jul 25 06:19:33 PM PDT 24
Peak memory 199644 kb
Host smart-51f479cd-f626-4956-95d2-37df28bb31ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317123992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2317123992
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2794561546
Short name T371
Test name
Test status
Simulation time 1926442210 ps
CPU time 11.65 seconds
Started Jul 25 06:17:22 PM PDT 24
Finished Jul 25 06:17:34 PM PDT 24
Peak memory 199708 kb
Host smart-c64781ac-02e9-4987-850d-d84010a8317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794561546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2794561546
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3289373305
Short name T494
Test name
Test status
Simulation time 7017180086 ps
CPU time 51.09 seconds
Started Jul 25 06:17:21 PM PDT 24
Finished Jul 25 06:18:12 PM PDT 24
Peak memory 199892 kb
Host smart-a2b25c2f-6966-4c99-97bd-993a557239b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289373305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3289373305
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3811758799
Short name T455
Test name
Test status
Simulation time 29766118 ps
CPU time 0.56 seconds
Started Jul 25 06:17:24 PM PDT 24
Finished Jul 25 06:17:25 PM PDT 24
Peak memory 194636 kb
Host smart-fdd50401-d47d-408e-9882-1875fc7ad497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811758799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3811758799
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2611257732
Short name T254
Test name
Test status
Simulation time 767148391 ps
CPU time 45.93 seconds
Started Jul 25 06:17:27 PM PDT 24
Finished Jul 25 06:18:13 PM PDT 24
Peak memory 199728 kb
Host smart-fa8e5d63-1357-4e16-a1fa-041b7c3e4c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611257732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2611257732
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1971521026
Short name T385
Test name
Test status
Simulation time 1292189278 ps
CPU time 23.13 seconds
Started Jul 25 06:17:27 PM PDT 24
Finished Jul 25 06:17:50 PM PDT 24
Peak memory 199724 kb
Host smart-eea35c70-7b52-43bf-8967-6f69864e6873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971521026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1971521026
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2812987538
Short name T175
Test name
Test status
Simulation time 7211594709 ps
CPU time 1286.65 seconds
Started Jul 25 06:17:27 PM PDT 24
Finished Jul 25 06:38:54 PM PDT 24
Peak memory 709480 kb
Host smart-8e438bf7-67be-4cab-b122-0d0a1ca343e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812987538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2812987538
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2524986840
Short name T245
Test name
Test status
Simulation time 3632052471 ps
CPU time 63.89 seconds
Started Jul 25 06:17:28 PM PDT 24
Finished Jul 25 06:18:32 PM PDT 24
Peak memory 199764 kb
Host smart-33889e52-e6bf-4d92-b24d-8c9596fd3375
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524986840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2524986840
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.802777453
Short name T458
Test name
Test status
Simulation time 4166592943 ps
CPU time 58.41 seconds
Started Jul 25 06:17:24 PM PDT 24
Finished Jul 25 06:18:22 PM PDT 24
Peak memory 199816 kb
Host smart-1166a086-9015-40d3-950f-6ef39cadea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802777453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.802777453
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1103449973
Short name T128
Test name
Test status
Simulation time 239566569 ps
CPU time 10.56 seconds
Started Jul 25 06:17:22 PM PDT 24
Finished Jul 25 06:17:33 PM PDT 24
Peak memory 199764 kb
Host smart-cb867cf0-0ce7-4b9d-9d6b-623dc67dd33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103449973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1103449973
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2116796631
Short name T477
Test name
Test status
Simulation time 73073460043 ps
CPU time 1546.79 seconds
Started Jul 25 06:17:29 PM PDT 24
Finished Jul 25 06:43:16 PM PDT 24
Peak memory 656284 kb
Host smart-48a6c14f-7dfa-4180-ac45-570afb483882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116796631 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2116796631
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2921992939
Short name T523
Test name
Test status
Simulation time 2442507572 ps
CPU time 18.18 seconds
Started Jul 25 06:17:28 PM PDT 24
Finished Jul 25 06:17:47 PM PDT 24
Peak memory 199796 kb
Host smart-0e40dbaa-3317-4ec0-9ec6-4ada21c51411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921992939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2921992939
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2174276042
Short name T167
Test name
Test status
Simulation time 11481082 ps
CPU time 0.59 seconds
Started Jul 25 06:17:37 PM PDT 24
Finished Jul 25 06:17:38 PM PDT 24
Peak memory 194640 kb
Host smart-9e622b11-9493-409d-a64d-322f9f59da26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174276042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2174276042
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3892563306
Short name T451
Test name
Test status
Simulation time 1089102455 ps
CPU time 53.41 seconds
Started Jul 25 06:17:33 PM PDT 24
Finished Jul 25 06:18:26 PM PDT 24
Peak memory 199792 kb
Host smart-6991f6ee-1ab6-4c86-a49a-83607a5c6ad9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892563306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3892563306
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.93797128
Short name T35
Test name
Test status
Simulation time 3409152297 ps
CPU time 46.45 seconds
Started Jul 25 06:17:34 PM PDT 24
Finished Jul 25 06:18:20 PM PDT 24
Peak memory 199764 kb
Host smart-57c988e1-604f-4900-9f69-d2a134f81242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93797128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.93797128
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3297596036
Short name T169
Test name
Test status
Simulation time 6010300543 ps
CPU time 1508.16 seconds
Started Jul 25 06:17:37 PM PDT 24
Finished Jul 25 06:42:45 PM PDT 24
Peak memory 798304 kb
Host smart-1d9d56f6-d59a-4615-bd9f-077f0bb57063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297596036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3297596036
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2914552539
Short name T174
Test name
Test status
Simulation time 25984351989 ps
CPU time 175.13 seconds
Started Jul 25 06:17:35 PM PDT 24
Finished Jul 25 06:20:30 PM PDT 24
Peak memory 199728 kb
Host smart-42268400-4012-4d3c-bc49-293015574ae5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914552539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2914552539
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1309810772
Short name T421
Test name
Test status
Simulation time 6289857519 ps
CPU time 86.7 seconds
Started Jul 25 06:17:38 PM PDT 24
Finished Jul 25 06:19:05 PM PDT 24
Peak memory 199688 kb
Host smart-70955f99-26c0-4a60-9dab-835032d5bfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309810772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1309810772
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2582513567
Short name T481
Test name
Test status
Simulation time 172174850 ps
CPU time 2.88 seconds
Started Jul 25 06:17:28 PM PDT 24
Finished Jul 25 06:17:31 PM PDT 24
Peak memory 199716 kb
Host smart-bf8be583-0ab5-427a-80e0-3da5e74fd01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582513567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2582513567
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3337393268
Short name T208
Test name
Test status
Simulation time 11640679663 ps
CPU time 167.96 seconds
Started Jul 25 06:17:33 PM PDT 24
Finished Jul 25 06:20:21 PM PDT 24
Peak memory 199796 kb
Host smart-25f401c4-2b70-4fa8-aa7f-d22f571d3040
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337393268 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3337393268
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2432820886
Short name T285
Test name
Test status
Simulation time 940487203 ps
CPU time 46.55 seconds
Started Jul 25 06:17:33 PM PDT 24
Finished Jul 25 06:18:20 PM PDT 24
Peak memory 199764 kb
Host smart-7b211a03-61a2-42f9-a18a-5bbc158dc272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432820886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2432820886
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1172472194
Short name T462
Test name
Test status
Simulation time 46136515 ps
CPU time 0.58 seconds
Started Jul 25 06:17:40 PM PDT 24
Finished Jul 25 06:17:41 PM PDT 24
Peak memory 195692 kb
Host smart-0b6ef318-5944-47c9-afec-770e5dab5c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172472194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1172472194
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3586083992
Short name T415
Test name
Test status
Simulation time 6970682402 ps
CPU time 80.18 seconds
Started Jul 25 06:17:35 PM PDT 24
Finished Jul 25 06:18:55 PM PDT 24
Peak memory 199832 kb
Host smart-bed4fa26-7757-485f-8580-7b366b642f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586083992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3586083992
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1452292369
Short name T322
Test name
Test status
Simulation time 1323666947 ps
CPU time 23.05 seconds
Started Jul 25 06:17:37 PM PDT 24
Finished Jul 25 06:18:00 PM PDT 24
Peak memory 199720 kb
Host smart-c98ab4e8-cd16-42fe-b88b-46db62093458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452292369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1452292369
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3331207276
Short name T352
Test name
Test status
Simulation time 4549654561 ps
CPU time 876.77 seconds
Started Jul 25 06:17:37 PM PDT 24
Finished Jul 25 06:32:14 PM PDT 24
Peak memory 739832 kb
Host smart-4157a812-1f2d-48d4-b431-f21296c239e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331207276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3331207276
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1931430082
Short name T104
Test name
Test status
Simulation time 7503828181 ps
CPU time 102.01 seconds
Started Jul 25 06:17:50 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 199408 kb
Host smart-43bdb282-bf59-4f1c-83cb-423d2b6c7ecf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931430082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1931430082
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3886946130
Short name T187
Test name
Test status
Simulation time 25669786673 ps
CPU time 168.61 seconds
Started Jul 25 06:17:37 PM PDT 24
Finished Jul 25 06:20:26 PM PDT 24
Peak memory 199752 kb
Host smart-6bc866ac-a7f6-4449-adc8-5378e71bca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886946130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3886946130
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.4101755473
Short name T251
Test name
Test status
Simulation time 346526047 ps
CPU time 6.18 seconds
Started Jul 25 06:17:35 PM PDT 24
Finished Jul 25 06:17:42 PM PDT 24
Peak memory 199684 kb
Host smart-4d566bcf-183b-47fe-b48e-adb9d68e0e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101755473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.4101755473
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2635097658
Short name T107
Test name
Test status
Simulation time 127136741007 ps
CPU time 1037.44 seconds
Started Jul 25 06:17:39 PM PDT 24
Finished Jul 25 06:34:57 PM PDT 24
Peak memory 622720 kb
Host smart-050640e3-5a99-424d-8f78-adc773e6fa7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635097658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2635097658
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.379670402
Short name T489
Test name
Test status
Simulation time 7220170683 ps
CPU time 23.98 seconds
Started Jul 25 06:17:39 PM PDT 24
Finished Jul 25 06:18:03 PM PDT 24
Peak memory 199784 kb
Host smart-8b478f9e-970b-42bd-9ebc-234c3b3c2de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379670402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.379670402
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3470714881
Short name T222
Test name
Test status
Simulation time 53361055 ps
CPU time 0.62 seconds
Started Jul 25 06:17:40 PM PDT 24
Finished Jul 25 06:17:40 PM PDT 24
Peak memory 195420 kb
Host smart-5d249d19-2886-4cca-8ffe-79217726c66c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470714881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3470714881
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2970122308
Short name T267
Test name
Test status
Simulation time 3144377431 ps
CPU time 91.48 seconds
Started Jul 25 06:17:39 PM PDT 24
Finished Jul 25 06:19:10 PM PDT 24
Peak memory 215244 kb
Host smart-e44120e8-b02f-4e5c-97ec-49ab7c97ffbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970122308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2970122308
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.897627443
Short name T457
Test name
Test status
Simulation time 1268547318 ps
CPU time 34.29 seconds
Started Jul 25 06:17:41 PM PDT 24
Finished Jul 25 06:18:15 PM PDT 24
Peak memory 199716 kb
Host smart-9cefb852-e256-48e1-ba79-6d86931d4ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897627443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.897627443
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3946381850
Short name T488
Test name
Test status
Simulation time 18321547980 ps
CPU time 739.89 seconds
Started Jul 25 06:17:40 PM PDT 24
Finished Jul 25 06:30:00 PM PDT 24
Peak memory 667972 kb
Host smart-b4ff75e9-ed49-446f-81e7-b157b789a2eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946381850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3946381850
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3836271257
Short name T343
Test name
Test status
Simulation time 3598378778 ps
CPU time 61.62 seconds
Started Jul 25 06:17:50 PM PDT 24
Finished Jul 25 06:18:51 PM PDT 24
Peak memory 199476 kb
Host smart-ed8f5482-4d80-4d98-8a86-2611f6a44aa2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836271257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3836271257
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3441369535
Short name T333
Test name
Test status
Simulation time 12640071334 ps
CPU time 109.09 seconds
Started Jul 25 06:17:36 PM PDT 24
Finished Jul 25 06:19:26 PM PDT 24
Peak memory 199776 kb
Host smart-e75a2280-3e1d-468f-94df-83bda4ba1849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441369535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3441369535
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.4217379903
Short name T165
Test name
Test status
Simulation time 614183010 ps
CPU time 7.86 seconds
Started Jul 25 06:17:50 PM PDT 24
Finished Jul 25 06:17:58 PM PDT 24
Peak memory 199588 kb
Host smart-4604bb6d-398d-4033-8cac-cce2d6c9f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217379903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4217379903
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3891316036
Short name T278
Test name
Test status
Simulation time 2131959180 ps
CPU time 37.5 seconds
Started Jul 25 06:17:41 PM PDT 24
Finished Jul 25 06:18:19 PM PDT 24
Peak memory 199700 kb
Host smart-194423e9-e1fb-4064-9e11-0cb5ff0802ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891316036 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3891316036
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.507894703
Short name T373
Test name
Test status
Simulation time 33739385949 ps
CPU time 71.35 seconds
Started Jul 25 06:17:41 PM PDT 24
Finished Jul 25 06:18:52 PM PDT 24
Peak memory 199748 kb
Host smart-dabce411-98d3-4aba-9379-2bd957552bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507894703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.507894703
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.61339180
Short name T216
Test name
Test status
Simulation time 20970436 ps
CPU time 0.59 seconds
Started Jul 25 06:17:52 PM PDT 24
Finished Jul 25 06:17:53 PM PDT 24
Peak memory 195652 kb
Host smart-74b80846-1f0c-4348-a884-eb591f46ed20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61339180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.61339180
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3309847822
Short name T29
Test name
Test status
Simulation time 1732965178 ps
CPU time 100.63 seconds
Started Jul 25 06:17:54 PM PDT 24
Finished Jul 25 06:19:35 PM PDT 24
Peak memory 199724 kb
Host smart-093aceac-aa86-4a9d-a6e5-e36e0db0e35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309847822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3309847822
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1838834815
Short name T19
Test name
Test status
Simulation time 909922302 ps
CPU time 37.2 seconds
Started Jul 25 06:17:54 PM PDT 24
Finished Jul 25 06:18:31 PM PDT 24
Peak memory 199760 kb
Host smart-f58ef945-ac4e-44d0-ac8a-63aad4c1c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838834815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1838834815
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3660371515
Short name T157
Test name
Test status
Simulation time 5163437544 ps
CPU time 991.59 seconds
Started Jul 25 06:17:54 PM PDT 24
Finished Jul 25 06:34:26 PM PDT 24
Peak memory 766688 kb
Host smart-33c512e4-35f8-4d28-905b-a5c308553222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660371515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3660371515
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1691247441
Short name T447
Test name
Test status
Simulation time 11607096521 ps
CPU time 209.87 seconds
Started Jul 25 06:17:55 PM PDT 24
Finished Jul 25 06:21:25 PM PDT 24
Peak memory 199748 kb
Host smart-078ef1e7-918c-48bc-b7c0-f0995fc87840
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691247441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1691247441
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1083182949
Short name T379
Test name
Test status
Simulation time 11134439590 ps
CPU time 148.36 seconds
Started Jul 25 06:17:54 PM PDT 24
Finished Jul 25 06:20:23 PM PDT 24
Peak memory 216104 kb
Host smart-559c163c-ec73-4474-95c4-0180163be499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083182949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1083182949
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3454396506
Short name T207
Test name
Test status
Simulation time 5001901763 ps
CPU time 9.29 seconds
Started Jul 25 06:17:53 PM PDT 24
Finished Jul 25 06:18:02 PM PDT 24
Peak memory 199776 kb
Host smart-d87d1c18-38be-480c-beb4-7290da4e5097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454396506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3454396506
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4092813376
Short name T68
Test name
Test status
Simulation time 79138657706 ps
CPU time 1340.34 seconds
Started Jul 25 06:17:50 PM PDT 24
Finished Jul 25 06:40:11 PM PDT 24
Peak memory 659156 kb
Host smart-4d921d8a-813e-4643-8144-6f19b455a25c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092813376 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4092813376
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1639113126
Short name T420
Test name
Test status
Simulation time 6677577380 ps
CPU time 84.68 seconds
Started Jul 25 06:17:51 PM PDT 24
Finished Jul 25 06:19:16 PM PDT 24
Peak memory 199780 kb
Host smart-9289c39a-5cdc-4680-bfa5-85fa5d0df89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639113126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1639113126
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3323722430
Short name T52
Test name
Test status
Simulation time 31693679 ps
CPU time 0.59 seconds
Started Jul 25 06:17:56 PM PDT 24
Finished Jul 25 06:17:57 PM PDT 24
Peak memory 195712 kb
Host smart-368f02ea-d3f4-49ed-97b2-bb6febf13fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323722430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3323722430
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1036366015
Short name T294
Test name
Test status
Simulation time 3636711217 ps
CPU time 53.04 seconds
Started Jul 25 06:17:51 PM PDT 24
Finished Jul 25 06:18:44 PM PDT 24
Peak memory 199832 kb
Host smart-efe08fe3-e099-4194-bcf3-34a531b800b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036366015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1036366015
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1673388736
Short name T118
Test name
Test status
Simulation time 17894655871 ps
CPU time 34.17 seconds
Started Jul 25 06:17:52 PM PDT 24
Finished Jul 25 06:18:27 PM PDT 24
Peak memory 207944 kb
Host smart-90016f16-fd42-4e01-8a64-6781dc61d921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673388736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1673388736
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1434301889
Short name T200
Test name
Test status
Simulation time 3666710718 ps
CPU time 138.76 seconds
Started Jul 25 06:17:53 PM PDT 24
Finished Jul 25 06:20:12 PM PDT 24
Peak memory 588996 kb
Host smart-6500938b-e3e0-49f3-a309-c8e9611f9ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434301889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1434301889
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1387367646
Short name T456
Test name
Test status
Simulation time 4523501835 ps
CPU time 98.61 seconds
Started Jul 25 06:17:57 PM PDT 24
Finished Jul 25 06:19:35 PM PDT 24
Peak memory 199784 kb
Host smart-80b7359f-9f3a-472a-905c-572a74c02d4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387367646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1387367646
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2286939919
Short name T276
Test name
Test status
Simulation time 11340310867 ps
CPU time 101.03 seconds
Started Jul 25 06:17:55 PM PDT 24
Finished Jul 25 06:19:36 PM PDT 24
Peak memory 199760 kb
Host smart-e5d154d4-f29e-4779-b7f4-a67709a30c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286939919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2286939919
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3206669121
Short name T300
Test name
Test status
Simulation time 235201090 ps
CPU time 11.11 seconds
Started Jul 25 06:17:55 PM PDT 24
Finished Jul 25 06:18:06 PM PDT 24
Peak memory 199764 kb
Host smart-901714d5-afd5-4341-92d6-ee0254a60854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206669121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3206669121
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1752487653
Short name T362
Test name
Test status
Simulation time 136654804347 ps
CPU time 3411.44 seconds
Started Jul 25 06:17:55 PM PDT 24
Finished Jul 25 07:14:46 PM PDT 24
Peak memory 791340 kb
Host smart-559e6a83-4a1f-4bb4-9975-d661ac323e44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752487653 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1752487653
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3408823828
Short name T490
Test name
Test status
Simulation time 2098321737 ps
CPU time 28.83 seconds
Started Jul 25 06:17:58 PM PDT 24
Finished Jul 25 06:18:26 PM PDT 24
Peak memory 199724 kb
Host smart-7a56cedc-b2fa-4efb-a1da-a72250053176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408823828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3408823828
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1169344719
Short name T472
Test name
Test status
Simulation time 78157082 ps
CPU time 0.62 seconds
Started Jul 25 06:18:02 PM PDT 24
Finished Jul 25 06:18:03 PM PDT 24
Peak memory 196400 kb
Host smart-05279d79-6f26-42bf-a6a6-725849a651eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169344719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1169344719
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1427703707
Short name T17
Test name
Test status
Simulation time 3522854963 ps
CPU time 54.16 seconds
Started Jul 25 06:17:55 PM PDT 24
Finished Jul 25 06:18:49 PM PDT 24
Peak memory 199748 kb
Host smart-6806636b-3846-456c-ab43-83806e4d512d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427703707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1427703707
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1527306265
Short name T199
Test name
Test status
Simulation time 13404501260 ps
CPU time 57.08 seconds
Started Jul 25 06:17:54 PM PDT 24
Finished Jul 25 06:18:51 PM PDT 24
Peak memory 199752 kb
Host smart-05acf3ec-fca2-4484-83bc-8a3cbacbdb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527306265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1527306265
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.88702740
Short name T528
Test name
Test status
Simulation time 563725118 ps
CPU time 142.12 seconds
Started Jul 25 06:17:57 PM PDT 24
Finished Jul 25 06:20:19 PM PDT 24
Peak memory 595800 kb
Host smart-7b792912-ed55-4275-869a-fd825bae0138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88702740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.88702740
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2533277574
Short name T518
Test name
Test status
Simulation time 20202411320 ps
CPU time 144.2 seconds
Started Jul 25 06:17:56 PM PDT 24
Finished Jul 25 06:20:20 PM PDT 24
Peak memory 199776 kb
Host smart-1a13c598-0e67-455f-893c-21f67f3e57b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533277574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2533277574
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.603049180
Short name T132
Test name
Test status
Simulation time 1251726238 ps
CPU time 72.51 seconds
Started Jul 25 06:17:54 PM PDT 24
Finished Jul 25 06:19:07 PM PDT 24
Peak memory 199704 kb
Host smart-42ab9f3a-63ef-4c7b-a81c-3a2b463f7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603049180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.603049180
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2763040718
Short name T435
Test name
Test status
Simulation time 330037240 ps
CPU time 8.02 seconds
Started Jul 25 06:17:51 PM PDT 24
Finished Jul 25 06:18:00 PM PDT 24
Peak memory 199748 kb
Host smart-042ea4c4-1e09-4ecb-aee8-c40f09c298b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763040718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2763040718
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2041232189
Short name T66
Test name
Test status
Simulation time 141038485634 ps
CPU time 986.44 seconds
Started Jul 25 06:17:59 PM PDT 24
Finished Jul 25 06:34:26 PM PDT 24
Peak memory 482244 kb
Host smart-db9092c4-3e23-45cb-8eaf-92bc7ce4b717
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041232189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2041232189
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.9974179
Short name T302
Test name
Test status
Simulation time 825490861 ps
CPU time 49.41 seconds
Started Jul 25 06:18:00 PM PDT 24
Finished Jul 25 06:18:50 PM PDT 24
Peak memory 199700 kb
Host smart-4ea063d0-0d41-4ff1-9864-f5f10b11bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9974179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.9974179
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1427136984
Short name T442
Test name
Test status
Simulation time 25001895 ps
CPU time 0.6 seconds
Started Jul 25 06:18:06 PM PDT 24
Finished Jul 25 06:18:07 PM PDT 24
Peak memory 196264 kb
Host smart-4edfaa32-0dca-4581-b61f-194f74bc56a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427136984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1427136984
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3474819401
Short name T280
Test name
Test status
Simulation time 2491995794 ps
CPU time 37.89 seconds
Started Jul 25 06:18:04 PM PDT 24
Finished Jul 25 06:18:42 PM PDT 24
Peak memory 199828 kb
Host smart-36953f40-2047-4358-ac83-4d710be7c2c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474819401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3474819401
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.508326399
Short name T155
Test name
Test status
Simulation time 2931467934 ps
CPU time 39.45 seconds
Started Jul 25 06:18:04 PM PDT 24
Finished Jul 25 06:18:44 PM PDT 24
Peak memory 199800 kb
Host smart-1ae48b79-c173-4dee-b8f7-7244c538f260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508326399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.508326399
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3968329289
Short name T319
Test name
Test status
Simulation time 3093031618 ps
CPU time 640.04 seconds
Started Jul 25 06:18:03 PM PDT 24
Finished Jul 25 06:28:43 PM PDT 24
Peak memory 682024 kb
Host smart-c7064956-d9a3-4605-8082-9c6f6e55be97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968329289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3968329289
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2698583
Short name T529
Test name
Test status
Simulation time 4071006663 ps
CPU time 73.51 seconds
Started Jul 25 06:18:03 PM PDT 24
Finished Jul 25 06:19:17 PM PDT 24
Peak memory 199744 kb
Host smart-1146657f-eec3-47ae-a161-05e28cc18ece
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2698583
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1481258953
Short name T164
Test name
Test status
Simulation time 16699810494 ps
CPU time 145.58 seconds
Started Jul 25 06:18:00 PM PDT 24
Finished Jul 25 06:20:25 PM PDT 24
Peak memory 199852 kb
Host smart-d4cf1609-352d-4920-8eb3-9cf3a2e059fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481258953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1481258953
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.4085217417
Short name T173
Test name
Test status
Simulation time 571617397 ps
CPU time 8.18 seconds
Started Jul 25 06:18:00 PM PDT 24
Finished Jul 25 06:18:09 PM PDT 24
Peak memory 199696 kb
Host smart-20294348-bb50-4c13-84ab-310fa7557281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085217417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4085217417
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1025797607
Short name T11
Test name
Test status
Simulation time 75790481158 ps
CPU time 1942.92 seconds
Started Jul 25 06:18:02 PM PDT 24
Finished Jul 25 06:50:25 PM PDT 24
Peak memory 712712 kb
Host smart-e582a7d2-9d9b-443c-b4e8-9636401d0b96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025797607 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1025797607
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3372948866
Short name T105
Test name
Test status
Simulation time 3088591095 ps
CPU time 84.28 seconds
Started Jul 25 06:18:00 PM PDT 24
Finished Jul 25 06:19:24 PM PDT 24
Peak memory 199820 kb
Host smart-1ffc927f-2a91-4eb2-bb16-67f41cdc9da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372948866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3372948866
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3307533996
Short name T258
Test name
Test status
Simulation time 20593640 ps
CPU time 0.61 seconds
Started Jul 25 06:14:37 PM PDT 24
Finished Jul 25 06:14:38 PM PDT 24
Peak memory 196444 kb
Host smart-77fdc5ca-8e08-4fac-8c69-a4821fce3678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307533996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3307533996
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1686953701
Short name T237
Test name
Test status
Simulation time 630610560 ps
CPU time 18.09 seconds
Started Jul 25 06:14:22 PM PDT 24
Finished Jul 25 06:14:41 PM PDT 24
Peak memory 199696 kb
Host smart-af5dd22e-b71f-4ad2-a912-b97c7e1becb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686953701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1686953701
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1897865062
Short name T291
Test name
Test status
Simulation time 5617891545 ps
CPU time 25.7 seconds
Started Jul 25 06:14:24 PM PDT 24
Finished Jul 25 06:14:50 PM PDT 24
Peak memory 199748 kb
Host smart-6e92d1fb-966e-4481-8df0-1793e657cfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897865062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1897865062
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.995491861
Short name T238
Test name
Test status
Simulation time 3006681383 ps
CPU time 602.5 seconds
Started Jul 25 06:14:22 PM PDT 24
Finished Jul 25 06:24:25 PM PDT 24
Peak memory 693856 kb
Host smart-8b028e55-29a8-4d70-a647-853c7e8a079c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995491861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.995491861
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2318480270
Short name T308
Test name
Test status
Simulation time 176372810582 ps
CPU time 141.43 seconds
Started Jul 25 06:14:32 PM PDT 24
Finished Jul 25 06:16:53 PM PDT 24
Peak memory 199732 kb
Host smart-accffb77-505d-427e-8ae4-5ba5fd1345e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318480270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2318480270
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2424457298
Short name T272
Test name
Test status
Simulation time 35614538708 ps
CPU time 107.96 seconds
Started Jul 25 06:14:23 PM PDT 24
Finished Jul 25 06:16:11 PM PDT 24
Peak memory 199772 kb
Host smart-cd39cda8-a984-41e9-9a82-646671d1736b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424457298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2424457298
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.78230492
Short name T40
Test name
Test status
Simulation time 149718579 ps
CPU time 0.96 seconds
Started Jul 25 06:14:38 PM PDT 24
Finished Jul 25 06:14:39 PM PDT 24
Peak memory 219344 kb
Host smart-d48694a7-0d56-4d8d-8112-1903e32dd2fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78230492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.78230492
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.3858884872
Short name T323
Test name
Test status
Simulation time 496172788 ps
CPU time 7.38 seconds
Started Jul 25 06:14:22 PM PDT 24
Finished Jul 25 06:14:30 PM PDT 24
Peak memory 199716 kb
Host smart-2aea4ecc-1d4b-40ac-91a7-aafc8ea17633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858884872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3858884872
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2076040410
Short name T349
Test name
Test status
Simulation time 459960142364 ps
CPU time 3291.99 seconds
Started Jul 25 06:14:33 PM PDT 24
Finished Jul 25 07:09:25 PM PDT 24
Peak memory 813504 kb
Host smart-38fe194c-32bb-43bd-82bd-44d3964f2748
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076040410 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2076040410
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1317914010
Short name T12
Test name
Test status
Simulation time 74357292949 ps
CPU time 1506.55 seconds
Started Jul 25 06:14:31 PM PDT 24
Finished Jul 25 06:39:38 PM PDT 24
Peak memory 696996 kb
Host smart-88d33697-efa1-44b4-9910-dc814152118d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317914010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1317914010
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.4075017165
Short name T400
Test name
Test status
Simulation time 1579349581 ps
CPU time 63.47 seconds
Started Jul 25 06:14:29 PM PDT 24
Finished Jul 25 06:15:33 PM PDT 24
Peak memory 199764 kb
Host smart-660a011f-fd64-4aab-882d-f4e196f3ecc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4075017165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.4075017165
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2151552288
Short name T388
Test name
Test status
Simulation time 4704350510 ps
CPU time 99.74 seconds
Started Jul 25 06:14:33 PM PDT 24
Finished Jul 25 06:16:13 PM PDT 24
Peak memory 199776 kb
Host smart-b859f05c-a722-4d17-943a-b5a38e5d9772
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2151552288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2151552288
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2227646294
Short name T360
Test name
Test status
Simulation time 16707849748 ps
CPU time 113.17 seconds
Started Jul 25 06:14:30 PM PDT 24
Finished Jul 25 06:16:23 PM PDT 24
Peak memory 199760 kb
Host smart-ea176b89-ffda-4725-9b90-261fc6f8ff56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2227646294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2227646294
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1029099675
Short name T478
Test name
Test status
Simulation time 47330833222 ps
CPU time 552.51 seconds
Started Jul 25 06:14:38 PM PDT 24
Finished Jul 25 06:23:51 PM PDT 24
Peak memory 199704 kb
Host smart-24cb6dab-23a7-4d2e-b02b-476c9439aece
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1029099675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1029099675
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.50406391
Short name T156
Test name
Test status
Simulation time 39548922311 ps
CPU time 2204.75 seconds
Started Jul 25 06:14:32 PM PDT 24
Finished Jul 25 06:51:17 PM PDT 24
Peak memory 214680 kb
Host smart-74f5942a-af19-4356-84e0-23dd30df61e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=50406391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.50406391
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.734064155
Short name T116
Test name
Test status
Simulation time 351959450688 ps
CPU time 2394.99 seconds
Started Jul 25 06:14:30 PM PDT 24
Finished Jul 25 06:54:26 PM PDT 24
Peak memory 216232 kb
Host smart-cf869899-6ca9-4559-b99e-57e19bd4f16f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=734064155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.734064155
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.510364372
Short name T225
Test name
Test status
Simulation time 2887050792 ps
CPU time 36.16 seconds
Started Jul 25 06:14:32 PM PDT 24
Finished Jul 25 06:15:08 PM PDT 24
Peak memory 199764 kb
Host smart-54ad1bda-c88d-4b44-8d01-8fd6f24bb10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510364372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.510364372
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3898919839
Short name T39
Test name
Test status
Simulation time 48068544 ps
CPU time 0.57 seconds
Started Jul 25 06:18:17 PM PDT 24
Finished Jul 25 06:18:17 PM PDT 24
Peak memory 195288 kb
Host smart-2b322df9-6a04-45f6-8292-3a00db1d2416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898919839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3898919839
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1347512567
Short name T28
Test name
Test status
Simulation time 7892598579 ps
CPU time 115.77 seconds
Started Jul 25 06:18:11 PM PDT 24
Finished Jul 25 06:20:07 PM PDT 24
Peak memory 199756 kb
Host smart-949a0800-ef0e-4c36-aba1-96c68ebbc3ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347512567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1347512567
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2918076218
Short name T383
Test name
Test status
Simulation time 1567442759 ps
CPU time 20.39 seconds
Started Jul 25 06:18:14 PM PDT 24
Finished Jul 25 06:18:34 PM PDT 24
Peak memory 199732 kb
Host smart-af4ac379-ffa3-46ff-8b06-6356194df268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918076218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2918076218
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1050004244
Short name T142
Test name
Test status
Simulation time 3229114559 ps
CPU time 645.5 seconds
Started Jul 25 06:18:13 PM PDT 24
Finished Jul 25 06:28:59 PM PDT 24
Peak memory 677108 kb
Host smart-0b1a0bdf-0afe-4264-999d-30bf3feb281d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050004244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1050004244
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4221182036
Short name T125
Test name
Test status
Simulation time 4902998106 ps
CPU time 88.36 seconds
Started Jul 25 06:18:11 PM PDT 24
Finished Jul 25 06:19:39 PM PDT 24
Peak memory 199868 kb
Host smart-af4f5de2-7395-47d8-9099-bc03c86172da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221182036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4221182036
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.577104639
Short name T340
Test name
Test status
Simulation time 53604626072 ps
CPU time 85.98 seconds
Started Jul 25 06:18:13 PM PDT 24
Finished Jul 25 06:19:40 PM PDT 24
Peak memory 199784 kb
Host smart-856c544b-a54b-4b5c-888b-533513f4650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577104639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.577104639
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2290569446
Short name T161
Test name
Test status
Simulation time 568342851 ps
CPU time 12.91 seconds
Started Jul 25 06:18:11 PM PDT 24
Finished Jul 25 06:18:24 PM PDT 24
Peak memory 199720 kb
Host smart-69806a47-f93d-400c-af24-1659b50dc83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290569446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2290569446
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3243795541
Short name T386
Test name
Test status
Simulation time 137780821770 ps
CPU time 2901.9 seconds
Started Jul 25 06:18:15 PM PDT 24
Finished Jul 25 07:06:37 PM PDT 24
Peak memory 794516 kb
Host smart-b2ef4af4-3711-48a9-8247-8bbfdcce0bc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243795541 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3243795541
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1096810855
Short name T463
Test name
Test status
Simulation time 653194998 ps
CPU time 14.71 seconds
Started Jul 25 06:18:11 PM PDT 24
Finished Jul 25 06:18:26 PM PDT 24
Peak memory 199716 kb
Host smart-20d8300a-161f-48ba-bc66-9280f26b1875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096810855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1096810855
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3357749953
Short name T446
Test name
Test status
Simulation time 49034489 ps
CPU time 0.6 seconds
Started Jul 25 06:18:24 PM PDT 24
Finished Jul 25 06:18:24 PM PDT 24
Peak memory 195720 kb
Host smart-87737f7d-7fe2-41a1-b3d7-765386e35d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357749953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3357749953
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.965991772
Short name T524
Test name
Test status
Simulation time 1395903687 ps
CPU time 77.97 seconds
Started Jul 25 06:18:14 PM PDT 24
Finished Jul 25 06:19:32 PM PDT 24
Peak memory 199716 kb
Host smart-c80583bb-12a7-4076-b0c4-bac0fa74e860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965991772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.965991772
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1788177077
Short name T23
Test name
Test status
Simulation time 9187184389 ps
CPU time 64.71 seconds
Started Jul 25 06:18:11 PM PDT 24
Finished Jul 25 06:19:16 PM PDT 24
Peak memory 199880 kb
Host smart-3d0eb909-67a1-4f89-a09d-6c60a839c487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788177077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1788177077
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2724185458
Short name T209
Test name
Test status
Simulation time 44500819629 ps
CPU time 1210.59 seconds
Started Jul 25 06:18:13 PM PDT 24
Finished Jul 25 06:38:24 PM PDT 24
Peak memory 690728 kb
Host smart-bf961614-3265-41a4-8a92-9c72d6b812f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724185458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2724185458
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.709105568
Short name T496
Test name
Test status
Simulation time 49800640323 ps
CPU time 207.74 seconds
Started Jul 25 06:18:14 PM PDT 24
Finished Jul 25 06:21:42 PM PDT 24
Peak memory 199840 kb
Host smart-00cfef7d-4375-4cd1-91d0-b81156e97839
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709105568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.709105568
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1384236102
Short name T148
Test name
Test status
Simulation time 989061960 ps
CPU time 53.6 seconds
Started Jul 25 06:18:12 PM PDT 24
Finished Jul 25 06:19:06 PM PDT 24
Peak memory 199704 kb
Host smart-39d5f638-4cd5-48af-9bd6-6170893bab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384236102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1384236102
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3554774670
Short name T190
Test name
Test status
Simulation time 161081499 ps
CPU time 7.22 seconds
Started Jul 25 06:18:13 PM PDT 24
Finished Jul 25 06:18:20 PM PDT 24
Peak memory 199768 kb
Host smart-155e1050-2d5b-4068-8de7-61b481104ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554774670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3554774670
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.444496476
Short name T527
Test name
Test status
Simulation time 253976420295 ps
CPU time 3056.56 seconds
Started Jul 25 06:18:21 PM PDT 24
Finished Jul 25 07:09:18 PM PDT 24
Peak memory 800768 kb
Host smart-2bbb4dce-4b06-4a99-88e5-3e996190cf9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444496476 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.444496476
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2931980857
Short name T351
Test name
Test status
Simulation time 4062510877 ps
CPU time 25.01 seconds
Started Jul 25 06:18:23 PM PDT 24
Finished Jul 25 06:18:48 PM PDT 24
Peak memory 199844 kb
Host smart-51be6e36-47f5-41a4-8319-fbc18eac9b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931980857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2931980857
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3891106517
Short name T530
Test name
Test status
Simulation time 33360648 ps
CPU time 0.57 seconds
Started Jul 25 06:18:21 PM PDT 24
Finished Jul 25 06:18:22 PM PDT 24
Peak memory 194656 kb
Host smart-561ca159-768f-45c8-bafe-b74558167913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891106517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3891106517
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1529464606
Short name T150
Test name
Test status
Simulation time 5916597428 ps
CPU time 79.1 seconds
Started Jul 25 06:18:18 PM PDT 24
Finished Jul 25 06:19:37 PM PDT 24
Peak memory 199760 kb
Host smart-fed81d09-37c1-4efb-87b6-a7571863441e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529464606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1529464606
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3863934437
Short name T394
Test name
Test status
Simulation time 184632258 ps
CPU time 9.53 seconds
Started Jul 25 06:18:23 PM PDT 24
Finished Jul 25 06:18:33 PM PDT 24
Peak memory 199720 kb
Host smart-240f18ad-7db3-4304-8db5-697fdff606c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863934437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3863934437
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3414963857
Short name T221
Test name
Test status
Simulation time 24203569452 ps
CPU time 1057.39 seconds
Started Jul 25 06:18:22 PM PDT 24
Finished Jul 25 06:36:00 PM PDT 24
Peak memory 702552 kb
Host smart-999a0245-8591-4e80-ad11-a3ac50e06311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414963857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3414963857
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1536024460
Short name T6
Test name
Test status
Simulation time 21476162665 ps
CPU time 38.54 seconds
Started Jul 25 06:18:22 PM PDT 24
Finished Jul 25 06:19:00 PM PDT 24
Peak memory 199836 kb
Host smart-3f2bf8e8-a425-4eb8-ba06-e78930a5ceba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536024460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1536024460
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2572046949
Short name T491
Test name
Test status
Simulation time 27129605164 ps
CPU time 188.87 seconds
Started Jul 25 06:18:20 PM PDT 24
Finished Jul 25 06:21:29 PM PDT 24
Peak memory 199756 kb
Host smart-cc247e14-0fe3-4441-a25c-4a9f674e2b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572046949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2572046949
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.828974364
Short name T192
Test name
Test status
Simulation time 284370282 ps
CPU time 9.26 seconds
Started Jul 25 06:18:22 PM PDT 24
Finished Jul 25 06:18:32 PM PDT 24
Peak memory 199696 kb
Host smart-046b8d83-05b7-4438-999d-be0ea6abf661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828974364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.828974364
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.954486748
Short name T354
Test name
Test status
Simulation time 234410875061 ps
CPU time 1447.46 seconds
Started Jul 25 06:18:21 PM PDT 24
Finished Jul 25 06:42:29 PM PDT 24
Peak memory 674108 kb
Host smart-e20b2b1e-699a-4d12-8537-a63354551172
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954486748 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.954486748
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2104692208
Short name T332
Test name
Test status
Simulation time 9649583509 ps
CPU time 33.52 seconds
Started Jul 25 06:18:20 PM PDT 24
Finished Jul 25 06:18:54 PM PDT 24
Peak memory 199840 kb
Host smart-c324696b-00ad-4006-a30a-e176eeb1f0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104692208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2104692208
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3294486170
Short name T243
Test name
Test status
Simulation time 13055932 ps
CPU time 0.59 seconds
Started Jul 25 06:18:31 PM PDT 24
Finished Jul 25 06:18:32 PM PDT 24
Peak memory 194696 kb
Host smart-d35e32bc-753c-4079-be0c-6bdab4ab2c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294486170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3294486170
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3209739847
Short name T33
Test name
Test status
Simulation time 718454734 ps
CPU time 11.8 seconds
Started Jul 25 06:18:30 PM PDT 24
Finished Jul 25 06:18:42 PM PDT 24
Peak memory 199760 kb
Host smart-3666571c-77cd-4231-ad4c-e6ea640cddce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209739847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3209739847
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3608659717
Short name T152
Test name
Test status
Simulation time 2554988249 ps
CPU time 23.28 seconds
Started Jul 25 06:18:29 PM PDT 24
Finished Jul 25 06:18:53 PM PDT 24
Peak memory 199792 kb
Host smart-e889fadd-16b3-44af-9cc3-af4b02a138f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608659717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3608659717
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2424100138
Short name T134
Test name
Test status
Simulation time 6592922634 ps
CPU time 575.36 seconds
Started Jul 25 06:18:28 PM PDT 24
Finished Jul 25 06:28:04 PM PDT 24
Peak memory 657328 kb
Host smart-a3f911cd-fbb6-488d-bbde-71158ff62174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424100138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2424100138
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4276893469
Short name T423
Test name
Test status
Simulation time 23258739584 ps
CPU time 70.15 seconds
Started Jul 25 06:18:29 PM PDT 24
Finished Jul 25 06:19:40 PM PDT 24
Peak memory 199728 kb
Host smart-53383dd6-9f47-4bb3-86df-7a5c75f35725
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276893469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4276893469
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.4098746468
Short name T485
Test name
Test status
Simulation time 21299348815 ps
CPU time 144.81 seconds
Started Jul 25 06:18:22 PM PDT 24
Finished Jul 25 06:20:47 PM PDT 24
Peak memory 199820 kb
Host smart-7716832e-b4ab-43f8-b294-932a245cb03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098746468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.4098746468
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2323120038
Short name T146
Test name
Test status
Simulation time 109152573 ps
CPU time 1.74 seconds
Started Jul 25 06:18:19 PM PDT 24
Finished Jul 25 06:18:21 PM PDT 24
Peak memory 199728 kb
Host smart-7201efad-4bfa-46f6-9ecb-d5627934f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323120038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2323120038
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3389627330
Short name T361
Test name
Test status
Simulation time 14725690066 ps
CPU time 65.53 seconds
Started Jul 25 06:18:31 PM PDT 24
Finished Jul 25 06:19:37 PM PDT 24
Peak memory 199808 kb
Host smart-e747a577-b796-49ae-a154-5060f5454c9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389627330 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3389627330
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2105638692
Short name T69
Test name
Test status
Simulation time 15620887325 ps
CPU time 35.06 seconds
Started Jul 25 06:18:29 PM PDT 24
Finished Jul 25 06:19:04 PM PDT 24
Peak memory 199784 kb
Host smart-8deca48f-b3cf-45da-9ee1-ca1731bc4940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105638692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2105638692
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.367107618
Short name T483
Test name
Test status
Simulation time 38577257 ps
CPU time 0.61 seconds
Started Jul 25 06:18:28 PM PDT 24
Finished Jul 25 06:18:29 PM PDT 24
Peak memory 196400 kb
Host smart-f6cc7c64-b421-4b7d-bccb-796c99f69fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367107618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.367107618
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.109280873
Short name T10
Test name
Test status
Simulation time 1132037867 ps
CPU time 59.95 seconds
Started Jul 25 06:18:26 PM PDT 24
Finished Jul 25 06:19:26 PM PDT 24
Peak memory 199724 kb
Host smart-df3ec150-cb78-4d5d-b83e-a065edeb1666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109280873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.109280873
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3325882892
Short name T230
Test name
Test status
Simulation time 1537199666 ps
CPU time 27.83 seconds
Started Jul 25 06:18:31 PM PDT 24
Finished Jul 25 06:18:59 PM PDT 24
Peak memory 199716 kb
Host smart-d6ea8cd7-d496-4b1e-87f6-61156c36db56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325882892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3325882892
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1736125910
Short name T468
Test name
Test status
Simulation time 894628372 ps
CPU time 188.55 seconds
Started Jul 25 06:18:30 PM PDT 24
Finished Jul 25 06:21:39 PM PDT 24
Peak memory 613708 kb
Host smart-2e56f9f0-12d5-4549-a7a3-5c5c13f57604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736125910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1736125910
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3703325820
Short name T292
Test name
Test status
Simulation time 19125811265 ps
CPU time 93.2 seconds
Started Jul 25 06:18:31 PM PDT 24
Finished Jul 25 06:20:04 PM PDT 24
Peak memory 199728 kb
Host smart-38e1d1aa-1840-4a63-8020-344b243c109a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703325820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3703325820
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1444680587
Short name T124
Test name
Test status
Simulation time 63903650433 ps
CPU time 112.22 seconds
Started Jul 25 06:18:30 PM PDT 24
Finished Jul 25 06:20:22 PM PDT 24
Peak memory 199792 kb
Host smart-98f18cbd-b211-42ad-b1ef-bc2d82892dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444680587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1444680587
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.586194036
Short name T75
Test name
Test status
Simulation time 3629704661 ps
CPU time 9.19 seconds
Started Jul 25 06:18:30 PM PDT 24
Finished Jul 25 06:18:39 PM PDT 24
Peak memory 199836 kb
Host smart-1298b12f-59b3-4595-807c-3f9a9b7d20a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586194036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.586194036
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2673354874
Short name T147
Test name
Test status
Simulation time 19049768627 ps
CPU time 138.78 seconds
Started Jul 25 06:18:29 PM PDT 24
Finished Jul 25 06:20:48 PM PDT 24
Peak memory 207972 kb
Host smart-616e80ab-e529-4f86-b039-c9315e93b8f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673354874 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2673354874
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2429828167
Short name T416
Test name
Test status
Simulation time 8498039623 ps
CPU time 28.32 seconds
Started Jul 25 06:18:30 PM PDT 24
Finished Jul 25 06:18:59 PM PDT 24
Peak memory 199844 kb
Host smart-7d1f5135-c92b-4b3f-a189-121e1883861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429828167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2429828167
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3307713087
Short name T297
Test name
Test status
Simulation time 9984276922 ps
CPU time 108.31 seconds
Started Jul 25 06:18:37 PM PDT 24
Finished Jul 25 06:20:25 PM PDT 24
Peak memory 208060 kb
Host smart-babad421-9301-47db-890c-49231a44b622
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307713087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3307713087
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2457843712
Short name T520
Test name
Test status
Simulation time 2358674825 ps
CPU time 44.37 seconds
Started Jul 25 06:18:37 PM PDT 24
Finished Jul 25 06:19:21 PM PDT 24
Peak memory 199780 kb
Host smart-5f2c36bd-3d10-4203-ba01-8a5a8440f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457843712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2457843712
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3997438135
Short name T359
Test name
Test status
Simulation time 5158413598 ps
CPU time 929.92 seconds
Started Jul 25 06:18:39 PM PDT 24
Finished Jul 25 06:34:10 PM PDT 24
Peak memory 684676 kb
Host smart-28b6899c-c10a-4aab-9cd5-c098115b2d74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3997438135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3997438135
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.905571300
Short name T422
Test name
Test status
Simulation time 9026200616 ps
CPU time 169.67 seconds
Started Jul 25 06:18:37 PM PDT 24
Finished Jul 25 06:21:27 PM PDT 24
Peak memory 199788 kb
Host smart-7c7fe7e2-bc2a-4a51-8c57-8fdf534a5644
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905571300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.905571300
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.274315778
Short name T338
Test name
Test status
Simulation time 2236702128 ps
CPU time 41.24 seconds
Started Jul 25 06:18:36 PM PDT 24
Finished Jul 25 06:19:17 PM PDT 24
Peak memory 199792 kb
Host smart-ede2939b-43cb-423d-9d09-7c751828a006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274315778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.274315778
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.707718826
Short name T120
Test name
Test status
Simulation time 6407663184 ps
CPU time 17.01 seconds
Started Jul 25 06:18:35 PM PDT 24
Finished Jul 25 06:18:52 PM PDT 24
Peak memory 199832 kb
Host smart-4340cd58-ca3a-463e-8a6b-d3c3b725b35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707718826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.707718826
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.439048770
Short name T347
Test name
Test status
Simulation time 109209154944 ps
CPU time 5016.56 seconds
Started Jul 25 06:18:39 PM PDT 24
Finished Jul 25 07:42:17 PM PDT 24
Peak memory 844772 kb
Host smart-28437a2d-710a-4e40-b906-0c204aa8f816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439048770 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.439048770
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3992038824
Short name T380
Test name
Test status
Simulation time 492283004 ps
CPU time 7.57 seconds
Started Jul 25 06:18:35 PM PDT 24
Finished Jul 25 06:18:43 PM PDT 24
Peak memory 199772 kb
Host smart-b33ce101-8c38-4b3c-9322-ddb10c1ff61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992038824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3992038824
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1499695183
Short name T427
Test name
Test status
Simulation time 40587567 ps
CPU time 0.59 seconds
Started Jul 25 06:18:47 PM PDT 24
Finished Jul 25 06:18:47 PM PDT 24
Peak memory 195712 kb
Host smart-101900cd-b14d-4210-9e36-bb5912873bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499695183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1499695183
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2662645404
Short name T206
Test name
Test status
Simulation time 3613551948 ps
CPU time 51.07 seconds
Started Jul 25 06:18:36 PM PDT 24
Finished Jul 25 06:19:27 PM PDT 24
Peak memory 199816 kb
Host smart-fce59a93-6fdb-479a-a90d-b10ed801abb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662645404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2662645404
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2370858560
Short name T471
Test name
Test status
Simulation time 1274600256 ps
CPU time 8.4 seconds
Started Jul 25 06:18:45 PM PDT 24
Finished Jul 25 06:18:53 PM PDT 24
Peak memory 199720 kb
Host smart-806001ef-31a7-47e7-950f-7f57a06d97f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370858560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2370858560
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.136490959
Short name T443
Test name
Test status
Simulation time 15764229627 ps
CPU time 192.59 seconds
Started Jul 25 06:18:46 PM PDT 24
Finished Jul 25 06:21:59 PM PDT 24
Peak memory 577964 kb
Host smart-289ba2ab-d113-43f6-9f21-b5b7ec61f98a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136490959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.136490959
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.973511308
Short name T495
Test name
Test status
Simulation time 5323034155 ps
CPU time 218.62 seconds
Started Jul 25 06:18:41 PM PDT 24
Finished Jul 25 06:22:19 PM PDT 24
Peak memory 199764 kb
Host smart-39eae262-bb8c-40f6-9f85-07380472965a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973511308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.973511308
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4235416211
Short name T288
Test name
Test status
Simulation time 28236989350 ps
CPU time 154.93 seconds
Started Jul 25 06:18:38 PM PDT 24
Finished Jul 25 06:21:13 PM PDT 24
Peak memory 199764 kb
Host smart-b53823bb-36ed-45f2-85d7-c98f040a3f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235416211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4235416211
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1195917207
Short name T430
Test name
Test status
Simulation time 38321991 ps
CPU time 1.85 seconds
Started Jul 25 06:18:38 PM PDT 24
Finished Jul 25 06:18:40 PM PDT 24
Peak memory 199736 kb
Host smart-2601c85e-2d6a-4712-881e-108840d81956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195917207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1195917207
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.872963429
Short name T426
Test name
Test status
Simulation time 19633081568 ps
CPU time 1347.56 seconds
Started Jul 25 06:18:46 PM PDT 24
Finished Jul 25 06:41:13 PM PDT 24
Peak memory 523680 kb
Host smart-8bb05fa0-8df4-4495-89ee-5e667ad8e005
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872963429 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.872963429
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2251801121
Short name T512
Test name
Test status
Simulation time 596866513 ps
CPU time 28.42 seconds
Started Jul 25 06:18:43 PM PDT 24
Finished Jul 25 06:19:11 PM PDT 24
Peak memory 199756 kb
Host smart-b03b0833-a8d8-4278-9416-f867eaba0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251801121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2251801121
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2255083860
Short name T493
Test name
Test status
Simulation time 37013394 ps
CPU time 0.55 seconds
Started Jul 25 06:18:56 PM PDT 24
Finished Jul 25 06:18:56 PM PDT 24
Peak memory 194564 kb
Host smart-af4e213e-e6e8-4d49-8edb-76d8e1db2b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255083860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2255083860
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1611603577
Short name T30
Test name
Test status
Simulation time 1675555330 ps
CPU time 51.02 seconds
Started Jul 25 06:18:44 PM PDT 24
Finished Jul 25 06:19:35 PM PDT 24
Peak memory 199716 kb
Host smart-05613e2c-8408-4c24-9d46-64c090cca840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611603577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1611603577
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2419259502
Short name T411
Test name
Test status
Simulation time 55891760 ps
CPU time 2.77 seconds
Started Jul 25 06:18:42 PM PDT 24
Finished Jul 25 06:18:45 PM PDT 24
Peak memory 199716 kb
Host smart-6fbc6e18-fd01-4f2c-b4d4-b337dead3721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419259502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2419259502
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1961425833
Short name T432
Test name
Test status
Simulation time 19497337187 ps
CPU time 219.04 seconds
Started Jul 25 06:18:47 PM PDT 24
Finished Jul 25 06:22:26 PM PDT 24
Peak memory 586292 kb
Host smart-d89afcf2-d87c-4361-ada5-88eb29de02fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961425833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1961425833
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3092542327
Short name T353
Test name
Test status
Simulation time 1982709736 ps
CPU time 118.02 seconds
Started Jul 25 06:18:45 PM PDT 24
Finished Jul 25 06:20:43 PM PDT 24
Peak memory 199696 kb
Host smart-23c021a0-1069-4719-b44e-5824aa597d93
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092542327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3092542327
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.343093549
Short name T409
Test name
Test status
Simulation time 3264333307 ps
CPU time 183.03 seconds
Started Jul 25 06:18:42 PM PDT 24
Finished Jul 25 06:21:46 PM PDT 24
Peak memory 199820 kb
Host smart-07c13bfb-6930-4593-b921-5cf1b55fb0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343093549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.343093549
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3875582605
Short name T131
Test name
Test status
Simulation time 563397604 ps
CPU time 2.68 seconds
Started Jul 25 06:18:44 PM PDT 24
Finished Jul 25 06:18:46 PM PDT 24
Peak memory 199812 kb
Host smart-376a28b5-df73-4b04-bed1-a736f63c8206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875582605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3875582605
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1686228850
Short name T160
Test name
Test status
Simulation time 2804299624 ps
CPU time 68.59 seconds
Started Jul 25 06:18:50 PM PDT 24
Finished Jul 25 06:19:59 PM PDT 24
Peak memory 199696 kb
Host smart-eeee96e6-2dea-4a90-8983-bba09a553e6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686228850 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1686228850
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2545108009
Short name T179
Test name
Test status
Simulation time 6378768256 ps
CPU time 66.84 seconds
Started Jul 25 06:18:45 PM PDT 24
Finished Jul 25 06:19:52 PM PDT 24
Peak memory 199840 kb
Host smart-1cb546e1-658f-4d93-b10a-403e76ef68ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545108009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2545108009
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2338644309
Short name T177
Test name
Test status
Simulation time 45947883 ps
CPU time 0.61 seconds
Started Jul 25 06:18:50 PM PDT 24
Finished Jul 25 06:18:51 PM PDT 24
Peak memory 196420 kb
Host smart-f7a64a9a-9235-4b9f-8081-3cc29c7a64d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338644309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2338644309
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4058199132
Short name T405
Test name
Test status
Simulation time 1879174090 ps
CPU time 26.1 seconds
Started Jul 25 06:18:50 PM PDT 24
Finished Jul 25 06:19:16 PM PDT 24
Peak memory 199764 kb
Host smart-f00bc53e-f2d7-4ec1-ada7-546806b759ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058199132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4058199132
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2971759550
Short name T374
Test name
Test status
Simulation time 4349393451 ps
CPU time 54.33 seconds
Started Jul 25 06:18:54 PM PDT 24
Finished Jul 25 06:19:48 PM PDT 24
Peak memory 199632 kb
Host smart-d0fc4ded-d121-464a-9a4d-098ce697ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971759550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2971759550
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1874790230
Short name T203
Test name
Test status
Simulation time 345827850 ps
CPU time 12.9 seconds
Started Jul 25 06:18:51 PM PDT 24
Finished Jul 25 06:19:04 PM PDT 24
Peak memory 215556 kb
Host smart-490001d6-af3f-4c84-ae57-3bcc7bdfac5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874790230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1874790230
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2945630942
Short name T408
Test name
Test status
Simulation time 2203267284 ps
CPU time 122.35 seconds
Started Jul 25 06:18:51 PM PDT 24
Finished Jul 25 06:20:53 PM PDT 24
Peak memory 199728 kb
Host smart-33d87458-055a-49fe-99dc-59d50c52ce00
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945630942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2945630942
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2609199550
Short name T326
Test name
Test status
Simulation time 575910592 ps
CPU time 9.03 seconds
Started Jul 25 06:18:50 PM PDT 24
Finished Jul 25 06:18:59 PM PDT 24
Peak memory 199600 kb
Host smart-bcaa54cf-a31d-48a3-88ff-52e5e3398f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609199550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2609199550
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1168810432
Short name T180
Test name
Test status
Simulation time 214952389 ps
CPU time 8.8 seconds
Started Jul 25 06:18:51 PM PDT 24
Finished Jul 25 06:19:00 PM PDT 24
Peak memory 199780 kb
Host smart-a3406f8d-e48f-4954-846b-290522a77e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168810432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1168810432
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1347307367
Short name T429
Test name
Test status
Simulation time 2071227578 ps
CPU time 26.41 seconds
Started Jul 25 06:18:50 PM PDT 24
Finished Jul 25 06:19:17 PM PDT 24
Peak memory 199736 kb
Host smart-a280774d-1ff5-4e6d-ada6-bb9fd2d6127d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347307367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1347307367
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2742969423
Short name T317
Test name
Test status
Simulation time 7885890687 ps
CPU time 112.27 seconds
Started Jul 25 06:18:47 PM PDT 24
Finished Jul 25 06:20:40 PM PDT 24
Peak memory 199836 kb
Host smart-506407a1-20b7-496d-ae55-ffc4a8c1fb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742969423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2742969423
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.968298376
Short name T144
Test name
Test status
Simulation time 11468554 ps
CPU time 0.56 seconds
Started Jul 25 06:18:57 PM PDT 24
Finished Jul 25 06:18:57 PM PDT 24
Peak memory 194708 kb
Host smart-16291ec6-935e-4c75-acdc-9ef81aeed99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968298376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.968298376
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2239345824
Short name T34
Test name
Test status
Simulation time 394113175 ps
CPU time 22.09 seconds
Started Jul 25 06:18:55 PM PDT 24
Finished Jul 25 06:19:17 PM PDT 24
Peak memory 199704 kb
Host smart-a0e88149-0f34-4fe9-a618-e6a7aa821a26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239345824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2239345824
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2642717682
Short name T151
Test name
Test status
Simulation time 2584454144 ps
CPU time 45.09 seconds
Started Jul 25 06:18:58 PM PDT 24
Finished Jul 25 06:19:44 PM PDT 24
Peak memory 199792 kb
Host smart-079c170d-17e4-4945-8e44-6bf02d4b5588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642717682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2642717682
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2546028467
Short name T123
Test name
Test status
Simulation time 2891443244 ps
CPU time 488.56 seconds
Started Jul 25 06:18:58 PM PDT 24
Finished Jul 25 06:27:06 PM PDT 24
Peak memory 687872 kb
Host smart-a7a1fb2b-d722-46a8-8a62-344e28091dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546028467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2546028467
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.73920306
Short name T15
Test name
Test status
Simulation time 4289524465 ps
CPU time 225.63 seconds
Started Jul 25 06:18:58 PM PDT 24
Finished Jul 25 06:22:44 PM PDT 24
Peak memory 199824 kb
Host smart-234d6676-b156-4d34-9bf6-d5d03b7dfce4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73920306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.73920306
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2494556515
Short name T410
Test name
Test status
Simulation time 72273099858 ps
CPU time 238.54 seconds
Started Jul 25 06:18:59 PM PDT 24
Finished Jul 25 06:22:58 PM PDT 24
Peak memory 207976 kb
Host smart-18694126-68af-4a47-bdc5-516cbd37b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494556515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2494556515
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2578123870
Short name T255
Test name
Test status
Simulation time 133542792 ps
CPU time 5.49 seconds
Started Jul 25 06:18:56 PM PDT 24
Finished Jul 25 06:19:02 PM PDT 24
Peak memory 199728 kb
Host smart-591a7e98-bc78-47ae-ae5b-a832df5822e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578123870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2578123870
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.185333429
Short name T63
Test name
Test status
Simulation time 379351810186 ps
CPU time 1128.59 seconds
Started Jul 25 06:19:00 PM PDT 24
Finished Jul 25 06:37:49 PM PDT 24
Peak memory 639448 kb
Host smart-c1917a62-2b9c-4356-b490-47ff0775da04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185333429 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.185333429
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1254907156
Short name T401
Test name
Test status
Simulation time 3277964206 ps
CPU time 9.39 seconds
Started Jul 25 06:19:02 PM PDT 24
Finished Jul 25 06:19:12 PM PDT 24
Peak memory 199640 kb
Host smart-24768300-38e5-4cb5-a31b-2986c4260178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254907156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1254907156
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3761298727
Short name T252
Test name
Test status
Simulation time 13531113 ps
CPU time 0.6 seconds
Started Jul 25 06:14:34 PM PDT 24
Finished Jul 25 06:14:35 PM PDT 24
Peak memory 195668 kb
Host smart-84e42910-f6c0-4af3-93c1-c711197403d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761298727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3761298727
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2640362204
Short name T139
Test name
Test status
Simulation time 658191940 ps
CPU time 36.86 seconds
Started Jul 25 06:14:37 PM PDT 24
Finished Jul 25 06:15:14 PM PDT 24
Peak memory 199756 kb
Host smart-a9abda27-2e9e-43b3-bd5b-42cf059eecb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640362204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2640362204
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.99133357
Short name T486
Test name
Test status
Simulation time 1108331092 ps
CPU time 62.26 seconds
Started Jul 25 06:14:36 PM PDT 24
Finished Jul 25 06:15:38 PM PDT 24
Peak memory 199724 kb
Host smart-1853793c-aef3-4acc-baef-d2b30666d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99133357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.99133357
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3307111808
Short name T344
Test name
Test status
Simulation time 6833255575 ps
CPU time 1428.08 seconds
Started Jul 25 06:14:37 PM PDT 24
Finished Jul 25 06:38:26 PM PDT 24
Peak memory 758244 kb
Host smart-b4119f0d-f0b1-4cd9-b8a9-47018f96fa9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307111808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3307111808
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.4267890522
Short name T127
Test name
Test status
Simulation time 4817946470 ps
CPU time 88.56 seconds
Started Jul 25 06:14:40 PM PDT 24
Finished Jul 25 06:16:08 PM PDT 24
Peak memory 199772 kb
Host smart-862ebc1e-62b8-44e0-b486-47b17b1f80d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267890522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.4267890522
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3501675961
Short name T445
Test name
Test status
Simulation time 8965504769 ps
CPU time 64.65 seconds
Started Jul 25 06:14:39 PM PDT 24
Finished Jul 25 06:15:44 PM PDT 24
Peak memory 199828 kb
Host smart-487d8acf-fc18-421a-b607-45ce91874b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501675961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3501675961
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3451434529
Short name T295
Test name
Test status
Simulation time 205368098 ps
CPU time 3.57 seconds
Started Jul 25 06:14:35 PM PDT 24
Finished Jul 25 06:14:39 PM PDT 24
Peak memory 199688 kb
Host smart-709d8e95-5375-4176-82ab-ce1a462f8185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451434529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3451434529
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1075105664
Short name T248
Test name
Test status
Simulation time 22208017065 ps
CPU time 103.15 seconds
Started Jul 25 06:14:40 PM PDT 24
Finished Jul 25 06:16:23 PM PDT 24
Peak memory 199748 kb
Host smart-1fe4f05f-b5a3-4043-9c75-a6d123eb984d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075105664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1075105664
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.484830813
Short name T59
Test name
Test status
Simulation time 81765487036 ps
CPU time 1465.22 seconds
Started Jul 25 06:14:40 PM PDT 24
Finished Jul 25 06:39:05 PM PDT 24
Peak memory 664812 kb
Host smart-d57ed710-8c27-4216-a571-6faecc28ac8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484830813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.484830813
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.522152293
Short name T204
Test name
Test status
Simulation time 3117889964 ps
CPU time 14.42 seconds
Started Jul 25 06:14:40 PM PDT 24
Finished Jul 25 06:14:54 PM PDT 24
Peak memory 199812 kb
Host smart-7d01d255-1234-487f-a0a5-5c8cd27cdb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522152293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.522152293
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3886032526
Short name T403
Test name
Test status
Simulation time 10864687 ps
CPU time 0.6 seconds
Started Jul 25 06:14:53 PM PDT 24
Finished Jul 25 06:14:53 PM PDT 24
Peak memory 195724 kb
Host smart-182bc338-14fa-4cdf-93f5-652b29b67089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886032526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3886032526
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3531556535
Short name T49
Test name
Test status
Simulation time 6590656092 ps
CPU time 34.94 seconds
Started Jul 25 06:14:43 PM PDT 24
Finished Jul 25 06:15:18 PM PDT 24
Peak memory 199776 kb
Host smart-5d4cae07-b839-454c-8857-bbe5869758b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531556535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3531556535
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1012365197
Short name T198
Test name
Test status
Simulation time 13252343849 ps
CPU time 50.08 seconds
Started Jul 25 06:14:49 PM PDT 24
Finished Jul 25 06:15:39 PM PDT 24
Peak memory 207968 kb
Host smart-af67b28d-ffb0-454c-aec1-a14b9b1f5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012365197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1012365197
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3480167362
Short name T509
Test name
Test status
Simulation time 22524495 ps
CPU time 1.07 seconds
Started Jul 25 06:14:51 PM PDT 24
Finished Jul 25 06:14:52 PM PDT 24
Peak memory 207760 kb
Host smart-2141cb8d-cf3b-4719-8995-0b2b7bdc1719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480167362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3480167362
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.413794014
Short name T487
Test name
Test status
Simulation time 2396029141 ps
CPU time 13.35 seconds
Started Jul 25 06:14:44 PM PDT 24
Finished Jul 25 06:14:57 PM PDT 24
Peak memory 199724 kb
Host smart-20191ce4-2010-434f-92e8-7dd5c51b92ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413794014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.413794014
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2122279077
Short name T166
Test name
Test status
Simulation time 221181842 ps
CPU time 13 seconds
Started Jul 25 06:14:50 PM PDT 24
Finished Jul 25 06:15:03 PM PDT 24
Peak memory 199544 kb
Host smart-e37fc88f-8dfd-4607-b9b5-8df064cb28b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122279077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2122279077
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3786277796
Short name T397
Test name
Test status
Simulation time 209367314 ps
CPU time 8.69 seconds
Started Jul 25 06:14:50 PM PDT 24
Finished Jul 25 06:14:59 PM PDT 24
Peak memory 199588 kb
Host smart-7c66c285-77c3-4bdb-94cb-c6af40c75b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786277796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3786277796
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.504064115
Short name T215
Test name
Test status
Simulation time 25993200433 ps
CPU time 88.37 seconds
Started Jul 25 06:14:44 PM PDT 24
Finished Jul 25 06:16:13 PM PDT 24
Peak memory 199772 kb
Host smart-6cad1a21-47c9-4f53-9f50-c025d920da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504064115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.504064115
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3196779971
Short name T46
Test name
Test status
Simulation time 65255310 ps
CPU time 0.59 seconds
Started Jul 25 06:14:49 PM PDT 24
Finished Jul 25 06:14:49 PM PDT 24
Peak memory 195480 kb
Host smart-c080e0cc-0d62-4294-900f-9b724ceb49fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196779971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3196779971
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1845382395
Short name T286
Test name
Test status
Simulation time 1480649413 ps
CPU time 45.06 seconds
Started Jul 25 06:14:49 PM PDT 24
Finished Jul 25 06:15:34 PM PDT 24
Peak memory 199708 kb
Host smart-43948483-9185-4581-9c49-dbb65055b47e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845382395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1845382395
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3103647438
Short name T507
Test name
Test status
Simulation time 1627481189 ps
CPU time 9.55 seconds
Started Jul 25 06:14:54 PM PDT 24
Finished Jul 25 06:15:03 PM PDT 24
Peak memory 199696 kb
Host smart-dcc737c2-dc47-4f69-9cb4-300371051e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103647438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3103647438
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2664139305
Short name T196
Test name
Test status
Simulation time 2517601819 ps
CPU time 431.88 seconds
Started Jul 25 06:14:50 PM PDT 24
Finished Jul 25 06:22:02 PM PDT 24
Peak memory 603300 kb
Host smart-c849c8db-2f01-4dc3-b198-34dfe396c958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664139305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2664139305
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2016363479
Short name T223
Test name
Test status
Simulation time 3342510487 ps
CPU time 185.72 seconds
Started Jul 25 06:14:52 PM PDT 24
Finished Jul 25 06:17:58 PM PDT 24
Peak memory 199772 kb
Host smart-de62cecf-76ed-42d4-8361-30e6a4b9035c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016363479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2016363479
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4180179886
Short name T261
Test name
Test status
Simulation time 16083679141 ps
CPU time 134.54 seconds
Started Jul 25 06:14:53 PM PDT 24
Finished Jul 25 06:17:07 PM PDT 24
Peak memory 216172 kb
Host smart-425c40b8-66f1-4e98-9f61-f0f420289aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180179886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4180179886
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3768701888
Short name T392
Test name
Test status
Simulation time 149349889 ps
CPU time 6.94 seconds
Started Jul 25 06:14:52 PM PDT 24
Finished Jul 25 06:14:59 PM PDT 24
Peak memory 199716 kb
Host smart-3426411b-eb84-4358-b3c6-a956ad5fff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768701888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3768701888
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1914171670
Short name T505
Test name
Test status
Simulation time 69383737472 ps
CPU time 1148.1 seconds
Started Jul 25 06:14:52 PM PDT 24
Finished Jul 25 06:34:00 PM PDT 24
Peak memory 489064 kb
Host smart-4d0c3777-8bab-4234-a693-6ac519661989
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914171670 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1914171670
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1867901803
Short name T13
Test name
Test status
Simulation time 145253821120 ps
CPU time 810.22 seconds
Started Jul 25 06:14:49 PM PDT 24
Finished Jul 25 06:28:19 PM PDT 24
Peak memory 681832 kb
Host smart-bca3d081-b381-4b90-87a8-49e0fd051780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867901803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1867901803
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2713373250
Short name T460
Test name
Test status
Simulation time 3644577805 ps
CPU time 69.78 seconds
Started Jul 25 06:14:51 PM PDT 24
Finished Jul 25 06:16:01 PM PDT 24
Peak memory 199708 kb
Host smart-a6f13345-3403-4e72-9d8a-e5dc5edd2f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713373250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2713373250
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3529711367
Short name T419
Test name
Test status
Simulation time 13111569 ps
CPU time 0.57 seconds
Started Jul 25 06:15:03 PM PDT 24
Finished Jul 25 06:15:04 PM PDT 24
Peak memory 195336 kb
Host smart-8e7655c0-f46e-4100-8ff8-a43c7bbe540c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529711367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3529711367
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1377251350
Short name T433
Test name
Test status
Simulation time 86945029 ps
CPU time 2.6 seconds
Started Jul 25 06:14:59 PM PDT 24
Finished Jul 25 06:15:02 PM PDT 24
Peak memory 199560 kb
Host smart-d64c28ef-7bc8-4c35-b41b-282fa997bf77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377251350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1377251350
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1150780641
Short name T36
Test name
Test status
Simulation time 6300933611 ps
CPU time 53.56 seconds
Started Jul 25 06:15:02 PM PDT 24
Finished Jul 25 06:15:55 PM PDT 24
Peak memory 199760 kb
Host smart-762b419d-1e2d-42e1-92f2-2af11b1dc8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150780641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1150780641
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4074030624
Short name T301
Test name
Test status
Simulation time 2668987297 ps
CPU time 117.62 seconds
Started Jul 25 06:15:03 PM PDT 24
Finished Jul 25 06:17:00 PM PDT 24
Peak memory 416972 kb
Host smart-9a997e26-c07b-4370-9488-6ce8b375f9d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074030624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4074030624
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3016547408
Short name T158
Test name
Test status
Simulation time 3410285506 ps
CPU time 44.95 seconds
Started Jul 25 06:15:07 PM PDT 24
Finished Jul 25 06:15:52 PM PDT 24
Peak memory 199796 kb
Host smart-8ef6eb8a-a05d-44df-9758-6825d9e69c17
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016547408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3016547408
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1104605941
Short name T265
Test name
Test status
Simulation time 4554261674 ps
CPU time 80.98 seconds
Started Jul 25 06:14:57 PM PDT 24
Finished Jul 25 06:16:18 PM PDT 24
Peak memory 199776 kb
Host smart-5c501c2a-7f4d-4ef0-bdcd-2c9c5255ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104605941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1104605941
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.490106885
Short name T281
Test name
Test status
Simulation time 546741648 ps
CPU time 1.5 seconds
Started Jul 25 06:14:57 PM PDT 24
Finished Jul 25 06:14:58 PM PDT 24
Peak memory 199764 kb
Host smart-24bba91f-c6fe-41f2-869f-3daa1d2eb405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490106885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.490106885
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1643446668
Short name T27
Test name
Test status
Simulation time 20400552989 ps
CPU time 1652.62 seconds
Started Jul 25 06:15:06 PM PDT 24
Finished Jul 25 06:42:39 PM PDT 24
Peak memory 764812 kb
Host smart-314875e1-b67a-4fc3-bb77-2956ced7c6a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643446668 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1643446668
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2219469857
Short name T9
Test name
Test status
Simulation time 2448056466293 ps
CPU time 2429.4 seconds
Started Jul 25 06:15:07 PM PDT 24
Finished Jul 25 06:55:37 PM PDT 24
Peak memory 533292 kb
Host smart-ab6c68ec-0366-49a0-bbae-2955133b48b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219469857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2219469857
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2426128359
Short name T26
Test name
Test status
Simulation time 10958605858 ps
CPU time 142.47 seconds
Started Jul 25 06:15:04 PM PDT 24
Finished Jul 25 06:17:26 PM PDT 24
Peak memory 199800 kb
Host smart-bbe5a4a3-a4ff-4c3f-94c5-5cc318a8b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426128359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2426128359
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.493688431
Short name T48
Test name
Test status
Simulation time 16899924 ps
CPU time 0.59 seconds
Started Jul 25 06:15:17 PM PDT 24
Finished Jul 25 06:15:18 PM PDT 24
Peak memory 195720 kb
Host smart-49110534-829c-41f0-997d-5f16203a14c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493688431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.493688431
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4191847944
Short name T229
Test name
Test status
Simulation time 4372602052 ps
CPU time 59.57 seconds
Started Jul 25 06:15:13 PM PDT 24
Finished Jul 25 06:16:12 PM PDT 24
Peak memory 199816 kb
Host smart-a3d18eba-e93b-45a6-a294-14ccb964b7f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191847944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4191847944
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1907582142
Short name T436
Test name
Test status
Simulation time 335646191 ps
CPU time 18.08 seconds
Started Jul 25 06:15:11 PM PDT 24
Finished Jul 25 06:15:29 PM PDT 24
Peak memory 199752 kb
Host smart-24c1ab3d-b03e-467b-b847-a796e57a107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907582142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1907582142
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1503534937
Short name T470
Test name
Test status
Simulation time 2940595547 ps
CPU time 387.12 seconds
Started Jul 25 06:15:12 PM PDT 24
Finished Jul 25 06:21:40 PM PDT 24
Peak memory 631428 kb
Host smart-fcbb078d-d55a-470d-9d96-179df4668b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503534937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1503534937
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1435425082
Short name T71
Test name
Test status
Simulation time 407706669 ps
CPU time 23.06 seconds
Started Jul 25 06:15:11 PM PDT 24
Finished Jul 25 06:15:34 PM PDT 24
Peak memory 199588 kb
Host smart-42c497ae-8320-4b51-b193-7633acc8455e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435425082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1435425082
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2619130317
Short name T231
Test name
Test status
Simulation time 53320138593 ps
CPU time 182.5 seconds
Started Jul 25 06:15:04 PM PDT 24
Finished Jul 25 06:18:06 PM PDT 24
Peak memory 199768 kb
Host smart-f079b6e5-2da3-4208-9638-e7cb5e2d7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619130317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2619130317
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3758717737
Short name T138
Test name
Test status
Simulation time 2371677013 ps
CPU time 7.39 seconds
Started Jul 25 06:15:02 PM PDT 24
Finished Jul 25 06:15:10 PM PDT 24
Peak memory 199724 kb
Host smart-a56decc3-ca84-497f-ab9e-92d24db825c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758717737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3758717737
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3672820771
Short name T37
Test name
Test status
Simulation time 866989036087 ps
CPU time 2777.76 seconds
Started Jul 25 06:15:16 PM PDT 24
Finished Jul 25 07:01:34 PM PDT 24
Peak memory 709556 kb
Host smart-69d103e2-7249-4277-9a4d-084d93e7b218
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672820771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3672820771
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.21613717
Short name T21
Test name
Test status
Simulation time 51631884001 ps
CPU time 790.49 seconds
Started Jul 25 06:15:19 PM PDT 24
Finished Jul 25 06:28:30 PM PDT 24
Peak memory 699392 kb
Host smart-276a686f-fabd-4e1a-bdd4-3ec4667a12fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21613717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.21613717
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2095293003
Short name T80
Test name
Test status
Simulation time 37095433692 ps
CPU time 60.97 seconds
Started Jul 25 06:15:09 PM PDT 24
Finished Jul 25 06:16:10 PM PDT 24
Peak memory 199816 kb
Host smart-9e54c050-04d0-4dcf-84e2-53d4e93dcfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095293003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2095293003
Directory /workspace/9.hmac_wipe_secret/latest
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