Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19519040	1			T1	40955		T2	9237		T3	10336
all_values[1]	19519040	1			T1	40955		T2	9237		T3	10336
all_values[2]	19519040	1			T1	40955		T2	9237		T3	10336

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

292021

1

T14

302

T6

193

T11

668

auto[1]

58265099

1

T1

122865

T2

27711

T3

31008

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49817600

1

T1

101025

T2

23759

T3

25823

auto[1]

8739520

1

T1

21840

T2

3952

T3

5185

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96473	1			T14	66		T6	154		T11	376
all_values[0]	auto[0]	auto[1]	369	1			T14	2		T6	3		T11	2
all_values[0]	auto[1]	auto[0]	19401485	1			T1	40946		T2	9225		T3	10329
all_values[0]	auto[1]	auto[1]	20713	1			T1	9		T2	12		T3	7
all_values[1]	auto[0]	auto[0]	91283	1			T14	166		T6	10		T10	11
all_values[1]	auto[0]	auto[1]	225	1			T6	9		T10	2		T8	9
all_values[1]	auto[1]	auto[0]	19427175	1			T1	40955		T2	9237		T3	10336
all_values[1]	auto[1]	auto[1]	357	1			T6	12		T10	4		T8	13
all_values[2]	auto[0]	auto[0]	72686	1			T14	68		T6	10		T11	2
all_values[2]	auto[0]	auto[1]	30985	1			T6	7		T11	288		T10	4
all_values[2]	auto[1]	auto[0]	10728498	1			T1	19124		T2	5297		T3	5158
all_values[2]	auto[1]	auto[1]	8686871	1			T1	21831		T2	3940		T3	5178