Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124693

1

T1

34

T2

22

T3

12

auto[1]

132152

1

T1

24

T2

2

T3

18

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	98745	1			T1	29		T2	6		T3	15
len_1026_2046	6748	1			T4	1		T7	283		T5	1
len_514_1022	3735	1			T2	3		T4	1		T7	2
len_2_510	2900	1			T7	1		T6	22		T11	5
len_2056	203	1			T6	11		T10	4		T8	1
len_2048	354	1			T5	1		T6	25		T10	1
len_2040	186	1			T6	14		T10	2		T8	3
len_1032	248	1			T6	9		T8	1		T66	1
len_1024	1846	1			T4	2		T5	1		T6	27
len_1016	175	1			T14	2		T6	23		T28	1
len_520	211	1			T6	9		T10	2		T8	3
len_512	537	1			T6	13		T11	2		T10	3
len_504	178	1			T6	4		T10	1		T28	1
len_8	1274	1			T6	51		T10	16		T28	1
len_0	11082	1			T2	3		T7	10		T6	103

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

109

1

T5

1

T6

5

T11

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	49229	1			T1	17		T2	5		T3	6
auto[0]	len_1026_2046	2883	1			T7	3		T5	1		T6	21
auto[0]	len_514_1022	2264	1			T2	3		T7	1		T6	11
auto[0]	len_2_510	2100	1			T7	1		T6	12		T11	2
auto[0]	len_2056	92	1			T6	6		T8	1		T105	2
auto[0]	len_2048	191	1			T5	1		T6	17		T8	1
auto[0]	len_2040	79	1			T6	7		T10	2		T8	1
auto[0]	len_1032	97	1			T6	5		T8	1		T66	1
auto[0]	len_1024	272	1			T4	1		T6	18		T11	1
auto[0]	len_1016	100	1			T6	13		T28	1		T105	5
auto[0]	len_520	117	1			T6	4		T10	1		T8	1
auto[0]	len_512	383	1			T6	6		T11	1		T10	3
auto[0]	len_504	111	1			T6	2		T28	1		T66	2
auto[0]	len_8	42	1			T28	1		T106	1		T107	1
auto[0]	len_0	4386	1			T2	3		T6	49		T11	331
auto[1]	len_2050_plus	49516	1			T1	12		T2	1		T3	9
auto[1]	len_1026_2046	3865	1			T4	1		T7	280		T6	37
auto[1]	len_514_1022	1471	1			T4	1		T7	1		T6	17
auto[1]	len_2_510	800	1			T6	10		T11	3		T10	3
auto[1]	len_2056	111	1			T6	5		T10	4		T58	2
auto[1]	len_2048	163	1			T6	8		T10	1		T8	4
auto[1]	len_2040	107	1			T6	7		T8	2		T108	2
auto[1]	len_1032	151	1			T6	4		T109	2		T110	3
auto[1]	len_1024	1574	1			T4	1		T5	1		T6	9
auto[1]	len_1016	75	1			T14	2		T6	10		T66	2
auto[1]	len_520	94	1			T6	5		T10	1		T8	2
auto[1]	len_512	154	1			T6	7		T11	1		T9	1
auto[1]	len_504	67	1			T6	2		T10	1		T66	2
auto[1]	len_8	1232	1			T6	51		T10	16		T29	18
auto[1]	len_0	6696	1			T7	10		T6	54		T11	70

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

55

1

T5

1

T6

3

T10

2

auto[1]

len_upper

54

1

T6

2

T11

2

T8

7