Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4832868

1

T1

5694

T2

1954

T3

2927

auto[1]

3020358

1

T1

5362

T2

2612

T3

2237

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2979114

1

T1

7263

T2

1929

T3

3626

auto[1]

4874112

1

T1

3793

T2

2637

T3

1538

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3395625

1

T1

5298

T2

2524

T3

2582

auto[1]

4457601

1

T1

5758

T2

2042

T3

2582

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4764960

1

T1

5129

T2

2553

T3

2157

auto[1]

3088266

1

T1

5927

T2

2013

T3

3007

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7148707	1			T1	10971		T2	4100		T3	5105
fifo_depth[1]	126905	1			T1	81		T2	70		T3	41
fifo_depth[2]	94902	1			T1	4		T2	65		T3	14
fifo_depth[3]	72818	1			T2	67		T3	4		T4	1
fifo_depth[4]	64628	1			T2	65		T7	6		T5	1
fifo_depth[5]	49479	1			T2	64		T7	1		T5	1
fifo_depth[6]	39643	1			T2	62		T7	5		T5	1
fifo_depth[7]	25851	1			T2	37		T7	4		T5	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704519

1

T1

85

T2

466

T3

59

auto[1]

7148707

1

T1

10971

T2

4100

T3

5105

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7840090

1

T1

11056

T2

4566

T3

5164

auto[1]

13136

1

T6

248

T8

231

T9

865

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

25850

1

T2

50

T4

2

T5

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27168

1

T1

1

T4

1

T5

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30441

1

T2

107

T3

12

T6

2283

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

36292

1

T1

16

T3

1

T5

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

169098

1

T4

2

T7

18

T6

1619

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29275

1

T5

1

T6

3452

T11

69

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

28542

1

T1

11

T2

167

T6

1640

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29749

1

T2

4

T5

1

T6

1630

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45148

1

T1

12

T4

1

T6

1690

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

38663

1

T1

5

T14

3

T6

3073

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35013

1

T3

6

T4

1

T5

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34041

1

T2

138

T3

33

T4

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43458

1

T1

40

T4

1

T5

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

46766

1

T3

7

T7

12

T6

3566

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47090

1

T7

3

T6

4312

T11

37

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37925

1

T5

1

T6

2078

T11

34

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

177959

1

T1

2

T2

168

T3

1076

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

179534

1

T1

744

T2

391

T3

251

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

167720

1

T1

410

T2

431

T3

345

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

200867

1

T1

3284

T2

36

T3

391

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1717320

1

T3

440

T4

1

T7

62

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

204686

1

T2

275

T4

1

T5

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

181624

1

T1

337

T2

560

T3

66

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

189500

1

T1

493

T2

335

T4

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

500189

1

T1

1726

T2

242

T4

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

498672

1

T1

573

T3

486

T4

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

508864

1

T1

2

T3

203

T7

158

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

472693

1

T1

488

T2

366

T3

822

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

550901

1

T1

2589

T2

828

T4

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

578181

1

T1

2

T3

667

T4

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

535743

1

T3

9

T4

3

T7

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

484254

1

T1

321

T2

468

T3

349

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

203348

1

T1

2

T2

218

T3

1076

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

206325

1

T1

745

T2

391

T3

251

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

197030

1

T1

410

T2

538

T3

357

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

235157

1

T1

3300

T2

36

T3

392

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1884531

1

T3

440

T4

3

T7

80

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

233366

1

T2

275

T4

1

T5

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

209819

1

T1

348

T2

727

T3

66

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

218568

1

T1

493

T2

339

T4

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

544149

1

T1

1738

T2

242

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

536303

1

T1

578

T3

486

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

542810

1

T1

2

T3

209

T4

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

506551

1

T1

488

T2

504

T3

855

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

593392

1

T1

2629

T2

828

T4

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

624683

1

T1

2

T3

674

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

582183

1

T3

9

T4

3

T7

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

521875

1

T1

321

T2

468

T3

349

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

461

1

T8

79

T9

15

T30

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

377

1

T30

15

T15

7

T12

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1131

1

T6

13

T8

5

T111

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2002

1

T6

32

T8

8

T9

460

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1887

1

T8

2

T112

4

T12

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

595

1

T6

113

T30

8

T113

15

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

347

1

T6

5

T15

7

T113

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

681

1

T8

22

T15

168

T113

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1188

1

T9

2

T30

460

T12

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1032

1

T6

9

T8

86

T114

90

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1067

1

T9

48

T30

3

T12

87

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

183

1

T8

25

T114

4

T12

13

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

967

1

T9

182

T113

13

T12

78

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

264

1

T6

70

T113

10

T115

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

650

1

T6

6

T9

96

T15

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

304

1

T8

4

T9

62

T12

5

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

177959

1

T1

2

T2

168

T3

1076

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

179534

1

T1

744

T2

391

T3

251

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

167720

1

T1

410

T2

431

T3

345

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

200867

1

T1

3284

T2

36

T3

391

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1717320

1

T3

440

T4

1

T7

62

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

204686

1

T2

275

T4

1

T5

3

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

181624

1

T1

337

T2

560

T3

66

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

189500

1

T1

493

T2

335

T4

2

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

500189

1

T1

1726

T2

242

T4

2

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

498672

1

T1

573

T3

486

T4

1

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

508864

1

T1

2

T3

203

T7

158

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

472693

1

T1

488

T2

366

T3

822

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

550901

1

T1

2589

T2

828

T4

4

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

578181

1

T1

2

T3

667

T4

1

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

535743

1

T3

9

T4

3

T7

3

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

484254

1

T1

321

T2

468

T3

349

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3155

1

T2

10

T5

1

T6

295

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3127

1

T1

1

T6

110

T10

41

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3114

1

T2

12

T3

9

T6

205

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3944

1

T1

16

T3

1

T6

277

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

47681

1

T6

244

T10

89

T8

61

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3776

1

T6

321

T11

3

T10

62

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3659

1

T1

10

T2

24

T6

189

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3477

1

T2

1

T6

292

T10

11

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6126

1

T1

11

T6

287

T11

4

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6439

1

T1

5

T14

2

T6

351

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6449

1

T3

3

T6

346

T10

25

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6528

1

T2

23

T3

24

T6

223

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8281

1

T1

38

T6

429

T11

2

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7834

1

T3

4

T7

1

T6

550

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

7224

1

T7

1

T6

714

T11

6

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6091

1

T6

328

T11

5

T10

110

fifo_depth[2]

auto[0]

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2165

1

T2

7

T4

1

T6

275

fifo_depth[2]

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auto[0]

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2372

1

T5

1

T6

112

T10

9

fifo_depth[2]

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auto[1]

auto[0]

2192

1

T2

18

T3

2

T6

185

fifo_depth[2]

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2968

1

T6

215

T11

4

T10

6

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1

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2

T6

233

T10

26

fifo_depth[2]

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2921

1

T6

309

T11

20

T10

6

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auto[0]

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1

T1

1

T2

25

T6

153

fifo_depth[2]

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auto[1]

auto[1]

2735

1

T2

1

T6

308

T10

2

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auto[0]

auto[0]

4862

1

T1

1

T6

280

T11

3

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auto[0]

auto[1]

4940

1

T14

1

T6

344

T10

11

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auto[1]

auto[0]

5146

1

T3

3

T6

342

T10

3

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auto[1]

5120

1

T2

14

T3

8

T6

245

fifo_depth[2]

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1

T1

2

T6

382

T11

3

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auto[0]

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6511

1

T3

1

T7

5

T6

536

fifo_depth[2]

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auto[0]

5862

1

T6

620

T11

6

T10

69

fifo_depth[2]

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auto[1]

auto[1]

4542

1

T6

337

T11

4

T10

48

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auto[0]

auto[0]

1479

1

T2

7

T5

1

T6

243

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1724

1

T6

104

T10

3

T8

82

fifo_depth[3]

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auto[0]

1740

1

T2

15

T3

1

T6

205

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[1]

2221

1

T6

220

T11

3

T8

92

fifo_depth[3]

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auto[0]

auto[0]

25389

1

T4

1

T6

261

T10

7

fifo_depth[3]

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1

T6

291

T8

176

T24

2

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auto[0]

1843

1

T2

24

T6

138

T8

309

fifo_depth[3]

auto[0]

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auto[1]

1875

1

T6

270

T10

2

T8

203

fifo_depth[3]

auto[1]

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auto[0]

auto[0]

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1

T6

261

T11

2

T10

1

fifo_depth[3]

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3841

1

T6

374

T10

2

T8

21

fifo_depth[3]

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auto[0]

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1

T6

284

T10

1

T8

77

fifo_depth[3]

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auto[1]

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1

T2

21

T3

1

T6

221

fifo_depth[3]

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auto[0]

auto[0]

4740

1

T6

340

T11

2

T10

4

fifo_depth[3]

auto[1]

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auto[0]

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5075

1

T3

2

T6

427

T10

7

fifo_depth[3]

auto[1]

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auto[0]

4968

1

T6

617

T11

3

T10

13

fifo_depth[3]

auto[1]

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auto[1]

auto[1]

3626

1

T6

307

T11

4

T10

9

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

1448

1

T2

6

T6

216

T8

133

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

1984

1

T6

83

T10

1

T8

67

fifo_depth[4]

auto[0]

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auto[0]

1712

1

T2

17

T6

163

T11

3

fifo_depth[4]

auto[0]

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auto[1]

auto[1]

2420

1

T6

177

T11

3

T8

98

fifo_depth[4]

auto[0]

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auto[0]

auto[0]

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1

T7

4

T6

243

T10

2

fifo_depth[4]

auto[0]

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auto[0]

auto[1]

2115

1

T6

264

T11

16

T8

145

fifo_depth[4]

auto[0]

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auto[1]

auto[0]

1795

1

T2

17

T6

93

T8

263

fifo_depth[4]

auto[0]

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auto[1]

auto[1]

1990

1

T2

2

T6

228

T8

204

fifo_depth[4]

auto[1]

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auto[0]

auto[0]

3853

1

T6

267

T11

2

T8

51

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

3609

1

T6

295

T10

1

T8

20

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

3867

1

T6

279

T10

1

T8

65

fifo_depth[4]

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3914

1

T2

23

T6

196

T11

17

fifo_depth[4]

auto[1]

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1

T5

1

T6

302

T11

2

fifo_depth[4]

auto[1]

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auto[0]

auto[1]

5032

1

T7

2

T6

438

T10

2

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4633

1

T6

582

T11

5

T10

3

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

3638

1

T6

297

T11

6

T8

179

fifo_depth[5]

auto[0]

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1

T2

6

T6

151

T8

84

fifo_depth[5]

auto[0]

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auto[0]

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1

T6

73

T8

77

T27

5

fifo_depth[5]

auto[0]

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auto[1]

auto[0]

1488

1

T2

17

T6

151

T10

1

fifo_depth[5]

auto[0]

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auto[1]

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1

T6

141

T11

1

T8

89

fifo_depth[5]

auto[0]

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auto[0]

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1

T7

1

T6

197

T8

42

fifo_depth[5]

auto[0]

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auto[0]

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1

T6

183

T11

3

T8

163

fifo_depth[5]

auto[0]

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auto[0]

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1

T2

25

T6

90

T8

207

fifo_depth[5]

auto[0]

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1492

1

T6

201

T8

165

T27

13

fifo_depth[5]

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auto[0]

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1

T6

207

T11

2

T8

58

fifo_depth[5]

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2987

1

T6

316

T8

16

T27

37

fifo_depth[5]

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auto[1]

auto[0]

3092

1

T5

1

T6

228

T8

38

fifo_depth[5]

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3318

1

T2

16

T6

129

T11

7

fifo_depth[5]

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auto[0]

3417

1

T6

273

T11

2

T8

73

fifo_depth[5]

auto[1]

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1

T6

326

T8

96

T116

26

fifo_depth[5]

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auto[0]

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1

T6

501

T11

2

T10

1

fifo_depth[5]

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auto[1]

2876

1

T6

237

T11

4

T8

154

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802

1

T2

8

T6

104

T8

49

fifo_depth[6]

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1

T6

72

T8

52

T27

15

fifo_depth[6]

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auto[0]

1092

1

T2

13

T6

105

T11

2

fifo_depth[6]

auto[0]

auto[0]

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auto[1]

1577

1

T6

107

T11

2

T8

93

fifo_depth[6]

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auto[0]

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1

T7

2

T6

130

T8

44

fifo_depth[6]

auto[0]

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1350

1

T6

155

T11

16

T8

114

fifo_depth[6]

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auto[0]

1058

1

T2

28

T6

72

T8

140

fifo_depth[6]

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1358

1

T6

148

T8

146

T27

7

fifo_depth[6]

auto[1]

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auto[0]

auto[0]

2616

1

T6

154

T8

42

T27

2

fifo_depth[6]

auto[1]

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2447

1

T6

204

T8

16

T27

37

fifo_depth[6]

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auto[0]

2458

1

T5

1

T6

188

T8

32

fifo_depth[6]

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auto[1]

2652

1

T2

13

T6

105

T11

6

fifo_depth[6]

auto[1]

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auto[0]

auto[0]

2792

1

T6

206

T11

2

T8

60

fifo_depth[6]

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auto[0]

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3492

1

T7

3

T6

296

T8

82

fifo_depth[6]

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auto[0]

3138

1

T6

339

T11

7

T8

48

fifo_depth[6]

auto[1]

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2621

1

T6

205

T11

4

T8

120

fifo_depth[7]

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auto[0]

auto[0]

587

1

T2

2

T5

1

T6

61

fifo_depth[7]

auto[0]

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827

1

T5

1

T6

42

T8

46

fifo_depth[7]

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950

1

T2

6

T6

67

T11

2

fifo_depth[7]

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auto[1]

1059

1

T6

54

T11

7

T8

47

fifo_depth[7]

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auto[0]

auto[0]

5197

1

T7

4

T6

85

T8

19

fifo_depth[7]

auto[0]

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auto[0]

auto[1]

779

1

T6

77

T8

71

T27

14

fifo_depth[7]

auto[0]

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auto[1]

auto[0]

647

1

T2

14

T6

44

T8

77

fifo_depth[7]

auto[0]

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auto[1]

auto[1]

1114

1

T6

96

T8

158

T27

8

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

1741

1

T6

118

T11

1

T8

30

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1595

1

T6

151

T8

13

T27

17

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1542

1

T6

138

T8

32

T27

7

fifo_depth[7]

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auto[0]

auto[1]

auto[1]

1823

1

T2

15

T6

60

T11

1

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

1824

1

T6

156

T11

2

T8

57

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

2302

1

T6

197

T8

37

T116

22

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

2270

1

T6

239

T11

3

T8

34

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

1594

1

T6

126

T11

3

T8

81