Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19519040	1			T1	40955		T2	9237		T3	10336
all_pins[1]	19519040	1			T1	40955		T2	9237		T3	10336
all_pins[2]	19519040	1			T1	40955		T2	9237		T3	10336

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49848326	1			T1	101025		T2	23758		T3	25822
values[0x1]	8708794	1			T1	21840		T2	3953		T3	5186
transitions[0x0=>0x1]	8708608	1			T1	21840		T2	3953		T3	5186
transitions[0x1=>0x0]	8708623	1			T1	21840		T2	3953		T3	5186

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19497504	1			T1	40946		T2	9224		T3	10328
all_pins[0]	values[0x1]	21536	1			T1	9		T2	13		T3	8
all_pins[0]	transitions[0x0=>0x1]	21449	1			T1	9		T2	13		T3	8
all_pins[0]	transitions[0x1=>0x0]	8686799	1			T1	21831		T2	3940		T3	5178
all_pins[1]	values[0x0]	19518653	1			T1	40955		T2	9237		T3	10336
all_pins[1]	values[0x1]	387	1			T6	14		T10	4		T8	13
all_pins[1]	transitions[0x0=>0x1]	334	1			T6	10		T10	3		T8	12
all_pins[1]	transitions[0x1=>0x0]	21483	1			T1	9		T2	13		T3	8
all_pins[2]	values[0x0]	10832169	1			T1	19124		T2	5297		T3	5158
all_pins[2]	values[0x1]	8686871	1			T1	21831		T2	3940		T3	5178
all_pins[2]	transitions[0x0=>0x1]	8686825	1			T1	21831		T2	3940		T3	5178
all_pins[2]	transitions[0x1=>0x0]	341	1			T6	14		T10	3		T8	13