Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1049 1 T6 28 T10 24 T8 28
all_values[1] 1049 1 T6 28 T10 24 T8 28
all_values[2] 1049 1 T6 28 T10 24 T8 28


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1544 1 T6 33 T10 36 T8 36
auto[1] 1603 1 T6 51 T10 36 T8 48


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1146 1 T6 23 T10 34 T8 37
auto[1] 2001 1 T6 61 T10 38 T8 47


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1813 1 T6 43 T10 48 T8 52
auto[1] 1334 1 T6 41 T10 24 T8 32


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 187 1 T6 2 T10 8 T8 4
all_values[0] auto[0] auto[0] auto[1] 87 1 T6 1 T10 2 T57 1
all_values[0] auto[0] auto[1] auto[0] 209 1 T6 8 T10 2 T8 8
all_values[0] auto[0] auto[1] auto[1] 110 1 T6 3 T10 2 T8 5
all_values[0] auto[1] auto[0] auto[1] 238 1 T6 3 T10 5 T8 4
all_values[0] auto[1] auto[1] auto[1] 218 1 T6 11 T10 5 T8 7
all_values[1] auto[0] auto[0] auto[0] 155 1 T6 2 T10 9 T8 5
all_values[1] auto[0] auto[0] auto[1] 135 1 T6 4 T10 2 T8 3
all_values[1] auto[0] auto[1] auto[0] 177 1 T6 3 T10 3 T8 6
all_values[1] auto[0] auto[1] auto[1] 127 1 T6 4 T10 4 T8 2
all_values[1] auto[1] auto[0] auto[1] 225 1 T6 10 T10 3 T8 6
all_values[1] auto[1] auto[1] auto[1] 230 1 T6 5 T10 3 T8 6
all_values[2] auto[0] auto[0] auto[0] 215 1 T6 2 T10 3 T8 4
all_values[2] auto[0] auto[0] auto[1] 95 1 T6 3 T10 1 T8 4
all_values[2] auto[0] auto[1] auto[0] 203 1 T6 6 T10 9 T8 10
all_values[2] auto[0] auto[1] auto[1] 113 1 T6 5 T10 3 T8 1
all_values[2] auto[1] auto[0] auto[1] 207 1 T6 6 T10 3 T8 6
all_values[2] auto[1] auto[1] auto[1] 216 1 T6 6 T10 5 T8 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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