Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4528	1			T1	3		T2	3		T3	7
sha2_none	4457	1			T1	5		T2	7		T3	7
sha2_512	7955	1			T1	5		T2	4		T3	3
sha2_384	7731	1			T1	7		T2	3		T3	3
sha2_256	6744	1			T1	6		T2	3		T3	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19633

1

T1

14

T2

9

T3

9

auto[1]

12216

1

T1

15

T2

12

T3

14

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12095

1

T1

19

T2

10

T3

16

auto[1]

19754

1

T1

10

T2

11

T3

7

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16588

1

T1

15

T2

6

T3

11

disabled

15261

1

T1

14

T2

15

T3

12

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5025	1			T1	9		T2	5		T3	5
key_none	7982	1			T1	6		T2	4		T3	4
key_1024	4521	1			T1	3		T2	2		T3	4
key_512	3952	1			T1	4		T2	3		T3	3
key_384	3722	1			T1	5		T2	5		T3	3
key_256	3429	1			T1	1		T3	4		T4	4
key_128	3134	1			T1	1		T2	2		T4	6

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19802

1

T1

13

T2

11

T3

10

auto[1]

12047

1

T1

16

T2

10

T3

13

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31626

1

T1

29

T2

21

T3

23

disabled

223

1

T6

6

T10

7

T8

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1757

1

T1

3

T2

2

T4

3

enabled

auto[0]

auto[0]

auto[1]

1740

1

T1

2

T3

2

T4

1

enabled

auto[0]

auto[1]

auto[0]

1700

1

T3

2

T4

2

T7

1

enabled

auto[0]

auto[1]

auto[1]

1700

1

T1

3

T2

1

T3

3

enabled

auto[1]

auto[0]

auto[0]

4386

1

T1

4

T2

2

T4

6

enabled

auto[1]

auto[0]

auto[1]

1748

1

T1

1

T3

2

T4

1

enabled

auto[1]

auto[1]

auto[0]

1886

1

T1

1

T3

1

T4

3

enabled

auto[1]

auto[1]

auto[1]

1671

1

T1

1

T2

1

T3

1

disabled

auto[0]

auto[0]

auto[0]

1300

1

T1

2

T2

2

T3

3

disabled

auto[0]

auto[0]

auto[1]

1253

1

T1

2

T2

1

T3

1

disabled

auto[0]

auto[1]

auto[0]

1285

1

T1

2

T2

3

T3

1

disabled

auto[0]

auto[1]

auto[1]

1360

1

T1

5

T2

1

T3

4

disabled

auto[1]

auto[0]

auto[0]

6131

1

T3

1

T4

3

T7

2

disabled

auto[1]

auto[0]

auto[1]

1318

1

T2

2

T4

1

T5

4

disabled

auto[1]

auto[1]

auto[0]

1357

1

T1

1

T2

2

T3

2

disabled

auto[1]

auto[1]

auto[1]

1257

1

T1

2

T2

4

T4

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16507

1

T1

15

T2

6

T3

11

enabled

disabled

81

1

T6

1

T10

3

T8

1

disabled

disabled

142

1

T6

5

T10

4

T8

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15119

1

T1

14

T2

15

T3

12

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1205	1			T1	2		T2	1		T3	2
key_invalid	sha2_none	934	1			T1	1		T2	1		T3	1
key_invalid	sha2_512	934	1			T3	1		T4	2		T7	1
key_invalid	sha2_384	924	1			T1	2		T2	2		T3	1
key_invalid	sha2_256	917	1			T1	2		T2	1		T4	1
key_none	sha2_invalid	555	1			T3	2		T7	1		T5	1
key_none	sha2_none	576	1			T1	1		T2	2		T3	2
key_none	sha2_512	2548	1			T1	1		T2	1		T4	2
key_none	sha2_384	2592	1			T1	1		T4	6		T5	3
key_none	sha2_256	1655	1			T1	2		T4	1		T6	26
key_1024	sha2_invalid	540	1			T3	1		T7	1		T6	18
key_1024	sha2_none	581	1			T1	1		T3	2		T4	1
key_1024	sha2_512	1826	1			T2	1		T4	2		T5	1
key_1024	sha2_384	904	1			T1	1		T3	1		T4	2
key_512	sha2_invalid	560	1			T2	2		T3	1		T4	1
key_512	sha2_none	543	1			T1	2		T2	1		T4	2
key_512	sha2_512	643	1			T1	1		T3	2		T4	1
key_512	sha2_384	1242	1			T1	1		T4	3		T7	1
key_512	sha2_256	914	1			T5	2		T6	34		T11	3
key_384	sha2_invalid	525	1			T1	1		T3	1		T7	1
key_384	sha2_none	625	1			T2	3		T4	4		T5	2
key_384	sha2_512	651	1			T1	3		T2	2		T5	2
key_384	sha2_384	712	1			T3	1		T4	3		T7	1
key_384	sha2_256	1146	1			T1	1		T3	1		T5	1
key_256	sha2_invalid	554	1			T7	1		T6	27		T10	11
key_256	sha2_none	579	1			T3	2		T6	18		T10	13
key_256	sha2_512	708	1			T4	3		T5	1		T6	28
key_256	sha2_384	727	1			T1	1		T5	1		T6	27
key_256	sha2_256	814	1			T3	1		T4	1		T6	46
key_128	sha2_invalid	568	1			T4	2		T7	1		T5	3
key_128	sha2_none	604	1			T7	1		T5	2		T6	27
key_128	sha2_512	630	1			T7	1		T6	28		T11	1
key_128	sha2_384	617	1			T1	1		T2	1		T4	4
key_128	sha2_256	658	1			T2	1		T14	1		T7	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

621

1

T1

1

T2

1

T7

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1205	1			T1	2		T2	1		T3	2
key_invalid	sha2_none	934	1			T1	1		T2	1		T3	1
key_invalid	sha2_512	934	1			T3	1		T4	2		T7	1
key_invalid	sha2_384	924	1			T1	2		T2	2		T3	1
key_invalid	sha2_256	917	1			T1	2		T2	1		T4	1
key_none	sha2_invalid	555	1			T3	2		T7	1		T5	1
key_none	sha2_none	576	1			T1	1		T2	2		T3	2
key_none	sha2_512	2548	1			T1	1		T2	1		T4	2
key_none	sha2_384	2592	1			T1	1		T4	6		T5	3
key_none	sha2_256	1655	1			T1	2		T4	1		T6	26
key_1024	sha2_invalid	540	1			T3	1		T7	1		T6	18
key_1024	sha2_none	581	1			T1	1		T3	2		T4	1
key_1024	sha2_512	1826	1			T2	1		T4	2		T5	1
key_1024	sha2_384	904	1			T1	1		T3	1		T4	2
key_1024	sha2_256	621	1			T1	1		T2	1		T7	1
key_512	sha2_invalid	560	1			T2	2		T3	1		T4	1
key_512	sha2_none	543	1			T1	2		T2	1		T4	2
key_512	sha2_512	643	1			T1	1		T3	2		T4	1
key_512	sha2_384	1242	1			T1	1		T4	3		T7	1
key_512	sha2_256	914	1			T5	2		T6	34		T11	3
key_384	sha2_invalid	525	1			T1	1		T3	1		T7	1
key_384	sha2_none	625	1			T2	3		T4	4		T5	2
key_384	sha2_512	651	1			T1	3		T2	2		T5	2
key_384	sha2_384	712	1			T3	1		T4	3		T7	1
key_384	sha2_256	1146	1			T1	1		T3	1		T5	1
key_256	sha2_invalid	554	1			T7	1		T6	27		T10	11
key_256	sha2_none	579	1			T3	2		T6	18		T10	13
key_256	sha2_512	708	1			T4	3		T5	1		T6	28
key_256	sha2_384	727	1			T1	1		T5	1		T6	27
key_256	sha2_256	814	1			T3	1		T4	1		T6	46
key_128	sha2_invalid	568	1			T4	2		T7	1		T5	3
key_128	sha2_none	604	1			T7	1		T5	2		T6	27
key_128	sha2_512	630	1			T7	1		T6	28		T11	1
key_128	sha2_384	617	1			T1	1		T2	1		T4	4
key_128	sha2_256	658	1			T2	1		T14	1		T7	1