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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.40 97.22 100.00 94.12 98.27 98.48 99.85


Total test records in report: 660
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T72 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4153156014 Jul 26 05:26:53 PM PDT 24 Jul 26 05:26:59 PM PDT 24 187382736 ps
T537 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.309992448 Jul 26 05:27:05 PM PDT 24 Jul 26 05:27:06 PM PDT 24 29066405 ps
T538 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1656637680 Jul 26 05:27:26 PM PDT 24 Jul 26 05:27:27 PM PDT 24 115400920 ps
T88 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1330653770 Jul 26 05:27:20 PM PDT 24 Jul 26 05:27:22 PM PDT 24 192575199 ps
T539 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1483757905 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:25 PM PDT 24 31949001 ps
T540 /workspace/coverage/cover_reg_top/8.hmac_intr_test.4128541808 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:07 PM PDT 24 55820931 ps
T541 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2231520804 Jul 26 05:27:04 PM PDT 24 Jul 26 05:41:02 PM PDT 24 509747534478 ps
T542 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3680187345 Jul 26 05:27:12 PM PDT 24 Jul 26 05:27:14 PM PDT 24 109672537 ps
T543 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4149599584 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:08 PM PDT 24 74638562 ps
T544 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2639389554 Jul 26 05:27:27 PM PDT 24 Jul 26 05:27:28 PM PDT 24 12736361 ps
T545 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3796262660 Jul 26 05:27:20 PM PDT 24 Jul 26 05:27:21 PM PDT 24 23359009 ps
T89 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2366845669 Jul 26 05:27:12 PM PDT 24 Jul 26 05:27:14 PM PDT 24 90229509 ps
T73 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1053066063 Jul 26 05:26:52 PM PDT 24 Jul 26 05:26:53 PM PDT 24 16184866 ps
T74 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1676261499 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:11 PM PDT 24 183495153 ps
T90 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3403720448 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:08 PM PDT 24 158696597 ps
T49 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.560520198 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:13 PM PDT 24 204898047 ps
T546 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3118728677 Jul 26 05:27:03 PM PDT 24 Jul 26 05:27:07 PM PDT 24 729675967 ps
T91 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3728683144 Jul 26 05:27:09 PM PDT 24 Jul 26 05:27:10 PM PDT 24 224423533 ps
T547 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3193708120 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:22 PM PDT 24 39397298 ps
T92 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2065803783 Jul 26 05:27:23 PM PDT 24 Jul 26 05:27:25 PM PDT 24 25582364 ps
T93 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3326464109 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:23 PM PDT 24 77751697 ps
T548 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2684480559 Jul 26 05:27:25 PM PDT 24 Jul 26 05:27:25 PM PDT 24 41015233 ps
T549 /workspace/coverage/cover_reg_top/9.hmac_intr_test.229352333 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:11 PM PDT 24 12091717 ps
T550 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4003306987 Jul 26 05:27:23 PM PDT 24 Jul 26 05:27:24 PM PDT 24 15312219 ps
T551 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3589661555 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:24 PM PDT 24 305705449 ps
T94 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3939244950 Jul 26 05:27:21 PM PDT 24 Jul 26 05:27:22 PM PDT 24 33989021 ps
T75 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2877718304 Jul 26 05:27:11 PM PDT 24 Jul 26 05:27:12 PM PDT 24 82581672 ps
T552 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1086806662 Jul 26 05:27:14 PM PDT 24 Jul 26 05:27:18 PM PDT 24 332103155 ps
T553 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2837645171 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:05 PM PDT 24 773750677 ps
T554 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1991779177 Jul 26 05:27:23 PM PDT 24 Jul 26 05:27:23 PM PDT 24 19452200 ps
T555 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2714583599 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:08 PM PDT 24 114644102 ps
T556 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2616170246 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:07 PM PDT 24 45958762 ps
T557 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1453366537 Jul 26 05:27:27 PM PDT 24 Jul 26 05:27:28 PM PDT 24 27415957 ps
T558 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2195667706 Jul 26 05:27:08 PM PDT 24 Jul 26 05:32:49 PM PDT 24 96848038668 ps
T559 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4252510702 Jul 26 05:27:17 PM PDT 24 Jul 26 05:27:17 PM PDT 24 11547310 ps
T560 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3776423766 Jul 26 05:27:08 PM PDT 24 Jul 26 05:27:10 PM PDT 24 34340076 ps
T561 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2047500860 Jul 26 05:27:18 PM PDT 24 Jul 26 05:27:19 PM PDT 24 23950046 ps
T562 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.358173581 Jul 26 05:27:01 PM PDT 24 Jul 26 05:27:07 PM PDT 24 1322190448 ps
T563 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1017447152 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:13 PM PDT 24 256557603 ps
T564 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3170518038 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:20 PM PDT 24 1098482092 ps
T565 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1701329751 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:23 PM PDT 24 31760743 ps
T566 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2142525665 Jul 26 05:27:03 PM PDT 24 Jul 26 05:27:04 PM PDT 24 93632622 ps
T76 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2460428398 Jul 26 05:27:18 PM PDT 24 Jul 26 05:27:19 PM PDT 24 26648845 ps
T567 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2953596787 Jul 26 05:27:02 PM PDT 24 Jul 26 05:27:05 PM PDT 24 89412165 ps
T50 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3289068925 Jul 26 05:27:12 PM PDT 24 Jul 26 05:27:16 PM PDT 24 214264088 ps
T568 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3732224913 Jul 26 05:27:05 PM PDT 24 Jul 26 05:27:06 PM PDT 24 84908535 ps
T51 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.890927788 Jul 26 05:27:02 PM PDT 24 Jul 26 05:27:07 PM PDT 24 226436228 ps
T569 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1315453569 Jul 26 05:27:05 PM PDT 24 Jul 26 05:27:06 PM PDT 24 132390642 ps
T570 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3394657129 Jul 26 05:27:30 PM PDT 24 Jul 26 05:27:32 PM PDT 24 105597700 ps
T571 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3014978597 Jul 26 05:27:15 PM PDT 24 Jul 26 05:27:16 PM PDT 24 59578314 ps
T572 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.783958822 Jul 26 05:27:13 PM PDT 24 Jul 26 05:27:16 PM PDT 24 119515077 ps
T573 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2964718261 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:12 PM PDT 24 424198077 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3476510489 Jul 26 05:27:03 PM PDT 24 Jul 26 05:27:05 PM PDT 24 106364736 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_intr_test.457746872 Jul 26 05:27:05 PM PDT 24 Jul 26 05:27:06 PM PDT 24 26023991 ps
T575 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4154377894 Jul 26 05:27:31 PM PDT 24 Jul 26 05:27:32 PM PDT 24 50098067 ps
T576 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1854153547 Jul 26 05:27:02 PM PDT 24 Jul 26 05:27:03 PM PDT 24 194190950 ps
T577 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.490872841 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:07 PM PDT 24 172322488 ps
T578 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1583471736 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:06 PM PDT 24 110884460 ps
T579 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2446973867 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:05 PM PDT 24 65264493 ps
T580 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1235946657 Jul 26 05:27:23 PM PDT 24 Jul 26 05:27:24 PM PDT 24 23321736 ps
T581 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1866758573 Jul 26 05:27:28 PM PDT 24 Jul 26 05:27:31 PM PDT 24 43462514 ps
T77 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4201572992 Jul 26 05:27:07 PM PDT 24 Jul 26 05:27:08 PM PDT 24 21171460 ps
T582 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2197261154 Jul 26 05:27:17 PM PDT 24 Jul 26 05:27:18 PM PDT 24 30346872 ps
T96 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2323650310 Jul 26 05:27:15 PM PDT 24 Jul 26 05:27:17 PM PDT 24 82886264 ps
T101 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3125407306 Jul 26 05:27:03 PM PDT 24 Jul 26 05:27:06 PM PDT 24 152705926 ps
T583 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2844408809 Jul 26 05:27:13 PM PDT 24 Jul 26 05:27:15 PM PDT 24 45449219 ps
T78 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.283867187 Jul 26 05:27:21 PM PDT 24 Jul 26 05:27:23 PM PDT 24 55121273 ps
T79 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2612831765 Jul 26 05:27:07 PM PDT 24 Jul 26 05:27:08 PM PDT 24 52361217 ps
T584 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3796675751 Jul 26 05:27:33 PM PDT 24 Jul 26 05:27:34 PM PDT 24 46414980 ps
T585 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2257924605 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:25 PM PDT 24 51607043 ps
T80 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2468093344 Jul 26 05:27:07 PM PDT 24 Jul 26 05:27:13 PM PDT 24 394997977 ps
T586 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3912228234 Jul 26 05:27:13 PM PDT 24 Jul 26 05:27:14 PM PDT 24 34618879 ps
T587 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1886426539 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:07 PM PDT 24 107710887 ps
T81 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.32255319 Jul 26 05:27:07 PM PDT 24 Jul 26 05:27:08 PM PDT 24 27557410 ps
T99 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.597169815 Jul 26 05:27:15 PM PDT 24 Jul 26 05:27:19 PM PDT 24 500663233 ps
T82 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.617712544 Jul 26 05:27:11 PM PDT 24 Jul 26 05:27:12 PM PDT 24 64956910 ps
T588 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1694360297 Jul 26 05:27:13 PM PDT 24 Jul 26 05:27:15 PM PDT 24 135091918 ps
T104 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3518227370 Jul 26 05:27:16 PM PDT 24 Jul 26 05:27:21 PM PDT 24 496302969 ps
T589 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3075732916 Jul 26 05:27:16 PM PDT 24 Jul 26 05:27:18 PM PDT 24 188241108 ps
T590 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1373350923 Jul 26 05:27:12 PM PDT 24 Jul 26 05:27:13 PM PDT 24 13225267 ps
T102 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3613417693 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:15 PM PDT 24 1086551242 ps
T591 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4068333440 Jul 26 05:27:25 PM PDT 24 Jul 26 05:27:26 PM PDT 24 42401067 ps
T83 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2610132949 Jul 26 05:27:05 PM PDT 24 Jul 26 05:27:09 PM PDT 24 798586422 ps
T592 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3404723280 Jul 26 05:27:23 PM PDT 24 Jul 26 05:27:23 PM PDT 24 12504607 ps
T593 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2570564242 Jul 26 05:27:21 PM PDT 24 Jul 26 05:27:21 PM PDT 24 17862554 ps
T594 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1244253487 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:25 PM PDT 24 14925188 ps
T595 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1535805913 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:23 PM PDT 24 23128591 ps
T596 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3682925034 Jul 26 05:27:11 PM PDT 24 Jul 26 05:27:14 PM PDT 24 468891771 ps
T597 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1222902160 Jul 26 05:27:13 PM PDT 24 Jul 26 05:27:15 PM PDT 24 163623836 ps
T97 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2939598504 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:07 PM PDT 24 681411764 ps
T84 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2311671313 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:17 PM PDT 24 2840471941 ps
T98 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1094320870 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:27 PM PDT 24 91150960 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3817730750 Jul 26 05:26:53 PM PDT 24 Jul 26 05:26:58 PM PDT 24 2410150730 ps
T598 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1915761080 Jul 26 05:27:21 PM PDT 24 Jul 26 05:27:21 PM PDT 24 25829801 ps
T599 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.334800521 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:08 PM PDT 24 313526722 ps
T600 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3456186411 Jul 26 05:27:01 PM PDT 24 Jul 26 05:27:03 PM PDT 24 23863034 ps
T601 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.562959975 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:09 PM PDT 24 598043101 ps
T602 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3973750395 Jul 26 05:27:36 PM PDT 24 Jul 26 05:27:37 PM PDT 24 43154697 ps
T603 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2065637259 Jul 26 05:27:13 PM PDT 24 Jul 26 05:27:14 PM PDT 24 11344315 ps
T85 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2027199427 Jul 26 05:27:05 PM PDT 24 Jul 26 05:27:06 PM PDT 24 67153716 ps
T604 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3770473173 Jul 26 05:27:37 PM PDT 24 Jul 26 05:27:38 PM PDT 24 38054938 ps
T605 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2586996312 Jul 26 05:26:55 PM PDT 24 Jul 26 05:26:56 PM PDT 24 22526234 ps
T606 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1456023514 Jul 26 05:27:25 PM PDT 24 Jul 26 05:27:26 PM PDT 24 36037005 ps
T86 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1349109707 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:11 PM PDT 24 250144581 ps
T607 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3598699784 Jul 26 05:27:07 PM PDT 24 Jul 26 05:27:10 PM PDT 24 96051053 ps
T608 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3334806618 Jul 26 05:27:01 PM PDT 24 Jul 26 05:27:08 PM PDT 24 1242973893 ps
T609 /workspace/coverage/cover_reg_top/29.hmac_intr_test.153830065 Jul 26 05:27:23 PM PDT 24 Jul 26 05:27:24 PM PDT 24 99488060 ps
T610 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.248696035 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:05 PM PDT 24 158914145 ps
T611 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1964340945 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:11 PM PDT 24 202407634 ps
T612 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1156257768 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:12 PM PDT 24 69150544 ps
T613 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3141990144 Jul 26 05:27:21 PM PDT 24 Jul 26 05:27:21 PM PDT 24 38105757 ps
T614 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4142380872 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:27 PM PDT 24 141135209 ps
T615 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2896468500 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:22 PM PDT 24 44413696 ps
T616 /workspace/coverage/cover_reg_top/2.hmac_intr_test.4057739707 Jul 26 05:27:02 PM PDT 24 Jul 26 05:27:03 PM PDT 24 40220321 ps
T617 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1211292560 Jul 26 05:27:31 PM PDT 24 Jul 26 05:27:33 PM PDT 24 249667556 ps
T618 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3039670390 Jul 26 05:27:01 PM PDT 24 Jul 26 05:27:02 PM PDT 24 129036400 ps
T619 /workspace/coverage/cover_reg_top/41.hmac_intr_test.328870158 Jul 26 05:27:25 PM PDT 24 Jul 26 05:27:26 PM PDT 24 13031785 ps
T620 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1449139505 Jul 26 05:27:17 PM PDT 24 Jul 26 05:27:20 PM PDT 24 127967251 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2780778007 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:24 PM PDT 24 56044603 ps
T622 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3335737952 Jul 26 05:27:07 PM PDT 24 Jul 26 05:27:13 PM PDT 24 1505543700 ps
T623 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3586489619 Jul 26 05:27:17 PM PDT 24 Jul 26 05:27:21 PM PDT 24 204981558 ps
T624 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1783581848 Jul 26 05:26:55 PM PDT 24 Jul 26 05:26:56 PM PDT 24 10693842 ps
T625 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3449876328 Jul 26 05:27:36 PM PDT 24 Jul 26 05:27:37 PM PDT 24 44111375 ps
T626 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2069311567 Jul 26 05:27:31 PM PDT 24 Jul 26 05:27:32 PM PDT 24 14644389 ps
T627 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3184023788 Jul 26 05:27:17 PM PDT 24 Jul 26 05:27:22 PM PDT 24 253359156 ps
T628 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1408830960 Jul 26 05:26:55 PM PDT 24 Jul 26 05:26:58 PM PDT 24 65447171 ps
T629 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2670194938 Jul 26 05:27:19 PM PDT 24 Jul 26 05:27:20 PM PDT 24 18263014 ps
T630 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3445601567 Jul 26 05:27:18 PM PDT 24 Jul 26 05:27:19 PM PDT 24 26279467 ps
T631 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1410157278 Jul 26 05:27:35 PM PDT 24 Jul 26 05:27:36 PM PDT 24 199180549 ps
T632 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3533368575 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:25 PM PDT 24 44032565 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3662352670 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:08 PM PDT 24 110797636 ps
T634 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3754599722 Jul 26 05:27:36 PM PDT 24 Jul 26 05:27:37 PM PDT 24 16037275 ps
T635 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3907293667 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:22 PM PDT 24 92880191 ps
T636 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2133117153 Jul 26 05:27:02 PM PDT 24 Jul 26 05:27:03 PM PDT 24 22632529 ps
T637 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.657212121 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:12 PM PDT 24 110239638 ps
T103 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.876644069 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:28 PM PDT 24 726197357 ps
T638 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2011099240 Jul 26 05:27:11 PM PDT 24 Jul 26 05:27:13 PM PDT 24 347466284 ps
T639 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1676555313 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:06 PM PDT 24 10719781 ps
T640 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3722935494 Jul 26 05:27:07 PM PDT 24 Jul 26 05:27:10 PM PDT 24 115634353 ps
T641 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3935466224 Jul 26 05:27:03 PM PDT 24 Jul 26 05:27:05 PM PDT 24 90582827 ps
T642 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4279636323 Jul 26 05:27:01 PM PDT 24 Jul 26 05:27:02 PM PDT 24 14304851 ps
T643 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1446632952 Jul 26 05:27:15 PM PDT 24 Jul 26 05:27:17 PM PDT 24 562507887 ps
T644 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2265940986 Jul 26 05:27:10 PM PDT 24 Jul 26 05:27:11 PM PDT 24 11913371 ps
T645 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3931326269 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:25 PM PDT 24 17232157 ps
T646 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1492368678 Jul 26 05:27:15 PM PDT 24 Jul 26 05:27:17 PM PDT 24 244004175 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1539000847 Jul 26 05:27:08 PM PDT 24 Jul 26 05:27:10 PM PDT 24 120546997 ps
T52 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1670842831 Jul 26 05:27:11 PM PDT 24 Jul 26 05:27:15 PM PDT 24 1011973613 ps
T648 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1186864356 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:22 PM PDT 24 14452323 ps
T649 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2649325459 Jul 26 05:27:17 PM PDT 24 Jul 26 05:27:19 PM PDT 24 169842825 ps
T650 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4217264150 Jul 26 05:27:05 PM PDT 24 Jul 26 05:27:08 PM PDT 24 92111145 ps
T651 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4076128645 Jul 26 05:27:15 PM PDT 24 Jul 26 05:46:23 PM PDT 24 78816041926 ps
T652 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.688422324 Jul 26 05:27:08 PM PDT 24 Jul 26 05:27:10 PM PDT 24 87474866 ps
T653 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4243513047 Jul 26 05:27:24 PM PDT 24 Jul 26 05:27:26 PM PDT 24 79200627 ps
T654 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.713276106 Jul 26 05:27:04 PM PDT 24 Jul 26 05:27:05 PM PDT 24 42044184 ps
T655 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3034106495 Jul 26 05:27:23 PM PDT 24 Jul 26 05:27:24 PM PDT 24 13391650 ps
T656 /workspace/coverage/cover_reg_top/43.hmac_intr_test.861090594 Jul 26 05:27:37 PM PDT 24 Jul 26 05:27:37 PM PDT 24 35178175 ps
T657 /workspace/coverage/cover_reg_top/10.hmac_intr_test.219655702 Jul 26 05:27:06 PM PDT 24 Jul 26 05:27:06 PM PDT 24 21372383 ps
T658 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2974762022 Jul 26 05:27:11 PM PDT 24 Jul 26 05:44:19 PM PDT 24 2209621263188 ps
T659 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1682283815 Jul 26 05:27:03 PM PDT 24 Jul 26 05:27:05 PM PDT 24 64010497 ps
T660 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2613875659 Jul 26 05:27:22 PM PDT 24 Jul 26 05:27:23 PM PDT 24 23993493 ps

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3282531591
Short name T6
Test name
Test status
Simulation time 1141478392420 ps
CPU time 9661.25 seconds
Started Jul 26 06:02:43 PM PDT 24
Finished Jul 26 08:43:45 PM PDT 24
Peak memory 947764 kb
Host smart-14468de0-f1d9-4424-af37-e0c4d0e83e11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282531591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3282531591
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2018621140
Short name T8
Test name
Test status
Simulation time 24924037002 ps
CPU time 1370.4 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:29:06 PM PDT 24
Peak memory 216028 kb
Host smart-52a47c07-1625-4925-a911-6213ed63d4c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018621140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2018621140
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.890927788
Short name T51
Test name
Test status
Simulation time 226436228 ps
CPU time 4.4 seconds
Started Jul 26 05:27:02 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 199896 kb
Host smart-c73ac8d3-0ac9-4bde-8381-794e552cf30f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890927788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.890927788
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1684400944
Short name T34
Test name
Test status
Simulation time 13508492 ps
CPU time 0.58 seconds
Started Jul 26 06:04:17 PM PDT 24
Finished Jul 26 06:04:17 PM PDT 24
Peak memory 195624 kb
Host smart-d6d29d1b-52c2-4778-8247-88cc7c263e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684400944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1684400944
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2877718304
Short name T75
Test name
Test status
Simulation time 82581672 ps
CPU time 0.93 seconds
Started Jul 26 05:27:11 PM PDT 24
Finished Jul 26 05:27:12 PM PDT 24
Peak memory 199680 kb
Host smart-03c4ab82-18cd-465a-925d-230482b25b47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877718304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2877718304
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2899524188
Short name T38
Test name
Test status
Simulation time 237365573 ps
CPU time 0.94 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:02:10 PM PDT 24
Peak memory 219364 kb
Host smart-21b84937-15af-4a0f-9196-dfb428ea31e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899524188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2899524188
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4139407885
Short name T334
Test name
Test status
Simulation time 55327991724 ps
CPU time 3537.11 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 07:04:00 PM PDT 24
Peak memory 826152 kb
Host smart-25b0829f-6f97-4c14-95b5-4a5061e67c1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139407885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4139407885
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3483992421
Short name T10
Test name
Test status
Simulation time 1117806248334 ps
CPU time 2956.29 seconds
Started Jul 26 06:05:07 PM PDT 24
Finished Jul 26 06:54:24 PM PDT 24
Peak memory 792192 kb
Host smart-a1f5f3df-9238-4e2c-bde4-ebfe9d643630
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483992421 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3483992421
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3817730750
Short name T100
Test name
Test status
Simulation time 2410150730 ps
CPU time 4.4 seconds
Started Jul 26 05:26:53 PM PDT 24
Finished Jul 26 05:26:58 PM PDT 24
Peak memory 199876 kb
Host smart-621705d1-f198-462c-9dbe-1c867adfc215
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817730750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3817730750
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3518227370
Short name T104
Test name
Test status
Simulation time 496302969 ps
CPU time 4.05 seconds
Started Jul 26 05:27:16 PM PDT 24
Finished Jul 26 05:27:21 PM PDT 24
Peak memory 199864 kb
Host smart-945dcdae-a326-43a7-91da-e996ce4206a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518227370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3518227370
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1670842831
Short name T52
Test name
Test status
Simulation time 1011973613 ps
CPU time 3.22 seconds
Started Jul 26 05:27:11 PM PDT 24
Finished Jul 26 05:27:15 PM PDT 24
Peak memory 199812 kb
Host smart-8d1bd833-a85e-4d55-93df-556d43f5bebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670842831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1670842831
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3051491725
Short name T13
Test name
Test status
Simulation time 81127845769 ps
CPU time 1735.29 seconds
Started Jul 26 06:02:07 PM PDT 24
Finished Jul 26 06:31:03 PM PDT 24
Peak memory 625872 kb
Host smart-feaf2545-4b79-49f1-8180-1acb2d815e31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3051491725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3051491725
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2133504535
Short name T249
Test name
Test status
Simulation time 7253723065 ps
CPU time 76.83 seconds
Started Jul 26 06:03:05 PM PDT 24
Finished Jul 26 06:04:22 PM PDT 24
Peak memory 199656 kb
Host smart-12e2ea80-5b5c-4aee-97ee-496c1a9fbc44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133504535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2133504535
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1349109707
Short name T86
Test name
Test status
Simulation time 250144581 ps
CPU time 5.14 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:11 PM PDT 24
Peak memory 199840 kb
Host smart-8ded340c-e8e2-4dd0-a8d2-a7863998a4d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349109707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1349109707
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4153156014
Short name T72
Test name
Test status
Simulation time 187382736 ps
CPU time 5.29 seconds
Started Jul 26 05:26:53 PM PDT 24
Finished Jul 26 05:26:59 PM PDT 24
Peak memory 198320 kb
Host smart-37155f75-0da5-41de-9a6f-9071b5f3b7de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153156014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4153156014
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2586996312
Short name T605
Test name
Test status
Simulation time 22526234 ps
CPU time 0.96 seconds
Started Jul 26 05:26:55 PM PDT 24
Finished Jul 26 05:26:56 PM PDT 24
Peak memory 199664 kb
Host smart-afedde1f-f079-40b2-b0b0-8ec540c074ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586996312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2586996312
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2837645171
Short name T553
Test name
Test status
Simulation time 773750677 ps
CPU time 1.29 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199820 kb
Host smart-5ead23db-c028-4c54-af0e-6fca00ceb82d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837645171 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2837645171
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1053066063
Short name T73
Test name
Test status
Simulation time 16184866 ps
CPU time 0.68 seconds
Started Jul 26 05:26:52 PM PDT 24
Finished Jul 26 05:26:53 PM PDT 24
Peak memory 197384 kb
Host smart-f2c703d8-820c-4ab9-863d-e5d8528a2a4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053066063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1053066063
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1783581848
Short name T624
Test name
Test status
Simulation time 10693842 ps
CPU time 0.58 seconds
Started Jul 26 05:26:55 PM PDT 24
Finished Jul 26 05:26:56 PM PDT 24
Peak memory 194760 kb
Host smart-333be391-cffa-4fa3-888f-5a3f22e68a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783581848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1783581848
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3776423766
Short name T560
Test name
Test status
Simulation time 34340076 ps
CPU time 1.63 seconds
Started Jul 26 05:27:08 PM PDT 24
Finished Jul 26 05:27:10 PM PDT 24
Peak memory 199824 kb
Host smart-624c15ab-2303-45c0-9642-2699bb0fb62a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776423766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3776423766
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1408830960
Short name T628
Test name
Test status
Simulation time 65447171 ps
CPU time 3.55 seconds
Started Jul 26 05:26:55 PM PDT 24
Finished Jul 26 05:26:58 PM PDT 24
Peak memory 199784 kb
Host smart-7127c965-144c-4649-a37d-43388d0b8bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408830960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1408830960
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3334806618
Short name T608
Test name
Test status
Simulation time 1242973893 ps
CPU time 6.18 seconds
Started Jul 26 05:27:01 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199808 kb
Host smart-d1d17dfd-c1c4-46e3-b39b-7018fa64ac48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334806618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3334806618
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.358173581
Short name T562
Test name
Test status
Simulation time 1322190448 ps
CPU time 6.01 seconds
Started Jul 26 05:27:01 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 199844 kb
Host smart-5cc59dc7-ac9f-4189-b432-2b39d70619f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358173581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.358173581
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2133117153
Short name T636
Test name
Test status
Simulation time 22632529 ps
CPU time 0.75 seconds
Started Jul 26 05:27:02 PM PDT 24
Finished Jul 26 05:27:03 PM PDT 24
Peak memory 198204 kb
Host smart-5cb56085-df5a-469b-9558-10e3350bb854
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133117153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2133117153
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2231520804
Short name T541
Test name
Test status
Simulation time 509747534478 ps
CPU time 837.15 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:41:02 PM PDT 24
Peak memory 216348 kb
Host smart-93894979-1949-47df-9fbf-e0962f3d7d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231520804 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2231520804
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2446973867
Short name T579
Test name
Test status
Simulation time 65264493 ps
CPU time 0.9 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199512 kb
Host smart-5715149e-9c3e-4ac0-8e5c-3d039403703e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446973867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2446973867
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.457746872
Short name T574
Test name
Test status
Simulation time 26023991 ps
CPU time 0.61 seconds
Started Jul 26 05:27:05 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 194720 kb
Host smart-9442c288-a82c-40dc-99f5-f3e778c4f2bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457746872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.457746872
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1854153547
Short name T576
Test name
Test status
Simulation time 194190950 ps
CPU time 1.3 seconds
Started Jul 26 05:27:02 PM PDT 24
Finished Jul 26 05:27:03 PM PDT 24
Peak memory 199568 kb
Host smart-9f83866e-7f57-43a2-8dd9-8ef1437c72dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854153547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1854153547
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3662352670
Short name T633
Test name
Test status
Simulation time 110797636 ps
CPU time 2.06 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199772 kb
Host smart-43bc7eb7-d8f1-4321-a17f-6607c6e1c68d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662352670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3662352670
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1682283815
Short name T659
Test name
Test status
Simulation time 64010497 ps
CPU time 1.71 seconds
Started Jul 26 05:27:03 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199840 kb
Host smart-632e88d4-33d9-4872-a0e2-a2cec5f58c87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682283815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1682283815
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2197261154
Short name T582
Test name
Test status
Simulation time 30346872 ps
CPU time 1.61 seconds
Started Jul 26 05:27:17 PM PDT 24
Finished Jul 26 05:27:18 PM PDT 24
Peak memory 200004 kb
Host smart-1ab142ea-914d-4586-9687-bbdc8e6415f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197261154 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2197261154
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1964340945
Short name T611
Test name
Test status
Simulation time 202407634 ps
CPU time 0.96 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:11 PM PDT 24
Peak memory 199676 kb
Host smart-5aa1be15-26a8-42dd-8f71-e7fca1652bc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964340945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1964340945
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.219655702
Short name T657
Test name
Test status
Simulation time 21372383 ps
CPU time 0.56 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 194744 kb
Host smart-1f674b53-6b23-4995-b2f8-3bb56fc49224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219655702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.219655702
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2492823385
Short name T87
Test name
Test status
Simulation time 25468651 ps
CPU time 1.13 seconds
Started Jul 26 05:27:19 PM PDT 24
Finished Jul 26 05:27:20 PM PDT 24
Peak memory 199792 kb
Host smart-e192cedb-1ef3-4d63-a491-205c0b0f5981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492823385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2492823385
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2714583599
Short name T555
Test name
Test status
Simulation time 114644102 ps
CPU time 1.63 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199864 kb
Host smart-3375d537-2c61-4ec1-b998-f426d8d63a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714583599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2714583599
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3598699784
Short name T607
Test name
Test status
Simulation time 96051053 ps
CPU time 2.93 seconds
Started Jul 26 05:27:07 PM PDT 24
Finished Jul 26 05:27:10 PM PDT 24
Peak memory 199876 kb
Host smart-f1241d0e-b5c2-4b17-a11f-9cdc93fbafc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598699784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3598699784
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1492368678
Short name T646
Test name
Test status
Simulation time 244004175 ps
CPU time 1.84 seconds
Started Jul 26 05:27:15 PM PDT 24
Finished Jul 26 05:27:17 PM PDT 24
Peak memory 199916 kb
Host smart-12d6967b-9e89-471c-a9db-47f8b2945e42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492368678 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1492368678
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3014978597
Short name T571
Test name
Test status
Simulation time 59578314 ps
CPU time 0.97 seconds
Started Jul 26 05:27:15 PM PDT 24
Finished Jul 26 05:27:16 PM PDT 24
Peak memory 199636 kb
Host smart-9c78e81f-f332-4e3a-aed8-01bc7054add3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014978597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3014978597
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2570564242
Short name T593
Test name
Test status
Simulation time 17862554 ps
CPU time 0.63 seconds
Started Jul 26 05:27:21 PM PDT 24
Finished Jul 26 05:27:21 PM PDT 24
Peak memory 194732 kb
Host smart-106d2641-e79f-441b-bd7c-94c457475422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570564242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2570564242
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1535805913
Short name T595
Test name
Test status
Simulation time 23128591 ps
CPU time 1.12 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:23 PM PDT 24
Peak memory 198364 kb
Host smart-e7330082-892f-4bb1-9771-e28c8a84b864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535805913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1535805913
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1449139505
Short name T620
Test name
Test status
Simulation time 127967251 ps
CPU time 2.75 seconds
Started Jul 26 05:27:17 PM PDT 24
Finished Jul 26 05:27:20 PM PDT 24
Peak memory 199852 kb
Host smart-1ece2789-2bd2-4e15-92a6-0badc519a92a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449139505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1449139505
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3289068925
Short name T50
Test name
Test status
Simulation time 214264088 ps
CPU time 4.18 seconds
Started Jul 26 05:27:12 PM PDT 24
Finished Jul 26 05:27:16 PM PDT 24
Peak memory 199868 kb
Host smart-04825ebe-cfb8-4095-82b2-196a056be8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289068925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3289068925
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2844408809
Short name T583
Test name
Test status
Simulation time 45449219 ps
CPU time 1.68 seconds
Started Jul 26 05:27:13 PM PDT 24
Finished Jul 26 05:27:15 PM PDT 24
Peak memory 199820 kb
Host smart-01ca7ef7-c54d-4cab-ae98-eb9288a4602b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844408809 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2844408809
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1483757905
Short name T539
Test name
Test status
Simulation time 31949001 ps
CPU time 0.72 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:25 PM PDT 24
Peak memory 197832 kb
Host smart-a7deed50-9e24-48fc-9973-1af2aa86db5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483757905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1483757905
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1373350923
Short name T590
Test name
Test status
Simulation time 13225267 ps
CPU time 0.61 seconds
Started Jul 26 05:27:12 PM PDT 24
Finished Jul 26 05:27:13 PM PDT 24
Peak memory 194892 kb
Host smart-a5621383-20f3-431d-8ad0-dc56c674d5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373350923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1373350923
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.783958822
Short name T572
Test name
Test status
Simulation time 119515077 ps
CPU time 2.32 seconds
Started Jul 26 05:27:13 PM PDT 24
Finished Jul 26 05:27:16 PM PDT 24
Peak memory 199768 kb
Host smart-fb25ebb8-c4f7-4044-b7df-7834f4a7c268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783958822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.783958822
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3680187345
Short name T542
Test name
Test status
Simulation time 109672537 ps
CPU time 2.19 seconds
Started Jul 26 05:27:12 PM PDT 24
Finished Jul 26 05:27:14 PM PDT 24
Peak memory 199768 kb
Host smart-07b2455f-e2bc-45cc-ae69-201a9e0cbedd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680187345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3680187345
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4142380872
Short name T614
Test name
Test status
Simulation time 141135209 ps
CPU time 1.89 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:27 PM PDT 24
Peak memory 199796 kb
Host smart-0d066cea-ec74-4e3c-b45e-5805220212b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142380872 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4142380872
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.283867187
Short name T78
Test name
Test status
Simulation time 55121273 ps
CPU time 0.93 seconds
Started Jul 26 05:27:21 PM PDT 24
Finished Jul 26 05:27:23 PM PDT 24
Peak memory 199632 kb
Host smart-919a75d5-0b2d-4a02-93ef-f04eda1ccc98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283867187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.283867187
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2896468500
Short name T615
Test name
Test status
Simulation time 44413696 ps
CPU time 0.56 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 194672 kb
Host smart-6b2d6815-364f-4a27-a803-5411961a8e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896468500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2896468500
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3939244950
Short name T94
Test name
Test status
Simulation time 33989021 ps
CPU time 1.64 seconds
Started Jul 26 05:27:21 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 199840 kb
Host smart-ae662eb2-bd6e-4b96-8b88-eb99bcc1d21f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939244950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3939244950
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1409019406
Short name T535
Test name
Test status
Simulation time 85287383 ps
CPU time 4.17 seconds
Started Jul 26 05:27:16 PM PDT 24
Finished Jul 26 05:27:20 PM PDT 24
Peak memory 199868 kb
Host smart-53829101-0124-4289-8f13-ee52754ff0ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409019406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1409019406
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.597169815
Short name T99
Test name
Test status
Simulation time 500663233 ps
CPU time 3.98 seconds
Started Jul 26 05:27:15 PM PDT 24
Finished Jul 26 05:27:19 PM PDT 24
Peak memory 199760 kb
Host smart-70cad988-ee97-44d5-81be-4bb60910294d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597169815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.597169815
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4076128645
Short name T651
Test name
Test status
Simulation time 78816041926 ps
CPU time 1147.83 seconds
Started Jul 26 05:27:15 PM PDT 24
Finished Jul 26 05:46:23 PM PDT 24
Peak memory 217248 kb
Host smart-0a753167-ee34-41f6-a332-d52af6cf00d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076128645 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4076128645
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2460428398
Short name T76
Test name
Test status
Simulation time 26648845 ps
CPU time 0.79 seconds
Started Jul 26 05:27:18 PM PDT 24
Finished Jul 26 05:27:19 PM PDT 24
Peak memory 199020 kb
Host smart-01f31b18-5cb5-404c-a73a-d48d0e1abe60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460428398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2460428398
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4252510702
Short name T559
Test name
Test status
Simulation time 11547310 ps
CPU time 0.6 seconds
Started Jul 26 05:27:17 PM PDT 24
Finished Jul 26 05:27:17 PM PDT 24
Peak memory 194776 kb
Host smart-2db96df5-fab3-4a06-a668-91522dcdfe45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252510702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4252510702
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2366845669
Short name T89
Test name
Test status
Simulation time 90229509 ps
CPU time 1.68 seconds
Started Jul 26 05:27:12 PM PDT 24
Finished Jul 26 05:27:14 PM PDT 24
Peak memory 199996 kb
Host smart-f65e0890-e551-4bc6-9735-81bebf8c55cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366845669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2366845669
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3586489619
Short name T623
Test name
Test status
Simulation time 204981558 ps
CPU time 4.04 seconds
Started Jul 26 05:27:17 PM PDT 24
Finished Jul 26 05:27:21 PM PDT 24
Peak memory 199944 kb
Host smart-6cdbb292-6bd7-47de-a117-0c59b3dcd934
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586489619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3586489619
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2323650310
Short name T96
Test name
Test status
Simulation time 82886264 ps
CPU time 1.75 seconds
Started Jul 26 05:27:15 PM PDT 24
Finished Jul 26 05:27:17 PM PDT 24
Peak memory 199780 kb
Host smart-8b9af04b-2af9-41a5-b4a7-337235e497a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323650310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2323650310
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1446632952
Short name T643
Test name
Test status
Simulation time 562507887 ps
CPU time 1.68 seconds
Started Jul 26 05:27:15 PM PDT 24
Finished Jul 26 05:27:17 PM PDT 24
Peak memory 199888 kb
Host smart-72af6680-c940-4f56-87da-8be0bf79c4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446632952 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1446632952
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1244253487
Short name T594
Test name
Test status
Simulation time 14925188 ps
CPU time 0.82 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:25 PM PDT 24
Peak memory 199300 kb
Host smart-cca9cd06-cb2c-4558-b02f-5f0f142851cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244253487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1244253487
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2065637259
Short name T603
Test name
Test status
Simulation time 11344315 ps
CPU time 0.59 seconds
Started Jul 26 05:27:13 PM PDT 24
Finished Jul 26 05:27:14 PM PDT 24
Peak memory 194704 kb
Host smart-d0fccb19-59f0-43e8-828a-4b80899f0f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065637259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2065637259
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1235946657
Short name T580
Test name
Test status
Simulation time 23321736 ps
CPU time 1.1 seconds
Started Jul 26 05:27:23 PM PDT 24
Finished Jul 26 05:27:24 PM PDT 24
Peak memory 198176 kb
Host smart-c4f7a697-8bbf-4eb6-8154-d9b8e3ba93a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235946657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1235946657
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3184023788
Short name T627
Test name
Test status
Simulation time 253359156 ps
CPU time 4.36 seconds
Started Jul 26 05:27:17 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 199848 kb
Host smart-b970819d-3fea-4885-b67f-d43da38cebf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184023788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3184023788
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1094320870
Short name T98
Test name
Test status
Simulation time 91150960 ps
CPU time 2.8 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:27 PM PDT 24
Peak memory 199840 kb
Host smart-55dc0b93-27aa-44ea-9007-e17ad0058c46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094320870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1094320870
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4243513047
Short name T653
Test name
Test status
Simulation time 79200627 ps
CPU time 2.62 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:26 PM PDT 24
Peak memory 208040 kb
Host smart-b63a0ead-d933-41aa-9d66-980d12958bd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243513047 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4243513047
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3912228234
Short name T586
Test name
Test status
Simulation time 34618879 ps
CPU time 0.7 seconds
Started Jul 26 05:27:13 PM PDT 24
Finished Jul 26 05:27:14 PM PDT 24
Peak memory 197756 kb
Host smart-db84e6da-3c44-4b76-bf6b-e98eae96181c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912228234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3912228234
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3445601567
Short name T630
Test name
Test status
Simulation time 26279467 ps
CPU time 0.63 seconds
Started Jul 26 05:27:18 PM PDT 24
Finished Jul 26 05:27:19 PM PDT 24
Peak memory 194732 kb
Host smart-a2e167b0-03fb-4e4b-8f4d-532c96642344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445601567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3445601567
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1330653770
Short name T88
Test name
Test status
Simulation time 192575199 ps
CPU time 1.18 seconds
Started Jul 26 05:27:20 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 199736 kb
Host smart-0d576788-4955-4b2c-8efe-3bf33f9079bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330653770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1330653770
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3589661555
Short name T551
Test name
Test status
Simulation time 305705449 ps
CPU time 1.79 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:24 PM PDT 24
Peak memory 199796 kb
Host smart-0df7a3e3-b6c8-40a8-8a6a-62479449b2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589661555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3589661555
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1694360297
Short name T588
Test name
Test status
Simulation time 135091918 ps
CPU time 1.95 seconds
Started Jul 26 05:27:13 PM PDT 24
Finished Jul 26 05:27:15 PM PDT 24
Peak memory 199896 kb
Host smart-3f5e6af6-2ec4-4345-9875-82fd4dc12a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694360297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1694360297
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4262719073
Short name T534
Test name
Test status
Simulation time 23304551025 ps
CPU time 225.08 seconds
Started Jul 26 05:27:16 PM PDT 24
Finished Jul 26 05:31:02 PM PDT 24
Peak memory 215684 kb
Host smart-85b4cf4d-3bb3-4213-b311-12baf79a4093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262719073 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4262719073
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2670194938
Short name T629
Test name
Test status
Simulation time 18263014 ps
CPU time 0.8 seconds
Started Jul 26 05:27:19 PM PDT 24
Finished Jul 26 05:27:20 PM PDT 24
Peak memory 198900 kb
Host smart-e9709eb6-8d52-45d5-9c61-fe80a88dfc54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670194938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2670194938
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2780778007
Short name T621
Test name
Test status
Simulation time 56044603 ps
CPU time 0.59 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:24 PM PDT 24
Peak memory 194828 kb
Host smart-1da686e4-d7d3-4249-ad55-0c617888dc6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780778007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2780778007
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3394657129
Short name T570
Test name
Test status
Simulation time 105597700 ps
CPU time 1.16 seconds
Started Jul 26 05:27:30 PM PDT 24
Finished Jul 26 05:27:32 PM PDT 24
Peak memory 199592 kb
Host smart-92330b70-cf2d-4510-80d2-7122e710662a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394657129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3394657129
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1086806662
Short name T552
Test name
Test status
Simulation time 332103155 ps
CPU time 3.57 seconds
Started Jul 26 05:27:14 PM PDT 24
Finished Jul 26 05:27:18 PM PDT 24
Peak memory 199864 kb
Host smart-f8346426-219e-44d2-a42b-961aa9dd239e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086806662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1086806662
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1866758573
Short name T581
Test name
Test status
Simulation time 43462514 ps
CPU time 2.78 seconds
Started Jul 26 05:27:28 PM PDT 24
Finished Jul 26 05:27:31 PM PDT 24
Peak memory 215412 kb
Host smart-37c2ab48-c95c-4c50-a1d1-535e3380523e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866758573 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1866758573
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2047500860
Short name T561
Test name
Test status
Simulation time 23950046 ps
CPU time 0.7 seconds
Started Jul 26 05:27:18 PM PDT 24
Finished Jul 26 05:27:19 PM PDT 24
Peak memory 197672 kb
Host smart-dacd48bf-8ea1-4b76-81cf-bd708d3d79e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047500860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2047500860
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3141990144
Short name T613
Test name
Test status
Simulation time 38105757 ps
CPU time 0.61 seconds
Started Jul 26 05:27:21 PM PDT 24
Finished Jul 26 05:27:21 PM PDT 24
Peak memory 194700 kb
Host smart-1227a7c9-3a7f-4549-83c9-d277c21cc0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141990144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3141990144
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3326464109
Short name T93
Test name
Test status
Simulation time 77751697 ps
CPU time 1.16 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:23 PM PDT 24
Peak memory 199772 kb
Host smart-3cf2161e-c054-4027-a9e8-1edab465c451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326464109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3326464109
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2649325459
Short name T649
Test name
Test status
Simulation time 169842825 ps
CPU time 2.13 seconds
Started Jul 26 05:27:17 PM PDT 24
Finished Jul 26 05:27:19 PM PDT 24
Peak memory 199864 kb
Host smart-a425c543-d729-49e3-9b4e-144aa86d3097
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649325459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2649325459
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3075732916
Short name T589
Test name
Test status
Simulation time 188241108 ps
CPU time 1.81 seconds
Started Jul 26 05:27:16 PM PDT 24
Finished Jul 26 05:27:18 PM PDT 24
Peak memory 199872 kb
Host smart-7aa3c343-eb9e-460f-8eee-85de04b9a14c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075732916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3075732916
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4068333440
Short name T591
Test name
Test status
Simulation time 42401067 ps
CPU time 1.23 seconds
Started Jul 26 05:27:25 PM PDT 24
Finished Jul 26 05:27:26 PM PDT 24
Peak memory 199680 kb
Host smart-4dd3efd4-bc74-42fb-a2ea-884fc48bcd19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068333440 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4068333440
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2065803783
Short name T92
Test name
Test status
Simulation time 25582364 ps
CPU time 0.85 seconds
Started Jul 26 05:27:23 PM PDT 24
Finished Jul 26 05:27:25 PM PDT 24
Peak memory 199180 kb
Host smart-9213b1b9-1fba-43cb-ae98-42999426fcb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065803783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2065803783
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1991779177
Short name T554
Test name
Test status
Simulation time 19452200 ps
CPU time 0.66 seconds
Started Jul 26 05:27:23 PM PDT 24
Finished Jul 26 05:27:23 PM PDT 24
Peak memory 194720 kb
Host smart-50e76a7f-5210-46d8-9df2-f171317752c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991779177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1991779177
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4154377894
Short name T575
Test name
Test status
Simulation time 50098067 ps
CPU time 1.12 seconds
Started Jul 26 05:27:31 PM PDT 24
Finished Jul 26 05:27:32 PM PDT 24
Peak memory 199684 kb
Host smart-8cb3a27b-1525-48bc-9881-ff7034aa6427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154377894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4154377894
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1211292560
Short name T617
Test name
Test status
Simulation time 249667556 ps
CPU time 2.65 seconds
Started Jul 26 05:27:31 PM PDT 24
Finished Jul 26 05:27:33 PM PDT 24
Peak memory 199656 kb
Host smart-45440f7b-0718-4a74-b6cd-365e538fa5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211292560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1211292560
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.876644069
Short name T103
Test name
Test status
Simulation time 726197357 ps
CPU time 3.26 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:28 PM PDT 24
Peak memory 199820 kb
Host smart-901b352d-28a1-43f7-a226-c9f45002db00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876644069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.876644069
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3118728677
Short name T546
Test name
Test status
Simulation time 729675967 ps
CPU time 3.21 seconds
Started Jul 26 05:27:03 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 199836 kb
Host smart-5bed58c8-7387-4179-bb6c-c408b3400228
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118728677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3118728677
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3335737952
Short name T622
Test name
Test status
Simulation time 1505543700 ps
CPU time 5.7 seconds
Started Jul 26 05:27:07 PM PDT 24
Finished Jul 26 05:27:13 PM PDT 24
Peak memory 199828 kb
Host smart-3156e3e8-baf6-4424-97c2-fdea4b4b1a88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335737952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3335737952
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3039670390
Short name T618
Test name
Test status
Simulation time 129036400 ps
CPU time 1.04 seconds
Started Jul 26 05:27:01 PM PDT 24
Finished Jul 26 05:27:02 PM PDT 24
Peak memory 199372 kb
Host smart-9f2ebfe5-cb8b-436b-b257-7aa9f1ba19b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039670390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3039670390
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2195667706
Short name T558
Test name
Test status
Simulation time 96848038668 ps
CPU time 340.65 seconds
Started Jul 26 05:27:08 PM PDT 24
Finished Jul 26 05:32:49 PM PDT 24
Peak memory 216316 kb
Host smart-3fdef4c7-b944-495b-b2ab-cf56ba0c9f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195667706 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2195667706
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.248696035
Short name T610
Test name
Test status
Simulation time 158914145 ps
CPU time 0.85 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199280 kb
Host smart-c7c93879-7adb-44ae-a07a-5903f66a0fff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248696035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.248696035
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4057739707
Short name T616
Test name
Test status
Simulation time 40220321 ps
CPU time 0.6 seconds
Started Jul 26 05:27:02 PM PDT 24
Finished Jul 26 05:27:03 PM PDT 24
Peak memory 194748 kb
Host smart-dd9d0a03-c296-487d-94a4-1c4eaeb92f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057739707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4057739707
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3456186411
Short name T600
Test name
Test status
Simulation time 23863034 ps
CPU time 1.19 seconds
Started Jul 26 05:27:01 PM PDT 24
Finished Jul 26 05:27:03 PM PDT 24
Peak memory 199680 kb
Host smart-c0bf0096-3ef3-42d8-a3cb-ab50a6ef040e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456186411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3456186411
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.490872841
Short name T577
Test name
Test status
Simulation time 172322488 ps
CPU time 2.41 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 199868 kb
Host smart-d0e4395f-59ce-41e2-8b22-7b6f1c1dd4b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490872841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.490872841
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3476510489
Short name T95
Test name
Test status
Simulation time 106364736 ps
CPU time 1.87 seconds
Started Jul 26 05:27:03 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199864 kb
Host smart-545773ee-8594-40b6-8095-3c68c7ab21df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476510489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3476510489
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3796262660
Short name T545
Test name
Test status
Simulation time 23359009 ps
CPU time 0.57 seconds
Started Jul 26 05:27:20 PM PDT 24
Finished Jul 26 05:27:21 PM PDT 24
Peak memory 194768 kb
Host smart-5c8dbb66-61af-4b41-a33c-8e92f6466cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796262660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3796262660
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2639389554
Short name T544
Test name
Test status
Simulation time 12736361 ps
CPU time 0.57 seconds
Started Jul 26 05:27:27 PM PDT 24
Finished Jul 26 05:27:28 PM PDT 24
Peak memory 194672 kb
Host smart-6048d4cc-4a8a-4522-873c-4e4510c4aa5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639389554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2639389554
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1186864356
Short name T648
Test name
Test status
Simulation time 14452323 ps
CPU time 0.58 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 194740 kb
Host smart-ee63775b-a35b-477a-8141-97ff60deef03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186864356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1186864356
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2684480559
Short name T548
Test name
Test status
Simulation time 41015233 ps
CPU time 0.59 seconds
Started Jul 26 05:27:25 PM PDT 24
Finished Jul 26 05:27:25 PM PDT 24
Peak memory 194712 kb
Host smart-9e27c92e-3a06-45b7-a0e7-4ba0e5ed0a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684480559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2684480559
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3193708120
Short name T547
Test name
Test status
Simulation time 39397298 ps
CPU time 0.6 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 194796 kb
Host smart-e18ad5ff-8473-4e7d-8e9c-a74097e947d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193708120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3193708120
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1915761080
Short name T598
Test name
Test status
Simulation time 25829801 ps
CPU time 0.6 seconds
Started Jul 26 05:27:21 PM PDT 24
Finished Jul 26 05:27:21 PM PDT 24
Peak memory 194752 kb
Host smart-1e57d91d-c5bb-4727-851e-0a534c09ab32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915761080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1915761080
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3931326269
Short name T645
Test name
Test status
Simulation time 17232157 ps
CPU time 0.63 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:25 PM PDT 24
Peak memory 194752 kb
Host smart-bfb00b00-e5e5-4a95-8e8f-02078917032c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931326269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3931326269
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2257924605
Short name T585
Test name
Test status
Simulation time 51607043 ps
CPU time 0.65 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:25 PM PDT 24
Peak memory 194784 kb
Host smart-513351d8-663b-483e-865c-46d64aee006e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257924605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2257924605
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4003306987
Short name T550
Test name
Test status
Simulation time 15312219 ps
CPU time 0.61 seconds
Started Jul 26 05:27:23 PM PDT 24
Finished Jul 26 05:27:24 PM PDT 24
Peak memory 194744 kb
Host smart-7deaa1e0-b94e-4b12-a5e0-c8498ffd44a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003306987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4003306987
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.153830065
Short name T609
Test name
Test status
Simulation time 99488060 ps
CPU time 0.59 seconds
Started Jul 26 05:27:23 PM PDT 24
Finished Jul 26 05:27:24 PM PDT 24
Peak memory 194812 kb
Host smart-208797a1-c48c-4452-a3c7-2c1685c1d137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153830065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.153830065
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2610132949
Short name T83
Test name
Test status
Simulation time 798586422 ps
CPU time 3.48 seconds
Started Jul 26 05:27:05 PM PDT 24
Finished Jul 26 05:27:09 PM PDT 24
Peak memory 199796 kb
Host smart-2f535ba7-7f56-4ddb-ad1a-621453fac6c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610132949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2610132949
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2311671313
Short name T84
Test name
Test status
Simulation time 2840471941 ps
CPU time 11.41 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:17 PM PDT 24
Peak memory 199936 kb
Host smart-ec1d7890-9ffc-4143-89e1-e116d8462f38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311671313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2311671313
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4201572992
Short name T77
Test name
Test status
Simulation time 21171460 ps
CPU time 0.76 seconds
Started Jul 26 05:27:07 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 198152 kb
Host smart-3c97ab98-f721-489b-bfac-a7445aaed2ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201572992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4201572992
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1315453569
Short name T569
Test name
Test status
Simulation time 132390642 ps
CPU time 1.14 seconds
Started Jul 26 05:27:05 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 199708 kb
Host smart-e9f2726d-b09d-43da-a898-5f8f9258dbff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315453569 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1315453569
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1886426539
Short name T587
Test name
Test status
Simulation time 107710887 ps
CPU time 0.81 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 199668 kb
Host smart-9b40b350-579b-4f84-9103-8a105cb8caf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886426539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1886426539
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4279636323
Short name T642
Test name
Test status
Simulation time 14304851 ps
CPU time 0.58 seconds
Started Jul 26 05:27:01 PM PDT 24
Finished Jul 26 05:27:02 PM PDT 24
Peak memory 194752 kb
Host smart-d8a62835-5d1b-44b0-9897-9421b47754d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279636323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4279636323
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3732224913
Short name T568
Test name
Test status
Simulation time 84908535 ps
CPU time 1.17 seconds
Started Jul 26 05:27:05 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 199708 kb
Host smart-0b37ab08-66d0-4a28-8aff-5ee2ca6f63b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732224913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3732224913
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2953596787
Short name T567
Test name
Test status
Simulation time 89412165 ps
CPU time 1.82 seconds
Started Jul 26 05:27:02 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199764 kb
Host smart-fdc8dffd-312e-4f08-b89c-23525b2edf86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953596787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2953596787
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2069311567
Short name T626
Test name
Test status
Simulation time 14644389 ps
CPU time 0.57 seconds
Started Jul 26 05:27:31 PM PDT 24
Finished Jul 26 05:27:32 PM PDT 24
Peak memory 194700 kb
Host smart-84a574cf-1588-439a-960c-4d3c9b6ecd1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069311567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2069311567
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2613875659
Short name T660
Test name
Test status
Simulation time 23993493 ps
CPU time 0.6 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:23 PM PDT 24
Peak memory 194696 kb
Host smart-8739f1d2-b9fc-48cf-bef9-abeffd3ade94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613875659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2613875659
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3533368575
Short name T632
Test name
Test status
Simulation time 44032565 ps
CPU time 0.62 seconds
Started Jul 26 05:27:24 PM PDT 24
Finished Jul 26 05:27:25 PM PDT 24
Peak memory 194708 kb
Host smart-19901408-d11b-4eaf-ab87-b84267d50032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533368575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3533368575
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3136524388
Short name T536
Test name
Test status
Simulation time 18953056 ps
CPU time 0.62 seconds
Started Jul 26 05:27:28 PM PDT 24
Finished Jul 26 05:27:29 PM PDT 24
Peak memory 194880 kb
Host smart-7f02da71-aa68-4ac4-81f8-5ff6be5df792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136524388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3136524388
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1701329751
Short name T565
Test name
Test status
Simulation time 31760743 ps
CPU time 0.64 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:23 PM PDT 24
Peak memory 194904 kb
Host smart-46ab9668-6bc6-472d-b756-cb99f8da8099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701329751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1701329751
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3907293667
Short name T635
Test name
Test status
Simulation time 92880191 ps
CPU time 0.63 seconds
Started Jul 26 05:27:22 PM PDT 24
Finished Jul 26 05:27:22 PM PDT 24
Peak memory 194900 kb
Host smart-c6f39127-a150-4816-bcbc-c6a8c597f1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907293667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3907293667
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3034106495
Short name T655
Test name
Test status
Simulation time 13391650 ps
CPU time 0.57 seconds
Started Jul 26 05:27:23 PM PDT 24
Finished Jul 26 05:27:24 PM PDT 24
Peak memory 194732 kb
Host smart-0d267500-38c2-4d47-89cf-652cec01eed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034106495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3034106495
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1338669282
Short name T533
Test name
Test status
Simulation time 22727388 ps
CPU time 0.57 seconds
Started Jul 26 05:27:25 PM PDT 24
Finished Jul 26 05:27:26 PM PDT 24
Peak memory 194724 kb
Host smart-b0235ab9-b528-45c1-be47-2dd8ca944a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338669282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1338669282
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3404723280
Short name T592
Test name
Test status
Simulation time 12504607 ps
CPU time 0.59 seconds
Started Jul 26 05:27:23 PM PDT 24
Finished Jul 26 05:27:23 PM PDT 24
Peak memory 194836 kb
Host smart-c925b64c-5097-4d2d-853d-d43f1c24d213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404723280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3404723280
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1453366537
Short name T557
Test name
Test status
Simulation time 27415957 ps
CPU time 0.59 seconds
Started Jul 26 05:27:27 PM PDT 24
Finished Jul 26 05:27:28 PM PDT 24
Peak memory 194688 kb
Host smart-b2b4c3da-33f1-4b9c-bdc4-d597db0ba408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453366537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1453366537
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2468093344
Short name T80
Test name
Test status
Simulation time 394997977 ps
CPU time 5.78 seconds
Started Jul 26 05:27:07 PM PDT 24
Finished Jul 26 05:27:13 PM PDT 24
Peak memory 199524 kb
Host smart-e920c6bb-d0a1-4bbf-a4fc-3d47e5777ac0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468093344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2468093344
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3170518038
Short name T564
Test name
Test status
Simulation time 1098482092 ps
CPU time 15.83 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:20 PM PDT 24
Peak memory 199884 kb
Host smart-2c297856-25c0-457a-a598-43d75acbc7f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170518038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3170518038
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2027199427
Short name T85
Test name
Test status
Simulation time 67153716 ps
CPU time 1.01 seconds
Started Jul 26 05:27:05 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 199456 kb
Host smart-598006f3-8f75-419a-8e32-d878310d7d00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027199427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2027199427
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4149599584
Short name T543
Test name
Test status
Simulation time 74638562 ps
CPU time 1.7 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199844 kb
Host smart-89047e64-105b-4b2f-b931-a2cc8474313f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149599584 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4149599584
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1676261499
Short name T74
Test name
Test status
Simulation time 183495153 ps
CPU time 0.67 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:11 PM PDT 24
Peak memory 198192 kb
Host smart-de1a55ad-bfa1-4264-99fe-24f42def2ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676261499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1676261499
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2616170246
Short name T556
Test name
Test status
Simulation time 45958762 ps
CPU time 0.62 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 194760 kb
Host smart-7bf9ba9b-0977-4bd5-9b2a-4eba5207ac88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616170246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2616170246
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3403720448
Short name T90
Test name
Test status
Simulation time 158696597 ps
CPU time 2.15 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199728 kb
Host smart-b9fb4002-98f5-4c3a-8d12-e43d7006f9e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403720448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3403720448
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1539000847
Short name T647
Test name
Test status
Simulation time 120546997 ps
CPU time 1.35 seconds
Started Jul 26 05:27:08 PM PDT 24
Finished Jul 26 05:27:10 PM PDT 24
Peak memory 199812 kb
Host smart-0c0d6808-0531-4b11-a0fd-1b3e266c458d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539000847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1539000847
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3125407306
Short name T101
Test name
Test status
Simulation time 152705926 ps
CPU time 3.07 seconds
Started Jul 26 05:27:03 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 199808 kb
Host smart-740d76d8-ac5c-4e4d-85dd-513947ebcc37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125407306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3125407306
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1456023514
Short name T606
Test name
Test status
Simulation time 36037005 ps
CPU time 0.56 seconds
Started Jul 26 05:27:25 PM PDT 24
Finished Jul 26 05:27:26 PM PDT 24
Peak memory 194728 kb
Host smart-05e7c219-21f3-4456-948e-d15a7adcfa61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456023514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1456023514
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.328870158
Short name T619
Test name
Test status
Simulation time 13031785 ps
CPU time 0.57 seconds
Started Jul 26 05:27:25 PM PDT 24
Finished Jul 26 05:27:26 PM PDT 24
Peak memory 194720 kb
Host smart-ae279b13-0964-4225-9cdd-13b93a5f79d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328870158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.328870158
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1656637680
Short name T538
Test name
Test status
Simulation time 115400920 ps
CPU time 0.57 seconds
Started Jul 26 05:27:26 PM PDT 24
Finished Jul 26 05:27:27 PM PDT 24
Peak memory 194680 kb
Host smart-1a477652-83fb-4864-a697-24589280b704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656637680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1656637680
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.861090594
Short name T656
Test name
Test status
Simulation time 35178175 ps
CPU time 0.59 seconds
Started Jul 26 05:27:37 PM PDT 24
Finished Jul 26 05:27:37 PM PDT 24
Peak memory 194636 kb
Host smart-3b3ada62-f66e-48af-903f-52c2ebac8939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861090594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.861090594
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3973750395
Short name T602
Test name
Test status
Simulation time 43154697 ps
CPU time 0.61 seconds
Started Jul 26 05:27:36 PM PDT 24
Finished Jul 26 05:27:37 PM PDT 24
Peak memory 194864 kb
Host smart-e92dd0dc-d140-4cc2-8937-11c24cf0d2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973750395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3973750395
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3449876328
Short name T625
Test name
Test status
Simulation time 44111375 ps
CPU time 0.66 seconds
Started Jul 26 05:27:36 PM PDT 24
Finished Jul 26 05:27:37 PM PDT 24
Peak memory 194716 kb
Host smart-eee503b9-104b-4efb-87d7-937f5a7c5c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449876328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3449876328
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3770473173
Short name T604
Test name
Test status
Simulation time 38054938 ps
CPU time 0.58 seconds
Started Jul 26 05:27:37 PM PDT 24
Finished Jul 26 05:27:38 PM PDT 24
Peak memory 194724 kb
Host smart-983ce313-0c70-45a2-96bf-ee1dc7dec349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770473173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3770473173
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3796675751
Short name T584
Test name
Test status
Simulation time 46414980 ps
CPU time 0.58 seconds
Started Jul 26 05:27:33 PM PDT 24
Finished Jul 26 05:27:34 PM PDT 24
Peak memory 194796 kb
Host smart-65257b2c-c3ce-4e6f-8a90-b5e7f3d152bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796675751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3796675751
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3754599722
Short name T634
Test name
Test status
Simulation time 16037275 ps
CPU time 0.64 seconds
Started Jul 26 05:27:36 PM PDT 24
Finished Jul 26 05:27:37 PM PDT 24
Peak memory 194788 kb
Host smart-b536d998-d7dc-47ca-a83a-477d9d7a9605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754599722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3754599722
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1410157278
Short name T631
Test name
Test status
Simulation time 199180549 ps
CPU time 0.62 seconds
Started Jul 26 05:27:35 PM PDT 24
Finished Jul 26 05:27:36 PM PDT 24
Peak memory 194756 kb
Host smart-3b0da589-f425-4bae-8168-fbd76b570c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410157278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1410157278
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4217264150
Short name T650
Test name
Test status
Simulation time 92111145 ps
CPU time 2.47 seconds
Started Jul 26 05:27:05 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199900 kb
Host smart-9b110648-0b2f-4dc3-b315-22d2edd90c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217264150 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4217264150
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.32255319
Short name T81
Test name
Test status
Simulation time 27557410 ps
CPU time 0.91 seconds
Started Jul 26 05:27:07 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199408 kb
Host smart-ae95a413-8291-4b05-8d7f-4a2a1a46a513
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32255319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.32255319
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2142525665
Short name T566
Test name
Test status
Simulation time 93632622 ps
CPU time 0.63 seconds
Started Jul 26 05:27:03 PM PDT 24
Finished Jul 26 05:27:04 PM PDT 24
Peak memory 194856 kb
Host smart-3e5bf233-f68e-4f42-92e3-42756e298a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142525665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2142525665
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.713276106
Short name T654
Test name
Test status
Simulation time 42044184 ps
CPU time 1.03 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199876 kb
Host smart-a942da9d-9ed6-45c0-b3ca-54e00c8f4085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713276106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.713276106
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3722935494
Short name T640
Test name
Test status
Simulation time 115634353 ps
CPU time 2.96 seconds
Started Jul 26 05:27:07 PM PDT 24
Finished Jul 26 05:27:10 PM PDT 24
Peak memory 199760 kb
Host smart-2dc84e4a-3efe-4c52-ab26-af4c2dc55c41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722935494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3722935494
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1583471736
Short name T578
Test name
Test status
Simulation time 110884460 ps
CPU time 1.91 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 199832 kb
Host smart-fbfb0546-a945-42fd-944f-e5f17b7cedbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583471736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1583471736
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1156257768
Short name T612
Test name
Test status
Simulation time 69150544 ps
CPU time 1.18 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:12 PM PDT 24
Peak memory 199784 kb
Host smart-c9fe849a-a36c-4b77-a664-6659f71472f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156257768 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1156257768
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.309992448
Short name T537
Test name
Test status
Simulation time 29066405 ps
CPU time 0.95 seconds
Started Jul 26 05:27:05 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 199300 kb
Host smart-40f797ed-5978-4205-be42-fd1d90b74689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309992448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.309992448
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1676555313
Short name T639
Test name
Test status
Simulation time 10719781 ps
CPU time 0.63 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:06 PM PDT 24
Peak memory 194844 kb
Host smart-d7f34d76-64cb-46ce-bb2a-c5882e44a993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676555313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1676555313
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1222902160
Short name T597
Test name
Test status
Simulation time 163623836 ps
CPU time 2.14 seconds
Started Jul 26 05:27:13 PM PDT 24
Finished Jul 26 05:27:15 PM PDT 24
Peak memory 199776 kb
Host smart-7006a328-052b-4835-8a79-b3d6adbef04a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222902160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1222902160
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.562959975
Short name T601
Test name
Test status
Simulation time 598043101 ps
CPU time 3.45 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:09 PM PDT 24
Peak memory 199908 kb
Host smart-5db5a192-cac7-401e-9a85-82eacbcd9249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562959975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.562959975
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2939598504
Short name T97
Test name
Test status
Simulation time 681411764 ps
CPU time 3.14 seconds
Started Jul 26 05:27:04 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 199884 kb
Host smart-34f1be95-d8c9-400f-9c06-db8cac181047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939598504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2939598504
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1017447152
Short name T563
Test name
Test status
Simulation time 256557603 ps
CPU time 2.54 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:13 PM PDT 24
Peak memory 199968 kb
Host smart-eb955170-91a2-4e53-81de-f0f130eac3ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017447152 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1017447152
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2265940986
Short name T644
Test name
Test status
Simulation time 11913371 ps
CPU time 0.57 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:11 PM PDT 24
Peak memory 194724 kb
Host smart-584dae27-f58c-43df-9ba4-9dc0f0cf0dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265940986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2265940986
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2011099240
Short name T638
Test name
Test status
Simulation time 347466284 ps
CPU time 1.6 seconds
Started Jul 26 05:27:11 PM PDT 24
Finished Jul 26 05:27:13 PM PDT 24
Peak memory 199944 kb
Host smart-5111510f-a4ff-44be-830f-bab2e67777b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011099240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2011099240
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3682925034
Short name T596
Test name
Test status
Simulation time 468891771 ps
CPU time 2.43 seconds
Started Jul 26 05:27:11 PM PDT 24
Finished Jul 26 05:27:14 PM PDT 24
Peak memory 199848 kb
Host smart-18dbdf89-4b79-464b-9af8-5b69c656b4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682925034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3682925034
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.560520198
Short name T49
Test name
Test status
Simulation time 204898047 ps
CPU time 1.81 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:13 PM PDT 24
Peak memory 199844 kb
Host smart-a5258266-3a5e-4574-a065-95161aa170d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560520198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.560520198
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2974762022
Short name T658
Test name
Test status
Simulation time 2209621263188 ps
CPU time 1028.03 seconds
Started Jul 26 05:27:11 PM PDT 24
Finished Jul 26 05:44:19 PM PDT 24
Peak memory 216644 kb
Host smart-417de106-7d5c-4686-943e-b0fd283eef9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974762022 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2974762022
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2612831765
Short name T79
Test name
Test status
Simulation time 52361217 ps
CPU time 0.8 seconds
Started Jul 26 05:27:07 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 198808 kb
Host smart-7c817e88-4c2c-4666-a906-30d80401f6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612831765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2612831765
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.4128541808
Short name T540
Test name
Test status
Simulation time 55820931 ps
CPU time 0.56 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:07 PM PDT 24
Peak memory 194684 kb
Host smart-21c2fe0c-a947-4452-b91d-0bf510d55344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128541808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.4128541808
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3728683144
Short name T91
Test name
Test status
Simulation time 224423533 ps
CPU time 1.19 seconds
Started Jul 26 05:27:09 PM PDT 24
Finished Jul 26 05:27:10 PM PDT 24
Peak memory 199616 kb
Host smart-abcb7898-cc24-4f3b-81ef-cdb8132c7ef1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728683144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3728683144
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3935466224
Short name T641
Test name
Test status
Simulation time 90582827 ps
CPU time 2.18 seconds
Started Jul 26 05:27:03 PM PDT 24
Finished Jul 26 05:27:05 PM PDT 24
Peak memory 199904 kb
Host smart-318b5ba0-69ae-4bb1-9c27-b5ef99d3d7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935466224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3935466224
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.334800521
Short name T599
Test name
Test status
Simulation time 313526722 ps
CPU time 1.84 seconds
Started Jul 26 05:27:06 PM PDT 24
Finished Jul 26 05:27:08 PM PDT 24
Peak memory 199820 kb
Host smart-9ab70a7e-fd0f-4871-8591-b97723642e68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334800521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.334800521
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.688422324
Short name T652
Test name
Test status
Simulation time 87474866 ps
CPU time 1.75 seconds
Started Jul 26 05:27:08 PM PDT 24
Finished Jul 26 05:27:10 PM PDT 24
Peak memory 199896 kb
Host smart-12306c35-df97-45ac-9006-5ae5107df114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688422324 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.688422324
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.617712544
Short name T82
Test name
Test status
Simulation time 64956910 ps
CPU time 0.93 seconds
Started Jul 26 05:27:11 PM PDT 24
Finished Jul 26 05:27:12 PM PDT 24
Peak memory 199500 kb
Host smart-ea519f20-c14d-428f-a865-a9531135a036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617712544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.617712544
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.229352333
Short name T549
Test name
Test status
Simulation time 12091717 ps
CPU time 0.56 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:11 PM PDT 24
Peak memory 194704 kb
Host smart-d4d03e4a-af9b-4491-a2ee-e870ede37a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229352333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.229352333
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.657212121
Short name T637
Test name
Test status
Simulation time 110239638 ps
CPU time 1.14 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:12 PM PDT 24
Peak memory 199564 kb
Host smart-5ddcf88b-74c4-40d3-864f-a4a55454d4b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657212121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.657212121
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2964718261
Short name T573
Test name
Test status
Simulation time 424198077 ps
CPU time 2.44 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:12 PM PDT 24
Peak memory 199856 kb
Host smart-000d1a55-41b2-43e6-940c-81e40999d838
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964718261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2964718261
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3613417693
Short name T102
Test name
Test status
Simulation time 1086551242 ps
CPU time 4.4 seconds
Started Jul 26 05:27:10 PM PDT 24
Finished Jul 26 05:27:15 PM PDT 24
Peak memory 199884 kb
Host smart-d83cf5c9-caba-4bd5-9b40-0ef8db7399ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613417693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3613417693
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1900320037
Short name T294
Test name
Test status
Simulation time 13549277 ps
CPU time 0.61 seconds
Started Jul 26 06:02:08 PM PDT 24
Finished Jul 26 06:02:09 PM PDT 24
Peak memory 196340 kb
Host smart-a51e2c41-787b-4447-8579-6e81f3907416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900320037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1900320037
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1919182064
Short name T326
Test name
Test status
Simulation time 5649756582 ps
CPU time 86.93 seconds
Started Jul 26 06:02:08 PM PDT 24
Finished Jul 26 06:03:35 PM PDT 24
Peak memory 199668 kb
Host smart-86b40bda-d1c7-42fb-be00-10e43509cb8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919182064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1919182064
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.332775344
Short name T349
Test name
Test status
Simulation time 732049654 ps
CPU time 5.25 seconds
Started Jul 26 06:02:07 PM PDT 24
Finished Jul 26 06:02:12 PM PDT 24
Peak memory 199560 kb
Host smart-2ac2dd2b-c2b2-49ec-aab2-26e4c1bb3557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332775344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.332775344
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2319816901
Short name T164
Test name
Test status
Simulation time 2915855354 ps
CPU time 500.84 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:10:30 PM PDT 24
Peak memory 657020 kb
Host smart-468a024d-f9e3-4fb4-8de7-63dc5ebd526f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319816901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2319816901
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1910994262
Short name T405
Test name
Test status
Simulation time 20022584003 ps
CPU time 143.7 seconds
Started Jul 26 06:02:08 PM PDT 24
Finished Jul 26 06:04:32 PM PDT 24
Peak memory 199676 kb
Host smart-656b5c91-c46a-43d3-9141-7a6027ddaa2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910994262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1910994262
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.485509402
Short name T485
Test name
Test status
Simulation time 30494180 ps
CPU time 0.78 seconds
Started Jul 26 06:02:07 PM PDT 24
Finished Jul 26 06:02:08 PM PDT 24
Peak memory 197404 kb
Host smart-ae9f6659-ebf1-4571-8160-2e778dc67f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485509402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.485509402
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.233788101
Short name T511
Test name
Test status
Simulation time 207718993 ps
CPU time 2.94 seconds
Started Jul 26 06:02:08 PM PDT 24
Finished Jul 26 06:02:11 PM PDT 24
Peak memory 199680 kb
Host smart-fbbaa922-7a44-41c2-b2fc-17fb845e0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233788101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.233788101
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2085673415
Short name T114
Test name
Test status
Simulation time 21779464394 ps
CPU time 307.1 seconds
Started Jul 26 06:02:08 PM PDT 24
Finished Jul 26 06:07:15 PM PDT 24
Peak memory 199696 kb
Host smart-fe895598-b071-47e3-ba14-293ddf19009d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085673415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2085673415
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.958527108
Short name T360
Test name
Test status
Simulation time 4349182053 ps
CPU time 71.79 seconds
Started Jul 26 06:02:08 PM PDT 24
Finished Jul 26 06:03:20 PM PDT 24
Peak memory 199672 kb
Host smart-3f0a7ca7-49e3-4377-bd26-3cf4334e559a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=958527108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.958527108
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2091625844
Short name T215
Test name
Test status
Simulation time 24875629502 ps
CPU time 93.67 seconds
Started Jul 26 06:02:08 PM PDT 24
Finished Jul 26 06:03:41 PM PDT 24
Peak memory 199664 kb
Host smart-53647d50-18a7-45cc-ba72-736391c1d15d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2091625844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2091625844
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3410055909
Short name T452
Test name
Test status
Simulation time 2942200595 ps
CPU time 106.42 seconds
Started Jul 26 06:02:10 PM PDT 24
Finished Jul 26 06:03:57 PM PDT 24
Peak memory 199708 kb
Host smart-81177dc1-ce77-4576-ad9c-c823acf9880a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3410055909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3410055909
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3103873670
Short name T482
Test name
Test status
Simulation time 267982327036 ps
CPU time 668.55 seconds
Started Jul 26 06:02:05 PM PDT 24
Finished Jul 26 06:13:14 PM PDT 24
Peak memory 199692 kb
Host smart-033feaf6-5fba-4d85-b9fd-5f0a1cbab28a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3103873670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3103873670
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2308085698
Short name T173
Test name
Test status
Simulation time 253713324379 ps
CPU time 2285.96 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:40:15 PM PDT 24
Peak memory 215688 kb
Host smart-76876d0d-729c-4345-be11-ce43d04ea9d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2308085698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2308085698
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1427438715
Short name T28
Test name
Test status
Simulation time 81895471910 ps
CPU time 2250.08 seconds
Started Jul 26 06:02:06 PM PDT 24
Finished Jul 26 06:39:36 PM PDT 24
Peak memory 215392 kb
Host smart-6fc97ac5-afd4-42c5-9b1b-b81748f88a33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1427438715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1427438715
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3258812700
Short name T71
Test name
Test status
Simulation time 9794490686 ps
CPU time 124.44 seconds
Started Jul 26 06:02:06 PM PDT 24
Finished Jul 26 06:04:11 PM PDT 24
Peak memory 199736 kb
Host smart-3dd0d54e-5591-47d1-b374-d0ebf9b1efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258812700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3258812700
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3624012828
Short name T237
Test name
Test status
Simulation time 15301928 ps
CPU time 0.6 seconds
Started Jul 26 06:02:29 PM PDT 24
Finished Jul 26 06:02:29 PM PDT 24
Peak memory 194668 kb
Host smart-efd626ea-01e1-461e-8158-1f4e47a4507e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624012828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3624012828
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4240046917
Short name T289
Test name
Test status
Simulation time 225917026 ps
CPU time 12.54 seconds
Started Jul 26 06:02:10 PM PDT 24
Finished Jul 26 06:02:23 PM PDT 24
Peak memory 199672 kb
Host smart-2d417e47-ac47-4c62-9464-1e3f789f6f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240046917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4240046917
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1443590626
Short name T157
Test name
Test status
Simulation time 614248173 ps
CPU time 7.78 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:02:17 PM PDT 24
Peak memory 199592 kb
Host smart-1b6151d1-3652-4b26-adc9-0bd7ae93b079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443590626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1443590626
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3617400587
Short name T180
Test name
Test status
Simulation time 7731330441 ps
CPU time 893.81 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:17:03 PM PDT 24
Peak memory 732900 kb
Host smart-bf55a3ab-46a4-44e6-9fc4-4c852727d223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3617400587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3617400587
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.106477676
Short name T444
Test name
Test status
Simulation time 8947025465 ps
CPU time 139.65 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:04:29 PM PDT 24
Peak memory 199692 kb
Host smart-17a0ad5b-ead1-4e05-bdcb-edce96672031
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106477676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.106477676
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4112157529
Short name T43
Test name
Test status
Simulation time 15020609637 ps
CPU time 136.59 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:04:25 PM PDT 24
Peak memory 199676 kb
Host smart-eb3baa9f-cd9b-4182-b7d8-5b24f872526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112157529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4112157529
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2667334633
Short name T39
Test name
Test status
Simulation time 1269712594 ps
CPU time 0.96 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:02:21 PM PDT 24
Peak memory 219400 kb
Host smart-8cf1eab4-dc98-48e8-8fa7-d2213f71710d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667334633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2667334633
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2215601185
Short name T418
Test name
Test status
Simulation time 955374378 ps
CPU time 11.89 seconds
Started Jul 26 06:02:09 PM PDT 24
Finished Jul 26 06:02:21 PM PDT 24
Peak memory 199604 kb
Host smart-266f18f7-e22c-45ac-ae06-9896e18ce7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215601185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2215601185
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.441053806
Short name T406
Test name
Test status
Simulation time 25853953351 ps
CPU time 156.07 seconds
Started Jul 26 06:02:19 PM PDT 24
Finished Jul 26 06:04:55 PM PDT 24
Peak memory 199776 kb
Host smart-f6c3b558-a9bf-49f4-a873-f6df5ab398d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441053806 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.441053806
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2125503264
Short name T56
Test name
Test status
Simulation time 186549944930 ps
CPU time 4721.88 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 07:21:03 PM PDT 24
Peak memory 830636 kb
Host smart-a905996a-ca0a-4b48-b201-de645fcdd35e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125503264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2125503264
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2106142365
Short name T440
Test name
Test status
Simulation time 3846293336 ps
CPU time 49.6 seconds
Started Jul 26 06:02:21 PM PDT 24
Finished Jul 26 06:03:11 PM PDT 24
Peak memory 199704 kb
Host smart-48b53f03-6fe2-4839-b45b-05678aa6dcfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2106142365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2106142365
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.540201811
Short name T517
Test name
Test status
Simulation time 67063878292 ps
CPU time 68.5 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:03:29 PM PDT 24
Peak memory 199716 kb
Host smart-d0896ce5-edcb-486f-b173-ac7d626a8b4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=540201811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.540201811
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.378311610
Short name T309
Test name
Test status
Simulation time 86357385701 ps
CPU time 79.51 seconds
Started Jul 26 06:02:22 PM PDT 24
Finished Jul 26 06:03:41 PM PDT 24
Peak memory 199676 kb
Host smart-dade490d-d3c6-4350-9553-9f5160b7384d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=378311610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.378311610
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1415253591
Short name T350
Test name
Test status
Simulation time 37269268056 ps
CPU time 658.26 seconds
Started Jul 26 06:02:11 PM PDT 24
Finished Jul 26 06:13:09 PM PDT 24
Peak memory 199748 kb
Host smart-92ed4354-5c32-4bbb-aba6-2452b692f550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1415253591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1415253591
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.863212648
Short name T346
Test name
Test status
Simulation time 835225426544 ps
CPU time 2683.71 seconds
Started Jul 26 06:02:19 PM PDT 24
Finished Jul 26 06:47:03 PM PDT 24
Peak memory 215500 kb
Host smart-10246f82-bf18-4013-a0d0-6fc561a98efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=863212648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.863212648
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.981638279
Short name T486
Test name
Test status
Simulation time 157646025513 ps
CPU time 2219.68 seconds
Started Jul 26 06:02:21 PM PDT 24
Finished Jul 26 06:39:21 PM PDT 24
Peak memory 215784 kb
Host smart-0951e9f7-975a-4bd1-9869-fd7fdd0f9294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=981638279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.981638279
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.508133951
Short name T236
Test name
Test status
Simulation time 4193271213 ps
CPU time 76.83 seconds
Started Jul 26 06:02:11 PM PDT 24
Finished Jul 26 06:03:28 PM PDT 24
Peak memory 199748 kb
Host smart-44d29fb9-dcf8-41fb-b18f-f1ceedaaadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508133951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.508133951
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1621094148
Short name T188
Test name
Test status
Simulation time 18970320 ps
CPU time 0.58 seconds
Started Jul 26 06:02:52 PM PDT 24
Finished Jul 26 06:02:53 PM PDT 24
Peak memory 196336 kb
Host smart-2bd1035d-fa17-4be6-97dd-fd8cdf751b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621094148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1621094148
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1394397287
Short name T128
Test name
Test status
Simulation time 1984383694 ps
CPU time 55.15 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:03:48 PM PDT 24
Peak memory 199644 kb
Host smart-26082bcb-9a00-4dc4-a5be-a3dfe7634050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394397287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1394397287
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2188329899
Short name T436
Test name
Test status
Simulation time 3551803814 ps
CPU time 44.83 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:03:49 PM PDT 24
Peak memory 199724 kb
Host smart-4c76ef43-67d2-4260-8d7a-e79eddf502f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188329899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2188329899
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1665030225
Short name T171
Test name
Test status
Simulation time 64104392474 ps
CPU time 1240 seconds
Started Jul 26 06:02:54 PM PDT 24
Finished Jul 26 06:23:35 PM PDT 24
Peak memory 726444 kb
Host smart-dc873f33-fc93-42c1-a77e-590e054f2f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665030225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1665030225
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1437811967
Short name T496
Test name
Test status
Simulation time 756496074 ps
CPU time 15.2 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:03:09 PM PDT 24
Peak memory 199640 kb
Host smart-934613f8-aa7f-4794-9c31-53e1a36f5e73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437811967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1437811967
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.606413408
Short name T42
Test name
Test status
Simulation time 5349616758 ps
CPU time 34.97 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:03:39 PM PDT 24
Peak memory 199708 kb
Host smart-493aabd6-b265-4382-b6fe-2f5111564f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606413408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.606413408
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2309213008
Short name T206
Test name
Test status
Simulation time 645286896 ps
CPU time 5.63 seconds
Started Jul 26 06:02:55 PM PDT 24
Finished Jul 26 06:03:01 PM PDT 24
Peak memory 199640 kb
Host smart-aa9794e2-3921-420b-b171-5a2fa71560a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309213008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2309213008
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1222623942
Short name T323
Test name
Test status
Simulation time 17050960506 ps
CPU time 783.05 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:15:56 PM PDT 24
Peak memory 709924 kb
Host smart-2af02be7-9fb1-4280-b0fe-83e2a9b4a5c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222623942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1222623942
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.396777901
Short name T404
Test name
Test status
Simulation time 39439059740 ps
CPU time 97.96 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:04:42 PM PDT 24
Peak memory 199708 kb
Host smart-08051ee3-97d6-464a-8305-ae132f967379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396777901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.396777901
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1731746029
Short name T492
Test name
Test status
Simulation time 44705111 ps
CPU time 0.56 seconds
Started Jul 26 06:02:55 PM PDT 24
Finished Jul 26 06:02:56 PM PDT 24
Peak memory 195228 kb
Host smart-599fb77b-0d49-460d-8e40-08bb5a88ce75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731746029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1731746029
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2112403858
Short name T489
Test name
Test status
Simulation time 3191775032 ps
CPU time 14.36 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:03:08 PM PDT 24
Peak memory 199728 kb
Host smart-f19976c6-1b56-4bc5-bbe3-c4409343069a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112403858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2112403858
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3191182464
Short name T255
Test name
Test status
Simulation time 5197510173 ps
CPU time 65.86 seconds
Started Jul 26 06:02:55 PM PDT 24
Finished Jul 26 06:04:01 PM PDT 24
Peak memory 199596 kb
Host smart-30bb7d8a-ee8a-4c4e-a111-068d5b62c9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191182464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3191182464
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.209130694
Short name T125
Test name
Test status
Simulation time 8230691225 ps
CPU time 294.32 seconds
Started Jul 26 06:02:57 PM PDT 24
Finished Jul 26 06:07:51 PM PDT 24
Peak memory 660440 kb
Host smart-395e5840-fc22-42f7-b959-79cd7c0c1b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209130694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.209130694
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1946080
Short name T225
Test name
Test status
Simulation time 7388853791 ps
CPU time 70.58 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:04:04 PM PDT 24
Peak memory 199684 kb
Host smart-89b5f5f8-5d61-470f-a5ef-2774fc8f865a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1946080
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.340989742
Short name T361
Test name
Test status
Simulation time 6036323581 ps
CPU time 108.16 seconds
Started Jul 26 06:02:56 PM PDT 24
Finished Jul 26 06:04:44 PM PDT 24
Peak memory 199660 kb
Host smart-8d80901d-9fea-4c04-8efc-10c31f456d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340989742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.340989742
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.650209316
Short name T336
Test name
Test status
Simulation time 4357895726 ps
CPU time 11.21 seconds
Started Jul 26 06:02:56 PM PDT 24
Finished Jul 26 06:03:07 PM PDT 24
Peak memory 199704 kb
Host smart-4137d6db-2591-41b7-ad4d-f718cae3d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650209316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.650209316
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2993024226
Short name T310
Test name
Test status
Simulation time 304143804224 ps
CPU time 1384.99 seconds
Started Jul 26 06:02:54 PM PDT 24
Finished Jul 26 06:25:59 PM PDT 24
Peak memory 678680 kb
Host smart-fb05a6dc-78ad-4ed1-82f2-174cdcb09ca3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993024226 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2993024226
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2042171501
Short name T431
Test name
Test status
Simulation time 2445783380 ps
CPU time 97.79 seconds
Started Jul 26 06:02:54 PM PDT 24
Finished Jul 26 06:04:32 PM PDT 24
Peak memory 199684 kb
Host smart-22424746-1b55-42cf-b4cd-3d26a0fc605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042171501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2042171501
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4271525851
Short name T322
Test name
Test status
Simulation time 34251815 ps
CPU time 0.56 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:03:04 PM PDT 24
Peak memory 195672 kb
Host smart-c5aac4be-8476-4187-9f89-5a543d300c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271525851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4271525851
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2823481236
Short name T4
Test name
Test status
Simulation time 1433000623 ps
CPU time 79 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:04:12 PM PDT 24
Peak memory 199748 kb
Host smart-4a33a3df-5bbc-48fa-96aa-a20d4edafa80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823481236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2823481236
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1052420830
Short name T286
Test name
Test status
Simulation time 21603551396 ps
CPU time 69.18 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:04:12 PM PDT 24
Peak memory 207892 kb
Host smart-238a0c3e-66f5-40f2-915c-7c2dae3a0180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052420830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1052420830
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4199767386
Short name T159
Test name
Test status
Simulation time 29435440065 ps
CPU time 1608.67 seconds
Started Jul 26 06:03:05 PM PDT 24
Finished Jul 26 06:29:54 PM PDT 24
Peak memory 785148 kb
Host smart-11b45e3d-6b5e-40e7-8f2c-5df3633a56b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199767386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4199767386
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1368617645
Short name T145
Test name
Test status
Simulation time 4993455017 ps
CPU time 61.22 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:04:05 PM PDT 24
Peak memory 199740 kb
Host smart-80673894-33cf-4a53-95c1-a551316c63c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368617645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1368617645
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3012601892
Short name T122
Test name
Test status
Simulation time 6181240512 ps
CPU time 105.57 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:04:39 PM PDT 24
Peak memory 199732 kb
Host smart-81b3c447-5f59-459d-9154-9cebfaca98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012601892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3012601892
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1646038058
Short name T263
Test name
Test status
Simulation time 250466503 ps
CPU time 6.43 seconds
Started Jul 26 06:02:55 PM PDT 24
Finished Jul 26 06:03:02 PM PDT 24
Peak memory 199716 kb
Host smart-b4d2129c-0cc0-4a68-a273-fe79f1a69912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646038058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1646038058
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.776114539
Short name T504
Test name
Test status
Simulation time 37570056734 ps
CPU time 650.45 seconds
Started Jul 26 06:03:05 PM PDT 24
Finished Jul 26 06:13:56 PM PDT 24
Peak memory 216020 kb
Host smart-eb6794f7-0fbb-4340-9d8a-2365650da0b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776114539 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.776114539
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3992256465
Short name T219
Test name
Test status
Simulation time 438947924 ps
CPU time 17.34 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:03:22 PM PDT 24
Peak memory 199652 kb
Host smart-583e76d3-7250-4740-a86c-24b485ba2987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992256465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3992256465
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.237364522
Short name T151
Test name
Test status
Simulation time 47591516 ps
CPU time 0.59 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:03:05 PM PDT 24
Peak memory 195668 kb
Host smart-336e5a49-5307-441e-a507-f01b62f94262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237364522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.237364522
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2762238041
Short name T481
Test name
Test status
Simulation time 2828762542 ps
CPU time 68.85 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:04:12 PM PDT 24
Peak memory 199716 kb
Host smart-89433b3c-5a4e-41bb-99d9-43b09458418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762238041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2762238041
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.725297943
Short name T175
Test name
Test status
Simulation time 10856624703 ps
CPU time 987.98 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:19:31 PM PDT 24
Peak memory 706740 kb
Host smart-a1e24a9f-8fd6-4953-a54b-4a2f05ba3df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725297943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.725297943
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3801222852
Short name T270
Test name
Test status
Simulation time 26539776019 ps
CPU time 82.09 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:04:27 PM PDT 24
Peak memory 199668 kb
Host smart-439faaf2-e7b6-4ee4-88ae-dcca60ad6926
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801222852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3801222852
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.461076922
Short name T471
Test name
Test status
Simulation time 11474906223 ps
CPU time 47.98 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:03:51 PM PDT 24
Peak memory 199740 kb
Host smart-0ba93545-7f94-48d8-af6f-9234a7648064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461076922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.461076922
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2153537442
Short name T166
Test name
Test status
Simulation time 1768386804 ps
CPU time 14.74 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:03:19 PM PDT 24
Peak memory 199644 kb
Host smart-49e246c4-f2e3-4561-92d2-43380141fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153537442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2153537442
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1747536825
Short name T58
Test name
Test status
Simulation time 129247675393 ps
CPU time 3376.87 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:59:22 PM PDT 24
Peak memory 780816 kb
Host smart-a9f0ee25-808f-4f17-80fd-3f29ab94fa07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747536825 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1747536825
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.325702423
Short name T512
Test name
Test status
Simulation time 13605623783 ps
CPU time 80.17 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:04:25 PM PDT 24
Peak memory 199752 kb
Host smart-5cc23ac1-46de-490f-a916-7cc349be9d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325702423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.325702423
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4118904053
Short name T285
Test name
Test status
Simulation time 21545937 ps
CPU time 0.59 seconds
Started Jul 26 06:03:17 PM PDT 24
Finished Jul 26 06:03:18 PM PDT 24
Peak memory 195664 kb
Host smart-da18f5b5-1190-4d81-b584-d856af51a305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118904053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4118904053
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3028737939
Short name T473
Test name
Test status
Simulation time 5508948346 ps
CPU time 76.34 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:04:20 PM PDT 24
Peak memory 199720 kb
Host smart-3d1fe38b-155d-4666-8f41-3030ff464f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028737939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3028737939
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4010906034
Short name T141
Test name
Test status
Simulation time 1503558563 ps
CPU time 26.67 seconds
Started Jul 26 06:03:22 PM PDT 24
Finished Jul 26 06:03:48 PM PDT 24
Peak memory 199620 kb
Host smart-828d956c-ce7a-42e0-83df-47d3b96af1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010906034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4010906034
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.626903178
Short name T174
Test name
Test status
Simulation time 30663595699 ps
CPU time 735.01 seconds
Started Jul 26 06:03:05 PM PDT 24
Finished Jul 26 06:15:20 PM PDT 24
Peak memory 731124 kb
Host smart-1e576167-cad3-423a-9ca2-7e04ce63296d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626903178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.626903178
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3899527236
Short name T467
Test name
Test status
Simulation time 18851100905 ps
CPU time 85.96 seconds
Started Jul 26 06:03:20 PM PDT 24
Finished Jul 26 06:04:46 PM PDT 24
Peak memory 199712 kb
Host smart-c7cc7fb7-d991-4978-96ff-77af82c36942
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899527236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3899527236
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.262661549
Short name T261
Test name
Test status
Simulation time 10262477730 ps
CPU time 186.14 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:06:09 PM PDT 24
Peak memory 199736 kb
Host smart-c6868a51-46dc-4370-810d-5b5437e989ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262661549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.262661549
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3606321942
Short name T146
Test name
Test status
Simulation time 450620736 ps
CPU time 11.78 seconds
Started Jul 26 06:03:03 PM PDT 24
Finished Jul 26 06:03:15 PM PDT 24
Peak memory 199652 kb
Host smart-e0a05058-6613-43d2-b11c-be8305fd99e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606321942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3606321942
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2645509360
Short name T442
Test name
Test status
Simulation time 328174826891 ps
CPU time 1804.59 seconds
Started Jul 26 06:03:19 PM PDT 24
Finished Jul 26 06:33:23 PM PDT 24
Peak memory 734040 kb
Host smart-06ada81b-44e1-4062-b428-5ea3898656d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645509360 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2645509360
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2833368598
Short name T387
Test name
Test status
Simulation time 3637130862 ps
CPU time 94.19 seconds
Started Jul 26 06:03:20 PM PDT 24
Finished Jul 26 06:04:54 PM PDT 24
Peak memory 199692 kb
Host smart-b8f6f170-7f08-4241-b64b-404e9399ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833368598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2833368598
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4174917350
Short name T464
Test name
Test status
Simulation time 35259789 ps
CPU time 0.58 seconds
Started Jul 26 06:03:20 PM PDT 24
Finished Jul 26 06:03:21 PM PDT 24
Peak memory 195232 kb
Host smart-35163f45-1460-464b-878f-3371f518e59e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174917350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4174917350
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.948532129
Short name T477
Test name
Test status
Simulation time 3614826190 ps
CPU time 40.91 seconds
Started Jul 26 06:03:21 PM PDT 24
Finished Jul 26 06:04:02 PM PDT 24
Peak memory 199700 kb
Host smart-f193b9b2-d0fe-4262-b623-c05a5a81cfd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948532129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.948532129
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1409469139
Short name T395
Test name
Test status
Simulation time 946811490 ps
CPU time 49.98 seconds
Started Jul 26 06:03:20 PM PDT 24
Finished Jul 26 06:04:10 PM PDT 24
Peak memory 199648 kb
Host smart-6627778a-a165-4199-86e7-995940345d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409469139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1409469139
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2785781861
Short name T494
Test name
Test status
Simulation time 4042677410 ps
CPU time 387.01 seconds
Started Jul 26 06:03:19 PM PDT 24
Finished Jul 26 06:09:46 PM PDT 24
Peak memory 661176 kb
Host smart-9e4358eb-c94f-4946-b9b2-b1fa771d588a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785781861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2785781861
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2505383942
Short name T317
Test name
Test status
Simulation time 2201802787 ps
CPU time 39.44 seconds
Started Jul 26 06:03:21 PM PDT 24
Finished Jul 26 06:04:00 PM PDT 24
Peak memory 199716 kb
Host smart-3b8c5568-aab9-469b-82bc-ee56a05673be
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505383942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2505383942
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4276772242
Short name T200
Test name
Test status
Simulation time 10176604223 ps
CPU time 87.19 seconds
Started Jul 26 06:03:19 PM PDT 24
Finished Jul 26 06:04:47 PM PDT 24
Peak memory 207924 kb
Host smart-8ddae910-12a7-44f3-8d7a-981523a2b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276772242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4276772242
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3095599176
Short name T220
Test name
Test status
Simulation time 737866682 ps
CPU time 12.72 seconds
Started Jul 26 06:03:18 PM PDT 24
Finished Jul 26 06:03:30 PM PDT 24
Peak memory 199864 kb
Host smart-8a8e60a7-88a2-44a2-9084-31983dc0611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095599176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3095599176
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1782917973
Short name T64
Test name
Test status
Simulation time 105172167870 ps
CPU time 128.26 seconds
Started Jul 26 06:03:19 PM PDT 24
Finished Jul 26 06:05:27 PM PDT 24
Peak memory 199588 kb
Host smart-bef721b8-d138-4e1d-9bc0-14224401d0d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782917973 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1782917973
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3204058197
Short name T407
Test name
Test status
Simulation time 1000946217 ps
CPU time 3.77 seconds
Started Jul 26 06:03:21 PM PDT 24
Finished Jul 26 06:03:25 PM PDT 24
Peak memory 199700 kb
Host smart-3dbcf9ab-b88d-4ef3-ad88-a6f7d4cab951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204058197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3204058197
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2265955917
Short name T135
Test name
Test status
Simulation time 57824779 ps
CPU time 0.55 seconds
Started Jul 26 06:03:35 PM PDT 24
Finished Jul 26 06:03:36 PM PDT 24
Peak memory 194648 kb
Host smart-a5872339-1006-4d30-af7d-932800f14f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265955917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2265955917
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3196779514
Short name T278
Test name
Test status
Simulation time 607083486 ps
CPU time 9 seconds
Started Jul 26 06:03:20 PM PDT 24
Finished Jul 26 06:03:29 PM PDT 24
Peak memory 199628 kb
Host smart-8c5e0c5e-f3c2-46c7-9fb7-92caaafab5c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196779514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3196779514
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.957557794
Short name T487
Test name
Test status
Simulation time 2291295471 ps
CPU time 10.49 seconds
Started Jul 26 06:03:34 PM PDT 24
Finished Jul 26 06:03:44 PM PDT 24
Peak memory 199696 kb
Host smart-248f585a-dab9-4f49-b4ad-9f71a8fe7fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957557794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.957557794
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.188570017
Short name T525
Test name
Test status
Simulation time 2361804815 ps
CPU time 436.28 seconds
Started Jul 26 06:03:18 PM PDT 24
Finished Jul 26 06:10:35 PM PDT 24
Peak memory 671824 kb
Host smart-9d2d3d0d-0fdd-4da5-8249-b7f63c512e0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188570017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.188570017
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.567566853
Short name T434
Test name
Test status
Simulation time 14511032756 ps
CPU time 113.94 seconds
Started Jul 26 06:03:35 PM PDT 24
Finished Jul 26 06:05:29 PM PDT 24
Peak memory 199744 kb
Host smart-3bfa7740-b677-408c-b120-e362491a2e6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567566853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.567566853
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1135494882
Short name T140
Test name
Test status
Simulation time 7821110512 ps
CPU time 33.26 seconds
Started Jul 26 06:03:20 PM PDT 24
Finished Jul 26 06:03:53 PM PDT 24
Peak memory 199644 kb
Host smart-faf6533b-e60b-4b83-ae11-b5fbe8c685d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135494882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1135494882
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.89804225
Short name T523
Test name
Test status
Simulation time 610236510 ps
CPU time 12.61 seconds
Started Jul 26 06:03:20 PM PDT 24
Finished Jul 26 06:03:33 PM PDT 24
Peak memory 199676 kb
Host smart-2b15d7ee-73a7-4eb0-9ec1-f477773decd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89804225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.89804225
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.221975302
Short name T19
Test name
Test status
Simulation time 54715794169 ps
CPU time 754.74 seconds
Started Jul 26 06:03:34 PM PDT 24
Finished Jul 26 06:16:09 PM PDT 24
Peak memory 199780 kb
Host smart-dba3d9f2-0c8a-4737-b890-db341db22bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221975302 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.221975302
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.229683391
Short name T47
Test name
Test status
Simulation time 6267368673 ps
CPU time 106.42 seconds
Started Jul 26 06:03:34 PM PDT 24
Finished Jul 26 06:05:20 PM PDT 24
Peak memory 199608 kb
Host smart-3fef1ec1-37c5-4cb8-8003-bf9a3a87389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229683391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.229683391
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1320156646
Short name T531
Test name
Test status
Simulation time 14203719 ps
CPU time 0.6 seconds
Started Jul 26 06:03:44 PM PDT 24
Finished Jul 26 06:03:45 PM PDT 24
Peak memory 196340 kb
Host smart-6e199dec-9e68-4a52-bbca-6f2f675a1eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320156646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1320156646
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.235683575
Short name T212
Test name
Test status
Simulation time 267844530 ps
CPU time 16.34 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:03:59 PM PDT 24
Peak memory 199648 kb
Host smart-81e7ad85-89fa-4964-84d5-86e96bdcf6fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235683575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.235683575
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3930315968
Short name T168
Test name
Test status
Simulation time 2375759427 ps
CPU time 39.52 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:04:22 PM PDT 24
Peak memory 199720 kb
Host smart-fd9e6e18-24fc-4b99-b5f5-5dae76e88ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930315968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3930315968
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3716421333
Short name T529
Test name
Test status
Simulation time 41374138578 ps
CPU time 1066.55 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:21:29 PM PDT 24
Peak memory 680156 kb
Host smart-aad77e07-8179-4b9a-af6c-9e87b611519b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716421333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3716421333
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3219456449
Short name T297
Test name
Test status
Simulation time 3868790525 ps
CPU time 52.85 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:04:36 PM PDT 24
Peak memory 199716 kb
Host smart-1820c981-01fd-4c71-90a7-1a7ce7d7e3cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219456449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3219456449
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3371171000
Short name T248
Test name
Test status
Simulation time 68355785762 ps
CPU time 101.63 seconds
Started Jul 26 06:03:41 PM PDT 24
Finished Jul 26 06:05:23 PM PDT 24
Peak memory 199724 kb
Host smart-ab60e2d9-2181-4aef-b375-5b2e37fe0dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371171000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3371171000
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1113931964
Short name T110
Test name
Test status
Simulation time 1250132443 ps
CPU time 15.69 seconds
Started Jul 26 06:03:34 PM PDT 24
Finished Jul 26 06:03:51 PM PDT 24
Peak memory 199696 kb
Host smart-e91551fb-f42c-46ff-8365-cdab8aeb9386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113931964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1113931964
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.244447120
Short name T527
Test name
Test status
Simulation time 38633216271 ps
CPU time 354.84 seconds
Started Jul 26 06:03:41 PM PDT 24
Finished Jul 26 06:09:36 PM PDT 24
Peak memory 199680 kb
Host smart-d8539792-652f-413b-90c3-916efc28cdbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244447120 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.244447120
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4082990972
Short name T298
Test name
Test status
Simulation time 7869468251 ps
CPU time 31.06 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:04:13 PM PDT 24
Peak memory 199764 kb
Host smart-1751732d-f2dc-4278-92dc-0ba0fbfa28d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082990972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4082990972
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.988524346
Short name T161
Test name
Test status
Simulation time 14239820 ps
CPU time 0.59 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:03:43 PM PDT 24
Peak memory 195284 kb
Host smart-6837abde-6cd8-4a98-8355-db2692fecdd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988524346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.988524346
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1748836476
Short name T300
Test name
Test status
Simulation time 3072244432 ps
CPU time 67.74 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:04:49 PM PDT 24
Peak memory 199644 kb
Host smart-ed86e459-e51c-47c6-b4c5-82e42498d84c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748836476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1748836476
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.354791019
Short name T312
Test name
Test status
Simulation time 2879779795 ps
CPU time 37.77 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:04:21 PM PDT 24
Peak memory 199744 kb
Host smart-a7a8918f-5c9c-4f38-a9d4-c8a3b0427a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354791019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.354791019
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1285562382
Short name T421
Test name
Test status
Simulation time 1939602798 ps
CPU time 346.17 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:09:30 PM PDT 24
Peak memory 635992 kb
Host smart-36143536-44cc-44d4-a122-b7a3cb9e2ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285562382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1285562382
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2697389302
Short name T185
Test name
Test status
Simulation time 6892912740 ps
CPU time 188.8 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:06:52 PM PDT 24
Peak memory 199760 kb
Host smart-e5638eb6-a57a-4ea9-b9a8-adf975931530
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697389302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2697389302
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1896698788
Short name T218
Test name
Test status
Simulation time 10567667408 ps
CPU time 31.01 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:04:14 PM PDT 24
Peak memory 215940 kb
Host smart-48a1e726-770f-43dc-a2c4-4ac360f54292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896698788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1896698788
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.882693638
Short name T365
Test name
Test status
Simulation time 395926050 ps
CPU time 5.18 seconds
Started Jul 26 06:03:41 PM PDT 24
Finished Jul 26 06:03:47 PM PDT 24
Peak memory 199652 kb
Host smart-27f8b76b-fd7f-4245-a334-ada8040fef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882693638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.882693638
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1312772834
Short name T369
Test name
Test status
Simulation time 176666228734 ps
CPU time 1139.61 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:22:43 PM PDT 24
Peak memory 484788 kb
Host smart-cb986aac-0693-4c20-903e-e715affbb4ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312772834 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1312772834
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2907987304
Short name T147
Test name
Test status
Simulation time 1743132236 ps
CPU time 32.14 seconds
Started Jul 26 06:03:41 PM PDT 24
Finished Jul 26 06:04:14 PM PDT 24
Peak memory 199704 kb
Host smart-ca980a0d-5f05-49c2-8208-dce5ee43f383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907987304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2907987304
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2780838708
Short name T340
Test name
Test status
Simulation time 44848766 ps
CPU time 0.59 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:03:44 PM PDT 24
Peak memory 196288 kb
Host smart-cf1edae0-e0b0-41b9-873e-93fee36841c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780838708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2780838708
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.29995444
Short name T498
Test name
Test status
Simulation time 1374259817 ps
CPU time 74.07 seconds
Started Jul 26 06:03:44 PM PDT 24
Finished Jul 26 06:04:59 PM PDT 24
Peak memory 199588 kb
Host smart-0d7eccb4-b14d-4b83-8ee6-3e31450d29d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29995444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.29995444
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.31885512
Short name T268
Test name
Test status
Simulation time 20233455897 ps
CPU time 75.71 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:04:57 PM PDT 24
Peak memory 199704 kb
Host smart-ee9d46e0-41f1-4067-8e89-67fb10c2f903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31885512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.31885512
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2447961187
Short name T130
Test name
Test status
Simulation time 1198759713 ps
CPU time 7.33 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:03:50 PM PDT 24
Peak memory 199596 kb
Host smart-d923dab0-2d72-43c7-8c9e-629739d5e865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2447961187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2447961187
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1264233175
Short name T465
Test name
Test status
Simulation time 4568612731 ps
CPU time 70.66 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:04:54 PM PDT 24
Peak memory 199668 kb
Host smart-1ae6e4e8-ae43-4a67-bb2f-9e5e32121511
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264233175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1264233175
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4235017109
Short name T120
Test name
Test status
Simulation time 19393706360 ps
CPU time 88.84 seconds
Started Jul 26 06:03:42 PM PDT 24
Finished Jul 26 06:05:11 PM PDT 24
Peak memory 199864 kb
Host smart-96244b86-a7b4-464c-89d3-d23fa81f27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235017109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4235017109
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.525754127
Short name T339
Test name
Test status
Simulation time 5119711254 ps
CPU time 15.21 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:03:58 PM PDT 24
Peak memory 199780 kb
Host smart-7ccd83ba-a9c6-4028-951e-cb9f13f4c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525754127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.525754127
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3855853608
Short name T528
Test name
Test status
Simulation time 2252636163 ps
CPU time 111.55 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:05:35 PM PDT 24
Peak memory 199740 kb
Host smart-f7652452-c0ec-459a-96df-37fa60d6bfe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855853608 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3855853608
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2372168708
Short name T27
Test name
Test status
Simulation time 2156300234 ps
CPU time 99.57 seconds
Started Jul 26 06:03:43 PM PDT 24
Finished Jul 26 06:05:23 PM PDT 24
Peak memory 199728 kb
Host smart-83b492c4-3b15-419e-ad10-740c8115785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372168708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2372168708
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2039310660
Short name T210
Test name
Test status
Simulation time 15206829 ps
CPU time 0.63 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:02:32 PM PDT 24
Peak memory 195656 kb
Host smart-8b7d5c99-de9c-4e90-963d-e2245f56cf54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039310660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2039310660
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.695354369
Short name T260
Test name
Test status
Simulation time 3168913179 ps
CPU time 45.92 seconds
Started Jul 26 06:02:19 PM PDT 24
Finished Jul 26 06:03:06 PM PDT 24
Peak memory 199664 kb
Host smart-5a8b92b1-a45a-4803-8dcf-18bd596acb9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695354369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.695354369
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2150039277
Short name T503
Test name
Test status
Simulation time 21091172512 ps
CPU time 63.1 seconds
Started Jul 26 06:02:29 PM PDT 24
Finished Jul 26 06:03:32 PM PDT 24
Peak memory 199736 kb
Host smart-3a712521-f21c-4711-8e8f-5ca7bf32419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150039277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2150039277
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3768898662
Short name T242
Test name
Test status
Simulation time 7466886649 ps
CPU time 92.14 seconds
Started Jul 26 06:02:21 PM PDT 24
Finished Jul 26 06:03:54 PM PDT 24
Peak memory 437328 kb
Host smart-ffd82c87-ebf5-4887-8c50-3c6d75869fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768898662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3768898662
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3877977199
Short name T363
Test name
Test status
Simulation time 14564573844 ps
CPU time 174.56 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:05:15 PM PDT 24
Peak memory 199668 kb
Host smart-c66c9b85-c2b0-4abd-a2e7-38b47982c34c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877977199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3877977199
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1641187053
Short name T234
Test name
Test status
Simulation time 1012198899 ps
CPU time 19.27 seconds
Started Jul 26 06:02:19 PM PDT 24
Finished Jul 26 06:02:38 PM PDT 24
Peak memory 199632 kb
Host smart-c09c2d55-bc1f-40ba-b0ef-4084efd456a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641187053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1641187053
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3093473792
Short name T35
Test name
Test status
Simulation time 631197934 ps
CPU time 0.81 seconds
Started Jul 26 06:02:21 PM PDT 24
Finished Jul 26 06:02:22 PM PDT 24
Peak memory 218176 kb
Host smart-42defcaf-f6c5-4357-861c-8f7d141fb223
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093473792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3093473792
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2188248391
Short name T129
Test name
Test status
Simulation time 1364647344 ps
CPU time 5.77 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:02:26 PM PDT 24
Peak memory 199692 kb
Host smart-7c6d68bb-46f9-47ef-a70d-4e3283cf1c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188248391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2188248391
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2017473865
Short name T156
Test name
Test status
Simulation time 170242339294 ps
CPU time 2494.38 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:43:55 PM PDT 24
Peak memory 843296 kb
Host smart-76e677fa-e2f5-47c0-95dd-059d68622071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017473865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2017473865
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3668570115
Short name T55
Test name
Test status
Simulation time 67390354738 ps
CPU time 1858.99 seconds
Started Jul 26 06:02:28 PM PDT 24
Finished Jul 26 06:33:28 PM PDT 24
Peak memory 696044 kb
Host smart-4911d9e9-2f8d-456f-8efc-44bb27a970bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668570115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3668570115
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.154252556
Short name T123
Test name
Test status
Simulation time 6403875240 ps
CPU time 61.48 seconds
Started Jul 26 06:02:28 PM PDT 24
Finished Jul 26 06:03:30 PM PDT 24
Peak memory 199764 kb
Host smart-1106505d-7f5d-40b8-824d-dd161812e50f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=154252556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.154252556
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1503139337
Short name T463
Test name
Test status
Simulation time 9750211390 ps
CPU time 114.72 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:04:15 PM PDT 24
Peak memory 199672 kb
Host smart-f9990548-ee4a-4165-bdbe-7233037ef24e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1503139337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1503139337
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1188466826
Short name T456
Test name
Test status
Simulation time 18962363325 ps
CPU time 109.91 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:04:10 PM PDT 24
Peak memory 199684 kb
Host smart-bb5e4dbf-10ff-45d7-9ab7-19c79fc8c829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1188466826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1188466826
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1283884001
Short name T176
Test name
Test status
Simulation time 40945343975 ps
CPU time 519.59 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:11:00 PM PDT 24
Peak memory 199720 kb
Host smart-033c8ae6-6f7f-4139-ab18-f3b839a37d7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1283884001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1283884001
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2192683916
Short name T402
Test name
Test status
Simulation time 255035887217 ps
CPU time 2339.81 seconds
Started Jul 26 06:02:20 PM PDT 24
Finished Jul 26 06:41:20 PM PDT 24
Peak memory 215160 kb
Host smart-adb63127-b11b-4484-8cfb-a5abddaafbda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2192683916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2192683916
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.34406145
Short name T284
Test name
Test status
Simulation time 170603221338 ps
CPU time 2338.76 seconds
Started Jul 26 06:02:21 PM PDT 24
Finished Jul 26 06:41:21 PM PDT 24
Peak memory 215152 kb
Host smart-58611826-e60d-4946-9cdb-158e14e73bdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=34406145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.34406145
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3328124428
Short name T149
Test name
Test status
Simulation time 1976672454 ps
CPU time 27.72 seconds
Started Jul 26 06:02:21 PM PDT 24
Finished Jul 26 06:02:49 PM PDT 24
Peak memory 199640 kb
Host smart-92cf815f-865b-4cff-820a-24974fa4c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328124428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3328124428
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.871195225
Short name T335
Test name
Test status
Simulation time 12480477 ps
CPU time 0.6 seconds
Started Jul 26 06:03:56 PM PDT 24
Finished Jul 26 06:03:57 PM PDT 24
Peak memory 196276 kb
Host smart-60e6b174-2c04-40c1-a705-e6968cfe49c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871195225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.871195225
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1120158851
Short name T313
Test name
Test status
Simulation time 45519768 ps
CPU time 2.52 seconds
Started Jul 26 06:03:44 PM PDT 24
Finished Jul 26 06:03:47 PM PDT 24
Peak memory 199588 kb
Host smart-c4bc6a22-f053-44c8-b360-caa42d87c6cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120158851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1120158851
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1738271747
Short name T439
Test name
Test status
Simulation time 1981736142 ps
CPU time 25.55 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:04:21 PM PDT 24
Peak memory 199664 kb
Host smart-2724321f-b076-4e2b-9b22-310b4e5d96ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738271747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1738271747
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.950011283
Short name T474
Test name
Test status
Simulation time 14576435029 ps
CPU time 1038.23 seconds
Started Jul 26 06:03:54 PM PDT 24
Finished Jul 26 06:21:13 PM PDT 24
Peak memory 657992 kb
Host smart-8a65d0ac-8c35-4cde-9e85-5427175d2121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950011283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.950011283
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3070962615
Short name T232
Test name
Test status
Simulation time 7059126878 ps
CPU time 96.79 seconds
Started Jul 26 06:03:53 PM PDT 24
Finished Jul 26 06:05:30 PM PDT 24
Peak memory 199752 kb
Host smart-a5079960-74bb-452e-b5bd-b63effae8635
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070962615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3070962615
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1524908904
Short name T356
Test name
Test status
Simulation time 8540773641 ps
CPU time 40.7 seconds
Started Jul 26 06:03:45 PM PDT 24
Finished Jul 26 06:04:26 PM PDT 24
Peak memory 199720 kb
Host smart-8ba90b73-abad-4a9f-9388-d43ed565d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524908904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1524908904
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1335900402
Short name T150
Test name
Test status
Simulation time 173830816 ps
CPU time 8.18 seconds
Started Jul 26 06:03:44 PM PDT 24
Finished Jul 26 06:03:52 PM PDT 24
Peak memory 199708 kb
Host smart-b57c507b-dd22-4e88-a2a1-3f603f408d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335900402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1335900402
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1142634051
Short name T470
Test name
Test status
Simulation time 73525909688 ps
CPU time 1746.97 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:33:02 PM PDT 24
Peak memory 679856 kb
Host smart-4626bb0c-c9c7-4714-8670-ff9fd29e69ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142634051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1142634051
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.608925507
Short name T391
Test name
Test status
Simulation time 1852271966 ps
CPU time 12.36 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:04:07 PM PDT 24
Peak memory 199652 kb
Host smart-62a702e3-d399-49bd-aba1-ca83410f6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608925507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.608925507
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.818304100
Short name T208
Test name
Test status
Simulation time 37905685 ps
CPU time 0.57 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:03:56 PM PDT 24
Peak memory 196352 kb
Host smart-d2ad6b99-c28b-4f84-8f43-d6dead943336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818304100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.818304100
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3349330789
Short name T327
Test name
Test status
Simulation time 329985835 ps
CPU time 17.99 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:04:13 PM PDT 24
Peak memory 199656 kb
Host smart-e881d7a5-8925-44e9-9bdc-7ba23739cafd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349330789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3349330789
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3847881707
Short name T449
Test name
Test status
Simulation time 4691067974 ps
CPU time 60.65 seconds
Started Jul 26 06:03:59 PM PDT 24
Finished Jul 26 06:05:00 PM PDT 24
Peak memory 199260 kb
Host smart-8615c827-662e-4256-bb99-f172efd99213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847881707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3847881707
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1792839225
Short name T136
Test name
Test status
Simulation time 4254244291 ps
CPU time 416.03 seconds
Started Jul 26 06:03:54 PM PDT 24
Finished Jul 26 06:10:50 PM PDT 24
Peak memory 679736 kb
Host smart-e3a967e6-7345-4ba3-8df0-6929c399b9a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792839225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1792839225
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.161432106
Short name T366
Test name
Test status
Simulation time 7839330794 ps
CPU time 50.03 seconds
Started Jul 26 06:03:53 PM PDT 24
Finished Jul 26 06:04:43 PM PDT 24
Peak memory 199756 kb
Host smart-ccf8f94b-7fbc-4062-8eb7-aabdd0b10d5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161432106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.161432106
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2861317989
Short name T178
Test name
Test status
Simulation time 7595557043 ps
CPU time 142.4 seconds
Started Jul 26 06:03:54 PM PDT 24
Finished Jul 26 06:06:17 PM PDT 24
Peak memory 199704 kb
Host smart-ca78f8d4-eef3-4bee-80d6-ec82c3dd0037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861317989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2861317989
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.81890185
Short name T478
Test name
Test status
Simulation time 494657607 ps
CPU time 4.68 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:04:00 PM PDT 24
Peak memory 199716 kb
Host smart-965bcbd7-b8de-4751-a206-20e827b1c943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81890185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.81890185
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2096190362
Short name T223
Test name
Test status
Simulation time 19007376881 ps
CPU time 495.83 seconds
Started Jul 26 06:03:59 PM PDT 24
Finished Jul 26 06:12:15 PM PDT 24
Peak memory 199580 kb
Host smart-cce3bd70-0233-48c8-b84d-bc71ebd5e6e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096190362 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2096190362
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2396066445
Short name T67
Test name
Test status
Simulation time 8856641044 ps
CPU time 111.45 seconds
Started Jul 26 06:03:54 PM PDT 24
Finished Jul 26 06:05:45 PM PDT 24
Peak memory 199728 kb
Host smart-b3be2440-ed12-4658-b2d6-e643c8552b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396066445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2396066445
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2559080891
Short name T142
Test name
Test status
Simulation time 26569898 ps
CPU time 0.58 seconds
Started Jul 26 06:04:07 PM PDT 24
Finished Jul 26 06:04:07 PM PDT 24
Peak memory 195660 kb
Host smart-a7801f14-1bb5-4071-b1b8-31f69a80328b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559080891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2559080891
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1644718658
Short name T308
Test name
Test status
Simulation time 1236582919 ps
CPU time 72.51 seconds
Started Jul 26 06:03:54 PM PDT 24
Finished Jul 26 06:05:06 PM PDT 24
Peak memory 199708 kb
Host smart-2a8158c4-70cb-4c76-aa8d-55b723e147e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644718658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1644718658
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4263719505
Short name T386
Test name
Test status
Simulation time 248621674 ps
CPU time 3.7 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:03:58 PM PDT 24
Peak memory 199656 kb
Host smart-4c70ce14-b266-479b-8753-c4bf3ebbd56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263719505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4263719505
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3527623252
Short name T182
Test name
Test status
Simulation time 6547875905 ps
CPU time 1275.64 seconds
Started Jul 26 06:03:55 PM PDT 24
Finished Jul 26 06:25:11 PM PDT 24
Peak memory 764408 kb
Host smart-b027a113-a30c-4675-8a0f-7aa261f1c155
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527623252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3527623252
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1605136580
Short name T370
Test name
Test status
Simulation time 13309019929 ps
CPU time 177.34 seconds
Started Jul 26 06:04:07 PM PDT 24
Finished Jul 26 06:07:04 PM PDT 24
Peak memory 199696 kb
Host smart-9a9334f2-9e24-4f33-a52c-a98fa6461278
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605136580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1605136580
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2401075981
Short name T319
Test name
Test status
Simulation time 42966225694 ps
CPU time 187.08 seconds
Started Jul 26 06:03:56 PM PDT 24
Finished Jul 26 06:07:03 PM PDT 24
Peak memory 199672 kb
Host smart-c3ac52a1-c355-4ab8-a68c-be802098c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401075981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2401075981
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2242370740
Short name T153
Test name
Test status
Simulation time 213707763 ps
CPU time 9.37 seconds
Started Jul 26 06:03:59 PM PDT 24
Finished Jul 26 06:04:09 PM PDT 24
Peak memory 199108 kb
Host smart-049cb215-688a-4bf4-88a5-8c775fb06836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242370740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2242370740
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1313128083
Short name T60
Test name
Test status
Simulation time 35772834459 ps
CPU time 933.43 seconds
Started Jul 26 06:04:06 PM PDT 24
Finished Jul 26 06:19:40 PM PDT 24
Peak memory 688636 kb
Host smart-37b5a7bf-1f39-4982-aae5-30c20bc7e5ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313128083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1313128083
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2741595840
Short name T388
Test name
Test status
Simulation time 5472552154 ps
CPU time 147.05 seconds
Started Jul 26 06:04:07 PM PDT 24
Finished Jul 26 06:06:34 PM PDT 24
Peak memory 199720 kb
Host smart-b85e5116-e804-433d-a8ea-5100f57ed41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741595840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2741595840
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2879973756
Short name T331
Test name
Test status
Simulation time 17431236 ps
CPU time 0.57 seconds
Started Jul 26 06:04:19 PM PDT 24
Finished Jul 26 06:04:20 PM PDT 24
Peak memory 195272 kb
Host smart-5964dd86-c1a1-4455-ae4a-1e1b3141ff3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879973756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2879973756
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.666383979
Short name T324
Test name
Test status
Simulation time 1834933131 ps
CPU time 106.58 seconds
Started Jul 26 06:04:06 PM PDT 24
Finished Jul 26 06:05:53 PM PDT 24
Peak memory 199616 kb
Host smart-279186b3-3371-4026-af66-d40502239905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666383979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.666383979
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.341989969
Short name T7
Test name
Test status
Simulation time 937206004 ps
CPU time 16.66 seconds
Started Jul 26 06:04:05 PM PDT 24
Finished Jul 26 06:04:22 PM PDT 24
Peak memory 199608 kb
Host smart-b9ee1bd8-2dfc-4e14-8390-cf733510fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341989969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.341989969
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2192410377
Short name T154
Test name
Test status
Simulation time 13796096048 ps
CPU time 666.98 seconds
Started Jul 26 06:04:05 PM PDT 24
Finished Jul 26 06:15:12 PM PDT 24
Peak memory 716404 kb
Host smart-491ad04e-494b-43da-a491-9977ba7ed06a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192410377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2192410377
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2463075840
Short name T277
Test name
Test status
Simulation time 5019595571 ps
CPU time 137.12 seconds
Started Jul 26 06:04:06 PM PDT 24
Finished Jul 26 06:06:23 PM PDT 24
Peak memory 199712 kb
Host smart-c1b653f9-656d-45f1-b070-28abff638f1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463075840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2463075840
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3446793837
Short name T138
Test name
Test status
Simulation time 10446807947 ps
CPU time 144.1 seconds
Started Jul 26 06:04:04 PM PDT 24
Finished Jul 26 06:06:28 PM PDT 24
Peak memory 199812 kb
Host smart-30cef981-1641-4c96-8845-0d9a47d69c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446793837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3446793837
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1998835686
Short name T332
Test name
Test status
Simulation time 61889208 ps
CPU time 3.06 seconds
Started Jul 26 06:04:04 PM PDT 24
Finished Jul 26 06:04:08 PM PDT 24
Peak memory 199652 kb
Host smart-54931ce6-c782-4af0-b58c-d072a1c6a35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998835686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1998835686
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.430444493
Short name T502
Test name
Test status
Simulation time 57531794515 ps
CPU time 3695.28 seconds
Started Jul 26 06:04:06 PM PDT 24
Finished Jul 26 07:05:42 PM PDT 24
Peak memory 846536 kb
Host smart-f538ab4e-ab3e-4fdd-aa28-dc4128a5912c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430444493 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.430444493
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3558062673
Short name T165
Test name
Test status
Simulation time 5106021607 ps
CPU time 60.02 seconds
Started Jul 26 06:04:05 PM PDT 24
Finished Jul 26 06:05:05 PM PDT 24
Peak memory 199672 kb
Host smart-815df24b-650f-4f1f-be33-642c1f3fa792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558062673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3558062673
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.563168047
Short name T410
Test name
Test status
Simulation time 16452291 ps
CPU time 0.63 seconds
Started Jul 26 06:04:17 PM PDT 24
Finished Jul 26 06:04:18 PM PDT 24
Peak memory 195660 kb
Host smart-fc04b7ee-90f9-4837-9bc0-bce77cd80f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563168047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.563168047
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2267521423
Short name T131
Test name
Test status
Simulation time 2328106292 ps
CPU time 66.09 seconds
Started Jul 26 06:04:17 PM PDT 24
Finished Jul 26 06:05:24 PM PDT 24
Peak memory 199660 kb
Host smart-c8429fc1-634d-421c-ae46-0173ce9afd66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267521423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2267521423
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.762129589
Short name T414
Test name
Test status
Simulation time 118025430 ps
CPU time 2.08 seconds
Started Jul 26 06:04:17 PM PDT 24
Finished Jul 26 06:04:19 PM PDT 24
Peak memory 199692 kb
Host smart-f7863f41-7ee9-4542-b7c3-3a9069bedfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762129589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.762129589
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1941451940
Short name T29
Test name
Test status
Simulation time 3144979170 ps
CPU time 539 seconds
Started Jul 26 06:04:17 PM PDT 24
Finished Jul 26 06:13:16 PM PDT 24
Peak memory 720780 kb
Host smart-a4cf3a3f-8316-44b4-a68f-261edf71507c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941451940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1941451940
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2112527376
Short name T216
Test name
Test status
Simulation time 18278171519 ps
CPU time 278.13 seconds
Started Jul 26 06:04:14 PM PDT 24
Finished Jul 26 06:08:52 PM PDT 24
Peak memory 199736 kb
Host smart-5a6b0b3f-8fae-47ea-9a21-703ce12b9558
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112527376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2112527376
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1172694437
Short name T194
Test name
Test status
Simulation time 60094446135 ps
CPU time 136.19 seconds
Started Jul 26 06:04:17 PM PDT 24
Finished Jul 26 06:06:34 PM PDT 24
Peak memory 199736 kb
Host smart-a28d6a50-b427-41a6-98fe-4ce08cca58bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172694437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1172694437
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1574680110
Short name T66
Test name
Test status
Simulation time 278520804 ps
CPU time 13.36 seconds
Started Jul 26 06:04:19 PM PDT 24
Finished Jul 26 06:04:33 PM PDT 24
Peak memory 199508 kb
Host smart-4b3dc922-d602-48d5-bb16-fa01b905837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574680110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1574680110
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1362153984
Short name T115
Test name
Test status
Simulation time 11744500405 ps
CPU time 964.65 seconds
Started Jul 26 06:04:16 PM PDT 24
Finished Jul 26 06:20:21 PM PDT 24
Peak memory 656516 kb
Host smart-0ef42996-b636-4190-9d89-e8e4cf44f513
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362153984 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1362153984
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1386863742
Short name T163
Test name
Test status
Simulation time 12259155996 ps
CPU time 117.12 seconds
Started Jul 26 06:04:15 PM PDT 24
Finished Jul 26 06:06:13 PM PDT 24
Peak memory 199720 kb
Host smart-fe6a31d2-dd1b-4eb8-9aae-5fdd18a197a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386863742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1386863742
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3323443204
Short name T139
Test name
Test status
Simulation time 6306197028 ps
CPU time 103.78 seconds
Started Jul 26 06:04:18 PM PDT 24
Finished Jul 26 06:06:01 PM PDT 24
Peak memory 208028 kb
Host smart-d146c77d-2f0c-464b-938b-6a6987100693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323443204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3323443204
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.924791533
Short name T299
Test name
Test status
Simulation time 281942637 ps
CPU time 4.08 seconds
Started Jul 26 06:04:16 PM PDT 24
Finished Jul 26 06:04:20 PM PDT 24
Peak memory 199580 kb
Host smart-ce7b78e5-467e-4456-81c4-9d596203a8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924791533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.924791533
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2653061440
Short name T515
Test name
Test status
Simulation time 7564752216 ps
CPU time 655.81 seconds
Started Jul 26 06:04:16 PM PDT 24
Finished Jul 26 06:15:12 PM PDT 24
Peak memory 509360 kb
Host smart-92162179-1652-4aa5-af7b-af8f6f05cd3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2653061440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2653061440
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2078109996
Short name T519
Test name
Test status
Simulation time 401617004 ps
CPU time 23.47 seconds
Started Jul 26 06:04:19 PM PDT 24
Finished Jul 26 06:04:43 PM PDT 24
Peak memory 199556 kb
Host smart-95077db3-3356-4975-8785-0fb203de7930
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078109996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2078109996
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2818886820
Short name T190
Test name
Test status
Simulation time 186050831204 ps
CPU time 175.3 seconds
Started Jul 26 06:04:15 PM PDT 24
Finished Jul 26 06:07:11 PM PDT 24
Peak memory 199648 kb
Host smart-2125d2f0-d6d9-4a3e-85df-50a05828ab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818886820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2818886820
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1669442632
Short name T45
Test name
Test status
Simulation time 143245734 ps
CPU time 7.13 seconds
Started Jul 26 06:04:16 PM PDT 24
Finished Jul 26 06:04:23 PM PDT 24
Peak memory 199636 kb
Host smart-4e91152d-6bce-4c62-9a48-135cbe4f92ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669442632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1669442632
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3214880120
Short name T330
Test name
Test status
Simulation time 16741134060 ps
CPU time 818.8 seconds
Started Jul 26 06:04:14 PM PDT 24
Finished Jul 26 06:17:53 PM PDT 24
Peak memory 710144 kb
Host smart-73d97b4e-d463-433f-81fa-c9378837d1a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214880120 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3214880120
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1986222843
Short name T385
Test name
Test status
Simulation time 12768149373 ps
CPU time 57.68 seconds
Started Jul 26 06:04:16 PM PDT 24
Finished Jul 26 06:05:14 PM PDT 24
Peak memory 199792 kb
Host smart-ede111fa-44ef-4647-a3a1-14db3c816e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986222843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1986222843
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2229688293
Short name T276
Test name
Test status
Simulation time 14744359 ps
CPU time 0.59 seconds
Started Jul 26 06:04:28 PM PDT 24
Finished Jul 26 06:04:29 PM PDT 24
Peak memory 196276 kb
Host smart-9212145a-a052-4ce7-82c1-af6d38e61ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229688293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2229688293
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1140891341
Short name T152
Test name
Test status
Simulation time 5455491038 ps
CPU time 76.47 seconds
Started Jul 26 06:04:30 PM PDT 24
Finished Jul 26 06:05:47 PM PDT 24
Peak memory 199696 kb
Host smart-b00c39a0-e385-4553-97b4-7dbe1ac0843f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140891341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1140891341
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1747324207
Short name T235
Test name
Test status
Simulation time 7485641256 ps
CPU time 22.48 seconds
Started Jul 26 06:04:26 PM PDT 24
Finished Jul 26 06:04:49 PM PDT 24
Peak memory 199692 kb
Host smart-038214c3-577e-405c-80dd-2e80c0c070ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747324207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1747324207
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.742367763
Short name T450
Test name
Test status
Simulation time 664170476 ps
CPU time 95.15 seconds
Started Jul 26 06:04:29 PM PDT 24
Finished Jul 26 06:06:05 PM PDT 24
Peak memory 331660 kb
Host smart-6730d657-5db1-4256-b95b-cbcff085bb29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=742367763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.742367763
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.361267055
Short name T479
Test name
Test status
Simulation time 22663307697 ps
CPU time 159.16 seconds
Started Jul 26 06:04:30 PM PDT 24
Finished Jul 26 06:07:09 PM PDT 24
Peak memory 199716 kb
Host smart-40af9259-9c66-4ca8-abc1-38acaeb43cc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361267055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.361267055
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2175079756
Short name T124
Test name
Test status
Simulation time 8573988043 ps
CPU time 121.39 seconds
Started Jul 26 06:04:28 PM PDT 24
Finished Jul 26 06:06:29 PM PDT 24
Peak memory 199712 kb
Host smart-aa444768-07a6-492d-9cb6-ff8eb814d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175079756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2175079756
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.581645679
Short name T435
Test name
Test status
Simulation time 77144806 ps
CPU time 2.22 seconds
Started Jul 26 06:04:29 PM PDT 24
Finished Jul 26 06:04:31 PM PDT 24
Peak memory 199624 kb
Host smart-4fcea358-c241-41b2-9a15-c940f2ad1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581645679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.581645679
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1339747534
Short name T69
Test name
Test status
Simulation time 250389029064 ps
CPU time 3917.68 seconds
Started Jul 26 06:04:28 PM PDT 24
Finished Jul 26 07:09:47 PM PDT 24
Peak memory 831820 kb
Host smart-0d17aa9d-894f-4318-ad97-9fe1d3691951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339747534 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1339747534
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3302754100
Short name T337
Test name
Test status
Simulation time 8298142404 ps
CPU time 106.08 seconds
Started Jul 26 06:04:29 PM PDT 24
Finished Jul 26 06:06:15 PM PDT 24
Peak memory 199692 kb
Host smart-dc32c06c-c50c-4f72-bde4-69c99de0654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302754100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3302754100
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3235333093
Short name T305
Test name
Test status
Simulation time 12003878 ps
CPU time 0.58 seconds
Started Jul 26 06:04:30 PM PDT 24
Finished Jul 26 06:04:31 PM PDT 24
Peak memory 194616 kb
Host smart-a2c0cfb3-202d-4045-bd50-b3e4ee9e9822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235333093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3235333093
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3079518668
Short name T416
Test name
Test status
Simulation time 6237985648 ps
CPU time 86.91 seconds
Started Jul 26 06:04:29 PM PDT 24
Finished Jul 26 06:05:56 PM PDT 24
Peak memory 208056 kb
Host smart-de1ec137-f840-4222-9b92-4dc4a935841e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079518668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3079518668
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.456706106
Short name T448
Test name
Test status
Simulation time 4003343872 ps
CPU time 45.84 seconds
Started Jul 26 06:04:28 PM PDT 24
Finished Jul 26 06:05:14 PM PDT 24
Peak memory 199744 kb
Host smart-5faa280a-8fc1-46ec-9cd1-53ee05918582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456706106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.456706106
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3019336120
Short name T247
Test name
Test status
Simulation time 13016310277 ps
CPU time 1350.2 seconds
Started Jul 26 06:04:29 PM PDT 24
Finished Jul 26 06:26:59 PM PDT 24
Peak memory 759840 kb
Host smart-e44be6c2-1fa5-47de-b9fc-3b1e73c12fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019336120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3019336120
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.861516659
Short name T1
Test name
Test status
Simulation time 38332678095 ps
CPU time 221.14 seconds
Started Jul 26 06:04:29 PM PDT 24
Finished Jul 26 06:08:10 PM PDT 24
Peak memory 199740 kb
Host smart-356542b5-f3ed-46d3-ab3f-472abf978b99
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861516659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.861516659
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1587692489
Short name T46
Test name
Test status
Simulation time 11157503385 ps
CPU time 44.43 seconds
Started Jul 26 06:04:27 PM PDT 24
Finished Jul 26 06:05:12 PM PDT 24
Peak memory 215896 kb
Host smart-78c2f95d-343d-4a4a-b469-8c40ce8be104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587692489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1587692489
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2940220836
Short name T214
Test name
Test status
Simulation time 6161174640 ps
CPU time 7.63 seconds
Started Jul 26 06:04:27 PM PDT 24
Finished Jul 26 06:04:35 PM PDT 24
Peak memory 199764 kb
Host smart-eef87b8e-2cfd-4853-afe0-5f8219b364cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940220836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2940220836
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3495534161
Short name T253
Test name
Test status
Simulation time 54336986005 ps
CPU time 2774.98 seconds
Started Jul 26 06:04:29 PM PDT 24
Finished Jul 26 06:50:44 PM PDT 24
Peak memory 786708 kb
Host smart-c2428784-ba9e-4fb6-9d10-109b4d4428af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495534161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3495534161
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3396739159
Short name T400
Test name
Test status
Simulation time 1301606387 ps
CPU time 19.72 seconds
Started Jul 26 06:04:28 PM PDT 24
Finished Jul 26 06:04:48 PM PDT 24
Peak memory 199596 kb
Host smart-af28ae58-3ad3-46ea-b987-a76d1290bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396739159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3396739159
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.621581283
Short name T296
Test name
Test status
Simulation time 13128979 ps
CPU time 0.59 seconds
Started Jul 26 06:04:39 PM PDT 24
Finished Jul 26 06:04:40 PM PDT 24
Peak memory 195644 kb
Host smart-50b25cac-3ddd-4910-bb27-4c4e4a1e38f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621581283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.621581283
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2066249400
Short name T5
Test name
Test status
Simulation time 5007676465 ps
CPU time 75.75 seconds
Started Jul 26 06:04:38 PM PDT 24
Finished Jul 26 06:05:54 PM PDT 24
Peak memory 199728 kb
Host smart-f8cba0cd-1724-46b6-b651-b6df0b95cc81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066249400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2066249400
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1804268855
Short name T427
Test name
Test status
Simulation time 6149745668 ps
CPU time 8.09 seconds
Started Jul 26 06:04:41 PM PDT 24
Finished Jul 26 06:04:50 PM PDT 24
Peak memory 199672 kb
Host smart-8cd1e375-9c4a-4113-b684-ea080003a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804268855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1804268855
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1902685581
Short name T459
Test name
Test status
Simulation time 7432109291 ps
CPU time 293.07 seconds
Started Jul 26 06:04:40 PM PDT 24
Finished Jul 26 06:09:33 PM PDT 24
Peak memory 440216 kb
Host smart-4cc9a73d-d7f4-4cf6-98d2-4c70de21d7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902685581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1902685581
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3002450934
Short name T480
Test name
Test status
Simulation time 10041156714 ps
CPU time 126.77 seconds
Started Jul 26 06:04:42 PM PDT 24
Finished Jul 26 06:06:49 PM PDT 24
Peak memory 199760 kb
Host smart-91c6c452-bd66-412c-9370-7477304a84c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002450934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3002450934
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1486730943
Short name T228
Test name
Test status
Simulation time 1093105180 ps
CPU time 61.82 seconds
Started Jul 26 06:04:30 PM PDT 24
Finished Jul 26 06:05:32 PM PDT 24
Peak memory 199656 kb
Host smart-322146b5-0522-4593-9d28-d46d0c362e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486730943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1486730943
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1067530777
Short name T351
Test name
Test status
Simulation time 716476195 ps
CPU time 7.88 seconds
Started Jul 26 06:04:30 PM PDT 24
Finished Jul 26 06:04:38 PM PDT 24
Peak memory 199640 kb
Host smart-5adc74f4-cbff-4272-9a6d-ffc42060311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067530777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1067530777
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2606083915
Short name T520
Test name
Test status
Simulation time 44438682818 ps
CPU time 575.93 seconds
Started Jul 26 06:04:40 PM PDT 24
Finished Jul 26 06:14:16 PM PDT 24
Peak memory 215908 kb
Host smart-9784258b-2c66-47d6-9761-03f944252ded
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606083915 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2606083915
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.787239169
Short name T453
Test name
Test status
Simulation time 1639057400 ps
CPU time 28 seconds
Started Jul 26 06:04:41 PM PDT 24
Finished Jul 26 06:05:10 PM PDT 24
Peak memory 199504 kb
Host smart-5eb0a90a-dbc9-415b-93f6-849048469b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787239169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.787239169
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.219672546
Short name T302
Test name
Test status
Simulation time 14204002 ps
CPU time 0.58 seconds
Started Jul 26 06:05:07 PM PDT 24
Finished Jul 26 06:05:07 PM PDT 24
Peak memory 194616 kb
Host smart-720be567-2450-497e-a7d7-99fe83154376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219672546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.219672546
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.245483604
Short name T267
Test name
Test status
Simulation time 599947967 ps
CPU time 35.71 seconds
Started Jul 26 06:04:43 PM PDT 24
Finished Jul 26 06:05:19 PM PDT 24
Peak memory 199632 kb
Host smart-141d2ef5-7a95-4874-b2e3-1ca2ba6929d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245483604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.245483604
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.4234549464
Short name T458
Test name
Test status
Simulation time 16323129871 ps
CPU time 37.44 seconds
Started Jul 26 06:04:39 PM PDT 24
Finished Jul 26 06:05:16 PM PDT 24
Peak memory 199736 kb
Host smart-7d3371f0-f6ac-47a7-891a-3d42d655d79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234549464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.4234549464
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1571307369
Short name T488
Test name
Test status
Simulation time 7022684955 ps
CPU time 1352.68 seconds
Started Jul 26 06:04:39 PM PDT 24
Finished Jul 26 06:27:12 PM PDT 24
Peak memory 778504 kb
Host smart-a9503148-93f8-4ea1-aba2-5f79b753e54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571307369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1571307369
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1318109518
Short name T376
Test name
Test status
Simulation time 9256034732 ps
CPU time 133.15 seconds
Started Jul 26 06:04:41 PM PDT 24
Finished Jul 26 06:06:55 PM PDT 24
Peak memory 199656 kb
Host smart-e120bfad-f3b9-4383-a9f4-9ea4f36e418a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318109518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1318109518
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1079115187
Short name T306
Test name
Test status
Simulation time 75426605208 ps
CPU time 143.6 seconds
Started Jul 26 06:04:43 PM PDT 24
Finished Jul 26 06:07:07 PM PDT 24
Peak memory 199712 kb
Host smart-f05853b7-f065-4bd5-a319-062a343d3984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079115187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1079115187
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2984889533
Short name T262
Test name
Test status
Simulation time 5491895627 ps
CPU time 9.77 seconds
Started Jul 26 06:04:43 PM PDT 24
Finished Jul 26 06:04:53 PM PDT 24
Peak memory 199848 kb
Host smart-76b9c87e-f147-4ea8-a059-273461d61d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984889533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2984889533
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3330363079
Short name T291
Test name
Test status
Simulation time 64338564577 ps
CPU time 2119.97 seconds
Started Jul 26 06:04:39 PM PDT 24
Finished Jul 26 06:40:00 PM PDT 24
Peak memory 686384 kb
Host smart-b7359236-6e2c-442d-8d1a-97f44a1d46f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330363079 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3330363079
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2395901500
Short name T68
Test name
Test status
Simulation time 4517834344 ps
CPU time 60.08 seconds
Started Jul 26 06:04:40 PM PDT 24
Finished Jul 26 06:05:41 PM PDT 24
Peak memory 199708 kb
Host smart-f01abe2e-87be-44af-bbfb-f9887432f3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395901500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2395901500
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3485796622
Short name T495
Test name
Test status
Simulation time 11950031 ps
CPU time 0.55 seconds
Started Jul 26 06:02:34 PM PDT 24
Finished Jul 26 06:02:34 PM PDT 24
Peak memory 194560 kb
Host smart-47a64537-ea02-4fd8-857f-87ed311ee8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485796622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3485796622
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2086465427
Short name T292
Test name
Test status
Simulation time 5862175827 ps
CPU time 77.6 seconds
Started Jul 26 06:02:30 PM PDT 24
Finished Jul 26 06:03:48 PM PDT 24
Peak memory 199724 kb
Host smart-88f0c932-afad-401f-8fb4-886a0505bac3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086465427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2086465427
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.346179929
Short name T155
Test name
Test status
Simulation time 83079421 ps
CPU time 0.89 seconds
Started Jul 26 06:02:33 PM PDT 24
Finished Jul 26 06:02:34 PM PDT 24
Peak memory 198808 kb
Host smart-8374a8b7-8b6f-424d-8a36-594174271be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346179929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.346179929
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.29280091
Short name T281
Test name
Test status
Simulation time 16667358442 ps
CPU time 760.24 seconds
Started Jul 26 06:02:30 PM PDT 24
Finished Jul 26 06:15:10 PM PDT 24
Peak memory 750280 kb
Host smart-1e3325eb-7a15-474a-993a-af6e2bd343a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29280091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.29280091
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2620091732
Short name T505
Test name
Test status
Simulation time 260373896 ps
CPU time 3.98 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:02:35 PM PDT 24
Peak memory 199592 kb
Host smart-5c63ee5b-ccc0-4669-8721-c46d07194b5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620091732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2620091732
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2444656116
Short name T116
Test name
Test status
Simulation time 12380141752 ps
CPU time 177.2 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:05:29 PM PDT 24
Peak memory 207968 kb
Host smart-23c7e3b6-be6a-4f9a-9ebf-ac8e39b22fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444656116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2444656116
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3929975919
Short name T36
Test name
Test status
Simulation time 1790722722 ps
CPU time 1.19 seconds
Started Jul 26 06:02:29 PM PDT 24
Finished Jul 26 06:02:31 PM PDT 24
Peak memory 218184 kb
Host smart-547614cd-0b0e-414c-bd54-4e7dc1fe2a99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929975919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3929975919
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.103434463
Short name T390
Test name
Test status
Simulation time 2857725855 ps
CPU time 11.95 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:02:43 PM PDT 24
Peak memory 199600 kb
Host smart-e0055e5d-e921-4337-bb68-af9c83e7b7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103434463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.103434463
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.330960793
Short name T397
Test name
Test status
Simulation time 216182804170 ps
CPU time 3062.82 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:53:35 PM PDT 24
Peak memory 801808 kb
Host smart-f39d05ab-b06b-48cc-8920-017f753f3737
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330960793 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.330960793
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2892470635
Short name T15
Test name
Test status
Simulation time 151700214405 ps
CPU time 1830.26 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:33:01 PM PDT 24
Peak memory 751720 kb
Host smart-7e69f5ea-163b-4f46-9c39-6628a245e76c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892470635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2892470635
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3692427271
Short name T420
Test name
Test status
Simulation time 52738248475 ps
CPU time 86.87 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:03:58 PM PDT 24
Peak memory 199604 kb
Host smart-41a46650-83b4-4fb3-846e-65f14fe11d93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3692427271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3692427271
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3580774938
Short name T380
Test name
Test status
Simulation time 4881780164 ps
CPU time 97.76 seconds
Started Jul 26 06:02:29 PM PDT 24
Finished Jul 26 06:04:06 PM PDT 24
Peak memory 199948 kb
Host smart-90b0aec3-1356-435b-bf4c-31a6637e2f8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3580774938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3580774938
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.27993411
Short name T23
Test name
Test status
Simulation time 127592450650 ps
CPU time 123.51 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:04:34 PM PDT 24
Peak memory 199696 kb
Host smart-aa11863c-af5f-409c-a4d0-6e87a1598ffa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=27993411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.27993411
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3935748318
Short name T371
Test name
Test status
Simulation time 20322888618 ps
CPU time 541.29 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:11:33 PM PDT 24
Peak memory 199672 kb
Host smart-54fac51e-9b11-44d6-9485-37e28a5560d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3935748318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3935748318
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2603831484
Short name T106
Test name
Test status
Simulation time 302347483487 ps
CPU time 2523.69 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:44:36 PM PDT 24
Peak memory 215352 kb
Host smart-6cb1091f-5039-461a-8a5d-d127cb2cbc71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2603831484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2603831484
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1166795516
Short name T107
Test name
Test status
Simulation time 90955123032 ps
CPU time 2228.43 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:39:41 PM PDT 24
Peak memory 215468 kb
Host smart-4ad1322c-ae7f-426f-b665-03b8a5675cf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1166795516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1166795516
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3466970144
Short name T443
Test name
Test status
Simulation time 11839023597 ps
CPU time 13.1 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:02:45 PM PDT 24
Peak memory 199704 kb
Host smart-4b971eba-f3df-4cb1-bb71-ee79fc61cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466970144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3466970144
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1927828064
Short name T303
Test name
Test status
Simulation time 39292295 ps
CPU time 0.58 seconds
Started Jul 26 06:04:40 PM PDT 24
Finished Jul 26 06:04:40 PM PDT 24
Peak memory 196304 kb
Host smart-b9ae6399-3e0c-4156-8e26-a283468a4598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927828064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1927828064
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.877081093
Short name T246
Test name
Test status
Simulation time 1075122251 ps
CPU time 66.73 seconds
Started Jul 26 06:04:39 PM PDT 24
Finished Jul 26 06:05:46 PM PDT 24
Peak memory 199692 kb
Host smart-5409665e-fcbd-4b88-a830-97226e8037d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877081093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.877081093
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3732214627
Short name T113
Test name
Test status
Simulation time 1523458028 ps
CPU time 19.48 seconds
Started Jul 26 06:04:43 PM PDT 24
Finished Jul 26 06:05:03 PM PDT 24
Peak memory 199708 kb
Host smart-ce68656e-1b79-4dfd-aefa-a3e39962b8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732214627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3732214627
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3179706188
Short name T162
Test name
Test status
Simulation time 50703577 ps
CPU time 3.03 seconds
Started Jul 26 06:04:39 PM PDT 24
Finished Jul 26 06:04:42 PM PDT 24
Peak memory 199692 kb
Host smart-42e3b5a7-888d-40ff-98c7-73be75549428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179706188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3179706188
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.749060061
Short name T355
Test name
Test status
Simulation time 17935330947 ps
CPU time 181.34 seconds
Started Jul 26 06:04:40 PM PDT 24
Finished Jul 26 06:07:42 PM PDT 24
Peak memory 199708 kb
Host smart-a7df4676-fa6c-4d23-b589-9d6e8ed554d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749060061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.749060061
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1883436468
Short name T328
Test name
Test status
Simulation time 2207990992 ps
CPU time 38.93 seconds
Started Jul 26 06:04:38 PM PDT 24
Finished Jul 26 06:05:17 PM PDT 24
Peak memory 199684 kb
Host smart-74c5837a-d901-4110-9696-e979e9af52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883436468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1883436468
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1367230897
Short name T311
Test name
Test status
Simulation time 625194673 ps
CPU time 14.95 seconds
Started Jul 26 06:04:41 PM PDT 24
Finished Jul 26 06:04:57 PM PDT 24
Peak memory 199544 kb
Host smart-4b603ca8-91c4-4e21-9609-431d35e20b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367230897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1367230897
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1264860728
Short name T501
Test name
Test status
Simulation time 18201198735 ps
CPU time 128.93 seconds
Started Jul 26 06:04:41 PM PDT 24
Finished Jul 26 06:06:50 PM PDT 24
Peak memory 199644 kb
Host smart-d1a43d50-6452-43ea-83b6-69eab507d3c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264860728 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1264860728
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1628216285
Short name T399
Test name
Test status
Simulation time 2838918206 ps
CPU time 10.3 seconds
Started Jul 26 06:04:38 PM PDT 24
Finished Jul 26 06:04:49 PM PDT 24
Peak memory 199764 kb
Host smart-576f1c3f-b9fe-4293-bf71-c2206c299f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628216285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1628216285
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3394804743
Short name T357
Test name
Test status
Simulation time 14094604 ps
CPU time 0.59 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:04:52 PM PDT 24
Peak memory 196320 kb
Host smart-41b17f15-0fa4-4d5d-a866-cef3bd27e8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394804743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3394804743
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3025155670
Short name T423
Test name
Test status
Simulation time 835047551 ps
CPU time 17.17 seconds
Started Jul 26 06:04:52 PM PDT 24
Finished Jul 26 06:05:09 PM PDT 24
Peak memory 199692 kb
Host smart-c7df7fbc-26ec-4d73-ba59-afb17a557c55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025155670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3025155670
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3522327415
Short name T9
Test name
Test status
Simulation time 3936701415 ps
CPU time 53.08 seconds
Started Jul 26 06:04:52 PM PDT 24
Finished Jul 26 06:05:45 PM PDT 24
Peak memory 199808 kb
Host smart-e253415b-4adf-4e67-bc80-f3a79466b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522327415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3522327415
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.281488743
Short name T401
Test name
Test status
Simulation time 1610727836 ps
CPU time 43.28 seconds
Started Jul 26 06:04:52 PM PDT 24
Finished Jul 26 06:05:36 PM PDT 24
Peak memory 310396 kb
Host smart-ff6fc211-9f1d-4304-aa1e-a8b3c24d084a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281488743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.281488743
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2466763158
Short name T403
Test name
Test status
Simulation time 12337956338 ps
CPU time 159.68 seconds
Started Jul 26 06:04:53 PM PDT 24
Finished Jul 26 06:07:32 PM PDT 24
Peak memory 199752 kb
Host smart-6c8d0c0f-277b-4708-ae52-6b8d391e559f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466763158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2466763158
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4172896108
Short name T204
Test name
Test status
Simulation time 4231355481 ps
CPU time 21.14 seconds
Started Jul 26 06:04:49 PM PDT 24
Finished Jul 26 06:05:10 PM PDT 24
Peak memory 199948 kb
Host smart-dd2ec650-3abb-4447-a7ec-6ef481333c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172896108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4172896108
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.218074359
Short name T109
Test name
Test status
Simulation time 96009542 ps
CPU time 1.51 seconds
Started Jul 26 06:04:40 PM PDT 24
Finished Jul 26 06:04:42 PM PDT 24
Peak memory 199640 kb
Host smart-1c9a1e6a-bc30-4d22-ac38-7a5fafe164d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218074359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.218074359
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.631891595
Short name T460
Test name
Test status
Simulation time 13615372425 ps
CPU time 288.67 seconds
Started Jul 26 06:04:53 PM PDT 24
Finished Jul 26 06:09:42 PM PDT 24
Peak memory 465476 kb
Host smart-f690abcb-1788-4fb5-8c5f-ba4fbafbf040
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631891595 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.631891595
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1215435708
Short name T264
Test name
Test status
Simulation time 17588874438 ps
CPU time 114.05 seconds
Started Jul 26 06:04:52 PM PDT 24
Finished Jul 26 06:06:46 PM PDT 24
Peak memory 199716 kb
Host smart-4d0cfc8a-8f6d-40a0-b6bf-25283c13327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215435708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1215435708
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2031986676
Short name T509
Test name
Test status
Simulation time 16475269 ps
CPU time 0.62 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:04:52 PM PDT 24
Peak memory 195672 kb
Host smart-fc2a30f7-6a86-4a8b-ad85-9b0b430049fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031986676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2031986676
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3177931113
Short name T195
Test name
Test status
Simulation time 1572849014 ps
CPU time 22.69 seconds
Started Jul 26 06:04:52 PM PDT 24
Finished Jul 26 06:05:14 PM PDT 24
Peak memory 199688 kb
Host smart-dad74aaa-4a21-41db-bba2-9160a34a9454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177931113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3177931113
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.653037385
Short name T244
Test name
Test status
Simulation time 1459083232 ps
CPU time 20.78 seconds
Started Jul 26 06:04:48 PM PDT 24
Finished Jul 26 06:05:09 PM PDT 24
Peak memory 199644 kb
Host smart-ce5463ef-479f-4cff-88ec-f4245e1a0417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653037385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.653037385
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.529188377
Short name T26
Test name
Test status
Simulation time 482470596 ps
CPU time 95.74 seconds
Started Jul 26 06:04:50 PM PDT 24
Finished Jul 26 06:06:26 PM PDT 24
Peak memory 472940 kb
Host smart-a348aaac-eefa-4eff-ad76-5a1f57cff9c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529188377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.529188377
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1446535142
Short name T500
Test name
Test status
Simulation time 3126612133 ps
CPU time 45.96 seconds
Started Jul 26 06:04:52 PM PDT 24
Finished Jul 26 06:05:39 PM PDT 24
Peak memory 199688 kb
Host smart-a6152022-a0df-4696-8a5d-1ab26ae17d34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446535142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1446535142
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3812941607
Short name T389
Test name
Test status
Simulation time 5762416202 ps
CPU time 176.06 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:07:48 PM PDT 24
Peak memory 199696 kb
Host smart-324abc54-fd16-4a3c-bc55-c8f32b0bea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812941607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3812941607
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4054041486
Short name T304
Test name
Test status
Simulation time 157673566 ps
CPU time 3.77 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:04:55 PM PDT 24
Peak memory 199692 kb
Host smart-612c99da-4ee4-4701-ade4-f463d6c7f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054041486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4054041486
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2943080686
Short name T301
Test name
Test status
Simulation time 63504687362 ps
CPU time 2324.81 seconds
Started Jul 26 06:04:52 PM PDT 24
Finished Jul 26 06:43:38 PM PDT 24
Peak memory 695920 kb
Host smart-39ae6e38-e033-43b1-b801-d2217fed92d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943080686 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2943080686
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3934866825
Short name T183
Test name
Test status
Simulation time 9478414096 ps
CPU time 131.98 seconds
Started Jul 26 06:04:48 PM PDT 24
Finished Jul 26 06:07:00 PM PDT 24
Peak memory 199672 kb
Host smart-9f6a2184-20fe-488c-8ccb-6478087d778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934866825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3934866825
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2131441984
Short name T532
Test name
Test status
Simulation time 10653693 ps
CPU time 0.59 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:05:03 PM PDT 24
Peak memory 194672 kb
Host smart-c5453278-1201-4ae6-b828-d4f4f6d4134e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131441984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2131441984
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3064051503
Short name T422
Test name
Test status
Simulation time 5408427707 ps
CPU time 91.38 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:06:23 PM PDT 24
Peak memory 199668 kb
Host smart-a5ee7cb8-5cec-421a-b41b-fec37b0db95e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064051503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3064051503
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3923869686
Short name T379
Test name
Test status
Simulation time 70147699 ps
CPU time 3.91 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:05:06 PM PDT 24
Peak memory 199648 kb
Host smart-74ddafa6-e930-487a-9435-418ad9c137d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923869686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3923869686
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.582812756
Short name T438
Test name
Test status
Simulation time 31302194223 ps
CPU time 1225.82 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:25:17 PM PDT 24
Peak memory 735184 kb
Host smart-70ab054a-9afb-45bf-a4c8-cee9cb641f29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582812756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.582812756
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2041106713
Short name T283
Test name
Test status
Simulation time 1821558134 ps
CPU time 107.73 seconds
Started Jul 26 06:05:01 PM PDT 24
Finished Jul 26 06:06:49 PM PDT 24
Peak memory 199676 kb
Host smart-75da2e8d-ac21-42c8-b3d9-cc89f69ab3cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041106713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2041106713
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.728350055
Short name T368
Test name
Test status
Simulation time 5630498327 ps
CPU time 73.38 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:06:04 PM PDT 24
Peak memory 199692 kb
Host smart-066961e3-f72d-414b-9806-c637dad3e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728350055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.728350055
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3806952713
Short name T462
Test name
Test status
Simulation time 5661193358 ps
CPU time 16.13 seconds
Started Jul 26 06:04:51 PM PDT 24
Finished Jul 26 06:05:07 PM PDT 24
Peak memory 199724 kb
Host smart-4782ec95-f818-47ff-9afb-c2b012f59873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806952713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3806952713
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2142812077
Short name T62
Test name
Test status
Simulation time 1961060781324 ps
CPU time 5297.48 seconds
Started Jul 26 06:05:05 PM PDT 24
Finished Jul 26 07:33:23 PM PDT 24
Peak memory 842868 kb
Host smart-5b4aabe2-014b-45cf-b65a-76079efca62d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142812077 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2142812077
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3722233918
Short name T282
Test name
Test status
Simulation time 6411123204 ps
CPU time 104.6 seconds
Started Jul 26 06:05:05 PM PDT 24
Finished Jul 26 06:06:50 PM PDT 24
Peak memory 199680 kb
Host smart-621e1100-d6a1-45a9-bf6c-a413dc0906c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722233918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3722233918
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1219113337
Short name T375
Test name
Test status
Simulation time 42286122 ps
CPU time 0.61 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:05:03 PM PDT 24
Peak memory 195628 kb
Host smart-e9c5782a-ff09-41b7-b2ed-4c02d7d25506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219113337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1219113337
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.684378003
Short name T342
Test name
Test status
Simulation time 1277807091 ps
CPU time 73.71 seconds
Started Jul 26 06:05:01 PM PDT 24
Finished Jul 26 06:06:15 PM PDT 24
Peak memory 199652 kb
Host smart-38899250-4e6c-4d80-9265-f7f5ab3d66b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684378003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.684378003
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1308922935
Short name T30
Test name
Test status
Simulation time 1299070166 ps
CPU time 67.19 seconds
Started Jul 26 06:05:01 PM PDT 24
Finished Jul 26 06:06:08 PM PDT 24
Peak memory 199684 kb
Host smart-cdc4b87b-0279-4296-b18f-bcbad1445eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308922935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1308922935
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1575577546
Short name T196
Test name
Test status
Simulation time 1740586531 ps
CPU time 285.7 seconds
Started Jul 26 06:04:59 PM PDT 24
Finished Jul 26 06:09:45 PM PDT 24
Peak memory 484968 kb
Host smart-1e5c7694-f672-4ab9-bd56-70be73fc5778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1575577546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1575577546
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1456901988
Short name T272
Test name
Test status
Simulation time 363419183 ps
CPU time 20.2 seconds
Started Jul 26 06:05:03 PM PDT 24
Finished Jul 26 06:05:23 PM PDT 24
Peak memory 199652 kb
Host smart-cbd25ce7-3062-4051-a8bb-87cddda97dd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456901988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1456901988
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1297072602
Short name T362
Test name
Test status
Simulation time 4190133971 ps
CPU time 124.48 seconds
Started Jul 26 06:05:06 PM PDT 24
Finished Jul 26 06:07:11 PM PDT 24
Peak memory 199192 kb
Host smart-aeb81f38-0f6c-40de-b47c-69453f0d1b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297072602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1297072602
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2088517964
Short name T229
Test name
Test status
Simulation time 1352967394 ps
CPU time 13.56 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:05:16 PM PDT 24
Peak memory 199608 kb
Host smart-1778b342-a876-4d80-bce2-b5562a5ee116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088517964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2088517964
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.971365045
Short name T209
Test name
Test status
Simulation time 6230723643 ps
CPU time 69.41 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:06:12 PM PDT 24
Peak memory 199692 kb
Host smart-ce49bdef-9e3e-4d1a-aa25-f0ce6106c7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971365045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.971365045
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.235651232
Short name T430
Test name
Test status
Simulation time 12243110 ps
CPU time 0.6 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:05:02 PM PDT 24
Peak memory 195292 kb
Host smart-d1e8b03f-4cda-465b-bf70-de717f344c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235651232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.235651232
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.938559850
Short name T121
Test name
Test status
Simulation time 6550868542 ps
CPU time 91.26 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:06:34 PM PDT 24
Peak memory 199704 kb
Host smart-74c3823f-0875-4e23-b0d8-593b58b62b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938559850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.938559850
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3883993996
Short name T432
Test name
Test status
Simulation time 321905467 ps
CPU time 16.15 seconds
Started Jul 26 06:05:06 PM PDT 24
Finished Jul 26 06:05:23 PM PDT 24
Peak memory 199644 kb
Host smart-5f3e4487-67ce-45d1-887d-f81673bcbd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883993996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3883993996
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1909662547
Short name T455
Test name
Test status
Simulation time 17444674435 ps
CPU time 864.83 seconds
Started Jul 26 06:05:03 PM PDT 24
Finished Jul 26 06:19:28 PM PDT 24
Peak memory 506464 kb
Host smart-54cdb7e4-6fa9-44bf-b920-739ecab0b427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909662547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1909662547
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1298252184
Short name T118
Test name
Test status
Simulation time 2821566937 ps
CPU time 50.69 seconds
Started Jul 26 06:05:01 PM PDT 24
Finished Jul 26 06:05:52 PM PDT 24
Peak memory 199684 kb
Host smart-d87ef385-bb62-47eb-871b-0422fba21c26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298252184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1298252184
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3593563646
Short name T437
Test name
Test status
Simulation time 2117350471 ps
CPU time 57.03 seconds
Started Jul 26 06:05:01 PM PDT 24
Finished Jul 26 06:05:58 PM PDT 24
Peak memory 199604 kb
Host smart-61c1d4ef-fa04-4a6a-912a-250691cf9f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593563646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3593563646
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.608073760
Short name T358
Test name
Test status
Simulation time 740151867 ps
CPU time 4.9 seconds
Started Jul 26 06:05:03 PM PDT 24
Finished Jul 26 06:05:08 PM PDT 24
Peak memory 199644 kb
Host smart-6c4d60b0-ea57-4022-9740-72153fd6f2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608073760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.608073760
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1481836572
Short name T333
Test name
Test status
Simulation time 6106204095 ps
CPU time 35.74 seconds
Started Jul 26 06:05:06 PM PDT 24
Finished Jul 26 06:05:42 PM PDT 24
Peak memory 199156 kb
Host smart-95d99bad-85ba-4dd9-8b3e-1496b0858ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481836572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1481836572
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3614304375
Short name T226
Test name
Test status
Simulation time 114754462 ps
CPU time 0.62 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:05:15 PM PDT 24
Peak memory 195368 kb
Host smart-ca723426-5f63-4903-b560-939cf1e9cd0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614304375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3614304375
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.162672198
Short name T158
Test name
Test status
Simulation time 191785221 ps
CPU time 3.1 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:05:05 PM PDT 24
Peak memory 199668 kb
Host smart-7b19d4ec-85ef-4f6f-bf83-287cbd6f0b1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162672198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.162672198
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3497101547
Short name T111
Test name
Test status
Simulation time 684850781 ps
CPU time 38.78 seconds
Started Jul 26 06:05:03 PM PDT 24
Finished Jul 26 06:05:42 PM PDT 24
Peak memory 199644 kb
Host smart-2475620a-a37d-4cd7-9989-454afad1dba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497101547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3497101547
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.92879033
Short name T318
Test name
Test status
Simulation time 4177902614 ps
CPU time 921.79 seconds
Started Jul 26 06:05:02 PM PDT 24
Finished Jul 26 06:20:24 PM PDT 24
Peak memory 671228 kb
Host smart-7df70d60-c1af-4fe2-b9e1-c243ca48195f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92879033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.92879033
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3769938091
Short name T177
Test name
Test status
Simulation time 14768639232 ps
CPU time 185.94 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:08:21 PM PDT 24
Peak memory 199712 kb
Host smart-0a906b0b-aedd-4686-985e-52b7a8c148ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769938091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3769938091
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2856465466
Short name T433
Test name
Test status
Simulation time 35479585567 ps
CPU time 170.99 seconds
Started Jul 26 06:05:04 PM PDT 24
Finished Jul 26 06:07:55 PM PDT 24
Peak memory 199820 kb
Host smart-4dee4049-caca-4ba0-801e-0504c444d7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856465466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2856465466
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.240116945
Short name T424
Test name
Test status
Simulation time 163243145 ps
CPU time 2.23 seconds
Started Jul 26 06:05:03 PM PDT 24
Finished Jul 26 06:05:05 PM PDT 24
Peak memory 199604 kb
Host smart-32bf4585-3892-49bc-aa23-18c47a0afdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240116945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.240116945
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2996152307
Short name T170
Test name
Test status
Simulation time 2242252441 ps
CPU time 137.87 seconds
Started Jul 26 06:05:14 PM PDT 24
Finished Jul 26 06:07:32 PM PDT 24
Peak memory 260332 kb
Host smart-f30bbfbf-5067-4f25-bc53-0ee68ca9e23b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996152307 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2996152307
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2644598446
Short name T274
Test name
Test status
Simulation time 17686907213 ps
CPU time 87.69 seconds
Started Jul 26 06:05:13 PM PDT 24
Finished Jul 26 06:06:41 PM PDT 24
Peak memory 199716 kb
Host smart-23afaebb-e1f1-4dff-8746-7bd4d8d8c43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644598446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2644598446
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3567472207
Short name T224
Test name
Test status
Simulation time 21712399 ps
CPU time 0.59 seconds
Started Jul 26 06:05:16 PM PDT 24
Finished Jul 26 06:05:17 PM PDT 24
Peak memory 195696 kb
Host smart-42944b89-973a-46ba-b834-3b4555293b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567472207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3567472207
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.166119126
Short name T441
Test name
Test status
Simulation time 348934250 ps
CPU time 5.13 seconds
Started Jul 26 06:05:14 PM PDT 24
Finished Jul 26 06:05:20 PM PDT 24
Peak memory 199636 kb
Host smart-422b1834-1827-4787-ab64-4fdcb689a3fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166119126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.166119126
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3626138843
Short name T493
Test name
Test status
Simulation time 2837616129 ps
CPU time 51.16 seconds
Started Jul 26 06:05:13 PM PDT 24
Finished Jul 26 06:06:05 PM PDT 24
Peak memory 199708 kb
Host smart-638e2b9e-9549-4693-a6a5-f12be4157713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626138843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3626138843
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1794580939
Short name T447
Test name
Test status
Simulation time 4704409392 ps
CPU time 764.11 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:17:59 PM PDT 24
Peak memory 707700 kb
Host smart-a0b68b79-789a-4598-9395-d130fea91c92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794580939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1794580939
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4250835483
Short name T457
Test name
Test status
Simulation time 2911109911 ps
CPU time 167.94 seconds
Started Jul 26 06:05:14 PM PDT 24
Finished Jul 26 06:08:02 PM PDT 24
Peak memory 199580 kb
Host smart-2fd4b5c1-b437-49c6-8392-c47b09f88495
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250835483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4250835483
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3489735119
Short name T160
Test name
Test status
Simulation time 3799226211 ps
CPU time 22.35 seconds
Started Jul 26 06:05:13 PM PDT 24
Finished Jul 26 06:05:36 PM PDT 24
Peak memory 199708 kb
Host smart-175748bd-3c07-4577-9952-9ad6289e3ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489735119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3489735119
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.990931055
Short name T48
Test name
Test status
Simulation time 895762195 ps
CPU time 15.23 seconds
Started Jul 26 06:05:16 PM PDT 24
Finished Jul 26 06:05:32 PM PDT 24
Peak memory 199644 kb
Host smart-467b71be-809b-4853-bb9d-a2df8e03eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990931055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.990931055
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4172954300
Short name T59
Test name
Test status
Simulation time 20410584473 ps
CPU time 62.46 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:06:18 PM PDT 24
Peak memory 199672 kb
Host smart-48e4a8a2-8dc4-415d-be74-116d94cc38df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172954300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4172954300
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3694539017
Short name T231
Test name
Test status
Simulation time 22266501177 ps
CPU time 130.4 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:07:26 PM PDT 24
Peak memory 199716 kb
Host smart-97c9b000-8fd7-464c-a267-6bb2fba9886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694539017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3694539017
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.440229515
Short name T186
Test name
Test status
Simulation time 12575284 ps
CPU time 0.59 seconds
Started Jul 26 06:05:28 PM PDT 24
Finished Jul 26 06:05:29 PM PDT 24
Peak memory 194664 kb
Host smart-503a5b6b-0ae8-47e6-a5d8-3f8c7121abbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440229515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.440229515
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3483066737
Short name T227
Test name
Test status
Simulation time 1074769024 ps
CPU time 32.71 seconds
Started Jul 26 06:05:14 PM PDT 24
Finished Jul 26 06:05:47 PM PDT 24
Peak memory 199628 kb
Host smart-88b3fc6f-3df0-463e-a336-d08f00796bf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483066737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3483066737
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1592960728
Short name T112
Test name
Test status
Simulation time 1865056479 ps
CPU time 51.99 seconds
Started Jul 26 06:05:16 PM PDT 24
Finished Jul 26 06:06:08 PM PDT 24
Peak memory 199616 kb
Host smart-71d364bf-fc82-46ec-b10f-bb99aab42704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592960728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1592960728
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.425177237
Short name T396
Test name
Test status
Simulation time 5054219643 ps
CPU time 230.07 seconds
Started Jul 26 06:05:16 PM PDT 24
Finished Jul 26 06:09:06 PM PDT 24
Peak memory 622616 kb
Host smart-3fcccf10-4859-40cc-a6aa-7959946a1477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425177237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.425177237
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.4071282497
Short name T516
Test name
Test status
Simulation time 30112080100 ps
CPU time 189.35 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:08:24 PM PDT 24
Peak memory 199692 kb
Host smart-20b90b2b-0da3-4c6a-aceb-37c933c1e966
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071282497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.4071282497
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1963215133
Short name T252
Test name
Test status
Simulation time 890745675 ps
CPU time 12.11 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:05:27 PM PDT 24
Peak memory 199660 kb
Host smart-09c6f5c7-5ac7-4b49-bbfc-533e65b59f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963215133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1963215133
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.4120950570
Short name T507
Test name
Test status
Simulation time 535311431 ps
CPU time 5.99 seconds
Started Jul 26 06:05:14 PM PDT 24
Finished Jul 26 06:05:20 PM PDT 24
Peak memory 199620 kb
Host smart-74a53ddc-d3b0-4b37-9472-d73f4dbe6a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120950570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.4120950570
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3534575808
Short name T65
Test name
Test status
Simulation time 443450560862 ps
CPU time 2676.59 seconds
Started Jul 26 06:05:24 PM PDT 24
Finished Jul 26 06:50:01 PM PDT 24
Peak memory 787108 kb
Host smart-ddc5dfce-1f2f-4222-acfb-a95941c465e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534575808 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3534575808
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3179442423
Short name T413
Test name
Test status
Simulation time 24738837258 ps
CPU time 83.94 seconds
Started Jul 26 06:05:15 PM PDT 24
Finished Jul 26 06:06:39 PM PDT 24
Peak memory 199740 kb
Host smart-c237df9c-da77-459b-8365-8d735a12daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179442423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3179442423
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.35642154
Short name T530
Test name
Test status
Simulation time 56316602 ps
CPU time 0.58 seconds
Started Jul 26 06:05:30 PM PDT 24
Finished Jul 26 06:05:31 PM PDT 24
Peak memory 195648 kb
Host smart-1df66957-61a1-4511-b16f-1c50b6bbda8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35642154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.35642154
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.238093446
Short name T524
Test name
Test status
Simulation time 224395078 ps
CPU time 2.22 seconds
Started Jul 26 06:05:28 PM PDT 24
Finished Jul 26 06:05:30 PM PDT 24
Peak memory 199532 kb
Host smart-c6127f5b-914d-4456-bed0-c4220abd1037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238093446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.238093446
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.620797173
Short name T41
Test name
Test status
Simulation time 14559492258 ps
CPU time 45.89 seconds
Started Jul 26 06:05:27 PM PDT 24
Finished Jul 26 06:06:13 PM PDT 24
Peak memory 207916 kb
Host smart-ab8f3a07-b781-408e-b7cc-491be9dad134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620797173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.620797173
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1260100380
Short name T338
Test name
Test status
Simulation time 30395206767 ps
CPU time 1518.41 seconds
Started Jul 26 06:05:27 PM PDT 24
Finished Jul 26 06:30:46 PM PDT 24
Peak memory 775844 kb
Host smart-d64b46ca-b9a7-41a2-ae41-512ac41187e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260100380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1260100380
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2241250292
Short name T239
Test name
Test status
Simulation time 2703662802 ps
CPU time 155.84 seconds
Started Jul 26 06:05:26 PM PDT 24
Finished Jul 26 06:08:02 PM PDT 24
Peak memory 199712 kb
Host smart-5d0204c6-1f12-4d28-82ea-98764b4eee54
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241250292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2241250292
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3450973652
Short name T476
Test name
Test status
Simulation time 10638914088 ps
CPU time 141.96 seconds
Started Jul 26 06:05:27 PM PDT 24
Finished Jul 26 06:07:49 PM PDT 24
Peak memory 199608 kb
Host smart-673a3492-fb81-4763-a2e4-64b79f044af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450973652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3450973652
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.651018598
Short name T14
Test name
Test status
Simulation time 533307897 ps
CPU time 1.62 seconds
Started Jul 26 06:05:24 PM PDT 24
Finished Jul 26 06:05:26 PM PDT 24
Peak memory 199644 kb
Host smart-05979ea7-45ce-4815-a298-015be0deecd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651018598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.651018598
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.572662491
Short name T197
Test name
Test status
Simulation time 50106037915 ps
CPU time 666.88 seconds
Started Jul 26 06:05:27 PM PDT 24
Finished Jul 26 06:16:34 PM PDT 24
Peak memory 199700 kb
Host smart-4e68c320-2b89-4e8d-bd67-e9348a9e0248
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572662491 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.572662491
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1768997912
Short name T2
Test name
Test status
Simulation time 1014746267 ps
CPU time 47.06 seconds
Started Jul 26 06:05:26 PM PDT 24
Finished Jul 26 06:06:14 PM PDT 24
Peak memory 199648 kb
Host smart-d6b6e8ae-5ea0-4064-bda0-c258fd211872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768997912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1768997912
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1428832455
Short name T367
Test name
Test status
Simulation time 14022168 ps
CPU time 0.58 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:02:45 PM PDT 24
Peak memory 195632 kb
Host smart-67b7f33b-fc32-4a9f-a9ce-a3a5d57b479d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428832455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1428832455
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3835764483
Short name T245
Test name
Test status
Simulation time 2006077522 ps
CPU time 33.16 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:03:04 PM PDT 24
Peak memory 199652 kb
Host smart-f9f87e37-0316-4a75-948a-6218f0881b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835764483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3835764483
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1697671722
Short name T11
Test name
Test status
Simulation time 2265044766 ps
CPU time 37.66 seconds
Started Jul 26 06:02:34 PM PDT 24
Finished Jul 26 06:03:12 PM PDT 24
Peak memory 199728 kb
Host smart-06485521-9847-42eb-8a8b-db0d82a05ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697671722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1697671722
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1403516868
Short name T127
Test name
Test status
Simulation time 19851469406 ps
CPU time 1068.81 seconds
Started Jul 26 06:02:31 PM PDT 24
Finished Jul 26 06:20:20 PM PDT 24
Peak memory 746544 kb
Host smart-cc189f6a-bd3a-4275-8a70-2fdbc3755646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403516868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1403516868
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1034025730
Short name T344
Test name
Test status
Simulation time 22721573040 ps
CPU time 198.79 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:05:51 PM PDT 24
Peak memory 199760 kb
Host smart-14f25cb6-fe50-413e-8a0d-b0d3bf8a20f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034025730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1034025730
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2370210597
Short name T275
Test name
Test status
Simulation time 15760720926 ps
CPU time 134.85 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:04:47 PM PDT 24
Peak memory 199700 kb
Host smart-658a1140-87e7-4fad-a575-ccd6547e5d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370210597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2370210597
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4169066195
Short name T37
Test name
Test status
Simulation time 131255670 ps
CPU time 0.8 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:02:45 PM PDT 24
Peak memory 218336 kb
Host smart-1cab3d22-7d90-4005-b614-560d340fe5c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169066195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4169066195
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.293397751
Short name T287
Test name
Test status
Simulation time 347384974 ps
CPU time 7.43 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:02:39 PM PDT 24
Peak memory 199652 kb
Host smart-0713914e-cb52-4f4d-9695-3bc35bdb974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293397751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.293397751
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2908278551
Short name T265
Test name
Test status
Simulation time 55803617 ps
CPU time 2.01 seconds
Started Jul 26 06:02:47 PM PDT 24
Finished Jul 26 06:02:49 PM PDT 24
Peak memory 199660 kb
Host smart-f355bab7-8654-4f57-84f5-d3f24787b240
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908278551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2908278551
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.645882246
Short name T16
Test name
Test status
Simulation time 171269363615 ps
CPU time 807.84 seconds
Started Jul 26 06:02:41 PM PDT 24
Finished Jul 26 06:16:09 PM PDT 24
Peak memory 446692 kb
Host smart-a2e76716-96e8-49d1-a3ef-c621bf80c634
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645882246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.645882246
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1504196790
Short name T382
Test name
Test status
Simulation time 8783626800 ps
CPU time 50.15 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:03:35 PM PDT 24
Peak memory 199644 kb
Host smart-2dd10485-27c4-41ba-a44b-b9d8829a124b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1504196790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1504196790
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.4170127791
Short name T233
Test name
Test status
Simulation time 50587319336 ps
CPU time 100.82 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:04:23 PM PDT 24
Peak memory 199716 kb
Host smart-0bf8a2ab-054c-45c5-8c8d-2b57314cbe63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4170127791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.4170127791
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.434840250
Short name T329
Test name
Test status
Simulation time 16155618804 ps
CPU time 80.97 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:04:03 PM PDT 24
Peak memory 199800 kb
Host smart-0a83a910-c671-44f9-b484-e0890167f282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=434840250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.434840250
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2112641717
Short name T314
Test name
Test status
Simulation time 138284746808 ps
CPU time 622.48 seconds
Started Jul 26 06:02:34 PM PDT 24
Finished Jul 26 06:12:56 PM PDT 24
Peak memory 199764 kb
Host smart-2536f87d-069b-4440-ae44-f706614c077e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2112641717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2112641717
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1524843848
Short name T353
Test name
Test status
Simulation time 303584977358 ps
CPU time 2581.75 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:45:46 PM PDT 24
Peak memory 215252 kb
Host smart-7e6e05a3-29c7-46f2-86c9-4b34726975b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1524843848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1524843848
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1643211193
Short name T211
Test name
Test status
Simulation time 40035370514 ps
CPU time 2116.39 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:37:58 PM PDT 24
Peak memory 215368 kb
Host smart-fca635da-c715-474c-acd8-d0ecd46120a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1643211193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1643211193
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1953938595
Short name T445
Test name
Test status
Simulation time 943232750 ps
CPU time 49.64 seconds
Started Jul 26 06:02:32 PM PDT 24
Finished Jul 26 06:03:21 PM PDT 24
Peak memory 199712 kb
Host smart-645b5371-5270-4aee-b4a8-45f148aa14e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953938595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1953938595
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4290118798
Short name T201
Test name
Test status
Simulation time 13191527 ps
CPU time 0.57 seconds
Started Jul 26 06:05:39 PM PDT 24
Finished Jul 26 06:05:40 PM PDT 24
Peak memory 194592 kb
Host smart-4cd00d9f-8246-4ebc-97c3-319a784e65e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290118798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4290118798
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2656053530
Short name T412
Test name
Test status
Simulation time 1791268526 ps
CPU time 53.27 seconds
Started Jul 26 06:05:25 PM PDT 24
Finished Jul 26 06:06:18 PM PDT 24
Peak memory 199636 kb
Host smart-1190b452-aca4-44dc-99de-13cd1692acf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656053530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2656053530
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1961234806
Short name T133
Test name
Test status
Simulation time 1473521549 ps
CPU time 27.55 seconds
Started Jul 26 06:05:30 PM PDT 24
Finished Jul 26 06:05:57 PM PDT 24
Peak memory 199656 kb
Host smart-f86253e4-f891-4569-925c-a17eb6a44e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961234806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1961234806
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3002401716
Short name T316
Test name
Test status
Simulation time 12164203442 ps
CPU time 1045.63 seconds
Started Jul 26 06:05:28 PM PDT 24
Finished Jul 26 06:22:54 PM PDT 24
Peak memory 737160 kb
Host smart-2caea6af-9b14-4335-8c0a-ea40c54dbeca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002401716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3002401716
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.466507482
Short name T345
Test name
Test status
Simulation time 19666615 ps
CPU time 1.11 seconds
Started Jul 26 06:05:27 PM PDT 24
Finished Jul 26 06:05:28 PM PDT 24
Peak memory 199612 kb
Host smart-730eb275-5ab2-4eb3-998b-e5558a2df23a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466507482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.466507482
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3866378485
Short name T373
Test name
Test status
Simulation time 605901062 ps
CPU time 8.91 seconds
Started Jul 26 06:05:28 PM PDT 24
Finished Jul 26 06:05:37 PM PDT 24
Peak memory 199656 kb
Host smart-dbe1bd37-dc92-4e25-a292-d8eaa02bc440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866378485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3866378485
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.4148384752
Short name T325
Test name
Test status
Simulation time 604114715 ps
CPU time 12.64 seconds
Started Jul 26 06:05:27 PM PDT 24
Finished Jul 26 06:05:40 PM PDT 24
Peak memory 199652 kb
Host smart-25ae7581-da24-4927-984d-447f4db22483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148384752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.4148384752
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1588215443
Short name T241
Test name
Test status
Simulation time 253657434536 ps
CPU time 1705.91 seconds
Started Jul 26 06:05:46 PM PDT 24
Finished Jul 26 06:34:12 PM PDT 24
Peak memory 724772 kb
Host smart-37271048-acf9-49e4-99a4-e2ba8e84e9d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588215443 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1588215443
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1865736682
Short name T343
Test name
Test status
Simulation time 1071732919 ps
CPU time 14.14 seconds
Started Jul 26 06:05:40 PM PDT 24
Finished Jul 26 06:05:54 PM PDT 24
Peak memory 199648 kb
Host smart-23fb85f1-dc8e-40a5-8481-4c0c9f42fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865736682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1865736682
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3626390700
Short name T428
Test name
Test status
Simulation time 56904547 ps
CPU time 0.57 seconds
Started Jul 26 06:05:42 PM PDT 24
Finished Jul 26 06:05:43 PM PDT 24
Peak memory 196380 kb
Host smart-cb77a201-9fcb-47ac-9ad6-c3f9f1003da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626390700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3626390700
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1471472402
Short name T25
Test name
Test status
Simulation time 7447233739 ps
CPU time 102.34 seconds
Started Jul 26 06:05:43 PM PDT 24
Finished Jul 26 06:07:25 PM PDT 24
Peak memory 216084 kb
Host smart-20f4090f-6769-44e2-9fdd-298f3ccfe79d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1471472402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1471472402
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4148548836
Short name T199
Test name
Test status
Simulation time 2227512049 ps
CPU time 25.54 seconds
Started Jul 26 06:05:40 PM PDT 24
Finished Jul 26 06:06:06 PM PDT 24
Peak memory 199776 kb
Host smart-6f595fb7-f729-4467-ba80-29da71fba6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148548836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4148548836
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2753377394
Short name T250
Test name
Test status
Simulation time 14918541660 ps
CPU time 313.02 seconds
Started Jul 26 06:05:40 PM PDT 24
Finished Jul 26 06:10:54 PM PDT 24
Peak memory 642204 kb
Host smart-b47cf458-f450-467f-98bb-c06d91930869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753377394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2753377394
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.269041832
Short name T137
Test name
Test status
Simulation time 4645572862 ps
CPU time 60.57 seconds
Started Jul 26 06:05:39 PM PDT 24
Finished Jul 26 06:06:40 PM PDT 24
Peak memory 199740 kb
Host smart-36863fea-7ace-4ea1-96b4-78f8917e5241
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269041832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.269041832
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2813504147
Short name T117
Test name
Test status
Simulation time 5457836808 ps
CPU time 84.16 seconds
Started Jul 26 06:05:39 PM PDT 24
Finished Jul 26 06:07:03 PM PDT 24
Peak memory 199692 kb
Host smart-45792b74-19cc-4fb3-ba6f-bfffe4fa650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813504147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2813504147
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3005025570
Short name T189
Test name
Test status
Simulation time 1650158337 ps
CPU time 6.99 seconds
Started Jul 26 06:05:42 PM PDT 24
Finished Jul 26 06:05:49 PM PDT 24
Peak memory 199672 kb
Host smart-0deb8a14-7bdd-4a23-a6cf-94efe6f7c19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005025570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3005025570
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1652416819
Short name T469
Test name
Test status
Simulation time 127921216370 ps
CPU time 1546.77 seconds
Started Jul 26 06:05:44 PM PDT 24
Finished Jul 26 06:31:31 PM PDT 24
Peak memory 736648 kb
Host smart-ab7ffcfe-17e6-405b-a1bb-4cb21153ae7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652416819 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1652416819
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.712324738
Short name T352
Test name
Test status
Simulation time 15610911299 ps
CPU time 110.17 seconds
Started Jul 26 06:05:39 PM PDT 24
Finished Jul 26 06:07:29 PM PDT 24
Peak memory 199688 kb
Host smart-e5821d92-24fa-4dce-957a-0776a8fe7aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712324738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.712324738
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4097869676
Short name T425
Test name
Test status
Simulation time 31066898 ps
CPU time 0.54 seconds
Started Jul 26 06:05:43 PM PDT 24
Finished Jul 26 06:05:44 PM PDT 24
Peak memory 194576 kb
Host smart-a056fe9d-4f85-41c3-b6cd-d2a035d8f764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097869676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4097869676
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3163408424
Short name T193
Test name
Test status
Simulation time 708805917 ps
CPU time 39.51 seconds
Started Jul 26 06:05:39 PM PDT 24
Finished Jul 26 06:06:19 PM PDT 24
Peak memory 199640 kb
Host smart-4a844f70-8b15-4627-b71b-acc93731b4e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163408424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3163408424
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.4143470387
Short name T280
Test name
Test status
Simulation time 857529352 ps
CPU time 38.21 seconds
Started Jul 26 06:05:43 PM PDT 24
Finished Jul 26 06:06:22 PM PDT 24
Peak memory 199656 kb
Host smart-00fc742b-70e9-47dd-aa2b-5958ecf13447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143470387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.4143470387
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1214791892
Short name T526
Test name
Test status
Simulation time 3366633298 ps
CPU time 564.24 seconds
Started Jul 26 06:05:40 PM PDT 24
Finished Jul 26 06:15:04 PM PDT 24
Peak memory 468096 kb
Host smart-c0b05adb-ec30-4781-aff0-ac0dafc91397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214791892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1214791892
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3209102708
Short name T44
Test name
Test status
Simulation time 2738776841 ps
CPU time 25.32 seconds
Started Jul 26 06:05:40 PM PDT 24
Finished Jul 26 06:06:05 PM PDT 24
Peak memory 199548 kb
Host smart-e9ad4a5c-19d8-47e9-b6e9-74885b4ee419
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209102708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3209102708
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2610684292
Short name T454
Test name
Test status
Simulation time 63814936604 ps
CPU time 55.19 seconds
Started Jul 26 06:05:43 PM PDT 24
Finished Jul 26 06:06:39 PM PDT 24
Peak memory 199748 kb
Host smart-d0fb5bdb-4ac0-4639-9f03-b897657ede38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610684292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2610684292
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3181800612
Short name T105
Test name
Test status
Simulation time 383686232 ps
CPU time 8.9 seconds
Started Jul 26 06:05:43 PM PDT 24
Finished Jul 26 06:05:52 PM PDT 24
Peak memory 199652 kb
Host smart-e927e519-23c9-4f90-87d2-1fd4ac4bf06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181800612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3181800612
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.4250622804
Short name T475
Test name
Test status
Simulation time 63370447180 ps
CPU time 1167.92 seconds
Started Jul 26 06:05:39 PM PDT 24
Finished Jul 26 06:25:07 PM PDT 24
Peak memory 674168 kb
Host smart-5d293c76-e412-4498-8d3f-7c0a16df1716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250622804 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.4250622804
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.972602244
Short name T279
Test name
Test status
Simulation time 2932282907 ps
CPU time 69.15 seconds
Started Jul 26 06:05:39 PM PDT 24
Finished Jul 26 06:06:48 PM PDT 24
Peak memory 199724 kb
Host smart-d7ac56e0-7284-4120-bdfa-302f3207c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972602244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.972602244
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.682797464
Short name T169
Test name
Test status
Simulation time 56934201 ps
CPU time 0.6 seconds
Started Jul 26 06:05:57 PM PDT 24
Finished Jul 26 06:05:57 PM PDT 24
Peak memory 195676 kb
Host smart-45da8586-0947-49bb-b59f-893b689e97a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682797464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.682797464
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1771592427
Short name T258
Test name
Test status
Simulation time 6019668548 ps
CPU time 98.16 seconds
Started Jul 26 06:06:00 PM PDT 24
Finished Jul 26 06:07:38 PM PDT 24
Peak memory 216096 kb
Host smart-98732398-d73a-4a3b-8068-7e6c90e2964b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771592427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1771592427
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.37413802
Short name T179
Test name
Test status
Simulation time 15722426942 ps
CPU time 49.28 seconds
Started Jul 26 06:05:56 PM PDT 24
Finished Jul 26 06:06:46 PM PDT 24
Peak memory 199584 kb
Host smart-b8c3bed2-8e91-405b-a282-8915cd50f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37413802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.37413802
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.711483883
Short name T348
Test name
Test status
Simulation time 4016375699 ps
CPU time 757.08 seconds
Started Jul 26 06:05:57 PM PDT 24
Finished Jul 26 06:18:34 PM PDT 24
Peak memory 692548 kb
Host smart-a70a91b9-094b-45fd-98c6-2e355f0eb40d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711483883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.711483883
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1780189604
Short name T288
Test name
Test status
Simulation time 6677949540 ps
CPU time 41.13 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:06:39 PM PDT 24
Peak memory 199604 kb
Host smart-8720f392-beb1-4848-8548-998f16471011
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780189604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1780189604
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1485433868
Short name T256
Test name
Test status
Simulation time 40648541037 ps
CPU time 86.8 seconds
Started Jul 26 06:05:40 PM PDT 24
Finished Jul 26 06:07:07 PM PDT 24
Peak memory 199708 kb
Host smart-7b0a7407-3f13-4dff-ae07-dfae55a1d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485433868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1485433868
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.672656616
Short name T238
Test name
Test status
Simulation time 104618437 ps
CPU time 1.43 seconds
Started Jul 26 06:05:48 PM PDT 24
Finished Jul 26 06:05:49 PM PDT 24
Peak memory 199612 kb
Host smart-f2c4fc8f-7bfe-4118-8f8c-e0ea7d215c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672656616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.672656616
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1618407315
Short name T394
Test name
Test status
Simulation time 81837037006 ps
CPU time 2099.99 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:40:59 PM PDT 24
Peak memory 728980 kb
Host smart-27978861-a630-49cc-8240-4036d76bbd65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618407315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1618407315
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1389009279
Short name T364
Test name
Test status
Simulation time 21667649569 ps
CPU time 144.08 seconds
Started Jul 26 06:05:59 PM PDT 24
Finished Jul 26 06:08:23 PM PDT 24
Peak memory 199684 kb
Host smart-5c2e9c19-7602-4eb3-b274-434fac63ae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389009279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1389009279
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3922412815
Short name T384
Test name
Test status
Simulation time 52648891 ps
CPU time 0.61 seconds
Started Jul 26 06:05:59 PM PDT 24
Finished Jul 26 06:06:00 PM PDT 24
Peak memory 195644 kb
Host smart-a6fd090b-e296-434c-856f-99eb03182a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922412815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3922412815
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3082082147
Short name T20
Test name
Test status
Simulation time 1905923230 ps
CPU time 56.86 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:06:55 PM PDT 24
Peak memory 199676 kb
Host smart-f1dc9aad-189b-4557-b29e-a1fb7766eddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082082147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3082082147
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.464153008
Short name T257
Test name
Test status
Simulation time 1116795050 ps
CPU time 15.76 seconds
Started Jul 26 06:05:56 PM PDT 24
Finished Jul 26 06:06:11 PM PDT 24
Peak memory 199648 kb
Host smart-e6c135b9-197f-40fb-b3ef-c7301f872f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464153008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.464153008
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.75289284
Short name T466
Test name
Test status
Simulation time 32768660948 ps
CPU time 1157.76 seconds
Started Jul 26 06:05:56 PM PDT 24
Finished Jul 26 06:25:14 PM PDT 24
Peak memory 754796 kb
Host smart-f9278622-6533-4e83-ab32-4d22ce764a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75289284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.75289284
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.4221442643
Short name T293
Test name
Test status
Simulation time 13227415098 ps
CPU time 97.56 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:07:36 PM PDT 24
Peak memory 199712 kb
Host smart-ffc38297-3adb-4a30-aa3d-9223937e667a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221442643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.4221442643
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.405666169
Short name T230
Test name
Test status
Simulation time 2542557829 ps
CPU time 32.41 seconds
Started Jul 26 06:06:01 PM PDT 24
Finished Jul 26 06:06:33 PM PDT 24
Peak memory 199732 kb
Host smart-4bf1e5ae-5dc0-470f-858e-8464fd6e11f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405666169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.405666169
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3706752520
Short name T508
Test name
Test status
Simulation time 439389012 ps
CPU time 6.27 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:06:04 PM PDT 24
Peak memory 199616 kb
Host smart-69fc3bfc-7a95-4250-bcef-dd47779469f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706752520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3706752520
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.274232909
Short name T497
Test name
Test status
Simulation time 96626595577 ps
CPU time 3076.47 seconds
Started Jul 26 06:05:56 PM PDT 24
Finished Jul 26 06:57:13 PM PDT 24
Peak memory 772072 kb
Host smart-16355399-565b-4ee5-bbd4-aa037ac57333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274232909 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.274232909
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3135621357
Short name T240
Test name
Test status
Simulation time 577169735 ps
CPU time 13.62 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:06:12 PM PDT 24
Peak memory 199688 kb
Host smart-b1094075-b4da-4dad-b242-e4688b93f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135621357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3135621357
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.4095591159
Short name T32
Test name
Test status
Simulation time 12430935 ps
CPU time 0.59 seconds
Started Jul 26 06:06:11 PM PDT 24
Finished Jul 26 06:06:12 PM PDT 24
Peak memory 195284 kb
Host smart-2e293aec-94ee-4cdc-837d-80def9650c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095591159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4095591159
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3867731275
Short name T506
Test name
Test status
Simulation time 9246614023 ps
CPU time 44.56 seconds
Started Jul 26 06:06:00 PM PDT 24
Finished Jul 26 06:06:44 PM PDT 24
Peak memory 199828 kb
Host smart-3174dbc0-94b5-429f-abfc-20707923dcda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867731275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3867731275
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3971184289
Short name T307
Test name
Test status
Simulation time 2174743870 ps
CPU time 40.25 seconds
Started Jul 26 06:05:55 PM PDT 24
Finished Jul 26 06:06:35 PM PDT 24
Peak memory 199724 kb
Host smart-5b3c512a-a273-477e-8912-9d6a853abd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971184289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3971184289
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2108560535
Short name T426
Test name
Test status
Simulation time 15393727871 ps
CPU time 783.95 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:19:03 PM PDT 24
Peak memory 685404 kb
Host smart-0af9d83e-c609-4bae-81bb-91c08fb7cf3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108560535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2108560535
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2893908892
Short name T205
Test name
Test status
Simulation time 16841310453 ps
CPU time 209.57 seconds
Started Jul 26 06:05:59 PM PDT 24
Finished Jul 26 06:09:28 PM PDT 24
Peak memory 199764 kb
Host smart-40b3f6c9-b7ce-4141-9532-2f88dd27034a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893908892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2893908892
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2092136143
Short name T148
Test name
Test status
Simulation time 13871024027 ps
CPU time 72.72 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:07:11 PM PDT 24
Peak memory 199600 kb
Host smart-d4008774-ff7c-4b69-80d4-93b53b610514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092136143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2092136143
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1714775943
Short name T378
Test name
Test status
Simulation time 1836794147 ps
CPU time 12.87 seconds
Started Jul 26 06:05:58 PM PDT 24
Finished Jul 26 06:06:10 PM PDT 24
Peak memory 199652 kb
Host smart-b0428c7f-0fab-4fcc-bcb0-bf89937c7e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714775943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1714775943
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1336570013
Short name T57
Test name
Test status
Simulation time 91713776214 ps
CPU time 873.81 seconds
Started Jul 26 06:06:11 PM PDT 24
Finished Jul 26 06:20:45 PM PDT 24
Peak memory 653984 kb
Host smart-fe142e07-9a2e-44b9-85fe-0125cb4a41f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336570013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1336570013
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.311498427
Short name T119
Test name
Test status
Simulation time 284293695 ps
CPU time 11.28 seconds
Started Jul 26 06:05:57 PM PDT 24
Finished Jul 26 06:06:09 PM PDT 24
Peak memory 199628 kb
Host smart-d12d036d-41dd-4872-ad77-04f93478689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311498427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.311498427
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3346518141
Short name T359
Test name
Test status
Simulation time 79919936 ps
CPU time 0.58 seconds
Started Jul 26 06:06:12 PM PDT 24
Finished Jul 26 06:06:13 PM PDT 24
Peak memory 195536 kb
Host smart-7af7cd0e-2820-4efe-8f18-c0003695d72d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346518141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3346518141
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.228368984
Short name T21
Test name
Test status
Simulation time 1078268596 ps
CPU time 58.87 seconds
Started Jul 26 06:06:12 PM PDT 24
Finished Jul 26 06:07:11 PM PDT 24
Peak memory 199656 kb
Host smart-bc9e68a9-107f-41ee-93c9-cce9c862e3ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228368984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.228368984
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.648809527
Short name T202
Test name
Test status
Simulation time 4454806269 ps
CPU time 43.07 seconds
Started Jul 26 06:06:12 PM PDT 24
Finished Jul 26 06:06:56 PM PDT 24
Peak memory 199676 kb
Host smart-c8c08ba2-e636-4881-8f89-f960ee1e67f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648809527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.648809527
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.258319391
Short name T490
Test name
Test status
Simulation time 14243611556 ps
CPU time 1110.85 seconds
Started Jul 26 06:06:12 PM PDT 24
Finished Jul 26 06:24:43 PM PDT 24
Peak memory 740084 kb
Host smart-7552b20d-036a-4729-b17b-e5e7581b4771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258319391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.258319391
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2144828565
Short name T198
Test name
Test status
Simulation time 7560082393 ps
CPU time 31.64 seconds
Started Jul 26 06:06:10 PM PDT 24
Finished Jul 26 06:06:42 PM PDT 24
Peak memory 199992 kb
Host smart-51670478-1dbc-4732-842a-a2841d8f060b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144828565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2144828565
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.966987760
Short name T417
Test name
Test status
Simulation time 9985374682 ps
CPU time 62 seconds
Started Jul 26 06:06:11 PM PDT 24
Finished Jul 26 06:07:13 PM PDT 24
Peak memory 199696 kb
Host smart-dc7c0843-4cbe-434a-afea-6feec6d480e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966987760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.966987760
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2327881666
Short name T269
Test name
Test status
Simulation time 189211014 ps
CPU time 0.94 seconds
Started Jul 26 06:06:10 PM PDT 24
Finished Jul 26 06:06:11 PM PDT 24
Peak memory 199476 kb
Host smart-6fb921cf-ccb8-43ed-852c-132703696b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327881666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2327881666
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2973678535
Short name T514
Test name
Test status
Simulation time 12899492751 ps
CPU time 1156.95 seconds
Started Jul 26 06:06:12 PM PDT 24
Finished Jul 26 06:25:30 PM PDT 24
Peak memory 717652 kb
Host smart-ab8a0d8f-3ba6-4c75-b67f-c4493d4e3e34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973678535 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2973678535
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4102870346
Short name T221
Test name
Test status
Simulation time 7273499315 ps
CPU time 18.57 seconds
Started Jul 26 06:06:09 PM PDT 24
Finished Jul 26 06:06:28 PM PDT 24
Peak memory 199780 kb
Host smart-10e7c69f-8469-4c3a-a2fc-69a1e336ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102870346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4102870346
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3939632950
Short name T33
Test name
Test status
Simulation time 40643025 ps
CPU time 0.58 seconds
Started Jul 26 06:06:10 PM PDT 24
Finished Jul 26 06:06:11 PM PDT 24
Peak memory 195632 kb
Host smart-75eac8b9-0ac9-4cf1-946d-8cea32edb165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939632950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3939632950
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3519334496
Short name T18
Test name
Test status
Simulation time 3241924440 ps
CPU time 73.31 seconds
Started Jul 26 06:06:11 PM PDT 24
Finished Jul 26 06:07:25 PM PDT 24
Peak memory 215176 kb
Host smart-3421f00f-a9ad-421a-84ba-854af23fb029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519334496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3519334496
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1852951176
Short name T411
Test name
Test status
Simulation time 4170930729 ps
CPU time 52.57 seconds
Started Jul 26 06:06:16 PM PDT 24
Finished Jul 26 06:07:09 PM PDT 24
Peak memory 199700 kb
Host smart-b1301fbc-a9d9-4204-9fcc-792bd4517ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852951176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1852951176
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.759410185
Short name T192
Test name
Test status
Simulation time 4800755115 ps
CPU time 203.15 seconds
Started Jul 26 06:06:13 PM PDT 24
Finished Jul 26 06:09:37 PM PDT 24
Peak memory 598892 kb
Host smart-c2c24301-8cd1-4e86-93f3-59aa49cad35c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759410185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.759410185
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3926776488
Short name T217
Test name
Test status
Simulation time 3577055224 ps
CPU time 102.42 seconds
Started Jul 26 06:06:12 PM PDT 24
Finished Jul 26 06:07:55 PM PDT 24
Peak memory 199736 kb
Host smart-faa395b9-3866-4038-90de-200b33534a7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926776488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3926776488
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.632186333
Short name T408
Test name
Test status
Simulation time 1445642485 ps
CPU time 85.58 seconds
Started Jul 26 06:06:11 PM PDT 24
Finished Jul 26 06:07:37 PM PDT 24
Peak memory 199616 kb
Host smart-4df68610-9286-44a5-be0f-5f1f10a9b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632186333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.632186333
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3014174753
Short name T108
Test name
Test status
Simulation time 218291361 ps
CPU time 9.83 seconds
Started Jul 26 06:06:16 PM PDT 24
Finished Jul 26 06:06:26 PM PDT 24
Peak memory 199652 kb
Host smart-c386a12f-4392-4ce4-97f3-5470d930960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014174753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3014174753
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3198847344
Short name T251
Test name
Test status
Simulation time 20650633287 ps
CPU time 27.95 seconds
Started Jul 26 06:06:14 PM PDT 24
Finished Jul 26 06:06:42 PM PDT 24
Peak memory 199740 kb
Host smart-b892af3f-5e56-4846-b560-8f456e71635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198847344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3198847344
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3254722215
Short name T273
Test name
Test status
Simulation time 35981823 ps
CPU time 0.55 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:06:16 PM PDT 24
Peak memory 196332 kb
Host smart-dd121f78-2c48-4b47-b3b0-9a8b952cca12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254722215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3254722215
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1314422107
Short name T143
Test name
Test status
Simulation time 2293358639 ps
CPU time 63.57 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:07:19 PM PDT 24
Peak memory 199744 kb
Host smart-0ca7a210-0210-4a0a-a96c-f4c35be07c2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314422107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1314422107
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2864604031
Short name T134
Test name
Test status
Simulation time 11772886 ps
CPU time 0.64 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:06:16 PM PDT 24
Peak memory 196152 kb
Host smart-e42bfa93-6df7-491d-95ca-5a5841757d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864604031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2864604031
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3401583234
Short name T315
Test name
Test status
Simulation time 791027871 ps
CPU time 17.07 seconds
Started Jul 26 06:06:14 PM PDT 24
Finished Jul 26 06:06:31 PM PDT 24
Peak memory 232348 kb
Host smart-c48148da-4c73-42eb-afeb-551dfd720ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401583234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3401583234
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3543462342
Short name T321
Test name
Test status
Simulation time 56493447932 ps
CPU time 175.11 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:09:10 PM PDT 24
Peak memory 199712 kb
Host smart-e20b5cc4-86e4-42fc-adad-f27d1a929ea9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543462342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3543462342
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3446061943
Short name T429
Test name
Test status
Simulation time 22255987626 ps
CPU time 135.31 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:08:31 PM PDT 24
Peak memory 199724 kb
Host smart-afc294b7-e396-4aac-b933-f9098fedf6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446061943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3446061943
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3035843471
Short name T347
Test name
Test status
Simulation time 214750143 ps
CPU time 3.14 seconds
Started Jul 26 06:06:14 PM PDT 24
Finished Jul 26 06:06:17 PM PDT 24
Peak memory 199644 kb
Host smart-979832a9-466a-453f-8096-2ea540533029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035843471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3035843471
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2432771205
Short name T63
Test name
Test status
Simulation time 13479864376 ps
CPU time 192.91 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:09:28 PM PDT 24
Peak memory 199716 kb
Host smart-181ad991-36c9-4c1a-8c6d-28015aaf8d9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432771205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2432771205
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3929869289
Short name T243
Test name
Test status
Simulation time 3344053835 ps
CPU time 56.55 seconds
Started Jul 26 06:06:14 PM PDT 24
Finished Jul 26 06:07:11 PM PDT 24
Peak memory 199716 kb
Host smart-95e02fce-1f82-4dc9-ae51-52bb890cda6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929869289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3929869289
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1926197023
Short name T320
Test name
Test status
Simulation time 64420666 ps
CPU time 0.59 seconds
Started Jul 26 06:06:27 PM PDT 24
Finished Jul 26 06:06:28 PM PDT 24
Peak memory 195624 kb
Host smart-dde1bea3-1d52-4a2f-bca9-8f92ea9060e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926197023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1926197023
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2250124481
Short name T341
Test name
Test status
Simulation time 898398472 ps
CPU time 54.37 seconds
Started Jul 26 06:06:16 PM PDT 24
Finished Jul 26 06:07:10 PM PDT 24
Peak memory 199628 kb
Host smart-9f78294b-5ee5-4d09-be49-d8bdd536dbf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250124481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2250124481
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.432399677
Short name T184
Test name
Test status
Simulation time 691815380 ps
CPU time 12.19 seconds
Started Jul 26 06:06:14 PM PDT 24
Finished Jul 26 06:06:26 PM PDT 24
Peak memory 199580 kb
Host smart-63b49a38-8b80-450d-8199-9c5704366b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432399677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.432399677
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3691111059
Short name T419
Test name
Test status
Simulation time 140409071 ps
CPU time 4.86 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:06:20 PM PDT 24
Peak memory 199652 kb
Host smart-9aa38cc1-ba0d-4077-9344-09624713da93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691111059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3691111059
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1218141724
Short name T271
Test name
Test status
Simulation time 1996603849 ps
CPU time 108.61 seconds
Started Jul 26 06:06:13 PM PDT 24
Finished Jul 26 06:08:02 PM PDT 24
Peak memory 199632 kb
Host smart-93fdbf90-25d1-46c2-865a-e0dea157ffe6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218141724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1218141724
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4250575741
Short name T446
Test name
Test status
Simulation time 7866685825 ps
CPU time 26.69 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:06:41 PM PDT 24
Peak memory 199696 kb
Host smart-341264c7-fe7b-49a4-b1b2-9c74a96859b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250575741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4250575741
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2215702971
Short name T222
Test name
Test status
Simulation time 3325860727 ps
CPU time 5.83 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:06:21 PM PDT 24
Peak memory 199716 kb
Host smart-fefed071-0f9e-4f01-af35-6b5d7453b0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215702971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2215702971
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4020769597
Short name T461
Test name
Test status
Simulation time 19511402787 ps
CPU time 2431.66 seconds
Started Jul 26 06:06:28 PM PDT 24
Finished Jul 26 06:47:00 PM PDT 24
Peak memory 768792 kb
Host smart-26dc7a29-9f0d-41a8-b544-e36b36ba3bf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020769597 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4020769597
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.635633441
Short name T266
Test name
Test status
Simulation time 13019500576 ps
CPU time 44.83 seconds
Started Jul 26 06:06:15 PM PDT 24
Finished Jul 26 06:07:00 PM PDT 24
Peak memory 199728 kb
Host smart-f5707ada-e5c5-4522-9308-8676ee05c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635633441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.635633441
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.857204520
Short name T377
Test name
Test status
Simulation time 12761282 ps
CPU time 0.6 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:02:43 PM PDT 24
Peak memory 195652 kb
Host smart-4f676314-2af1-46dd-abf0-4d03817745ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857204520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.857204520
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.436160279
Short name T31
Test name
Test status
Simulation time 1407369340 ps
CPU time 80.43 seconds
Started Jul 26 06:02:41 PM PDT 24
Finished Jul 26 06:04:02 PM PDT 24
Peak memory 199652 kb
Host smart-65df2772-8ff8-4ec7-9620-785d02af8a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436160279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.436160279
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3939739733
Short name T40
Test name
Test status
Simulation time 22683440049 ps
CPU time 29.81 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:03:12 PM PDT 24
Peak memory 199964 kb
Host smart-3566d68f-46c0-4e9f-83a6-84f6577de04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939739733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3939739733
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1986641208
Short name T398
Test name
Test status
Simulation time 5474232489 ps
CPU time 880.28 seconds
Started Jul 26 06:02:48 PM PDT 24
Finished Jul 26 06:17:29 PM PDT 24
Peak memory 712936 kb
Host smart-9c59b66d-c807-41c2-ae2e-014801348aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986641208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1986641208
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1303017984
Short name T144
Test name
Test status
Simulation time 837408910 ps
CPU time 10.62 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:02:55 PM PDT 24
Peak memory 199580 kb
Host smart-c03d38e6-f074-4ecf-b662-e33ee7d9b384
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303017984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1303017984
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.937930524
Short name T510
Test name
Test status
Simulation time 11124353853 ps
CPU time 150.31 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:05:15 PM PDT 24
Peak memory 207904 kb
Host smart-8850e3a1-2f81-414d-9317-d4d3aaa37b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937930524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.937930524
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1896037602
Short name T259
Test name
Test status
Simulation time 854174412 ps
CPU time 3.82 seconds
Started Jul 26 06:02:48 PM PDT 24
Finished Jul 26 06:02:52 PM PDT 24
Peak memory 199640 kb
Host smart-bf3dc762-f0bc-4b3c-af0a-4a21188dd607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896037602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1896037602
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.834649941
Short name T393
Test name
Test status
Simulation time 193895683771 ps
CPU time 1348.54 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:25:13 PM PDT 24
Peak memory 709072 kb
Host smart-4105a896-059a-454d-bc11-146faf1d0fd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834649941 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.834649941
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3125784654
Short name T70
Test name
Test status
Simulation time 8362834677 ps
CPU time 102.26 seconds
Started Jul 26 06:02:45 PM PDT 24
Finished Jul 26 06:04:27 PM PDT 24
Peak memory 199732 kb
Host smart-865a0a65-dcea-4489-9662-3eac312afe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125784654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3125784654
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2746922661
Short name T518
Test name
Test status
Simulation time 46226190 ps
CPU time 0.59 seconds
Started Jul 26 06:02:48 PM PDT 24
Finished Jul 26 06:02:49 PM PDT 24
Peak memory 195644 kb
Host smart-17a0319a-d450-4073-b64e-f65921939d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746922661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2746922661
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1347238839
Short name T22
Test name
Test status
Simulation time 6814632336 ps
CPU time 93.26 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:04:18 PM PDT 24
Peak memory 199768 kb
Host smart-6f71539a-00be-4e29-8b20-638ef42f2def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347238839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1347238839
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1705465363
Short name T187
Test name
Test status
Simulation time 3939753941 ps
CPU time 24.53 seconds
Started Jul 26 06:02:49 PM PDT 24
Finished Jul 26 06:03:14 PM PDT 24
Peak memory 199704 kb
Host smart-12d4d262-ea08-4378-8c04-681fb0f1fc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705465363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1705465363
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3028154494
Short name T126
Test name
Test status
Simulation time 97498490683 ps
CPU time 835.26 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:16:38 PM PDT 24
Peak memory 697440 kb
Host smart-c7a13309-8f31-47d2-ae28-ef04f7b03abe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028154494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3028154494
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2472352917
Short name T415
Test name
Test status
Simulation time 17852735960 ps
CPU time 218.95 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:06:23 PM PDT 24
Peak memory 199672 kb
Host smart-97b4b654-24da-4989-aa55-a4751358a5da
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472352917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2472352917
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1723544029
Short name T24
Test name
Test status
Simulation time 43481288301 ps
CPU time 192.41 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:05:56 PM PDT 24
Peak memory 200008 kb
Host smart-c73e57f5-48fc-4c7c-ab27-8db592b468e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723544029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1723544029
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3589068386
Short name T483
Test name
Test status
Simulation time 272376026 ps
CPU time 2.68 seconds
Started Jul 26 06:02:45 PM PDT 24
Finished Jul 26 06:02:48 PM PDT 24
Peak memory 199624 kb
Host smart-bb71af03-4f4c-4f89-8ba5-5abc44c1ff39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589068386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3589068386
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1349828901
Short name T181
Test name
Test status
Simulation time 49963632759 ps
CPU time 1139.82 seconds
Started Jul 26 06:02:43 PM PDT 24
Finished Jul 26 06:21:44 PM PDT 24
Peak memory 415000 kb
Host smart-234ada05-a192-4928-9cde-aea341aaa0a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349828901 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1349828901
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1325953065
Short name T17
Test name
Test status
Simulation time 50634654630 ps
CPU time 363.55 seconds
Started Jul 26 06:02:41 PM PDT 24
Finished Jul 26 06:08:45 PM PDT 24
Peak memory 211132 kb
Host smart-f52c3eb3-f456-4b9b-bb30-0f97fdb232ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325953065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1325953065
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.60243835
Short name T207
Test name
Test status
Simulation time 38818237445 ps
CPU time 82.45 seconds
Started Jul 26 06:02:45 PM PDT 24
Finished Jul 26 06:04:07 PM PDT 24
Peak memory 199716 kb
Host smart-7b539501-3af2-437d-81a5-b5ed29bf6d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60243835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.60243835
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.943002571
Short name T132
Test name
Test status
Simulation time 22486690 ps
CPU time 0.57 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:02:42 PM PDT 24
Peak memory 195660 kb
Host smart-3cc75751-0de8-4bf9-8da5-61af27d9256e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943002571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.943002571
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.128960915
Short name T191
Test name
Test status
Simulation time 47973835 ps
CPU time 2.69 seconds
Started Jul 26 06:02:43 PM PDT 24
Finished Jul 26 06:02:46 PM PDT 24
Peak memory 199580 kb
Host smart-f9d58058-d9cc-4af6-a568-5a01fdbef2cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128960915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.128960915
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3745891716
Short name T290
Test name
Test status
Simulation time 3102698343 ps
CPU time 40.71 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:03:23 PM PDT 24
Peak memory 199696 kb
Host smart-ad453b19-1ecf-432d-8961-aa30c6a1473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745891716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3745891716
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2662323284
Short name T521
Test name
Test status
Simulation time 1032509696 ps
CPU time 66.92 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:03:49 PM PDT 24
Peak memory 307176 kb
Host smart-528f2378-b1cf-43f3-a293-0007aacc26fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662323284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2662323284
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1780641490
Short name T409
Test name
Test status
Simulation time 206082205 ps
CPU time 2.75 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:02:45 PM PDT 24
Peak memory 199560 kb
Host smart-7e572802-1e8f-4fa3-bc60-e75482eb25e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780641490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1780641490
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3918983202
Short name T468
Test name
Test status
Simulation time 369130324 ps
CPU time 7.38 seconds
Started Jul 26 06:02:48 PM PDT 24
Finished Jul 26 06:02:55 PM PDT 24
Peak memory 199656 kb
Host smart-4fb551f1-8303-413b-a43e-344c86cdcae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918983202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3918983202
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1411481687
Short name T392
Test name
Test status
Simulation time 1933731447 ps
CPU time 12.32 seconds
Started Jul 26 06:02:43 PM PDT 24
Finished Jul 26 06:02:56 PM PDT 24
Peak memory 199672 kb
Host smart-d0e0eb86-d890-4cd0-8467-0a39e0ae4262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411481687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1411481687
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1215148545
Short name T61
Test name
Test status
Simulation time 83569015326 ps
CPU time 1027.92 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:19:52 PM PDT 24
Peak memory 708540 kb
Host smart-0c3e536a-3d6d-4279-be52-7dcc6993c6b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215148545 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1215148545
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.4090088636
Short name T53
Test name
Test status
Simulation time 96443643813 ps
CPU time 1487.96 seconds
Started Jul 26 06:02:41 PM PDT 24
Finished Jul 26 06:27:30 PM PDT 24
Peak memory 641988 kb
Host smart-f07e8df3-b645-43f4-9227-30f35950a8dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090088636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.4090088636
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3234085509
Short name T295
Test name
Test status
Simulation time 129231047 ps
CPU time 5.21 seconds
Started Jul 26 06:02:42 PM PDT 24
Finished Jul 26 06:02:48 PM PDT 24
Peak memory 199676 kb
Host smart-e360dd72-60e2-4da5-8a4b-149d9e768a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234085509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3234085509
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.430535935
Short name T522
Test name
Test status
Simulation time 37247371 ps
CPU time 0.58 seconds
Started Jul 26 06:02:55 PM PDT 24
Finished Jul 26 06:02:56 PM PDT 24
Peak memory 195304 kb
Host smart-24fb1b9f-e656-438a-8d25-07ac3f83409a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430535935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.430535935
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1684931448
Short name T484
Test name
Test status
Simulation time 134674831 ps
CPU time 7.54 seconds
Started Jul 26 06:02:41 PM PDT 24
Finished Jul 26 06:02:49 PM PDT 24
Peak memory 199648 kb
Host smart-4a8dd163-4c98-4cbc-820d-ef168e61c472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684931448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1684931448
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.752853811
Short name T451
Test name
Test status
Simulation time 446933077 ps
CPU time 24.19 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:03:28 PM PDT 24
Peak memory 199624 kb
Host smart-a10078ce-b005-4e22-8445-46b2d529946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752853811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.752853811
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.729491632
Short name T491
Test name
Test status
Simulation time 3249339739 ps
CPU time 78.29 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:04:03 PM PDT 24
Peak memory 321808 kb
Host smart-bf5a0096-1bcf-4676-8f2c-51c3474940d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729491632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.729491632
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1400419643
Short name T213
Test name
Test status
Simulation time 3905861781 ps
CPU time 75.23 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:04:09 PM PDT 24
Peak memory 199716 kb
Host smart-faf132b1-0155-4c36-bf5a-fe7310b387ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400419643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1400419643
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2466259471
Short name T354
Test name
Test status
Simulation time 16148616184 ps
CPU time 139.7 seconds
Started Jul 26 06:02:43 PM PDT 24
Finished Jul 26 06:05:03 PM PDT 24
Peak memory 199716 kb
Host smart-4bdb70c7-e7fc-4072-ba86-e96964919deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466259471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2466259471
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1188949187
Short name T372
Test name
Test status
Simulation time 15253596 ps
CPU time 0.65 seconds
Started Jul 26 06:02:44 PM PDT 24
Finished Jul 26 06:02:45 PM PDT 24
Peak memory 196124 kb
Host smart-95598f77-da00-4bc7-8be3-9c784af7f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188949187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1188949187
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2471177933
Short name T254
Test name
Test status
Simulation time 116837172 ps
CPU time 2.34 seconds
Started Jul 26 06:02:54 PM PDT 24
Finished Jul 26 06:02:56 PM PDT 24
Peak memory 199644 kb
Host smart-7670a8de-7680-44de-aa85-97bad0f017af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471177933 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2471177933
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1015157697
Short name T54
Test name
Test status
Simulation time 122029591547 ps
CPU time 2169.94 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:39:14 PM PDT 24
Peak memory 493176 kb
Host smart-3e5555be-cf55-4932-b60f-42c65523538b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015157697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1015157697
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4184427651
Short name T167
Test name
Test status
Simulation time 13978588756 ps
CPU time 76.06 seconds
Started Jul 26 06:02:56 PM PDT 24
Finished Jul 26 06:04:12 PM PDT 24
Peak memory 199736 kb
Host smart-3193b4b2-0af0-4a98-8e42-e1b5634b94e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184427651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4184427651
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1139580639
Short name T383
Test name
Test status
Simulation time 49399338 ps
CPU time 0.59 seconds
Started Jul 26 06:02:55 PM PDT 24
Finished Jul 26 06:02:55 PM PDT 24
Peak memory 195540 kb
Host smart-309068ca-a60c-4833-9412-d24a6f84bb68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139580639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1139580639
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1762703969
Short name T499
Test name
Test status
Simulation time 943211520 ps
CPU time 54.36 seconds
Started Jul 26 06:02:56 PM PDT 24
Finished Jul 26 06:03:50 PM PDT 24
Peak memory 199620 kb
Host smart-1f919419-276e-42cc-8bcc-d9382e074c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762703969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1762703969
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2086732533
Short name T513
Test name
Test status
Simulation time 41452119366 ps
CPU time 54.84 seconds
Started Jul 26 06:03:04 PM PDT 24
Finished Jul 26 06:03:59 PM PDT 24
Peak memory 207968 kb
Host smart-4c19db86-dcf4-4c37-a59f-32ddb0e1e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086732533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2086732533
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3359640942
Short name T374
Test name
Test status
Simulation time 36436204115 ps
CPU time 346.68 seconds
Started Jul 26 06:02:52 PM PDT 24
Finished Jul 26 06:08:39 PM PDT 24
Peak memory 681092 kb
Host smart-f9573714-7aae-4b95-b195-2435e43db64b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359640942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3359640942
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.4283178084
Short name T472
Test name
Test status
Simulation time 2486092737 ps
CPU time 35.25 seconds
Started Jul 26 06:02:56 PM PDT 24
Finished Jul 26 06:03:31 PM PDT 24
Peak memory 199692 kb
Host smart-87b8cd69-2de3-4a26-b270-5fc34d82667d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283178084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.4283178084
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1725786136
Short name T381
Test name
Test status
Simulation time 36042914106 ps
CPU time 115.05 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:04:48 PM PDT 24
Peak memory 199664 kb
Host smart-a6cfe942-332d-4dc8-8dd9-0da978f0ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725786136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1725786136
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.880865487
Short name T203
Test name
Test status
Simulation time 983007055 ps
CPU time 15.94 seconds
Started Jul 26 06:02:52 PM PDT 24
Finished Jul 26 06:03:08 PM PDT 24
Peak memory 199696 kb
Host smart-c3dfe335-91d4-4ef2-8c52-cca4ccb3166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880865487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.880865487
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1543909920
Short name T172
Test name
Test status
Simulation time 134207871356 ps
CPU time 3329.24 seconds
Started Jul 26 06:02:53 PM PDT 24
Finished Jul 26 06:58:23 PM PDT 24
Peak memory 764788 kb
Host smart-41341bfd-b693-4aad-ae71-e51b9afaab7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543909920 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1543909920
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.273830612
Short name T12
Test name
Test status
Simulation time 68463750835 ps
CPU time 2607.01 seconds
Started Jul 26 06:02:52 PM PDT 24
Finished Jul 26 06:46:19 PM PDT 24
Peak memory 745524 kb
Host smart-590a5ebc-ee00-4eb3-b7bf-65d90bec3d51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273830612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.273830612
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.76172584
Short name T3
Test name
Test status
Simulation time 50867076073 ps
CPU time 59.03 seconds
Started Jul 26 06:02:55 PM PDT 24
Finished Jul 26 06:03:54 PM PDT 24
Peak memory 199724 kb
Host smart-b3b27dcb-ce49-4adb-8fd0-fdfd1224f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76172584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.76172584
Directory /workspace/9.hmac_wipe_secret/latest
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