Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19354596	1			T1	456177		T2	8506		T3	1264
all_values[1]	19354596	1			T1	456177		T2	8506		T3	1264
all_values[2]	19354596	1			T1	456177		T2	8506		T3	1264

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255577

1

T5

128

T6

3

T4

2

auto[1]

57808211

1

T1

136853

T2

25518

T3

3792

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49371733

1

T1

120697

T2

23053

T3

3511

auto[1]

8692055

1

T1

161555

T2

2465

T3

281

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	69347	1			T5	62		T6	3		T4	2
all_values[0]	auto[0]	auto[1]	374	1			T5	2		T22	4		T11	5
all_values[0]	auto[1]	auto[0]	19263464	1			T1	455791		T2	8470		T3	1251
all_values[0]	auto[1]	auto[1]	21411	1			T1	386		T2	36		T3	13
all_values[1]	auto[0]	auto[0]	118480	1			T5	64		T22	6375		T11	2
all_values[1]	auto[0]	auto[1]	199	1			T22	2		T11	4		T43	3
all_values[1]	auto[1]	auto[0]	19235636	1			T1	456177		T2	8506		T3	1264
all_values[1]	auto[1]	auto[1]	281	1			T22	1		T11	6		T8	1
all_values[2]	auto[0]	auto[0]	32646	1			T23	189		T22	837		T11	11
all_values[2]	auto[0]	auto[1]	34531	1			T23	572		T22	4		T11	1876
all_values[2]	auto[1]	auto[0]	10652160	1			T1	295008		T2	6077		T3	996
all_values[2]	auto[1]	auto[1]	8635259	1			T1	161169		T2	2429		T3	268