Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132877

1

T1

400

T2

42

T3

132

auto[1]

136402

1

T2

14

T3

1044

T6

44

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	99346	1			T1	68		T2	24		T3	514
len_1026_2046	6814	1			T1	1		T3	31		T7	1
len_514_1022	3310	1			T1	71		T2	1		T3	16
len_2_510	4598	1			T1	54		T3	23		T7	56
len_2056	232	1			T22	5		T11	5		T43	1
len_2048	516	1			T3	1		T22	7		T11	17
len_2040	183	1			T22	7		T11	7		T65	2
len_1032	270	1			T22	9		T118	1		T11	6
len_1024	1876	1			T1	2		T2	2		T3	3
len_1016	319	1			T1	1		T7	2		T22	9
len_520	334	1			T7	1		T11	9		T68	1
len_512	360	1			T1	1		T2	1		T7	1
len_504	236	1			T1	1		T7	1		T22	3
len_8	1269	1			T1	1		T7	2		T6	12
len_0	14977	1			T5	2		T14	4		T4	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

137

1

T11

4

T10

2

T133

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	49587	1			T1	68		T2	20		T3	58
auto[0]	len_1026_2046	3869	1			T1	1		T3	4		T7	1
auto[0]	len_514_1022	1854	1			T1	71		T7	57		T4	1
auto[0]	len_2_510	2232	1			T1	54		T3	3		T7	56
auto[0]	len_2056	94	1			T22	3		T11	3		T43	1
auto[0]	len_2048	216	1			T22	4		T11	7		T65	1
auto[0]	len_2040	100	1			T22	5		T11	3		T43	1
auto[0]	len_1032	192	1			T22	4		T118	1		T11	5
auto[0]	len_1024	293	1			T1	2		T3	1		T7	1
auto[0]	len_1016	146	1			T1	1		T7	2		T22	6
auto[0]	len_520	236	1			T7	1		T11	5		T68	1
auto[0]	len_512	207	1			T1	1		T2	1		T7	1
auto[0]	len_504	141	1			T1	1		T7	1		T22	2
auto[0]	len_8	164	1			T1	1		T7	2		T134	1
auto[0]	len_0	7108	1			T5	2		T14	2		T23	7
auto[1]	len_2050_plus	49759	1			T2	4		T3	456		T6	10
auto[1]	len_1026_2046	2945	1			T3	27		T4	2		T21	3
auto[1]	len_514_1022	1456	1			T2	1		T3	16		T21	2
auto[1]	len_2_510	2366	1			T3	20		T14	1		T23	1
auto[1]	len_2056	138	1			T22	2		T11	2		T87	1
auto[1]	len_2048	300	1			T3	1		T22	3		T11	10
auto[1]	len_2040	83	1			T22	2		T11	4		T65	2
auto[1]	len_1032	78	1			T22	5		T11	1		T68	1
auto[1]	len_1024	1583	1			T2	2		T3	2		T4	1
auto[1]	len_1016	173	1			T22	3		T11	5		T43	2
auto[1]	len_520	98	1			T11	4		T43	2		T79	2
auto[1]	len_512	153	1			T22	2		T11	6		T9	1
auto[1]	len_504	95	1			T22	1		T11	7		T68	2
auto[1]	len_8	1105	1			T6	12		T22	37		T38	9
auto[1]	len_0	7869	1			T14	2		T4	2		T15	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

58

1

T11

2

T135

2

T136

1

auto[1]

len_upper

79

1

T11

2

T10

2

T133

1