Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4717709

1

T1

147555

T2

20

T3

1952

auto[1]

3131411

1

T2

15

T3

337

T5

1

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3084797

1

T2

15

T3

1059

T5

387

auto[1]

4764323

1

T1

147555

T2

20

T3

1230

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3378196

1

T1

147555

T2

21

T3

288

auto[1]

4470924

1

T2

14

T3

2001

T6

35923

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4700987

1

T1

147555

T2

12

T3

1746

auto[1]

3148133

1

T2

23

T3

543

T5

192

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7186287	1			T1	145892		T2	21		T3	2232
fifo_depth[1]	113324	1			T1	1363		T2	1		T3	15
fifo_depth[2]	82895	1			T1	270		T2	1		T3	18
fifo_depth[3]	63921	1			T1	28		T3	7		T7	4005
fifo_depth[4]	60229	1			T1	2		T3	9		T7	2780
fifo_depth[5]	47480	1			T2	1		T3	3		T7	2004
fifo_depth[6]	38595	1			T2	1		T3	5		T7	1412
fifo_depth[7]	25772	1			T2	2		T7	890		T5	7

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

662833

1

T1

1663

T2

14

T3

57

auto[1]

7186287

1

T1

145892

T2

21

T3

2232

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7839811

1

T1

147555

T2

35

T3

2289

auto[1]

9309

1

T22

87

T8

110

T10

344

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

34646

1

T3

19

T5

133

T23

57

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34099

1

T2

5

T4

1

T21

28

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

25457

1

T21

26

T23

16

T22

691

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31345

1

T4

27

T21

7

T23

34

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

93472

1

T1

1663

T7

21307

T14

25

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

24429

1

T2

1

T5

66

T14

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

36014

1

T2

2

T4

81

T15

42

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

32729

1

T3

8

T14

9

T4

54

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41790

1

T3

4

T15

9

T21

57

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

42840

1

T2

1

T4

13

T21

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38830

1

T6

676

T14

1

T15

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

41262

1

T2

1

T3

2

T6

268

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57659

1

T3

9

T21

3

T23

18

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

42523

1

T2

1

T6

795

T14

43

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47536

1

T2

2

T3

15

T4

56

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38202

1

T2

1

T6

1435

T21

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

202180

1

T2

1

T3

148

T5

254

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

194001

1

T2

2

T14

432

T4

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

193197

1

T2

1

T14

1

T15

497

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

203201

1

T2

1

T14

1

T4

496

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1662631

1

T1

145892

T2

3

T7

125981

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

190056

1

T2

3

T3

5

T5

125

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

206300

1

T2

1

T14

47

T4

1543

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

214439

1

T2

1

T3

108

T5

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

441171

1

T3

492

T6

1834

T14

324

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

555377

1

T2

1

T3

334

T6

2366

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

485476

1

T6

3468

T14

892

T4

1386

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

519925

1

T2

2

T3

60

T6

3005

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

604016

1

T3

941

T6

3411

T14

358

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

496819

1

T2

2

T6

11265

T14

753

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

530612

1

T2

2

T3

118

T6

693

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

486886

1

T2

1

T3

26

T6

6707

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

236013

1

T2

1

T3

167

T5

387

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

227346

1

T2

7

T14

432

T4

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

218333

1

T2

1

T14

1

T15

497

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

234096

1

T2

1

T14

1

T4

523

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1755760

1

T1

147555

T2

3

T7

147288

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

214043

1

T2

4

T3

5

T5

191

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

242067

1

T2

3

T14

47

T4

1624

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

246710

1

T2

1

T3

116

T5

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

482293

1

T3

496

T6

1834

T14

324

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

597569

1

T2

2

T3

334

T6

2366

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

523816

1

T6

4144

T14

893

T4

1386

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

560341

1

T2

3

T3

62

T6

3273

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

660685

1

T3

950

T6

3411

T14

358

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

538547

1

T2

3

T6

12060

T14

796

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

577313

1

T2

4

T3

133

T6

693

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

524879

1

T2

2

T3

26

T6

8142

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

813

1

T22

58

T10

2

T36

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

754

1

T8

33

T10

3

T13

149

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

321

1

T36

1

T12

73

T90

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

450

1

T22

9

T12

20

T90

24

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

343

1

T8

1

T10

79

T36

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

442

1

T10

15

T36

5

T13

29

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

247

1

T22

5

T10

4

T12

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

458

1

T8

73

T10

58

T36

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

668

1

T22

2

T10

28

T12

26

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

648

1

T22

12

T12

1

T13

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

490

1

T10

66

T36

24

T60

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

846

1

T12

374

T60

117

T24

45

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

990

1

T22

1

T12

34

T60

77

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

795

1

T10

45

T12

7

T90

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

835

1

T8

3

T10

44

T12

14

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

209

1

T13

92

T137

8

T138

31

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

202180

1

T2

1

T3

148

T5

254

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

194001

1

T2

2

T14

432

T4

12

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

193197

1

T2

1

T14

1

T15

497

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

203201

1

T2

1

T14

1

T4

496

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1662631

1

T1

145892

T2

3

T7

125981

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

190056

1

T2

3

T3

5

T5

125

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

206300

1

T2

1

T14

47

T4

1543

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

214439

1

T2

1

T3

108

T5

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

441171

1

T3

492

T6

1834

T14

324

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

555377

1

T2

1

T3

334

T6

2366

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

485476

1

T6

3468

T14

892

T4

1386

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

519925

1

T2

2

T3

60

T6

3005

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

604016

1

T3

941

T6

3411

T14

358

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

496819

1

T2

2

T6

11265

T14

753

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

530612

1

T2

2

T3

118

T6

693

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

486886

1

T2

1

T3

26

T6

6707

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

4555

1

T3

5

T5

32

T23

42

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3981

1

T4

1

T21

20

T22

97

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3912

1

T21

23

T23

8

T22

158

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3938

1

T4

21

T21

4

T23

20

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

29780

1

T1

1363

T7

4852

T14

14

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3900

1

T5

14

T14

4

T4

15

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4107

1

T4

63

T15

30

T23

4

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3933

1

T14

9

T4

27

T23

11

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5990

1

T15

3

T21

45

T22

371

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6690

1

T4

9

T21

1

T23

30

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6596

1

T6

91

T14

1

T15

2

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6596

1

T6

47

T14

22

T15

23

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9349

1

T3

8

T21

3

T23

7

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7170

1

T2

1

T6

150

T14

24

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6685

1

T3

2

T4

32

T21

51

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6142

1

T6

200

T21

10

T22

108

fifo_depth[2]

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1

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33

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1

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11

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17

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44

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86

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1

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162

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83

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142

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6

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15

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26

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T22

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T22

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289

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125

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51

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49

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1

T6

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102

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37

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4

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1

T22

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41

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51

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1

T22

172

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43

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2

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1

T22

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41

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39

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1

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40

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38

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1

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T22

63

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T22

182

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2

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12

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1

T6

45

T22

130

T38

80

fifo_depth[7]

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1

T2

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54

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23

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1

T6

120

T22

86

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4