Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19354596	1			T1	456177		T2	8506		T3	1264
all_pins[1]	19354596	1			T1	456177		T2	8506		T3	1264
all_pins[2]	19354596	1			T1	456177		T2	8506		T3	1264

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49405969	1			T1	120697		T2	23043		T3	3511
values[0x1]	8657819	1			T1	161555		T2	2475		T3	281
transitions[0x0=>0x1]	8657646	1			T1	161555		T2	2475		T3	281
transitions[0x1=>0x0]	8657651	1			T1	161555		T2	2475		T3	281

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19332344	1			T1	455791		T2	8460		T3	1251
all_pins[0]	values[0x1]	22252	1			T1	386		T2	46		T3	13
all_pins[0]	transitions[0x0=>0x1]	22166	1			T1	386		T2	46		T3	13
all_pins[0]	transitions[0x1=>0x0]	8635178	1			T1	161169		T2	2429		T3	268
all_pins[1]	values[0x0]	19354288	1			T1	456177		T2	8506		T3	1264
all_pins[1]	values[0x1]	308	1			T22	1		T11	6		T8	1
all_pins[1]	transitions[0x0=>0x1]	273	1			T22	1		T11	4		T8	1
all_pins[1]	transitions[0x1=>0x0]	22217	1			T1	386		T2	46		T3	13
all_pins[2]	values[0x0]	10719337	1			T1	295008		T2	6077		T3	996
all_pins[2]	values[0x1]	8635259	1			T1	161169		T2	2429		T3	268
all_pins[2]	transitions[0x0=>0x1]	8635207	1			T1	161169		T2	2429		T3	268
all_pins[2]	transitions[0x1=>0x0]	256	1			T22	1		T11	6		T8	1