Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 988 1 T22 10 T11 17 T43 14
all_values[1] 988 1 T22 10 T11 17 T43 14
all_values[2] 988 1 T22 10 T11 17 T43 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1502 1 T22 16 T11 25 T43 31
auto[1] 1462 1 T22 14 T11 26 T43 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1087 1 T22 12 T11 16 T43 15
auto[1] 1877 1 T22 18 T11 35 T43 27


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1706 1 T22 18 T11 25 T43 24
auto[1] 1258 1 T22 12 T11 26 T43 18


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 195 1 T22 2 T11 3 T43 3
all_values[0] auto[0] auto[0] auto[1] 90 1 T22 1 T43 2 T12 6
all_values[0] auto[0] auto[1] auto[0] 201 1 T22 2 T11 1 T12 33
all_values[0] auto[0] auto[1] auto[1] 86 1 T11 2 T43 1 T12 4
all_values[0] auto[1] auto[0] auto[1] 232 1 T22 3 T11 8 T43 5
all_values[0] auto[1] auto[1] auto[1] 184 1 T22 2 T11 3 T43 3
all_values[1] auto[0] auto[0] auto[0] 156 1 T22 1 T43 3 T12 14
all_values[1] auto[0] auto[0] auto[1] 135 1 T22 1 T11 2 T43 3
all_values[1] auto[0] auto[1] auto[0] 187 1 T22 4 T11 2 T43 2
all_values[1] auto[0] auto[1] auto[1] 112 1 T22 1 T11 3 T43 1
all_values[1] auto[1] auto[0] auto[1] 196 1 T22 2 T11 3 T43 4
all_values[1] auto[1] auto[1] auto[1] 202 1 T22 1 T11 7 T43 1
all_values[2] auto[0] auto[0] auto[0] 188 1 T22 2 T11 6 T43 7
all_values[2] auto[0] auto[0] auto[1] 83 1 T22 2 T11 1 T12 4
all_values[2] auto[0] auto[1] auto[0] 160 1 T22 1 T11 4 T12 14
all_values[2] auto[0] auto[1] auto[1] 113 1 T22 1 T11 1 T43 2
all_values[2] auto[1] auto[0] auto[1] 227 1 T22 2 T11 2 T43 4
all_values[2] auto[1] auto[1] auto[1] 217 1 T22 2 T11 3 T43 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%