Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4870	1			T2	4		T3	4		T6	5
sha2_none	4907	1			T2	4		T5	1		T6	12
sha2_512	7896	1			T1	386		T2	15		T3	3
sha2_384	8177	1			T2	10		T3	6		T5	1
sha2_256	7125	1			T2	7		T3	3		T5	3

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20276

1

T1

386

T2

23

T3

8

auto[1]

13142

1

T2

17

T3

8

T5

1

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12921

1

T2

19

T3

8

T5

2

auto[1]

20497

1

T1

386

T2

21

T3

8

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17383

1

T2

17

T3

8

T6

39

disabled

16035

1

T1

386

T2

23

T3

8

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5380	1			T2	1		T3	3		T5	1
key_none	7933	1			T1	386		T2	7		T3	1
key_1024	4768	1			T2	11		T3	2		T5	1
key_512	4307	1			T2	6		T3	4		T5	1
key_384	4011	1			T2	6		T3	1		T6	7
key_256	3457	1			T2	6		T3	4		T6	8
key_128	3468	1			T2	3		T3	1		T5	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20278

1

T1

386

T2

13

T3

7

auto[1]

13140

1

T2

27

T3

9

T5

2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

33201

1

T1

386

T2

40

T3

16

disabled

217

1

T14

3

T22

6

T11

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1725

1

T3

1

T6

2

T14

1

enabled

auto[0]

auto[0]

auto[1]

1849

1

T2

3

T3

1

T6

3

enabled

auto[0]

auto[1]

auto[0]

1757

1

T6

6

T14

4

T4

3

enabled

auto[0]

auto[1]

auto[1]

1810

1

T2

4

T3

2

T6

4

enabled

auto[1]

auto[0]

auto[0]

4575

1

T3

1

T6

1

T14

2

enabled

auto[1]

auto[0]

auto[1]

1846

1

T2

3

T6

11

T14

3

enabled

auto[1]

auto[1]

auto[0]

1998

1

T2

5

T3

2

T6

3

enabled

auto[1]

auto[1]

auto[1]

1823

1

T2

2

T3

1

T6

9

disabled

auto[0]

auto[0]

auto[0]

1456

1

T2

1

T3

3

T5

2

disabled

auto[0]

auto[0]

auto[1]

1481

1

T2

9

T3

1

T14

2

disabled

auto[0]

auto[1]

auto[0]

1409

1

T2

1

T15

1

T21

3

disabled

auto[0]

auto[1]

auto[1]

1434

1

T2

1

T14

1

T4

2

disabled

auto[1]

auto[0]

auto[0]

5901

1

T1

386

T2

3

T7

386

disabled

auto[1]

auto[0]

auto[1]

1443

1

T2

4

T3

1

T5

1

disabled

auto[1]

auto[1]

auto[0]

1457

1

T2

3

T14

3

T4

2

disabled

auto[1]

auto[1]

auto[1]

1454

1

T2

1

T3

3

T5

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17289

1

T2

17

T3

8

T6

39

enabled

disabled

94

1

T14

2

T22

4

T69

1

disabled

disabled

123

1

T14

1

T22

2

T11

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15912

1

T1

386

T2

23

T3

8

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1236	1			T2	1		T3	1		T14	5
key_invalid	sha2_none	1001	1			T6	1		T14	4		T4	1
key_invalid	sha2_512	1014	1			T3	1		T6	3		T14	2
key_invalid	sha2_384	999	1			T3	1		T6	1		T14	1
key_invalid	sha2_256	1007	1			T5	1		T6	3		T14	1
key_none	sha2_invalid	607	1			T2	1		T22	18		T88	3
key_none	sha2_none	674	1			T2	2		T6	1		T14	1
key_none	sha2_512	2244	1			T1	386		T2	1		T7	386
key_none	sha2_384	2677	1			T2	1		T3	1		T4	1
key_none	sha2_256	1688	1			T2	2		T14	1		T4	1
key_1024	sha2_invalid	587	1			T2	1		T3	2		T14	1
key_1024	sha2_none	653	1			T2	1		T6	3		T15	2
key_1024	sha2_512	1825	1			T2	3		T23	3		T22	10
key_1024	sha2_384	979	1			T2	1		T4	1		T15	1
key_512	sha2_invalid	613	1			T2	1		T6	2		T4	1
key_512	sha2_none	641	1			T5	1		T4	1		T22	16
key_512	sha2_512	699	1			T2	4		T3	1		T6	1
key_512	sha2_384	1352	1			T2	1		T6	1		T4	1
key_512	sha2_256	945	1			T3	3		T6	1		T14	1
key_384	sha2_invalid	645	1			T21	1		T23	3		T22	12
key_384	sha2_none	639	1			T2	1		T6	4		T15	1
key_384	sha2_512	728	1			T2	1		T6	2		T4	3
key_384	sha2_384	732	1			T2	4		T3	1		T14	2
key_384	sha2_256	1209	1			T6	1		T23	1		T22	14
key_256	sha2_invalid	581	1			T3	1		T6	3		T15	1
key_256	sha2_none	621	1			T6	2		T14	1		T23	1
key_256	sha2_512	669	1			T2	3		T3	1		T6	1
key_256	sha2_384	708	1			T2	3		T3	2		T6	1
key_256	sha2_256	829	1			T6	1		T14	1		T4	1
key_128	sha2_invalid	580	1			T21	1		T23	1		T22	8
key_128	sha2_none	657	1			T6	1		T14	1		T21	1
key_128	sha2_512	702	1			T2	3		T6	2		T14	1
key_128	sha2_384	717	1			T3	1		T5	1		T6	2
key_128	sha2_256	754	1			T5	1		T14	2		T21	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

672

1

T2

5

T5

1

T14

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1236	1			T2	1		T3	1		T14	5
key_invalid	sha2_none	1001	1			T6	1		T14	4		T4	1
key_invalid	sha2_512	1014	1			T3	1		T6	3		T14	2
key_invalid	sha2_384	999	1			T3	1		T6	1		T14	1
key_invalid	sha2_256	1007	1			T5	1		T6	3		T14	1
key_none	sha2_invalid	607	1			T2	1		T22	18		T88	3
key_none	sha2_none	674	1			T2	2		T6	1		T14	1
key_none	sha2_512	2244	1			T1	386		T2	1		T7	386
key_none	sha2_384	2677	1			T2	1		T3	1		T4	1
key_none	sha2_256	1688	1			T2	2		T14	1		T4	1
key_1024	sha2_invalid	587	1			T2	1		T3	2		T14	1
key_1024	sha2_none	653	1			T2	1		T6	3		T15	2
key_1024	sha2_512	1825	1			T2	3		T23	3		T22	10
key_1024	sha2_384	979	1			T2	1		T4	1		T15	1
key_1024	sha2_256	672	1			T2	5		T5	1		T14	2
key_512	sha2_invalid	613	1			T2	1		T6	2		T4	1
key_512	sha2_none	641	1			T5	1		T4	1		T22	16
key_512	sha2_512	699	1			T2	4		T3	1		T6	1
key_512	sha2_384	1352	1			T2	1		T6	1		T4	1
key_512	sha2_256	945	1			T3	3		T6	1		T14	1
key_384	sha2_invalid	645	1			T21	1		T23	3		T22	12
key_384	sha2_none	639	1			T2	1		T6	4		T15	1
key_384	sha2_512	728	1			T2	1		T6	2		T4	3
key_384	sha2_384	732	1			T2	4		T3	1		T14	2
key_384	sha2_256	1209	1			T6	1		T23	1		T22	14
key_256	sha2_invalid	581	1			T3	1		T6	3		T15	1
key_256	sha2_none	621	1			T6	2		T14	1		T23	1
key_256	sha2_512	669	1			T2	3		T3	1		T6	1
key_256	sha2_384	708	1			T2	3		T3	2		T6	1
key_256	sha2_256	829	1			T6	1		T14	1		T4	1
key_128	sha2_invalid	580	1			T21	1		T23	1		T22	8
key_128	sha2_none	657	1			T6	1		T14	1		T21	1
key_128	sha2_512	702	1			T2	3		T6	2		T14	1
key_128	sha2_384	717	1			T3	1		T5	1		T6	2
key_128	sha2_256	754	1			T5	1		T14	2		T21	2