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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.40 97.22 100.00 94.12 98.27 98.48 99.85


Total test records in report: 659
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T111 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2394418137 Jul 27 04:59:13 PM PDT 24 Jul 27 04:59:15 PM PDT 24 154797290 ps
T538 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2537872528 Jul 27 04:59:06 PM PDT 24 Jul 27 04:59:07 PM PDT 24 47032712 ps
T539 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1814531007 Jul 27 04:59:06 PM PDT 24 Jul 27 04:59:07 PM PDT 24 12493089 ps
T540 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3386823829 Jul 27 04:58:47 PM PDT 24 Jul 27 04:58:50 PM PDT 24 262025135 ps
T95 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2894494173 Jul 27 04:58:47 PM PDT 24 Jul 27 04:58:48 PM PDT 24 21646592 ps
T541 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2914733005 Jul 27 04:59:11 PM PDT 24 Jul 27 04:59:11 PM PDT 24 115582322 ps
T542 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3704478918 Jul 27 04:58:49 PM PDT 24 Jul 27 04:58:55 PM PDT 24 49272189 ps
T56 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2914222274 Jul 27 04:59:00 PM PDT 24 Jul 27 04:59:01 PM PDT 24 162694046 ps
T543 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3934470086 Jul 27 04:58:53 PM PDT 24 Jul 27 04:58:59 PM PDT 24 1357078829 ps
T57 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3588791418 Jul 27 04:59:14 PM PDT 24 Jul 27 04:59:16 PM PDT 24 112322419 ps
T544 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3774747827 Jul 27 04:59:12 PM PDT 24 Jul 27 04:59:12 PM PDT 24 35946969 ps
T545 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1244494117 Jul 27 04:59:04 PM PDT 24 Jul 27 04:59:04 PM PDT 24 18870920 ps
T546 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1775158463 Jul 27 04:58:42 PM PDT 24 Jul 27 04:58:45 PM PDT 24 72864485 ps
T112 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1935393035 Jul 27 04:59:05 PM PDT 24 Jul 27 04:59:08 PM PDT 24 315446464 ps
T58 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3764435311 Jul 27 04:59:11 PM PDT 24 Jul 27 04:59:13 PM PDT 24 49827052 ps
T122 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.762716481 Jul 27 04:58:54 PM PDT 24 Jul 27 04:58:55 PM PDT 24 160450962 ps
T547 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.861103164 Jul 27 04:58:44 PM PDT 24 Jul 27 04:58:45 PM PDT 24 157455524 ps
T548 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1652709217 Jul 27 04:59:06 PM PDT 24 Jul 27 04:59:08 PM PDT 24 133260264 ps
T123 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.992032014 Jul 27 04:59:29 PM PDT 24 Jul 27 04:59:34 PM PDT 24 284827005 ps
T96 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.57545781 Jul 27 04:58:46 PM PDT 24 Jul 27 04:58:47 PM PDT 24 16113120 ps
T549 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1629365597 Jul 27 04:59:16 PM PDT 24 Jul 27 04:59:17 PM PDT 24 11685849 ps
T550 /workspace/coverage/cover_reg_top/16.hmac_intr_test.357174938 Jul 27 04:59:04 PM PDT 24 Jul 27 04:59:05 PM PDT 24 17756719 ps
T113 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1116958498 Jul 27 04:58:52 PM PDT 24 Jul 27 04:58:54 PM PDT 24 31938755 ps
T551 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2618535850 Jul 27 04:59:21 PM PDT 24 Jul 27 04:59:22 PM PDT 24 20472169 ps
T552 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4011562993 Jul 27 04:59:10 PM PDT 24 Jul 27 04:59:13 PM PDT 24 45535943 ps
T114 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.928315527 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:17 PM PDT 24 169800109 ps
T553 /workspace/coverage/cover_reg_top/32.hmac_intr_test.412861440 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:24 PM PDT 24 45533156 ps
T554 /workspace/coverage/cover_reg_top/17.hmac_intr_test.4154043634 Jul 27 04:59:20 PM PDT 24 Jul 27 04:59:20 PM PDT 24 11962869 ps
T555 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3752460086 Jul 27 04:59:16 PM PDT 24 Jul 27 04:59:16 PM PDT 24 34343732 ps
T556 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2087529290 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:21 PM PDT 24 108749451 ps
T557 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1457250285 Jul 27 04:58:57 PM PDT 24 Jul 27 04:59:01 PM PDT 24 402037150 ps
T115 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1543645283 Jul 27 04:58:59 PM PDT 24 Jul 27 04:59:01 PM PDT 24 270468431 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3303215507 Jul 27 04:58:43 PM PDT 24 Jul 27 04:58:44 PM PDT 24 102733206 ps
T558 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3889262980 Jul 27 04:59:05 PM PDT 24 Jul 27 04:59:07 PM PDT 24 144228100 ps
T559 /workspace/coverage/cover_reg_top/8.hmac_intr_test.605429602 Jul 27 04:59:01 PM PDT 24 Jul 27 04:59:02 PM PDT 24 86025208 ps
T116 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3736743644 Jul 27 04:58:50 PM PDT 24 Jul 27 04:58:52 PM PDT 24 121837816 ps
T127 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.816797550 Jul 27 04:59:10 PM PDT 24 Jul 27 04:59:13 PM PDT 24 1514841816 ps
T560 /workspace/coverage/cover_reg_top/35.hmac_intr_test.783581675 Jul 27 04:58:59 PM PDT 24 Jul 27 04:59:00 PM PDT 24 37078708 ps
T561 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4130017399 Jul 27 04:58:57 PM PDT 24 Jul 27 04:59:07 PM PDT 24 44602463 ps
T562 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.229806267 Jul 27 04:58:44 PM PDT 24 Jul 27 05:03:19 PM PDT 24 54896791802 ps
T130 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3593199629 Jul 27 04:59:00 PM PDT 24 Jul 27 04:59:04 PM PDT 24 236347533 ps
T563 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3137508176 Jul 27 04:58:39 PM PDT 24 Jul 27 04:58:40 PM PDT 24 38500915 ps
T564 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3320904541 Jul 27 04:59:19 PM PDT 24 Jul 27 04:59:20 PM PDT 24 11164635 ps
T565 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.712330135 Jul 27 04:59:00 PM PDT 24 Jul 27 04:59:06 PM PDT 24 2689795156 ps
T117 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4189807448 Jul 27 04:59:00 PM PDT 24 Jul 27 04:59:02 PM PDT 24 49611216 ps
T566 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1759301894 Jul 27 04:58:59 PM PDT 24 Jul 27 04:59:02 PM PDT 24 112970428 ps
T567 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.169695406 Jul 27 04:58:59 PM PDT 24 Jul 27 04:59:03 PM PDT 24 143745653 ps
T568 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3714169034 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:19 PM PDT 24 16545535 ps
T569 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2667577845 Jul 27 04:59:05 PM PDT 24 Jul 27 04:59:06 PM PDT 24 29045956 ps
T570 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1645137647 Jul 27 04:59:14 PM PDT 24 Jul 27 04:59:18 PM PDT 24 484774973 ps
T104 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1071437004 Jul 27 04:58:45 PM PDT 24 Jul 27 04:58:51 PM PDT 24 543507994 ps
T571 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1718016968 Jul 27 04:58:50 PM PDT 24 Jul 27 04:58:51 PM PDT 24 58109661 ps
T572 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3579169763 Jul 27 04:59:03 PM PDT 24 Jul 27 04:59:03 PM PDT 24 30351828 ps
T573 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.873888600 Jul 27 04:58:54 PM PDT 24 Jul 27 04:58:55 PM PDT 24 24395778 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1755577289 Jul 27 04:58:56 PM PDT 24 Jul 27 04:58:59 PM PDT 24 1254272175 ps
T575 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1709237092 Jul 27 04:58:39 PM PDT 24 Jul 27 04:58:43 PM PDT 24 177175943 ps
T98 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.995382852 Jul 27 04:58:39 PM PDT 24 Jul 27 04:58:40 PM PDT 24 18253826 ps
T576 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.298605956 Jul 27 04:58:50 PM PDT 24 Jul 27 04:58:52 PM PDT 24 198997749 ps
T577 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2904619338 Jul 27 04:58:43 PM PDT 24 Jul 27 04:58:44 PM PDT 24 39961751 ps
T578 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3059560258 Jul 27 04:58:43 PM PDT 24 Jul 27 04:58:46 PM PDT 24 1225384416 ps
T579 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3727612106 Jul 27 04:58:59 PM PDT 24 Jul 27 04:59:00 PM PDT 24 16084678 ps
T580 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.126015825 Jul 27 04:59:05 PM PDT 24 Jul 27 04:59:07 PM PDT 24 315706647 ps
T129 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.770306889 Jul 27 04:58:55 PM PDT 24 Jul 27 04:58:59 PM PDT 24 494888072 ps
T581 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1201463284 Jul 27 04:58:55 PM PDT 24 Jul 27 04:58:57 PM PDT 24 48205212 ps
T582 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4151686079 Jul 27 04:58:57 PM PDT 24 Jul 27 04:58:58 PM PDT 24 17250106 ps
T583 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1575837092 Jul 27 04:58:53 PM PDT 24 Jul 27 04:58:54 PM PDT 24 30289784 ps
T584 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3854439679 Jul 27 04:59:03 PM PDT 24 Jul 27 04:59:04 PM PDT 24 36111637 ps
T585 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3071496651 Jul 27 04:58:52 PM PDT 24 Jul 27 04:58:55 PM PDT 24 231707879 ps
T124 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2153948171 Jul 27 04:58:54 PM PDT 24 Jul 27 04:58:57 PM PDT 24 409740296 ps
T128 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.414025373 Jul 27 04:58:39 PM PDT 24 Jul 27 04:58:41 PM PDT 24 603697932 ps
T586 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2706349838 Jul 27 04:59:01 PM PDT 24 Jul 27 04:59:01 PM PDT 24 16996904 ps
T587 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2173294379 Jul 27 04:59:11 PM PDT 24 Jul 27 04:59:14 PM PDT 24 667482705 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.751120943 Jul 27 04:58:51 PM PDT 24 Jul 27 04:58:55 PM PDT 24 343190755 ps
T588 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1921984336 Jul 27 04:58:39 PM PDT 24 Jul 27 04:58:41 PM PDT 24 84547006 ps
T589 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3384994958 Jul 27 04:59:05 PM PDT 24 Jul 27 04:59:05 PM PDT 24 57575778 ps
T590 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2689486728 Jul 27 04:59:26 PM PDT 24 Jul 27 04:59:28 PM PDT 24 62345599 ps
T591 /workspace/coverage/cover_reg_top/2.hmac_intr_test.452991955 Jul 27 04:58:45 PM PDT 24 Jul 27 04:58:46 PM PDT 24 24048049 ps
T592 /workspace/coverage/cover_reg_top/15.hmac_intr_test.490299852 Jul 27 04:59:03 PM PDT 24 Jul 27 04:59:04 PM PDT 24 31578234 ps
T593 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2575005333 Jul 27 04:58:55 PM PDT 24 Jul 27 04:58:56 PM PDT 24 207978572 ps
T594 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2707675494 Jul 27 04:59:03 PM PDT 24 Jul 27 04:59:04 PM PDT 24 48178181 ps
T595 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1427776608 Jul 27 04:59:05 PM PDT 24 Jul 27 04:59:06 PM PDT 24 16917780 ps
T126 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3597562415 Jul 27 04:59:25 PM PDT 24 Jul 27 04:59:28 PM PDT 24 807116101 ps
T596 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1869166755 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:26 PM PDT 24 166991355 ps
T597 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.783618079 Jul 27 04:58:49 PM PDT 24 Jul 27 04:58:54 PM PDT 24 426494533 ps
T598 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2154229719 Jul 27 04:59:18 PM PDT 24 Jul 27 05:08:11 PM PDT 24 276333904902 ps
T599 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4053996936 Jul 27 04:59:07 PM PDT 24 Jul 27 04:59:10 PM PDT 24 263176104 ps
T600 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2210865359 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:19 PM PDT 24 13086816 ps
T131 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1544264820 Jul 27 04:58:56 PM PDT 24 Jul 27 04:58:58 PM PDT 24 325684284 ps
T601 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1187355542 Jul 27 04:59:14 PM PDT 24 Jul 27 04:59:14 PM PDT 24 21038719 ps
T602 /workspace/coverage/cover_reg_top/45.hmac_intr_test.962170585 Jul 27 04:59:10 PM PDT 24 Jul 27 04:59:11 PM PDT 24 11128229 ps
T603 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1117212426 Jul 27 04:59:12 PM PDT 24 Jul 27 04:59:16 PM PDT 24 772935538 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1861733210 Jul 27 04:58:50 PM PDT 24 Jul 27 04:58:51 PM PDT 24 27998443 ps
T604 /workspace/coverage/cover_reg_top/43.hmac_intr_test.817760429 Jul 27 04:59:14 PM PDT 24 Jul 27 04:59:15 PM PDT 24 36826340 ps
T605 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3632137638 Jul 27 04:59:03 PM PDT 24 Jul 27 04:59:07 PM PDT 24 266744192 ps
T606 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3171734855 Jul 27 04:58:52 PM PDT 24 Jul 27 04:58:53 PM PDT 24 137846439 ps
T607 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1733959912 Jul 27 04:58:44 PM PDT 24 Jul 27 04:58:45 PM PDT 24 29099175 ps
T608 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.725952052 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:16 PM PDT 24 36020193 ps
T609 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.923531944 Jul 27 04:59:04 PM PDT 24 Jul 27 04:59:10 PM PDT 24 146534841 ps
T610 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2331777260 Jul 27 04:59:16 PM PDT 24 Jul 27 04:59:17 PM PDT 24 100354991 ps
T611 /workspace/coverage/cover_reg_top/49.hmac_intr_test.950741887 Jul 27 04:59:21 PM PDT 24 Jul 27 04:59:21 PM PDT 24 100023233 ps
T612 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.371150485 Jul 27 04:59:17 PM PDT 24 Jul 27 04:59:20 PM PDT 24 2532394526 ps
T613 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2235355651 Jul 27 04:59:07 PM PDT 24 Jul 27 04:59:14 PM PDT 24 124184515 ps
T614 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2411900899 Jul 27 04:59:23 PM PDT 24 Jul 27 04:59:23 PM PDT 24 23323313 ps
T615 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.604858741 Jul 27 04:59:19 PM PDT 24 Jul 27 04:59:20 PM PDT 24 182425262 ps
T616 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2445860114 Jul 27 04:59:12 PM PDT 24 Jul 27 04:59:13 PM PDT 24 29673285 ps
T617 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3229479922 Jul 27 04:58:59 PM PDT 24 Jul 27 04:59:00 PM PDT 24 18170248 ps
T618 /workspace/coverage/cover_reg_top/33.hmac_intr_test.75621242 Jul 27 04:59:14 PM PDT 24 Jul 27 04:59:15 PM PDT 24 54629176 ps
T619 /workspace/coverage/cover_reg_top/3.hmac_intr_test.358352308 Jul 27 04:58:43 PM PDT 24 Jul 27 04:58:44 PM PDT 24 55232357 ps
T620 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.718098226 Jul 27 04:59:03 PM PDT 24 Jul 27 04:59:04 PM PDT 24 65228900 ps
T621 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3610868799 Jul 27 04:58:57 PM PDT 24 Jul 27 04:58:58 PM PDT 24 250677989 ps
T101 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1292627102 Jul 27 04:59:01 PM PDT 24 Jul 27 04:59:01 PM PDT 24 27184088 ps
T622 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2869898630 Jul 27 04:59:11 PM PDT 24 Jul 27 04:59:12 PM PDT 24 17348693 ps
T623 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2150968748 Jul 27 04:59:09 PM PDT 24 Jul 27 04:59:10 PM PDT 24 62777470 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4270094104 Jul 27 04:58:52 PM PDT 24 Jul 27 04:58:54 PM PDT 24 165343774 ps
T59 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.250754838 Jul 27 04:59:22 PM PDT 24 Jul 27 04:59:26 PM PDT 24 233855870 ps
T625 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2087787919 Jul 27 04:59:19 PM PDT 24 Jul 27 04:59:21 PM PDT 24 44232482 ps
T626 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4245683323 Jul 27 04:59:09 PM PDT 24 Jul 27 04:59:10 PM PDT 24 13898980 ps
T627 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1398150628 Jul 27 04:58:57 PM PDT 24 Jul 27 04:58:58 PM PDT 24 99734337 ps
T102 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1075365683 Jul 27 04:59:02 PM PDT 24 Jul 27 04:59:03 PM PDT 24 65913453 ps
T105 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3460563030 Jul 27 04:58:42 PM PDT 24 Jul 27 04:58:43 PM PDT 24 46701255 ps
T106 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1240682492 Jul 27 04:59:06 PM PDT 24 Jul 27 04:59:07 PM PDT 24 124023490 ps
T628 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2464325640 Jul 27 04:58:42 PM PDT 24 Jul 27 04:58:45 PM PDT 24 115992175 ps
T629 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3755784572 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:20 PM PDT 24 55801923 ps
T630 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1362437441 Jul 27 04:59:01 PM PDT 24 Jul 27 04:59:02 PM PDT 24 80486943 ps
T631 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.588120699 Jul 27 04:58:52 PM PDT 24 Jul 27 04:58:55 PM PDT 24 58654397 ps
T107 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2147676163 Jul 27 04:58:44 PM PDT 24 Jul 27 04:58:45 PM PDT 24 50116917 ps
T632 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3500942185 Jul 27 04:59:16 PM PDT 24 Jul 27 04:59:18 PM PDT 24 317267571 ps
T633 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2291473369 Jul 27 04:59:05 PM PDT 24 Jul 27 04:59:07 PM PDT 24 42624315 ps
T108 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1000850806 Jul 27 04:58:55 PM PDT 24 Jul 27 04:58:56 PM PDT 24 81042298 ps
T109 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2002043515 Jul 27 04:59:00 PM PDT 24 Jul 27 04:59:01 PM PDT 24 185041345 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3964803618 Jul 27 04:58:43 PM PDT 24 Jul 27 04:58:45 PM PDT 24 590766450 ps
T635 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.624475876 Jul 27 04:58:43 PM PDT 24 Jul 27 04:58:45 PM PDT 24 409213728 ps
T636 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.579949149 Jul 27 04:59:04 PM PDT 24 Jul 27 04:59:04 PM PDT 24 15212361 ps
T637 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2559793174 Jul 27 04:59:24 PM PDT 24 Jul 27 04:59:25 PM PDT 24 13530706 ps
T638 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2898831812 Jul 27 04:59:15 PM PDT 24 Jul 27 04:59:17 PM PDT 24 158898458 ps
T125 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.481486095 Jul 27 04:59:09 PM PDT 24 Jul 27 04:59:14 PM PDT 24 264614615 ps
T639 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1889986749 Jul 27 04:58:45 PM PDT 24 Jul 27 04:58:50 PM PDT 24 383302229 ps
T640 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1964814112 Jul 27 04:58:44 PM PDT 24 Jul 27 04:58:48 PM PDT 24 483749668 ps
T641 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2182891923 Jul 27 04:58:57 PM PDT 24 Jul 27 04:58:59 PM PDT 24 241389183 ps
T642 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.315590980 Jul 27 04:58:49 PM PDT 24 Jul 27 04:58:54 PM PDT 24 888284196 ps
T643 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1024111710 Jul 27 04:59:11 PM PDT 24 Jul 27 05:05:02 PM PDT 24 35382336209 ps
T644 /workspace/coverage/cover_reg_top/4.hmac_intr_test.245141634 Jul 27 04:58:47 PM PDT 24 Jul 27 04:58:48 PM PDT 24 32415906 ps
T645 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.977374250 Jul 27 04:59:02 PM PDT 24 Jul 27 04:59:03 PM PDT 24 18439748 ps
T646 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1133967059 Jul 27 04:58:49 PM PDT 24 Jul 27 04:58:55 PM PDT 24 449545159 ps
T647 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.533278609 Jul 27 04:59:18 PM PDT 24 Jul 27 04:59:20 PM PDT 24 421500933 ps
T648 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2692151109 Jul 27 04:59:04 PM PDT 24 Jul 27 04:59:04 PM PDT 24 24195565 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1516504552 Jul 27 04:58:43 PM PDT 24 Jul 27 04:58:47 PM PDT 24 212885799 ps
T650 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.326216086 Jul 27 04:59:00 PM PDT 24 Jul 27 04:59:01 PM PDT 24 28527811 ps
T651 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4256162896 Jul 27 04:58:56 PM PDT 24 Jul 27 04:58:59 PM PDT 24 603993390 ps
T132 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.529079262 Jul 27 04:59:13 PM PDT 24 Jul 27 04:59:17 PM PDT 24 313514362 ps
T652 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.23253108 Jul 27 04:58:55 PM PDT 24 Jul 27 04:58:56 PM PDT 24 28582438 ps
T653 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3929762169 Jul 27 04:58:57 PM PDT 24 Jul 27 04:58:58 PM PDT 24 27819362 ps
T110 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4088234324 Jul 27 04:58:51 PM PDT 24 Jul 27 04:59:08 PM PDT 24 8463511274 ps
T654 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1556255138 Jul 27 04:59:02 PM PDT 24 Jul 27 04:59:03 PM PDT 24 22608696 ps
T655 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2386145290 Jul 27 04:59:34 PM PDT 24 Jul 27 04:59:34 PM PDT 24 19143461 ps
T656 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1826296114 Jul 27 04:58:53 PM PDT 24 Jul 27 04:58:54 PM PDT 24 109119882 ps
T657 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2180770002 Jul 27 04:58:57 PM PDT 24 Jul 27 04:58:58 PM PDT 24 44781751 ps
T658 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2526130621 Jul 27 04:59:01 PM PDT 24 Jul 27 04:59:02 PM PDT 24 20612816 ps
T659 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1545273975 Jul 27 04:58:46 PM PDT 24 Jul 27 04:58:47 PM PDT 24 30840319 ps

Test location /workspace/coverage/default/38.hmac_long_msg.110454554
Short name T21
Test name
Test status
Simulation time 30693876427 ps
CPU time 112.45 seconds
Started Jul 27 05:49:54 PM PDT 24
Finished Jul 27 05:51:46 PM PDT 24
Peak memory 199776 kb
Host smart-18d18d64-c26f-4cce-904a-8a3460dc405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110454554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.110454554
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3041855652
Short name T11
Test name
Test status
Simulation time 337061881163 ps
CPU time 3233.7 seconds
Started Jul 27 05:48:51 PM PDT 24
Finished Jul 27 06:42:45 PM PDT 24
Peak memory 730976 kb
Host smart-b99a0a8f-6a24-4e65-9ad0-a1b5ee4b270b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041855652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3041855652
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_stress_all.448074977
Short name T22
Test name
Test status
Simulation time 127456857222 ps
CPU time 4204.41 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 06:59:47 PM PDT 24
Peak memory 831992 kb
Host smart-32b5974e-3761-494e-bf5f-961b51a30674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448074977 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.448074977
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.992032014
Short name T123
Test name
Test status
Simulation time 284827005 ps
CPU time 4.68 seconds
Started Jul 27 04:59:29 PM PDT 24
Finished Jul 27 04:59:34 PM PDT 24
Peak memory 199812 kb
Host smart-f40bbf52-8352-4ce2-ac02-72710bfeee99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992032014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.992032014
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3248488395
Short name T24
Test name
Test status
Simulation time 43078445557 ps
CPU time 1185.27 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 06:09:03 PM PDT 24
Peak memory 199780 kb
Host smart-cc9feda9-f2a4-4caf-b45b-d38cf4c750cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248488395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3248488395
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4129219259
Short name T31
Test name
Test status
Simulation time 14790104 ps
CPU time 0.62 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:49:16 PM PDT 24
Peak memory 195716 kb
Host smart-49c3276c-fc6e-4e4c-b562-5e8a6cee1667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129219259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4129219259
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.951597521
Short name T45
Test name
Test status
Simulation time 38165344 ps
CPU time 0.82 seconds
Started Jul 27 05:48:45 PM PDT 24
Finished Jul 27 05:48:46 PM PDT 24
Peak memory 218220 kb
Host smart-1bc235f5-3b5f-4811-a3e4-9204d1627b84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951597521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.951597521
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.751120943
Short name T99
Test name
Test status
Simulation time 343190755 ps
CPU time 3.25 seconds
Started Jul 27 04:58:51 PM PDT 24
Finished Jul 27 04:58:55 PM PDT 24
Peak memory 199816 kb
Host smart-526ea6c8-392e-4e7a-852d-99dcde740e4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751120943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.751120943
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3189692625
Short name T78
Test name
Test status
Simulation time 29079447 ps
CPU time 0.82 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:00 PM PDT 24
Peak memory 199156 kb
Host smart-e2d36774-bd9d-455b-b168-ac7daf393eaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189692625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3189692625
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.529079262
Short name T132
Test name
Test status
Simulation time 313514362 ps
CPU time 3.92 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 199784 kb
Host smart-137d60cb-cca8-40d5-8c19-0ed8d191059d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529079262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.529079262
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.250754838
Short name T59
Test name
Test status
Simulation time 233855870 ps
CPU time 3.99 seconds
Started Jul 27 04:59:22 PM PDT 24
Finished Jul 27 04:59:26 PM PDT 24
Peak memory 199768 kb
Host smart-51155267-afec-435a-bec2-c8cfbc051558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250754838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.250754838
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all.4280929913
Short name T36
Test name
Test status
Simulation time 8449741101 ps
CPU time 209.95 seconds
Started Jul 27 05:48:56 PM PDT 24
Finished Jul 27 05:52:26 PM PDT 24
Peak memory 216064 kb
Host smart-791e7340-cdcf-4b4c-9884-3aee523cb03f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280929913 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.4280929913
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3764435311
Short name T58
Test name
Test status
Simulation time 49827052 ps
CPU time 1.76 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 200044 kb
Host smart-a0576c98-5df3-4226-b5f7-8c4d377c2f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764435311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3764435311
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3692335918
Short name T1
Test name
Test status
Simulation time 583000585453 ps
CPU time 2718.29 seconds
Started Jul 27 05:48:45 PM PDT 24
Finished Jul 27 06:34:03 PM PDT 24
Peak memory 215988 kb
Host smart-93f3b142-148b-4383-83eb-5d80cfd28cb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3692335918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3692335918
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3404023600
Short name T20
Test name
Test status
Simulation time 195066888232 ps
CPU time 1654.98 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 06:16:39 PM PDT 24
Peak memory 763536 kb
Host smart-aa5800d8-acb0-4363-acdd-5c8eaa9740d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404023600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3404023600
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1709237092
Short name T575
Test name
Test status
Simulation time 177175943 ps
CPU time 3.19 seconds
Started Jul 27 04:58:39 PM PDT 24
Finished Jul 27 04:58:43 PM PDT 24
Peak memory 198680 kb
Host smart-c72d4f8b-a18d-4a8d-b1de-a12faefa862a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709237092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1709237092
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.783618079
Short name T597
Test name
Test status
Simulation time 426494533 ps
CPU time 5.14 seconds
Started Jul 27 04:58:49 PM PDT 24
Finished Jul 27 04:58:54 PM PDT 24
Peak memory 199804 kb
Host smart-4a3b8387-c62e-4d1c-8a74-2324b61f97f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783618079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.783618079
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1545273975
Short name T659
Test name
Test status
Simulation time 30840319 ps
CPU time 0.86 seconds
Started Jul 27 04:58:46 PM PDT 24
Finished Jul 27 04:58:47 PM PDT 24
Peak memory 198876 kb
Host smart-1076fbe7-3d89-40bb-acdf-600dd50373a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545273975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1545273975
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.229806267
Short name T562
Test name
Test status
Simulation time 54896791802 ps
CPU time 274.5 seconds
Started Jul 27 04:58:44 PM PDT 24
Finished Jul 27 05:03:19 PM PDT 24
Peak memory 208132 kb
Host smart-7b48ec3f-2c81-4b4c-b2ba-530d11c6ce6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229806267 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.229806267
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.995382852
Short name T98
Test name
Test status
Simulation time 18253826 ps
CPU time 0.88 seconds
Started Jul 27 04:58:39 PM PDT 24
Finished Jul 27 04:58:40 PM PDT 24
Peak memory 199612 kb
Host smart-8505d5f8-3bba-40ac-bcf2-9b6bc21da821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995382852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.995382852
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3137508176
Short name T563
Test name
Test status
Simulation time 38500915 ps
CPU time 0.57 seconds
Started Jul 27 04:58:39 PM PDT 24
Finished Jul 27 04:58:40 PM PDT 24
Peak memory 194712 kb
Host smart-d69146d1-3809-40be-afd0-8ac0d299b8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137508176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3137508176
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3736743644
Short name T116
Test name
Test status
Simulation time 121837816 ps
CPU time 1.66 seconds
Started Jul 27 04:58:50 PM PDT 24
Finished Jul 27 04:58:52 PM PDT 24
Peak memory 199840 kb
Host smart-8d2293c0-f6a6-4e32-98ad-a2fe957248e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736743644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3736743644
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3386823829
Short name T540
Test name
Test status
Simulation time 262025135 ps
CPU time 2.49 seconds
Started Jul 27 04:58:47 PM PDT 24
Finished Jul 27 04:58:50 PM PDT 24
Peak memory 199736 kb
Host smart-a8a79bf1-e46d-49e0-b0e3-b3f9e2fac555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386823829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3386823829
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1964814112
Short name T640
Test name
Test status
Simulation time 483749668 ps
CPU time 3.83 seconds
Started Jul 27 04:58:44 PM PDT 24
Finished Jul 27 04:58:48 PM PDT 24
Peak memory 199912 kb
Host smart-cdfdfa81-5718-4da2-8550-bcef555ff150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964814112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1964814112
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4088234324
Short name T110
Test name
Test status
Simulation time 8463511274 ps
CPU time 16.21 seconds
Started Jul 27 04:58:51 PM PDT 24
Finished Jul 27 04:59:08 PM PDT 24
Peak memory 199892 kb
Host smart-9ab072d1-6edc-4b9d-92ea-2002c12b68bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088234324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4088234324
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3303215507
Short name T97
Test name
Test status
Simulation time 102733206 ps
CPU time 0.88 seconds
Started Jul 27 04:58:43 PM PDT 24
Finished Jul 27 04:58:44 PM PDT 24
Peak memory 199348 kb
Host smart-814fd437-1743-4905-ba08-5768fb0e9f56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303215507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3303215507
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3610868799
Short name T621
Test name
Test status
Simulation time 250677989 ps
CPU time 1.82 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:58:58 PM PDT 24
Peak memory 199872 kb
Host smart-d6ceb1f1-46c0-4ae8-a370-2c53a8b4aaba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610868799 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3610868799
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3460563030
Short name T105
Test name
Test status
Simulation time 46701255 ps
CPU time 0.83 seconds
Started Jul 27 04:58:42 PM PDT 24
Finished Jul 27 04:58:43 PM PDT 24
Peak memory 199668 kb
Host smart-31193797-166e-4369-925a-68596ca1aef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460563030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3460563030
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1718016968
Short name T571
Test name
Test status
Simulation time 58109661 ps
CPU time 0.59 seconds
Started Jul 27 04:58:50 PM PDT 24
Finished Jul 27 04:58:51 PM PDT 24
Peak memory 194716 kb
Host smart-af583172-2696-49e1-b494-0bbea0bb211f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718016968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1718016968
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1755577289
Short name T574
Test name
Test status
Simulation time 1254272175 ps
CPU time 2.47 seconds
Started Jul 27 04:58:56 PM PDT 24
Finished Jul 27 04:58:59 PM PDT 24
Peak memory 199792 kb
Host smart-d0aab2be-66ea-4e93-b798-639aa0922821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755577289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1755577289
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1775158463
Short name T546
Test name
Test status
Simulation time 72864485 ps
CPU time 3.71 seconds
Started Jul 27 04:58:42 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 199840 kb
Host smart-82da5b7b-df02-4225-b63c-4db5e192f8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775158463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1775158463
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.414025373
Short name T128
Test name
Test status
Simulation time 603697932 ps
CPU time 1.81 seconds
Started Jul 27 04:58:39 PM PDT 24
Finished Jul 27 04:58:41 PM PDT 24
Peak memory 199836 kb
Host smart-7ecc92a9-0100-449a-886e-a625fa0b9f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414025373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.414025373
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3704478918
Short name T542
Test name
Test status
Simulation time 49272189 ps
CPU time 1.18 seconds
Started Jul 27 04:58:49 PM PDT 24
Finished Jul 27 04:58:55 PM PDT 24
Peak memory 199676 kb
Host smart-3e16bc4b-1156-4564-b3d7-494b96c86a01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704478918 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3704478918
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2331777260
Short name T610
Test name
Test status
Simulation time 100354991 ps
CPU time 0.97 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 199680 kb
Host smart-3eea8b0c-627e-4112-8c14-6a1edc9b2e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331777260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2331777260
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1244494117
Short name T545
Test name
Test status
Simulation time 18870920 ps
CPU time 0.58 seconds
Started Jul 27 04:59:04 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 194728 kb
Host smart-27f516a6-b292-4bd9-9a76-2bb3c0aaf72d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244494117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1244494117
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1543645283
Short name T115
Test name
Test status
Simulation time 270468431 ps
CPU time 2.23 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 199784 kb
Host smart-a4e46e50-838e-4661-82be-86d8ddfd2c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543645283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1543645283
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1117212426
Short name T603
Test name
Test status
Simulation time 772935538 ps
CPU time 3.69 seconds
Started Jul 27 04:59:12 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 199812 kb
Host smart-026d14c9-e94a-4e45-a866-1aece515f264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117212426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1117212426
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3755784572
Short name T629
Test name
Test status
Simulation time 55801923 ps
CPU time 1.78 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 199792 kb
Host smart-42ace397-1663-48a0-86ce-a95576594f19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755784572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3755784572
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1024111710
Short name T643
Test name
Test status
Simulation time 35382336209 ps
CPU time 350.59 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 05:05:02 PM PDT 24
Peak memory 216352 kb
Host smart-73fb50ba-1ffa-48ac-92a8-bbe628890615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024111710 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1024111710
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.718098226
Short name T620
Test name
Test status
Simulation time 65228900 ps
CPU time 0.7 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 197648 kb
Host smart-1426770e-a5d9-457b-bdd8-4f58bc5a03ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718098226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.718098226
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3171734855
Short name T606
Test name
Test status
Simulation time 137846439 ps
CPU time 0.54 seconds
Started Jul 27 04:58:52 PM PDT 24
Finished Jul 27 04:58:53 PM PDT 24
Peak memory 194652 kb
Host smart-814ea0c9-f699-4f38-b50f-b636ff14da97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171734855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3171734855
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.126015825
Short name T580
Test name
Test status
Simulation time 315706647 ps
CPU time 1.84 seconds
Started Jul 27 04:59:05 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 199888 kb
Host smart-bfb839ea-7510-43d0-9d34-53ec404a9ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126015825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.126015825
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2235355651
Short name T613
Test name
Test status
Simulation time 124184515 ps
CPU time 2.12 seconds
Started Jul 27 04:59:07 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 199764 kb
Host smart-c56018ae-3249-45e5-8264-06837f9c19e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235355651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2235355651
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3588791418
Short name T57
Test name
Test status
Simulation time 112322419 ps
CPU time 1.8 seconds
Started Jul 27 04:59:14 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 199884 kb
Host smart-43da20b9-5650-4dbf-84e1-8417712d626f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588791418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3588791418
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4270094104
Short name T624
Test name
Test status
Simulation time 165343774 ps
CPU time 1.68 seconds
Started Jul 27 04:58:52 PM PDT 24
Finished Jul 27 04:58:54 PM PDT 24
Peak memory 199908 kb
Host smart-3c0d1f94-c8a2-456d-8f06-e19d6147b8ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270094104 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4270094104
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.23253108
Short name T652
Test name
Test status
Simulation time 28582438 ps
CPU time 0.81 seconds
Started Jul 27 04:58:55 PM PDT 24
Finished Jul 27 04:58:56 PM PDT 24
Peak memory 199080 kb
Host smart-ec2157ed-4ccd-4fad-8dfb-332b1d2cb201
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.23253108
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1354667365
Short name T535
Test name
Test status
Simulation time 11759508 ps
CPU time 0.62 seconds
Started Jul 27 04:58:58 PM PDT 24
Finished Jul 27 04:58:59 PM PDT 24
Peak memory 194736 kb
Host smart-3b323919-d04d-489a-9589-d286277415b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354667365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1354667365
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3500942185
Short name T632
Test name
Test status
Simulation time 317267571 ps
CPU time 1.2 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:18 PM PDT 24
Peak memory 199640 kb
Host smart-65f746a4-7a51-44e0-a87b-34ae66c2597e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500942185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3500942185
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.588120699
Short name T631
Test name
Test status
Simulation time 58654397 ps
CPU time 2.97 seconds
Started Jul 27 04:58:52 PM PDT 24
Finished Jul 27 04:58:55 PM PDT 24
Peak memory 199836 kb
Host smart-e6559194-40fc-49fa-ab47-4e80d64a0d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588120699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.588120699
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2689486728
Short name T590
Test name
Test status
Simulation time 62345599 ps
CPU time 1.74 seconds
Started Jul 27 04:59:26 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 199832 kb
Host smart-bd78cc8c-cdcc-49aa-82e9-db666bc6cb78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689486728 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2689486728
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2002043515
Short name T109
Test name
Test status
Simulation time 185041345 ps
CPU time 0.83 seconds
Started Jul 27 04:59:00 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 199656 kb
Host smart-d589b4a6-9b18-4f64-bf5e-b853483ba1af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002043515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2002043515
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3579169763
Short name T572
Test name
Test status
Simulation time 30351828 ps
CPU time 0.59 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:03 PM PDT 24
Peak memory 194792 kb
Host smart-73b2d019-a997-44aa-9663-41ff35e65a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579169763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3579169763
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4189807448
Short name T117
Test name
Test status
Simulation time 49611216 ps
CPU time 2.2 seconds
Started Jul 27 04:59:00 PM PDT 24
Finished Jul 27 04:59:02 PM PDT 24
Peak memory 199344 kb
Host smart-c7c23eeb-6c01-46e5-8a46-e5709f8b941a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189807448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4189807448
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1826296114
Short name T656
Test name
Test status
Simulation time 109119882 ps
CPU time 1.68 seconds
Started Jul 27 04:58:53 PM PDT 24
Finished Jul 27 04:58:54 PM PDT 24
Peak memory 199832 kb
Host smart-e07644be-7da5-46c5-ac39-300aa7769529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826296114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1826296114
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1544264820
Short name T131
Test name
Test status
Simulation time 325684284 ps
CPU time 1.84 seconds
Started Jul 27 04:58:56 PM PDT 24
Finished Jul 27 04:58:58 PM PDT 24
Peak memory 199804 kb
Host smart-ba1ef321-cf39-481e-b522-52d587b19a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544264820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1544264820
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3889262980
Short name T558
Test name
Test status
Simulation time 144228100 ps
CPU time 1.85 seconds
Started Jul 27 04:59:05 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 199884 kb
Host smart-735bcd9c-34f9-4dde-bd8f-0fbde74ccae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889262980 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3889262980
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.326216086
Short name T650
Test name
Test status
Simulation time 28527811 ps
CPU time 0.67 seconds
Started Jul 27 04:59:00 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 198024 kb
Host smart-40fc3754-2450-40ed-b9df-c98e3d0b8ce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326216086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.326216086
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3929762169
Short name T653
Test name
Test status
Simulation time 27819362 ps
CPU time 0.59 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:58:58 PM PDT 24
Peak memory 194720 kb
Host smart-2c3ae161-68db-43d3-b0e2-6234194df1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929762169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3929762169
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2575005333
Short name T593
Test name
Test status
Simulation time 207978572 ps
CPU time 1.59 seconds
Started Jul 27 04:58:55 PM PDT 24
Finished Jul 27 04:58:56 PM PDT 24
Peak memory 199900 kb
Host smart-b3d557a1-b886-49a6-950d-91ec2e188449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575005333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2575005333
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1869166755
Short name T596
Test name
Test status
Simulation time 166991355 ps
CPU time 2.88 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:26 PM PDT 24
Peak memory 199828 kb
Host smart-f0eebce5-d6d3-4c49-b4b9-909861c932f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869166755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1869166755
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3593199629
Short name T130
Test name
Test status
Simulation time 236347533 ps
CPU time 3.76 seconds
Started Jul 27 04:59:00 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 199920 kb
Host smart-58c26ad5-7d70-4208-ab31-d63905a6df9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593199629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3593199629
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3059560258
Short name T578
Test name
Test status
Simulation time 1225384416 ps
CPU time 2.34 seconds
Started Jul 27 04:58:43 PM PDT 24
Finished Jul 27 04:58:46 PM PDT 24
Peak memory 199988 kb
Host smart-8066c808-9159-4bbb-98ab-a74d6c4ef78d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059560258 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3059560258
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1292627102
Short name T101
Test name
Test status
Simulation time 27184088 ps
CPU time 0.83 seconds
Started Jul 27 04:59:01 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 199632 kb
Host smart-1ff84634-3c10-4b11-b790-2ee83c8d7d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292627102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1292627102
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.490299852
Short name T592
Test name
Test status
Simulation time 31578234 ps
CPU time 0.56 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 194688 kb
Host smart-df8fcfd8-d2c3-46e3-908b-d228ccae76b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490299852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.490299852
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.928315527
Short name T114
Test name
Test status
Simulation time 169800109 ps
CPU time 1.67 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 199816 kb
Host smart-3cb216dd-096d-4350-8342-f56dddc99087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928315527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.928315527
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3071496651
Short name T585
Test name
Test status
Simulation time 231707879 ps
CPU time 3.33 seconds
Started Jul 27 04:58:52 PM PDT 24
Finished Jul 27 04:58:55 PM PDT 24
Peak memory 199892 kb
Host smart-84a0900a-bccc-48d3-8445-cd53f12c5ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071496651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3071496651
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1362437441
Short name T630
Test name
Test status
Simulation time 80486943 ps
CPU time 1.51 seconds
Started Jul 27 04:59:01 PM PDT 24
Finished Jul 27 04:59:02 PM PDT 24
Peak memory 199744 kb
Host smart-9e3e8e72-8008-4c78-821b-4643d9cb9d8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362437441 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1362437441
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.977374250
Short name T645
Test name
Test status
Simulation time 18439748 ps
CPU time 0.82 seconds
Started Jul 27 04:59:02 PM PDT 24
Finished Jul 27 04:59:03 PM PDT 24
Peak memory 199680 kb
Host smart-95d567fd-4df0-464c-9cff-7ed07cea7af6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977374250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.977374250
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.357174938
Short name T550
Test name
Test status
Simulation time 17756719 ps
CPU time 0.61 seconds
Started Jul 27 04:59:04 PM PDT 24
Finished Jul 27 04:59:05 PM PDT 24
Peak memory 194732 kb
Host smart-31b9570b-01ae-4d61-b2fa-ca4fc3711cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357174938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.357174938
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1759301894
Short name T566
Test name
Test status
Simulation time 112970428 ps
CPU time 2.23 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:02 PM PDT 24
Peak memory 199884 kb
Host smart-bbd9b921-8b28-4986-ac8b-11fef6d966f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759301894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1759301894
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3632137638
Short name T605
Test name
Test status
Simulation time 266744192 ps
CPU time 3.45 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 199836 kb
Host smart-bbd65145-0c29-414f-b018-2d488e1607b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632137638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3632137638
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2914222274
Short name T56
Test name
Test status
Simulation time 162694046 ps
CPU time 1.76 seconds
Started Jul 27 04:59:00 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 199780 kb
Host smart-2e773af8-2a71-4eea-a6fb-df7da02f989e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914222274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2914222274
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2173294379
Short name T587
Test name
Test status
Simulation time 667482705 ps
CPU time 2.56 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 199816 kb
Host smart-f4f7213f-95aa-4689-b1e7-ea4d35997fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173294379 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2173294379
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.725952052
Short name T608
Test name
Test status
Simulation time 36020193 ps
CPU time 0.95 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 199652 kb
Host smart-6e8daf16-e4fc-4293-a7b3-6e9bebe5da40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725952052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.725952052
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4154043634
Short name T554
Test name
Test status
Simulation time 11962869 ps
CPU time 0.56 seconds
Started Jul 27 04:59:20 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 194688 kb
Host smart-648b3a3e-948a-4d7c-81aa-3105a32ce2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154043634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4154043634
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.533278609
Short name T647
Test name
Test status
Simulation time 421500933 ps
CPU time 1.88 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 199852 kb
Host smart-65ff5353-ca58-4e09-a0e7-90e9b0499d69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533278609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.533278609
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1575837092
Short name T583
Test name
Test status
Simulation time 30289784 ps
CPU time 1.37 seconds
Started Jul 27 04:58:53 PM PDT 24
Finished Jul 27 04:58:54 PM PDT 24
Peak memory 199784 kb
Host smart-3915c873-b185-45a1-892b-c3195d6f6680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575837092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1575837092
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.816797550
Short name T127
Test name
Test status
Simulation time 1514841816 ps
CPU time 2.69 seconds
Started Jul 27 04:59:10 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 199760 kb
Host smart-f2ecca76-80dc-4576-92c7-57eb67091169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816797550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.816797550
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2087787919
Short name T625
Test name
Test status
Simulation time 44232482 ps
CPU time 1.16 seconds
Started Jul 27 04:59:19 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 199648 kb
Host smart-c7996f9f-b4f6-4b3c-9708-5fdca7a1bbb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087787919 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2087787919
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.923531944
Short name T609
Test name
Test status
Simulation time 146534841 ps
CPU time 0.8 seconds
Started Jul 27 04:59:04 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 199348 kb
Host smart-0057a2ab-0f84-41fc-add5-6cd35c8e95d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923531944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.923531944
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2210865359
Short name T600
Test name
Test status
Simulation time 13086816 ps
CPU time 0.57 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:19 PM PDT 24
Peak memory 194816 kb
Host smart-382b06a8-f36e-465f-8abe-fc52c4b87a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210865359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2210865359
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1935393035
Short name T112
Test name
Test status
Simulation time 315446464 ps
CPU time 2.34 seconds
Started Jul 27 04:59:05 PM PDT 24
Finished Jul 27 04:59:08 PM PDT 24
Peak memory 199844 kb
Host smart-6283a530-267b-41be-8ab6-220c2b533407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935393035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1935393035
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1201463284
Short name T581
Test name
Test status
Simulation time 48205212 ps
CPU time 2.44 seconds
Started Jul 27 04:58:55 PM PDT 24
Finished Jul 27 04:58:57 PM PDT 24
Peak memory 199872 kb
Host smart-fb83ff2a-d206-4c0f-a48b-942fc276096a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201463284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1201463284
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.770306889
Short name T129
Test name
Test status
Simulation time 494888072 ps
CPU time 3.78 seconds
Started Jul 27 04:58:55 PM PDT 24
Finished Jul 27 04:58:59 PM PDT 24
Peak memory 199832 kb
Host smart-23a0976a-f7bb-463f-b2ab-449d19874871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770306889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.770306889
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2150968748
Short name T623
Test name
Test status
Simulation time 62777470 ps
CPU time 1.57 seconds
Started Jul 27 04:59:09 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 199948 kb
Host smart-4870770b-a415-4211-8591-37f9118e8bbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150968748 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2150968748
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1075365683
Short name T102
Test name
Test status
Simulation time 65913453 ps
CPU time 0.92 seconds
Started Jul 27 04:59:02 PM PDT 24
Finished Jul 27 04:59:03 PM PDT 24
Peak memory 199356 kb
Host smart-d91add17-145e-46f8-992c-8a4e1ca4bf5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075365683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1075365683
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2526130621
Short name T658
Test name
Test status
Simulation time 20612816 ps
CPU time 0.59 seconds
Started Jul 27 04:59:01 PM PDT 24
Finished Jul 27 04:59:02 PM PDT 24
Peak memory 194636 kb
Host smart-dbe9af88-a85e-44d1-b75d-1926b60d445c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526130621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2526130621
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2394418137
Short name T111
Test name
Test status
Simulation time 154797290 ps
CPU time 1.73 seconds
Started Jul 27 04:59:13 PM PDT 24
Finished Jul 27 04:59:15 PM PDT 24
Peak memory 199644 kb
Host smart-09f24661-d6c3-45ce-925f-0f1936dde35d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394418137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2394418137
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1457250285
Short name T557
Test name
Test status
Simulation time 402037150 ps
CPU time 3.88 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 199820 kb
Host smart-a2ff3523-2df6-40c5-a07d-597ba0a60d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457250285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1457250285
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.481486095
Short name T125
Test name
Test status
Simulation time 264614615 ps
CPU time 4.34 seconds
Started Jul 27 04:59:09 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 199852 kb
Host smart-cfa49528-c6fa-47fc-b5ad-70cd74bb45e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481486095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.481486095
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1133967059
Short name T646
Test name
Test status
Simulation time 449545159 ps
CPU time 5.74 seconds
Started Jul 27 04:58:49 PM PDT 24
Finished Jul 27 04:58:55 PM PDT 24
Peak memory 199828 kb
Host smart-0cba1dc4-b062-4166-a777-5875addae96d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133967059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1133967059
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1889986749
Short name T639
Test name
Test status
Simulation time 383302229 ps
CPU time 5.5 seconds
Started Jul 27 04:58:45 PM PDT 24
Finished Jul 27 04:58:50 PM PDT 24
Peak memory 199076 kb
Host smart-c7c6c9a1-4396-486e-a4e6-41177ab8e883
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889986749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1889986749
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1000850806
Short name T108
Test name
Test status
Simulation time 81042298 ps
CPU time 0.97 seconds
Started Jul 27 04:58:55 PM PDT 24
Finished Jul 27 04:58:56 PM PDT 24
Peak memory 199640 kb
Host smart-aa0c149e-dad4-420e-b780-de1d76770fcb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000850806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1000850806
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1921984336
Short name T588
Test name
Test status
Simulation time 84547006 ps
CPU time 1.46 seconds
Started Jul 27 04:58:39 PM PDT 24
Finished Jul 27 04:58:41 PM PDT 24
Peak memory 200092 kb
Host smart-95b37dee-309c-4ae6-8ba2-0c5037f5bcfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921984336 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1921984336
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1733959912
Short name T607
Test name
Test status
Simulation time 29099175 ps
CPU time 0.81 seconds
Started Jul 27 04:58:44 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 199388 kb
Host smart-0435f2ae-e2ed-4026-9098-7fcfabf4b3cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733959912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1733959912
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.452991955
Short name T591
Test name
Test status
Simulation time 24048049 ps
CPU time 0.58 seconds
Started Jul 27 04:58:45 PM PDT 24
Finished Jul 27 04:58:46 PM PDT 24
Peak memory 194744 kb
Host smart-16f0503e-a531-4b17-8b38-22bfb06e5259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452991955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.452991955
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3964803618
Short name T634
Test name
Test status
Simulation time 590766450 ps
CPU time 2.38 seconds
Started Jul 27 04:58:43 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 199832 kb
Host smart-fb2a8cb9-31ba-438b-8934-e566b0c7fb40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964803618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3964803618
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2464325640
Short name T628
Test name
Test status
Simulation time 115992175 ps
CPU time 1.59 seconds
Started Jul 27 04:58:42 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 199752 kb
Host smart-d606135a-2f15-4d22-a6a3-ba6a982b1924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464325640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2464325640
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3597562415
Short name T126
Test name
Test status
Simulation time 807116101 ps
CPU time 3.18 seconds
Started Jul 27 04:59:25 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 199916 kb
Host smart-09f4705a-8c89-4c97-85af-c1eb06cf8e89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597562415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3597562415
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2692151109
Short name T648
Test name
Test status
Simulation time 24195565 ps
CPU time 0.59 seconds
Started Jul 27 04:59:04 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 194688 kb
Host smart-ddce98d7-6bc8-4650-a814-d32068318765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692151109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2692151109
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3714169034
Short name T568
Test name
Test status
Simulation time 16545535 ps
CPU time 0.57 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:19 PM PDT 24
Peak memory 194744 kb
Host smart-e77dc48c-5017-4800-8c46-3dcd7559d692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714169034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3714169034
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3320904541
Short name T564
Test name
Test status
Simulation time 11164635 ps
CPU time 0.61 seconds
Started Jul 27 04:59:19 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 194808 kb
Host smart-f69d71be-e0a6-45a5-a17c-cd8ae6c244bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320904541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3320904541
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4130017399
Short name T561
Test name
Test status
Simulation time 44602463 ps
CPU time 0.63 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 194868 kb
Host smart-c6691af3-17e6-4495-bdeb-7a918da005bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130017399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4130017399
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2706349838
Short name T586
Test name
Test status
Simulation time 16996904 ps
CPU time 0.61 seconds
Started Jul 27 04:59:01 PM PDT 24
Finished Jul 27 04:59:01 PM PDT 24
Peak memory 194796 kb
Host smart-6ad189f5-6b5a-4255-8ba3-f04694be3f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706349838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2706349838
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2445860114
Short name T616
Test name
Test status
Simulation time 29673285 ps
CPU time 0.6 seconds
Started Jul 27 04:59:12 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 194784 kb
Host smart-a35643f5-f1be-470c-80e0-15598fdcab74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445860114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2445860114
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3774747827
Short name T544
Test name
Test status
Simulation time 35946969 ps
CPU time 0.56 seconds
Started Jul 27 04:59:12 PM PDT 24
Finished Jul 27 04:59:12 PM PDT 24
Peak memory 194684 kb
Host smart-603c3fb0-b166-422c-9c27-8be5940651d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774747827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3774747827
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3756087428
Short name T534
Test name
Test status
Simulation time 122797529 ps
CPU time 0.59 seconds
Started Jul 27 04:59:27 PM PDT 24
Finished Jul 27 04:59:28 PM PDT 24
Peak memory 194768 kb
Host smart-6ead48e8-7258-4527-a8d1-10a9df3469c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756087428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3756087428
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3229479922
Short name T617
Test name
Test status
Simulation time 18170248 ps
CPU time 0.57 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:00 PM PDT 24
Peak memory 194780 kb
Host smart-40f2ee97-39c6-4569-89fa-adf980fc4611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229479922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3229479922
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1814531007
Short name T539
Test name
Test status
Simulation time 12493089 ps
CPU time 0.6 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 194732 kb
Host smart-ba09c3cb-255a-4a1c-8a55-e613df971e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814531007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1814531007
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3934470086
Short name T543
Test name
Test status
Simulation time 1357078829 ps
CPU time 5.69 seconds
Started Jul 27 04:58:53 PM PDT 24
Finished Jul 27 04:58:59 PM PDT 24
Peak memory 199744 kb
Host smart-ea0f3b0c-c3d8-4acf-9319-d6a62b5210e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934470086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3934470086
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1071437004
Short name T104
Test name
Test status
Simulation time 543507994 ps
CPU time 5.79 seconds
Started Jul 27 04:58:45 PM PDT 24
Finished Jul 27 04:58:51 PM PDT 24
Peak memory 199848 kb
Host smart-2efb9613-fce3-4934-9981-b9917f932d30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071437004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1071437004
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2147676163
Short name T107
Test name
Test status
Simulation time 50116917 ps
CPU time 1 seconds
Started Jul 27 04:58:44 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 199196 kb
Host smart-65c3bd89-9780-4235-820b-17ccd37041ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147676163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2147676163
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.861103164
Short name T547
Test name
Test status
Simulation time 157455524 ps
CPU time 1.17 seconds
Started Jul 27 04:58:44 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 199624 kb
Host smart-bf719e91-2673-4613-8326-e6a233fb4072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861103164 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.861103164
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.358352308
Short name T619
Test name
Test status
Simulation time 55232357 ps
CPU time 0.57 seconds
Started Jul 27 04:58:43 PM PDT 24
Finished Jul 27 04:58:44 PM PDT 24
Peak memory 194736 kb
Host smart-59979248-be1c-44b8-bd14-95566fb40e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358352308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.358352308
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.298605956
Short name T576
Test name
Test status
Simulation time 198997749 ps
CPU time 1.66 seconds
Started Jul 27 04:58:50 PM PDT 24
Finished Jul 27 04:58:52 PM PDT 24
Peak memory 199744 kb
Host smart-24fee230-2cdd-4dc0-8d8d-76ee8876c592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298605956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.298605956
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2898831812
Short name T638
Test name
Test status
Simulation time 158898458 ps
CPU time 1.91 seconds
Started Jul 27 04:59:15 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 199796 kb
Host smart-9a0e6132-dfda-4e8e-8a24-6d673748ac16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898831812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2898831812
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1398150628
Short name T627
Test name
Test status
Simulation time 99734337 ps
CPU time 1.73 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:58:58 PM PDT 24
Peak memory 199876 kb
Host smart-dd2dd523-d47d-4d4c-98e0-a7ca3fba07f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398150628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1398150628
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3854439679
Short name T584
Test name
Test status
Simulation time 36111637 ps
CPU time 0.56 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 194672 kb
Host smart-4ae3ed91-cd55-49cb-93f9-048ae067f1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854439679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3854439679
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2386145290
Short name T655
Test name
Test status
Simulation time 19143461 ps
CPU time 0.62 seconds
Started Jul 27 04:59:34 PM PDT 24
Finished Jul 27 04:59:34 PM PDT 24
Peak memory 194752 kb
Host smart-f3bfb820-76ab-4913-a235-440e0b1be243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386145290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2386145290
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.412861440
Short name T553
Test name
Test status
Simulation time 45533156 ps
CPU time 0.6 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:24 PM PDT 24
Peak memory 194796 kb
Host smart-fa687ba7-4169-463f-8364-266802ec1365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412861440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.412861440
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.75621242
Short name T618
Test name
Test status
Simulation time 54629176 ps
CPU time 0.69 seconds
Started Jul 27 04:59:14 PM PDT 24
Finished Jul 27 04:59:15 PM PDT 24
Peak memory 194752 kb
Host smart-bc1dab41-7930-4957-b6ad-61ce26750f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75621242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.75621242
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3384994958
Short name T589
Test name
Test status
Simulation time 57575778 ps
CPU time 0.58 seconds
Started Jul 27 04:59:05 PM PDT 24
Finished Jul 27 04:59:05 PM PDT 24
Peak memory 194720 kb
Host smart-61aeb9e2-8d19-4717-8fc6-e79cad319357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384994958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3384994958
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.783581675
Short name T560
Test name
Test status
Simulation time 37078708 ps
CPU time 0.58 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:00 PM PDT 24
Peak memory 194824 kb
Host smart-360fe5c0-571d-472b-a6ea-97bba7a88f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783581675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.783581675
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2667577845
Short name T569
Test name
Test status
Simulation time 29045956 ps
CPU time 0.59 seconds
Started Jul 27 04:59:05 PM PDT 24
Finished Jul 27 04:59:06 PM PDT 24
Peak memory 194760 kb
Host smart-63de282f-8951-4bed-ab1b-b7c767a54311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667577845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2667577845
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3752460086
Short name T555
Test name
Test status
Simulation time 34343732 ps
CPU time 0.59 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:16 PM PDT 24
Peak memory 194744 kb
Host smart-21813089-e096-40dd-b3fc-0d9c3362ffe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752460086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3752460086
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2618535850
Short name T551
Test name
Test status
Simulation time 20472169 ps
CPU time 0.59 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:22 PM PDT 24
Peak memory 194736 kb
Host smart-7bd59c44-0ed7-4753-8d86-c0f02c163d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618535850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2618535850
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2869898630
Short name T622
Test name
Test status
Simulation time 17348693 ps
CPU time 0.64 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:12 PM PDT 24
Peak memory 194740 kb
Host smart-334dde95-fedb-4c75-93d2-4e7058ddb05a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869898630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2869898630
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.712330135
Short name T565
Test name
Test status
Simulation time 2689795156 ps
CPU time 6.04 seconds
Started Jul 27 04:59:00 PM PDT 24
Finished Jul 27 04:59:06 PM PDT 24
Peak memory 199892 kb
Host smart-78ffe5fa-5d55-4630-adbb-7fa150168def
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712330135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.712330135
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1808354367
Short name T103
Test name
Test status
Simulation time 2109140485 ps
CPU time 15.62 seconds
Started Jul 27 04:58:54 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 199912 kb
Host smart-04636ca0-3235-4155-8641-08dfb72ccd51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808354367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1808354367
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1861733210
Short name T100
Test name
Test status
Simulation time 27998443 ps
CPU time 0.83 seconds
Started Jul 27 04:58:50 PM PDT 24
Finished Jul 27 04:58:51 PM PDT 24
Peak memory 199024 kb
Host smart-25bac5bf-43ed-4e56-aef1-c947996d9099
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861733210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1861733210
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2087529290
Short name T556
Test name
Test status
Simulation time 108749451 ps
CPU time 2.44 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 199852 kb
Host smart-319acfbc-3b02-4a95-bd45-b6e72b5d1e21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087529290 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2087529290
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.579949149
Short name T636
Test name
Test status
Simulation time 15212361 ps
CPU time 0.67 seconds
Started Jul 27 04:59:04 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 197452 kb
Host smart-3137bb96-d5b0-4149-bf01-d15be889b5df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579949149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.579949149
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.245141634
Short name T644
Test name
Test status
Simulation time 32415906 ps
CPU time 0.57 seconds
Started Jul 27 04:58:47 PM PDT 24
Finished Jul 27 04:58:48 PM PDT 24
Peak memory 194796 kb
Host smart-b5eeb328-0e13-4cce-b388-e2139fc5a1e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245141634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.245141634
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.873888600
Short name T573
Test name
Test status
Simulation time 24395778 ps
CPU time 1.05 seconds
Started Jul 27 04:58:54 PM PDT 24
Finished Jul 27 04:58:55 PM PDT 24
Peak memory 199872 kb
Host smart-0793db2b-575e-4f49-8ecd-d17ec0af6c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873888600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.873888600
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1652709217
Short name T548
Test name
Test status
Simulation time 133260264 ps
CPU time 1.78 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:08 PM PDT 24
Peak memory 199828 kb
Host smart-eb6d13d5-ab52-411d-9a21-806beb2ec578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652709217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1652709217
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.315590980
Short name T642
Test name
Test status
Simulation time 888284196 ps
CPU time 4.26 seconds
Started Jul 27 04:58:49 PM PDT 24
Finished Jul 27 04:58:54 PM PDT 24
Peak memory 199824 kb
Host smart-1eed2a71-b6b7-45b6-ae4e-c44071ee6268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315590980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.315590980
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2914733005
Short name T541
Test name
Test status
Simulation time 115582322 ps
CPU time 0.59 seconds
Started Jul 27 04:59:11 PM PDT 24
Finished Jul 27 04:59:11 PM PDT 24
Peak memory 194696 kb
Host smart-5962eaf9-b9a2-4ab2-8a04-2be8401666fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914733005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2914733005
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1427776608
Short name T595
Test name
Test status
Simulation time 16917780 ps
CPU time 0.62 seconds
Started Jul 27 04:59:05 PM PDT 24
Finished Jul 27 04:59:06 PM PDT 24
Peak memory 194736 kb
Host smart-b5395fe8-311d-4d48-b4cb-054f8af777af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427776608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1427776608
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4245683323
Short name T626
Test name
Test status
Simulation time 13898980 ps
CPU time 0.61 seconds
Started Jul 27 04:59:09 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 194760 kb
Host smart-69143c4c-99f6-4b5d-b42b-ac7e0336a3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245683323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4245683323
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.817760429
Short name T604
Test name
Test status
Simulation time 36826340 ps
CPU time 0.59 seconds
Started Jul 27 04:59:14 PM PDT 24
Finished Jul 27 04:59:15 PM PDT 24
Peak memory 194640 kb
Host smart-a75c4461-b94e-45da-91a1-c8158c8889e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817760429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.817760429
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2707675494
Short name T594
Test name
Test status
Simulation time 48178181 ps
CPU time 0.58 seconds
Started Jul 27 04:59:03 PM PDT 24
Finished Jul 27 04:59:04 PM PDT 24
Peak memory 194632 kb
Host smart-9b63fe33-e96b-4edc-b398-fd4d810527f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707675494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2707675494
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.962170585
Short name T602
Test name
Test status
Simulation time 11128229 ps
CPU time 0.63 seconds
Started Jul 27 04:59:10 PM PDT 24
Finished Jul 27 04:59:11 PM PDT 24
Peak memory 194776 kb
Host smart-951cb5e7-d135-4b16-a971-0528fcda0565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962170585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.962170585
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1629365597
Short name T549
Test name
Test status
Simulation time 11685849 ps
CPU time 0.58 seconds
Started Jul 27 04:59:16 PM PDT 24
Finished Jul 27 04:59:17 PM PDT 24
Peak memory 194644 kb
Host smart-9de61e09-0d73-4d24-a2dd-1506237d9b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629365597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1629365597
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2411900899
Short name T614
Test name
Test status
Simulation time 23323313 ps
CPU time 0.61 seconds
Started Jul 27 04:59:23 PM PDT 24
Finished Jul 27 04:59:23 PM PDT 24
Peak memory 194752 kb
Host smart-38f9a3cb-eac4-4d86-93ed-32c917cad1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411900899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2411900899
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1187355542
Short name T601
Test name
Test status
Simulation time 21038719 ps
CPU time 0.57 seconds
Started Jul 27 04:59:14 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 194732 kb
Host smart-bf3371b4-9146-4eb1-b6ad-8c2c476e183a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187355542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1187355542
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.950741887
Short name T611
Test name
Test status
Simulation time 100023233 ps
CPU time 0.57 seconds
Started Jul 27 04:59:21 PM PDT 24
Finished Jul 27 04:59:21 PM PDT 24
Peak memory 194668 kb
Host smart-3f3ff760-9134-47be-97cd-caf3ae205acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950741887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.950741887
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2291473369
Short name T633
Test name
Test status
Simulation time 42624315 ps
CPU time 2.6 seconds
Started Jul 27 04:59:05 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 199764 kb
Host smart-feae5dc3-9184-4a12-8dde-aa8e3c87322e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291473369 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2291473369
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1240682492
Short name T106
Test name
Test status
Simulation time 124023490 ps
CPU time 0.91 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 199624 kb
Host smart-9dda5ca0-7a7d-45d3-b083-dbb85f097c4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240682492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1240682492
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2235759509
Short name T537
Test name
Test status
Simulation time 29882357 ps
CPU time 0.57 seconds
Started Jul 27 04:58:45 PM PDT 24
Finished Jul 27 04:58:46 PM PDT 24
Peak memory 194788 kb
Host smart-fa0cd5c2-fb3d-4f9a-8cf5-4a366c35317a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235759509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2235759509
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2180770002
Short name T657
Test name
Test status
Simulation time 44781751 ps
CPU time 1.06 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:58:58 PM PDT 24
Peak memory 199624 kb
Host smart-4dff0189-aa7c-4b54-87d8-8278d995ce0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180770002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2180770002
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.169695406
Short name T567
Test name
Test status
Simulation time 143745653 ps
CPU time 3.08 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:03 PM PDT 24
Peak memory 199824 kb
Host smart-096cfd5f-6b61-4f3e-a7e3-ba28fceb7db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169695406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.169695406
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4256162896
Short name T651
Test name
Test status
Simulation time 603993390 ps
CPU time 3.16 seconds
Started Jul 27 04:58:56 PM PDT 24
Finished Jul 27 04:58:59 PM PDT 24
Peak memory 199836 kb
Host smart-791a3e67-7d9a-403f-81d7-bced7e5323c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256162896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.4256162896
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4011562993
Short name T552
Test name
Test status
Simulation time 45535943 ps
CPU time 2.94 seconds
Started Jul 27 04:59:10 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 208044 kb
Host smart-06fc062f-8693-4415-a26d-679e5a479acb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011562993 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4011562993
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4151686079
Short name T582
Test name
Test status
Simulation time 17250106 ps
CPU time 0.69 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:58:58 PM PDT 24
Peak memory 197740 kb
Host smart-fc47582e-d7aa-488b-b0d2-c94c4d3cf1bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151686079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4151686079
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3727612106
Short name T579
Test name
Test status
Simulation time 16084678 ps
CPU time 0.66 seconds
Started Jul 27 04:58:59 PM PDT 24
Finished Jul 27 04:59:00 PM PDT 24
Peak memory 194672 kb
Host smart-8ceda0b2-0b0e-4335-9403-d7f9ca86e76e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727612106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3727612106
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2182891923
Short name T641
Test name
Test status
Simulation time 241389183 ps
CPU time 1.57 seconds
Started Jul 27 04:58:57 PM PDT 24
Finished Jul 27 04:58:59 PM PDT 24
Peak memory 199664 kb
Host smart-51192f52-b6f2-4e9d-941f-2309bec1a8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182891923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2182891923
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4053996936
Short name T599
Test name
Test status
Simulation time 263176104 ps
CPU time 2.91 seconds
Started Jul 27 04:59:07 PM PDT 24
Finished Jul 27 04:59:10 PM PDT 24
Peak memory 199900 kb
Host smart-9c7fefa0-4483-4a72-b2cc-ed4104db4d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053996936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4053996936
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.762716481
Short name T122
Test name
Test status
Simulation time 160450962 ps
CPU time 1.7 seconds
Started Jul 27 04:58:54 PM PDT 24
Finished Jul 27 04:58:55 PM PDT 24
Peak memory 199796 kb
Host smart-d91cf324-b301-4458-a8c3-d3590e180712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762716481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.762716481
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.624475876
Short name T635
Test name
Test status
Simulation time 409213728 ps
CPU time 1.76 seconds
Started Jul 27 04:58:43 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 199788 kb
Host smart-79318926-9998-4937-b867-11309cae3ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624475876 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.624475876
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2559793174
Short name T637
Test name
Test status
Simulation time 13530706 ps
CPU time 0.68 seconds
Started Jul 27 04:59:24 PM PDT 24
Finished Jul 27 04:59:25 PM PDT 24
Peak memory 197372 kb
Host smart-27736934-50e3-406d-83c3-3ad0b63c57b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559793174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2559793174
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2537872528
Short name T538
Test name
Test status
Simulation time 47032712 ps
CPU time 0.62 seconds
Started Jul 27 04:59:06 PM PDT 24
Finished Jul 27 04:59:07 PM PDT 24
Peak memory 194736 kb
Host smart-cd08e5c6-3c94-44be-ade6-8167897871ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537872528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2537872528
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.604858741
Short name T615
Test name
Test status
Simulation time 182425262 ps
CPU time 1.16 seconds
Started Jul 27 04:59:19 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 199892 kb
Host smart-79d64bed-dd2d-4a8a-9d11-0debb2c5e3c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604858741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.604858741
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.371150485
Short name T612
Test name
Test status
Simulation time 2532394526 ps
CPU time 3.5 seconds
Started Jul 27 04:59:17 PM PDT 24
Finished Jul 27 04:59:20 PM PDT 24
Peak memory 199876 kb
Host smart-5635db9b-10ba-4613-a74e-7a07140e2f28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371150485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.371150485
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2153948171
Short name T124
Test name
Test status
Simulation time 409740296 ps
CPU time 3.22 seconds
Started Jul 27 04:58:54 PM PDT 24
Finished Jul 27 04:58:57 PM PDT 24
Peak memory 199776 kb
Host smart-d3b985ff-ef34-4337-9f31-59bbb35ba24b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153948171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2153948171
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1645137647
Short name T570
Test name
Test status
Simulation time 484774973 ps
CPU time 2.99 seconds
Started Jul 27 04:59:14 PM PDT 24
Finished Jul 27 04:59:18 PM PDT 24
Peak memory 216364 kb
Host smart-d325f67f-ac00-451c-8dcd-a5d48fca8c5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645137647 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1645137647
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2894494173
Short name T95
Test name
Test status
Simulation time 21646592 ps
CPU time 0.65 seconds
Started Jul 27 04:58:47 PM PDT 24
Finished Jul 27 04:58:48 PM PDT 24
Peak memory 197340 kb
Host smart-7fb9d1cd-1479-4b6e-a7ce-44d374756f65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894494173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2894494173
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.605429602
Short name T559
Test name
Test status
Simulation time 86025208 ps
CPU time 0.58 seconds
Started Jul 27 04:59:01 PM PDT 24
Finished Jul 27 04:59:02 PM PDT 24
Peak memory 194696 kb
Host smart-d0808cd8-896c-4f4a-9ff7-5b07d3a4274d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605429602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.605429602
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1116958498
Short name T113
Test name
Test status
Simulation time 31938755 ps
CPU time 1.52 seconds
Started Jul 27 04:58:52 PM PDT 24
Finished Jul 27 04:58:54 PM PDT 24
Peak memory 199740 kb
Host smart-140f0dad-29b1-425f-a38d-c2d042c1f8e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116958498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1116958498
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.236946861
Short name T536
Test name
Test status
Simulation time 68496471 ps
CPU time 1.57 seconds
Started Jul 27 04:59:04 PM PDT 24
Finished Jul 27 04:59:06 PM PDT 24
Peak memory 199756 kb
Host smart-14e0aa53-d1bd-4099-b313-2a97b455e2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236946861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.236946861
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2154229719
Short name T598
Test name
Test status
Simulation time 276333904902 ps
CPU time 532.28 seconds
Started Jul 27 04:59:18 PM PDT 24
Finished Jul 27 05:08:11 PM PDT 24
Peak memory 215760 kb
Host smart-1b0c4632-33cb-4235-ad23-9154216591d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154229719 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2154229719
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.57545781
Short name T96
Test name
Test status
Simulation time 16113120 ps
CPU time 0.68 seconds
Started Jul 27 04:58:46 PM PDT 24
Finished Jul 27 04:58:47 PM PDT 24
Peak memory 197708 kb
Host smart-2e622648-a2f8-4a02-a7a2-0867b38e0e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57545781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.57545781
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2904619338
Short name T577
Test name
Test status
Simulation time 39961751 ps
CPU time 0.58 seconds
Started Jul 27 04:58:43 PM PDT 24
Finished Jul 27 04:58:44 PM PDT 24
Peak memory 194760 kb
Host smart-56a80520-fdd3-419a-8abb-ee06251d4e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904619338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2904619338
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1556255138
Short name T654
Test name
Test status
Simulation time 22608696 ps
CPU time 1.07 seconds
Started Jul 27 04:59:02 PM PDT 24
Finished Jul 27 04:59:03 PM PDT 24
Peak memory 199676 kb
Host smart-307f4f19-aa7a-4c82-87eb-ea43f5906e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556255138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1556255138
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1516504552
Short name T649
Test name
Test status
Simulation time 212885799 ps
CPU time 3.73 seconds
Started Jul 27 04:58:43 PM PDT 24
Finished Jul 27 04:58:47 PM PDT 24
Peak memory 199756 kb
Host smart-4cf42dcc-e437-4bf9-bf55-a3df3b88c64e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516504552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1516504552
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3561676727
Short name T324
Test name
Test status
Simulation time 23424857 ps
CPU time 0.59 seconds
Started Jul 27 05:48:45 PM PDT 24
Finished Jul 27 05:48:46 PM PDT 24
Peak memory 195740 kb
Host smart-b8c91d6b-1b87-4c01-b707-2532d3f9c022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561676727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3561676727
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.130258916
Short name T319
Test name
Test status
Simulation time 1156836251 ps
CPU time 64.44 seconds
Started Jul 27 05:48:46 PM PDT 24
Finished Jul 27 05:49:51 PM PDT 24
Peak memory 199628 kb
Host smart-d978c5c7-8907-4137-b1e7-1fc596d1ce2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130258916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.130258916
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3594647564
Short name T446
Test name
Test status
Simulation time 2856248253 ps
CPU time 42.97 seconds
Started Jul 27 05:48:50 PM PDT 24
Finished Jul 27 05:49:33 PM PDT 24
Peak memory 199768 kb
Host smart-87f09ea3-5c55-4ad8-9d63-bafa3f84a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594647564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3594647564
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3054495599
Short name T308
Test name
Test status
Simulation time 58426022695 ps
CPU time 1177.2 seconds
Started Jul 27 05:48:44 PM PDT 24
Finished Jul 27 06:08:22 PM PDT 24
Peak memory 725720 kb
Host smart-2e3bad7c-b7f9-45c6-ace7-87e18a0f1958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054495599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3054495599
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2915698969
Short name T177
Test name
Test status
Simulation time 12613931370 ps
CPU time 72.5 seconds
Started Jul 27 05:48:45 PM PDT 24
Finished Jul 27 05:49:58 PM PDT 24
Peak memory 199788 kb
Host smart-d5bd6b69-306f-4201-b82c-fc1c7f6b0b24
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915698969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2915698969
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.603068942
Short name T231
Test name
Test status
Simulation time 94363421744 ps
CPU time 187.99 seconds
Started Jul 27 05:48:44 PM PDT 24
Finished Jul 27 05:51:52 PM PDT 24
Peak memory 216136 kb
Host smart-1063cf2d-d32a-41c2-8ef0-c66645db506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603068942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.603068942
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.1654286618
Short name T242
Test name
Test status
Simulation time 2049765833 ps
CPU time 8.53 seconds
Started Jul 27 05:48:45 PM PDT 24
Finished Jul 27 05:48:54 PM PDT 24
Peak memory 199708 kb
Host smart-583e0a71-1dc9-4d9a-868c-3f85cc13c7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654286618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1654286618
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3960942005
Short name T465
Test name
Test status
Simulation time 7570154172 ps
CPU time 22.05 seconds
Started Jul 27 05:48:46 PM PDT 24
Finished Jul 27 05:49:08 PM PDT 24
Peak memory 199804 kb
Host smart-ab0c3c07-ee7a-4ec5-8a34-6ece6a6db886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960942005 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3960942005
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.922087096
Short name T61
Test name
Test status
Simulation time 45173740708 ps
CPU time 1815.53 seconds
Started Jul 27 05:48:44 PM PDT 24
Finished Jul 27 06:19:00 PM PDT 24
Peak memory 794152 kb
Host smart-9c179656-e0c0-4d1f-a167-e06949999c67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922087096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.922087096
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3698144506
Short name T367
Test name
Test status
Simulation time 28539065836 ps
CPU time 81.27 seconds
Started Jul 27 05:48:46 PM PDT 24
Finished Jul 27 05:50:07 PM PDT 24
Peak memory 199752 kb
Host smart-0068149b-3911-4a89-8fc2-f01710a19246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3698144506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3698144506
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2517714355
Short name T67
Test name
Test status
Simulation time 16639220555 ps
CPU time 104.71 seconds
Started Jul 27 05:48:47 PM PDT 24
Finished Jul 27 05:50:32 PM PDT 24
Peak memory 199788 kb
Host smart-807d3d05-2b81-4289-9f77-e90b8a39bdeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2517714355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2517714355
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.4123604132
Short name T248
Test name
Test status
Simulation time 2163010924 ps
CPU time 69.68 seconds
Started Jul 27 05:48:45 PM PDT 24
Finished Jul 27 05:49:55 PM PDT 24
Peak memory 199788 kb
Host smart-74ef15d0-1690-4431-9653-ea9923793dce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4123604132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.4123604132
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3147714061
Short name T286
Test name
Test status
Simulation time 56770748199 ps
CPU time 698.88 seconds
Started Jul 27 05:48:46 PM PDT 24
Finished Jul 27 06:00:25 PM PDT 24
Peak memory 199768 kb
Host smart-ab41d608-999c-4c8f-b879-7a6c488e51ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3147714061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3147714061
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2275932759
Short name T469
Test name
Test status
Simulation time 754752388467 ps
CPU time 2505.47 seconds
Started Jul 27 05:48:47 PM PDT 24
Finished Jul 27 06:30:33 PM PDT 24
Peak memory 208012 kb
Host smart-f1a6c316-f2d2-412d-b4db-0baf87b282b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2275932759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2275932759
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3160785424
Short name T364
Test name
Test status
Simulation time 5133219400 ps
CPU time 117.19 seconds
Started Jul 27 05:48:44 PM PDT 24
Finished Jul 27 05:50:42 PM PDT 24
Peak memory 199704 kb
Host smart-4ec207ef-6d69-4307-abb7-cfbafec720bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160785424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3160785424
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3882562130
Short name T414
Test name
Test status
Simulation time 69623491 ps
CPU time 0.62 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:48:56 PM PDT 24
Peak memory 195692 kb
Host smart-5ee76065-0efa-4eaa-a270-5bc42892ddb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882562130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3882562130
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.91921846
Short name T296
Test name
Test status
Simulation time 960526448 ps
CPU time 27.48 seconds
Started Jul 27 05:48:46 PM PDT 24
Finished Jul 27 05:49:14 PM PDT 24
Peak memory 199696 kb
Host smart-52c27acc-6da5-4c7c-96e3-634927943067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91921846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.91921846
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3291587056
Short name T50
Test name
Test status
Simulation time 1273415166 ps
CPU time 63.35 seconds
Started Jul 27 05:48:51 PM PDT 24
Finished Jul 27 05:49:55 PM PDT 24
Peak memory 199680 kb
Host smart-c11776a6-866e-41c8-9dcd-7852672f0e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291587056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3291587056
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1368075891
Short name T191
Test name
Test status
Simulation time 18829487222 ps
CPU time 751.88 seconds
Started Jul 27 05:48:44 PM PDT 24
Finished Jul 27 06:01:16 PM PDT 24
Peak memory 747840 kb
Host smart-e797726e-d635-481a-be0d-aebf6509b53c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368075891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1368075891
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2563945058
Short name T175
Test name
Test status
Simulation time 6380230979 ps
CPU time 110.33 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:50:42 PM PDT 24
Peak memory 199732 kb
Host smart-05444ef3-2681-457d-8a2d-39e756c10339
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563945058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2563945058
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3247572898
Short name T283
Test name
Test status
Simulation time 6277948519 ps
CPU time 37.82 seconds
Started Jul 27 05:48:47 PM PDT 24
Finished Jul 27 05:49:24 PM PDT 24
Peak memory 199780 kb
Host smart-8f518525-b67c-4446-9b2c-e50d884df274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247572898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3247572898
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4001551636
Short name T44
Test name
Test status
Simulation time 62148153 ps
CPU time 0.88 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:48:53 PM PDT 24
Peak memory 218272 kb
Host smart-3895e09b-2cad-409f-b75e-f93f1fe7382f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001551636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4001551636
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2853029536
Short name T325
Test name
Test status
Simulation time 1154753701 ps
CPU time 12.82 seconds
Started Jul 27 05:48:47 PM PDT 24
Finished Jul 27 05:49:00 PM PDT 24
Peak memory 199780 kb
Host smart-4f34ca49-491d-4673-9855-845f05574564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853029536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2853029536
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2410393083
Short name T91
Test name
Test status
Simulation time 446632328420 ps
CPU time 664.37 seconds
Started Jul 27 05:48:56 PM PDT 24
Finished Jul 27 06:00:00 PM PDT 24
Peak memory 199764 kb
Host smart-c8ca133b-053f-4e1c-ab73-9653829c12fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410393083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2410393083
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.2991914387
Short name T483
Test name
Test status
Simulation time 6407044425 ps
CPU time 63.62 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:49:57 PM PDT 24
Peak memory 199728 kb
Host smart-9cc31361-d5cb-4d69-97ee-010dedb1ee5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2991914387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2991914387
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1137421863
Short name T470
Test name
Test status
Simulation time 18007717557 ps
CPU time 109.11 seconds
Started Jul 27 05:48:51 PM PDT 24
Finished Jul 27 05:50:40 PM PDT 24
Peak memory 199720 kb
Host smart-68ec2d10-e197-47ae-8f5c-5046752a1539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1137421863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1137421863
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2844666920
Short name T291
Test name
Test status
Simulation time 4125159469 ps
CPU time 68.32 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:50:03 PM PDT 24
Peak memory 199768 kb
Host smart-be92b41e-e0ce-4bc3-b054-e366001e8721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2844666920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2844666920
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3790197076
Short name T381
Test name
Test status
Simulation time 49511655418 ps
CPU time 711.09 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 06:00:44 PM PDT 24
Peak memory 199752 kb
Host smart-d65361c5-e1c5-40ec-81ed-d9b08843626c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3790197076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3790197076
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2687606622
Short name T271
Test name
Test status
Simulation time 550742784168 ps
CPU time 2477.36 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 06:30:10 PM PDT 24
Peak memory 215776 kb
Host smart-3c1989a6-dc8e-4ca5-943d-2bc265b2e3b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2687606622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2687606622
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2475598884
Short name T393
Test name
Test status
Simulation time 934199663048 ps
CPU time 2517.17 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 06:30:51 PM PDT 24
Peak memory 215696 kb
Host smart-e1b6ae66-59d3-4be7-98b1-55939577af3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2475598884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2475598884
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2848730311
Short name T120
Test name
Test status
Simulation time 758795328 ps
CPU time 45.55 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 199704 kb
Host smart-764c0c79-2fa3-410b-91a3-bb9e681ee59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848730311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2848730311
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.125581110
Short name T200
Test name
Test status
Simulation time 42071757 ps
CPU time 0.62 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:49:04 PM PDT 24
Peak memory 195748 kb
Host smart-d0015e0f-1553-4bf2-8586-94ca6fd2466c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125581110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.125581110
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2910579001
Short name T303
Test name
Test status
Simulation time 4738958151 ps
CPU time 16.9 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 05:49:25 PM PDT 24
Peak memory 199596 kb
Host smart-953dec70-f294-49e6-9947-a01e7421612a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910579001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2910579001
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4215541242
Short name T225
Test name
Test status
Simulation time 767911497 ps
CPU time 21.44 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:49:24 PM PDT 24
Peak memory 199776 kb
Host smart-0d944711-e684-4b30-b18b-06e4c84f5a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215541242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4215541242
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1426924173
Short name T374
Test name
Test status
Simulation time 3847341925 ps
CPU time 669.83 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 06:00:18 PM PDT 24
Peak memory 709444 kb
Host smart-2db812a9-8531-48f2-979e-4c1d3ca6b6d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426924173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1426924173
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3696555237
Short name T304
Test name
Test status
Simulation time 38196997565 ps
CPU time 160.8 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 05:51:49 PM PDT 24
Peak memory 199700 kb
Host smart-4f8b75c4-28d0-4c0f-9876-d577fc524db4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696555237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3696555237
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1064117207
Short name T52
Test name
Test status
Simulation time 3123995960 ps
CPU time 40.05 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:45 PM PDT 24
Peak memory 199764 kb
Host smart-f5c1a7b1-119d-4bc9-8b88-6b39c060d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064117207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1064117207
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.896285587
Short name T356
Test name
Test status
Simulation time 1714200349 ps
CPU time 5.99 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:49:08 PM PDT 24
Peak memory 199424 kb
Host smart-8ba965e6-708c-4d86-a666-90c7768028d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896285587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.896285587
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.880559048
Short name T300
Test name
Test status
Simulation time 62284020501 ps
CPU time 1485.29 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 06:13:49 PM PDT 24
Peak memory 677964 kb
Host smart-66d3c7b1-6600-4682-8826-f9a40526d4d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880559048 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.880559048
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1522435456
Short name T301
Test name
Test status
Simulation time 111896537 ps
CPU time 4.17 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 05:49:13 PM PDT 24
Peak memory 199572 kb
Host smart-3208faf9-52bd-480c-a272-51cf8a1d894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522435456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1522435456
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3095759406
Short name T204
Test name
Test status
Simulation time 46712285 ps
CPU time 0.64 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:49:17 PM PDT 24
Peak memory 195684 kb
Host smart-09db987f-8634-4432-9e10-5aec794328e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095759406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3095759406
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.631326026
Short name T35
Test name
Test status
Simulation time 1375100654 ps
CPU time 77.16 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:50:34 PM PDT 24
Peak memory 199588 kb
Host smart-6653070b-f6bb-41fe-8a49-25ce08bc4824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631326026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.631326026
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.613494634
Short name T332
Test name
Test status
Simulation time 3545355527 ps
CPU time 24.99 seconds
Started Jul 27 05:49:07 PM PDT 24
Finished Jul 27 05:49:32 PM PDT 24
Peak memory 199736 kb
Host smart-4112b084-0b37-4abd-b2da-bb44f3186d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613494634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.613494634
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2729799993
Short name T220
Test name
Test status
Simulation time 16419786149 ps
CPU time 912.5 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 06:04:29 PM PDT 24
Peak memory 744264 kb
Host smart-ecfcb578-18d9-4070-ab84-d8accce8c3d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729799993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2729799993
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1732134586
Short name T372
Test name
Test status
Simulation time 3717074663 ps
CPU time 61.7 seconds
Started Jul 27 05:49:06 PM PDT 24
Finished Jul 27 05:50:08 PM PDT 24
Peak memory 199748 kb
Host smart-5c8cbb6e-2615-4281-894d-7d32aa40937b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732134586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1732134586
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1696709283
Short name T153
Test name
Test status
Simulation time 171722107353 ps
CPU time 174.28 seconds
Started Jul 27 05:49:12 PM PDT 24
Finished Jul 27 05:52:06 PM PDT 24
Peak memory 199820 kb
Host smart-567b5ec4-1891-4a1b-919f-87b89ed369ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696709283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1696709283
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3317066015
Short name T307
Test name
Test status
Simulation time 625022245 ps
CPU time 14.35 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 05:49:28 PM PDT 24
Peak memory 199736 kb
Host smart-8ed2642d-b936-41f1-a91b-554e5b7a3a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317066015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3317066015
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1975915630
Short name T531
Test name
Test status
Simulation time 64297862599 ps
CPU time 157.9 seconds
Started Jul 27 05:49:21 PM PDT 24
Finished Jul 27 05:51:59 PM PDT 24
Peak memory 199732 kb
Host smart-6e17afd2-87fd-4dab-b2f5-afbbfc01247f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975915630 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1975915630
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1434520984
Short name T513
Test name
Test status
Simulation time 1147606543 ps
CPU time 56.43 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:50:13 PM PDT 24
Peak memory 199720 kb
Host smart-c257e813-fe4d-4b70-a86a-6c023100d28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434520984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1434520984
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4173467745
Short name T439
Test name
Test status
Simulation time 13598989 ps
CPU time 0.57 seconds
Started Jul 27 05:49:23 PM PDT 24
Finished Jul 27 05:49:24 PM PDT 24
Peak memory 195336 kb
Host smart-aad1ae32-93d0-46ff-bd76-afaf6e2ea26c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173467745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4173467745
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.904531313
Short name T474
Test name
Test status
Simulation time 659105403 ps
CPU time 38.92 seconds
Started Jul 27 05:49:06 PM PDT 24
Finished Jul 27 05:49:45 PM PDT 24
Peak memory 199736 kb
Host smart-b5065977-3a8a-4164-8143-31e400257507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=904531313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.904531313
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1806922670
Short name T270
Test name
Test status
Simulation time 1357806487 ps
CPU time 17.96 seconds
Started Jul 27 05:49:06 PM PDT 24
Finished Jul 27 05:49:24 PM PDT 24
Peak memory 199660 kb
Host smart-e67c2859-2f8c-4f78-8a3f-c1ff179052ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806922670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1806922670
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.886704937
Short name T447
Test name
Test status
Simulation time 6900621169 ps
CPU time 1457.6 seconds
Started Jul 27 05:49:07 PM PDT 24
Finished Jul 27 06:13:25 PM PDT 24
Peak memory 737640 kb
Host smart-6afa5855-7033-45ed-b278-21bf970741d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886704937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.886704937
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1790961719
Short name T519
Test name
Test status
Simulation time 2694300133 ps
CPU time 25.56 seconds
Started Jul 27 05:49:10 PM PDT 24
Finished Jul 27 05:49:36 PM PDT 24
Peak memory 199756 kb
Host smart-1b8ce95b-3545-4549-b573-3eecccf8bd56
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790961719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1790961719
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1777923177
Short name T386
Test name
Test status
Simulation time 5237841633 ps
CPU time 65.98 seconds
Started Jul 27 05:49:20 PM PDT 24
Finished Jul 27 05:50:27 PM PDT 24
Peak memory 199784 kb
Host smart-29ef3387-217e-4191-91bf-a105036b17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777923177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1777923177
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.4263410217
Short name T292
Test name
Test status
Simulation time 600040420 ps
CPU time 7.38 seconds
Started Jul 27 05:49:23 PM PDT 24
Finished Jul 27 05:49:31 PM PDT 24
Peak memory 199768 kb
Host smart-06c0e76a-38b0-4b77-8d66-fb9fe26d39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263410217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4263410217
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3206967739
Short name T407
Test name
Test status
Simulation time 11567235699 ps
CPU time 202.37 seconds
Started Jul 27 05:49:11 PM PDT 24
Finished Jul 27 05:52:33 PM PDT 24
Peak memory 199744 kb
Host smart-199c3bfc-a74f-4916-9607-df1f3a4b9204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206967739 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3206967739
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.532971027
Short name T23
Test name
Test status
Simulation time 33412558295 ps
CPU time 153.14 seconds
Started Jul 27 05:49:06 PM PDT 24
Finished Jul 27 05:51:40 PM PDT 24
Peak memory 199744 kb
Host smart-137bc949-bcf0-4ee7-914c-077b5cffd090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532971027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.532971027
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1739754963
Short name T287
Test name
Test status
Simulation time 187381673 ps
CPU time 0.57 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 05:49:08 PM PDT 24
Peak memory 195684 kb
Host smart-9f0b6722-059e-449b-b7b8-a99061e3295a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739754963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1739754963
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.507734219
Short name T422
Test name
Test status
Simulation time 1095541845 ps
CPU time 66.9 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:50:23 PM PDT 24
Peak memory 199644 kb
Host smart-1dddacd1-5cfc-4b22-9ebe-1b40f9eafeed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507734219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.507734219
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.594162804
Short name T171
Test name
Test status
Simulation time 103636736 ps
CPU time 5.68 seconds
Started Jul 27 05:49:09 PM PDT 24
Finished Jul 27 05:49:15 PM PDT 24
Peak memory 199732 kb
Host smart-d297557d-8831-4c07-82cb-ffb4e37150e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594162804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.594162804
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4122393337
Short name T462
Test name
Test status
Simulation time 23317188881 ps
CPU time 1000.65 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 06:05:55 PM PDT 24
Peak memory 661568 kb
Host smart-e0a1e764-2a7a-4cf2-b092-7256212385e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122393337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4122393337
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2180162972
Short name T86
Test name
Test status
Simulation time 12992307419 ps
CPU time 45.58 seconds
Started Jul 27 05:49:32 PM PDT 24
Finished Jul 27 05:50:18 PM PDT 24
Peak memory 199796 kb
Host smart-38dae7b8-5369-47a6-9112-cb921d3e8518
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180162972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2180162972
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3748708093
Short name T310
Test name
Test status
Simulation time 7887120586 ps
CPU time 88.86 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:50:56 PM PDT 24
Peak memory 216088 kb
Host smart-51f493c5-8cbc-4f07-abba-e5d88755fba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748708093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3748708093
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2915178626
Short name T532
Test name
Test status
Simulation time 5678231093 ps
CPU time 7.6 seconds
Started Jul 27 05:49:12 PM PDT 24
Finished Jul 27 05:49:20 PM PDT 24
Peak memory 199708 kb
Host smart-d13e5297-4f0f-40a2-bdf8-0187fd468096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915178626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2915178626
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2638904536
Short name T339
Test name
Test status
Simulation time 104511982710 ps
CPU time 506.01 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:57:48 PM PDT 24
Peak memory 317936 kb
Host smart-2a4333b2-e4d3-4793-8f2f-a31c1e04e217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638904536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2638904536
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1245729920
Short name T406
Test name
Test status
Simulation time 7080610654 ps
CPU time 130.63 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:51:26 PM PDT 24
Peak memory 199724 kb
Host smart-468831a7-d86e-4481-9e37-7cc0e63094de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245729920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1245729920
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1173114016
Short name T227
Test name
Test status
Simulation time 122403382 ps
CPU time 0.6 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 05:49:09 PM PDT 24
Peak memory 196392 kb
Host smart-39aa5e95-c7cb-4846-8da2-c7dd903fc583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173114016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1173114016
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3306680636
Short name T19
Test name
Test status
Simulation time 1262103586 ps
CPU time 74.95 seconds
Started Jul 27 05:49:32 PM PDT 24
Finished Jul 27 05:50:47 PM PDT 24
Peak memory 199772 kb
Host smart-1ab4b0ca-172c-4136-8240-e2907fded47f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306680636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3306680636
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3166547342
Short name T264
Test name
Test status
Simulation time 3018324775 ps
CPU time 40.75 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 05:49:55 PM PDT 24
Peak memory 199740 kb
Host smart-646e0559-6f7c-4f45-91f6-e95e2ebcf1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166547342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3166547342
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3419795583
Short name T354
Test name
Test status
Simulation time 3551977340 ps
CPU time 111.04 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:51:08 PM PDT 24
Peak memory 367620 kb
Host smart-202f19d6-2bf7-4dd7-a539-9cdfe81512dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419795583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3419795583
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.782311354
Short name T498
Test name
Test status
Simulation time 5635488552 ps
CPU time 89.13 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:50:46 PM PDT 24
Peak memory 199700 kb
Host smart-c8de41dc-82ca-4ad3-935c-2cd406f43953
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782311354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.782311354
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1462194052
Short name T405
Test name
Test status
Simulation time 24182150236 ps
CPU time 147.81 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:51:45 PM PDT 24
Peak memory 207960 kb
Host smart-2e0e5fad-c373-4a9f-87bb-7839e1fbcaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462194052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1462194052
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2036347098
Short name T467
Test name
Test status
Simulation time 1821946489 ps
CPU time 8.48 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 05:49:33 PM PDT 24
Peak memory 199772 kb
Host smart-465fbf96-0247-4b3e-8ba0-c0d911df5f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036347098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2036347098
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2686216735
Short name T333
Test name
Test status
Simulation time 23044447941 ps
CPU time 325.74 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:54:41 PM PDT 24
Peak memory 208012 kb
Host smart-ea0b3dc3-69ae-43cd-b25b-21e373a2b585
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686216735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2686216735
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3120595376
Short name T528
Test name
Test status
Simulation time 921796927 ps
CPU time 37.83 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:49:53 PM PDT 24
Peak memory 199768 kb
Host smart-3a7399a4-7c6b-4297-993e-df898b22b9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120595376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3120595376
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4146764328
Short name T362
Test name
Test status
Simulation time 18979478 ps
CPU time 0.59 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:49:17 PM PDT 24
Peak memory 195700 kb
Host smart-534f5954-bc65-48b9-a2f6-2098ff17671c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146764328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4146764328
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3374531352
Short name T503
Test name
Test status
Simulation time 758354908 ps
CPU time 41.16 seconds
Started Jul 27 05:49:09 PM PDT 24
Finished Jul 27 05:49:50 PM PDT 24
Peak memory 199724 kb
Host smart-c8a9dfb0-ec71-4d3c-903b-453332b7047d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374531352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3374531352
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1750410240
Short name T516
Test name
Test status
Simulation time 3704580656 ps
CPU time 15.2 seconds
Started Jul 27 05:49:04 PM PDT 24
Finished Jul 27 05:49:20 PM PDT 24
Peak memory 199744 kb
Host smart-d97e1bf8-db8a-406f-978c-e560454e71fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750410240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1750410240
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.4084193715
Short name T408
Test name
Test status
Simulation time 2031899937 ps
CPU time 313.43 seconds
Started Jul 27 05:49:09 PM PDT 24
Finished Jul 27 05:54:23 PM PDT 24
Peak memory 476900 kb
Host smart-2d4fbc66-4ca4-4345-986d-7f0cd35a60a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084193715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4084193715
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.53708255
Short name T351
Test name
Test status
Simulation time 2767243859 ps
CPU time 158.68 seconds
Started Jul 27 05:49:26 PM PDT 24
Finished Jul 27 05:52:05 PM PDT 24
Peak memory 199752 kb
Host smart-47f9e067-848a-454f-91a9-b8788ade5134
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53708255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.53708255
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.876001509
Short name T192
Test name
Test status
Simulation time 23213505319 ps
CPU time 36.12 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 05:49:50 PM PDT 24
Peak memory 199800 kb
Host smart-57f8338c-4a7a-43ad-87c2-c17b69b104d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876001509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.876001509
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4232658704
Short name T501
Test name
Test status
Simulation time 494287060 ps
CPU time 5.78 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 05:49:14 PM PDT 24
Peak memory 199732 kb
Host smart-4854b107-ef8f-4c29-961a-e170d453cfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232658704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4232658704
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.695560432
Short name T413
Test name
Test status
Simulation time 241010853314 ps
CPU time 1406.19 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 06:12:50 PM PDT 24
Peak memory 715576 kb
Host smart-a54c0282-9bbd-48e2-b066-962a86dac5e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695560432 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.695560432
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1180875786
Short name T229
Test name
Test status
Simulation time 1109455141 ps
CPU time 4.41 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:49:21 PM PDT 24
Peak memory 199712 kb
Host smart-e66e2839-853f-4cd8-a66d-989d0487cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180875786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1180875786
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2321850785
Short name T181
Test name
Test status
Simulation time 5792618183 ps
CPU time 86.82 seconds
Started Jul 27 05:49:32 PM PDT 24
Finished Jul 27 05:50:59 PM PDT 24
Peak memory 199788 kb
Host smart-757354ec-6f26-4777-83a6-893cf12f4f92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321850785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2321850785
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3950879918
Short name T189
Test name
Test status
Simulation time 1245906305 ps
CPU time 16.63 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:49:33 PM PDT 24
Peak memory 199592 kb
Host smart-8eaafec7-3e8e-4cc7-9a10-fc64bebd173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950879918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3950879918
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2917058674
Short name T284
Test name
Test status
Simulation time 3541731169 ps
CPU time 546.91 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:58:24 PM PDT 24
Peak memory 658500 kb
Host smart-e7261132-57bd-41ab-81f4-9aef9954caa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2917058674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2917058674
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.745093592
Short name T278
Test name
Test status
Simulation time 50575069145 ps
CPU time 233.1 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:53:08 PM PDT 24
Peak memory 199804 kb
Host smart-d82c0518-2cdc-42ea-ae61-19e57566a871
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745093592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.745093592
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1684992395
Short name T341
Test name
Test status
Simulation time 15489643175 ps
CPU time 50.29 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:50:07 PM PDT 24
Peak memory 199740 kb
Host smart-351f60d8-bb33-4d58-998b-644b0ec62dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684992395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1684992395
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.535780073
Short name T297
Test name
Test status
Simulation time 173837374 ps
CPU time 3.45 seconds
Started Jul 27 05:49:09 PM PDT 24
Finished Jul 27 05:49:13 PM PDT 24
Peak memory 199712 kb
Host smart-f208fbf8-02ef-422f-9f86-18f08fa53195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535780073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.535780073
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.956208761
Short name T72
Test name
Test status
Simulation time 567452729329 ps
CPU time 2708.26 seconds
Started Jul 27 05:49:20 PM PDT 24
Finished Jul 27 06:34:28 PM PDT 24
Peak memory 707468 kb
Host smart-47447a3a-5a5c-45bd-8a92-07ee3b985ed8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956208761 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.956208761
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.217001381
Short name T497
Test name
Test status
Simulation time 7714260722 ps
CPU time 104.75 seconds
Started Jul 27 05:49:19 PM PDT 24
Finished Jul 27 05:51:04 PM PDT 24
Peak memory 199708 kb
Host smart-486ad4d1-31c2-44bf-a3d8-b1421cc8aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217001381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.217001381
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4249784423
Short name T315
Test name
Test status
Simulation time 36729363 ps
CPU time 0.56 seconds
Started Jul 27 05:49:19 PM PDT 24
Finished Jul 27 05:49:19 PM PDT 24
Peak memory 194672 kb
Host smart-266cad21-df0c-4a4d-a6ae-ee7005f32947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249784423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4249784423
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1243040367
Short name T186
Test name
Test status
Simulation time 829444867 ps
CPU time 45.95 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 05:50:00 PM PDT 24
Peak memory 199644 kb
Host smart-a56e680b-ee18-485d-a4e0-c95bac233e5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243040367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1243040367
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2569600459
Short name T375
Test name
Test status
Simulation time 211767669 ps
CPU time 4.31 seconds
Started Jul 27 05:49:21 PM PDT 24
Finished Jul 27 05:49:26 PM PDT 24
Peak memory 199596 kb
Host smart-1077e8fc-2284-49bc-ad92-e9e52425e2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569600459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2569600459
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3730987199
Short name T164
Test name
Test status
Simulation time 1316301932 ps
CPU time 198.16 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:52:34 PM PDT 24
Peak memory 449172 kb
Host smart-d57dd379-56b9-49bb-9559-a025e8c77e56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730987199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3730987199
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1675122510
Short name T243
Test name
Test status
Simulation time 16315435070 ps
CPU time 155.28 seconds
Started Jul 27 05:49:40 PM PDT 24
Finished Jul 27 05:52:16 PM PDT 24
Peak memory 199716 kb
Host smart-9eaabafd-ec43-405b-91fe-f130fd19efe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675122510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1675122510
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.942278894
Short name T460
Test name
Test status
Simulation time 17712868246 ps
CPU time 97.94 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:50:54 PM PDT 24
Peak memory 200232 kb
Host smart-be505f11-09dd-4c06-8aa3-3c25c6259800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942278894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.942278894
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3943676533
Short name T155
Test name
Test status
Simulation time 218021934 ps
CPU time 10.19 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:49:27 PM PDT 24
Peak memory 199700 kb
Host smart-9b18630f-35c9-4baa-aee3-f56c9c0ea97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943676533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3943676533
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.146097702
Short name T380
Test name
Test status
Simulation time 16113153228 ps
CPU time 78.03 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:50:35 PM PDT 24
Peak memory 199756 kb
Host smart-7fa5970e-dc8d-4cad-b817-da5e9f951af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146097702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.146097702
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2959953231
Short name T504
Test name
Test status
Simulation time 24868194 ps
CPU time 0.59 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 05:49:25 PM PDT 24
Peak memory 195636 kb
Host smart-3754deb4-dddd-47cb-8ffd-6323f78136c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959953231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2959953231
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2099048630
Short name T167
Test name
Test status
Simulation time 5404296987 ps
CPU time 31.54 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 05:49:46 PM PDT 24
Peak memory 199696 kb
Host smart-0aa0648d-c01e-4436-8082-3e59e2e9e152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099048630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2099048630
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3978305438
Short name T10
Test name
Test status
Simulation time 1553667607 ps
CPU time 67.81 seconds
Started Jul 27 05:49:19 PM PDT 24
Finished Jul 27 05:50:27 PM PDT 24
Peak memory 199624 kb
Host smart-5e02cbad-a32d-4900-9a8a-3d7017f122c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978305438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3978305438
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3630308486
Short name T489
Test name
Test status
Simulation time 749867776 ps
CPU time 120.78 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:51:16 PM PDT 24
Peak memory 431264 kb
Host smart-67718292-9bdd-49f0-af5a-2d064ef80bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630308486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3630308486
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4195936985
Short name T518
Test name
Test status
Simulation time 55720187501 ps
CPU time 121.39 seconds
Started Jul 27 05:49:20 PM PDT 24
Finished Jul 27 05:51:21 PM PDT 24
Peak memory 199712 kb
Host smart-da021483-804c-4ac5-8418-eacf7698c56e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195936985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4195936985
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.302422040
Short name T4
Test name
Test status
Simulation time 21628262745 ps
CPU time 112.37 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:51:09 PM PDT 24
Peak memory 199964 kb
Host smart-b9d345f0-ee32-4a3b-95a8-a912c40116e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302422040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.302422040
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2022158404
Short name T371
Test name
Test status
Simulation time 236364288 ps
CPU time 10.24 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:49:25 PM PDT 24
Peak memory 199668 kb
Host smart-ac320e00-1249-4d5e-b91e-c36cd767722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022158404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2022158404
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1900504819
Short name T487
Test name
Test status
Simulation time 226085946729 ps
CPU time 982.39 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 06:05:37 PM PDT 24
Peak memory 216148 kb
Host smart-112e10e7-7785-44b7-b60a-9c414590c726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900504819 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1900504819
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.599612435
Short name T348
Test name
Test status
Simulation time 20221737502 ps
CPU time 105.04 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 05:50:59 PM PDT 24
Peak memory 199832 kb
Host smart-1ea1e79b-6cc0-4911-a4bb-b35f4518a103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599612435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.599612435
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.873508428
Short name T249
Test name
Test status
Simulation time 136552423 ps
CPU time 0.57 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:49:15 PM PDT 24
Peak memory 195360 kb
Host smart-015f0aec-df14-4cae-9f43-4c5f005be792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873508428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.873508428
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4037142905
Short name T2
Test name
Test status
Simulation time 6821537382 ps
CPU time 49.29 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:50:05 PM PDT 24
Peak memory 199776 kb
Host smart-912e52f7-2886-4663-8d0f-53d99609c7f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037142905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4037142905
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2978339053
Short name T55
Test name
Test status
Simulation time 845869793 ps
CPU time 15.95 seconds
Started Jul 27 05:49:29 PM PDT 24
Finished Jul 27 05:49:45 PM PDT 24
Peak memory 199672 kb
Host smart-43568017-1f1b-45e5-94aa-fac7dfe23da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978339053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2978339053
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2317990734
Short name T306
Test name
Test status
Simulation time 2916320065 ps
CPU time 200.78 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 05:52:45 PM PDT 24
Peak memory 402900 kb
Host smart-56bb3bac-3c5b-46cb-9e1b-eeffe27adf65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317990734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2317990734
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2644341201
Short name T369
Test name
Test status
Simulation time 68605044420 ps
CPU time 103.08 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 05:51:07 PM PDT 24
Peak memory 199764 kb
Host smart-6697cdd9-2851-4728-98b0-95a53db21b40
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644341201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2644341201
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2601021300
Short name T136
Test name
Test status
Simulation time 18607530180 ps
CPU time 174.68 seconds
Started Jul 27 05:49:18 PM PDT 24
Finished Jul 27 05:52:13 PM PDT 24
Peak memory 199964 kb
Host smart-b3ed3aab-4d50-42c4-8036-77d099ffe1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601021300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2601021300
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.577620255
Short name T488
Test name
Test status
Simulation time 4349221952 ps
CPU time 14.92 seconds
Started Jul 27 05:49:25 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 199764 kb
Host smart-7478a94b-4782-480f-b764-d6bf95dede87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577620255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.577620255
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3681702003
Short name T197
Test name
Test status
Simulation time 10385341962 ps
CPU time 42.56 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:49:58 PM PDT 24
Peak memory 199684 kb
Host smart-e3d383a5-5a49-46b7-9ad8-4a5f7716a97b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681702003 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3681702003
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2417361534
Short name T66
Test name
Test status
Simulation time 13203536298 ps
CPU time 56.5 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:50:13 PM PDT 24
Peak memory 199772 kb
Host smart-0d798b98-38b2-4a2c-a7f3-8e0b801dc514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417361534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2417361534
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3302689703
Short name T193
Test name
Test status
Simulation time 30350578 ps
CPU time 0.59 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:48:53 PM PDT 24
Peak memory 194676 kb
Host smart-5ac66c82-a357-468e-90dd-128e37df432a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302689703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3302689703
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.846523835
Short name T417
Test name
Test status
Simulation time 229946289 ps
CPU time 12.8 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:49:06 PM PDT 24
Peak memory 199760 kb
Host smart-a2b21f26-d1f0-49e3-b684-cf67464f0060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846523835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.846523835
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1814356748
Short name T482
Test name
Test status
Simulation time 4297732050 ps
CPU time 58.57 seconds
Started Jul 27 05:48:58 PM PDT 24
Finished Jul 27 05:49:57 PM PDT 24
Peak memory 199768 kb
Host smart-19bf3025-3785-48f1-b20e-caed3069d454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814356748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1814356748
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3982144565
Short name T38
Test name
Test status
Simulation time 5161345851 ps
CPU time 914.85 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 06:04:10 PM PDT 24
Peak memory 725316 kb
Host smart-cce5812d-f466-41d0-9b31-15d8caca2f9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982144565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3982144565
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.57392655
Short name T276
Test name
Test status
Simulation time 2271399008 ps
CPU time 37.81 seconds
Started Jul 27 05:48:56 PM PDT 24
Finished Jul 27 05:49:33 PM PDT 24
Peak memory 199660 kb
Host smart-5f22b368-faad-489c-9841-bd99c8bb626e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57392655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.57392655
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2679714842
Short name T387
Test name
Test status
Simulation time 6891706252 ps
CPU time 74.66 seconds
Started Jul 27 05:48:51 PM PDT 24
Finished Jul 27 05:50:06 PM PDT 24
Peak memory 215900 kb
Host smart-35b56a97-9c92-48a7-93ec-1fe8e9cd6f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679714842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2679714842
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.474640193
Short name T47
Test name
Test status
Simulation time 84484534 ps
CPU time 0.96 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:48:54 PM PDT 24
Peak memory 219320 kb
Host smart-0f2a19b1-58ed-47ee-ab9b-407dcb8842a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474640193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.474640193
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.701969227
Short name T32
Test name
Test status
Simulation time 191136553 ps
CPU time 7.81 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:49:00 PM PDT 24
Peak memory 199712 kb
Host smart-97035f96-ebaa-4bc3-9fcd-c4a38dd33a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701969227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.701969227
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3843389464
Short name T137
Test name
Test status
Simulation time 11991897528 ps
CPU time 308.31 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:54:02 PM PDT 24
Peak memory 199744 kb
Host smart-3583be31-fb45-4d79-9aa4-41bc76464bb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843389464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3843389464
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2857052226
Short name T63
Test name
Test status
Simulation time 82057815787 ps
CPU time 2350.23 seconds
Started Jul 27 05:48:54 PM PDT 24
Finished Jul 27 06:28:04 PM PDT 24
Peak memory 730752 kb
Host smart-78686989-cd03-4eb3-94a1-95a701b72215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857052226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2857052226
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3650686515
Short name T316
Test name
Test status
Simulation time 5314207596 ps
CPU time 37.86 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:49:33 PM PDT 24
Peak memory 199780 kb
Host smart-eafd7cde-c530-43de-97fb-6b2fd2f901d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3650686515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3650686515
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3289994770
Short name T247
Test name
Test status
Simulation time 3336115308 ps
CPU time 53.95 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:49:46 PM PDT 24
Peak memory 199812 kb
Host smart-7cc13e19-967d-43c9-9031-b67e720e5b37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3289994770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3289994770
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1575591215
Short name T219
Test name
Test status
Simulation time 2349116875 ps
CPU time 75.61 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:50:08 PM PDT 24
Peak memory 199700 kb
Host smart-2704f84f-3a8a-4c9f-88f0-48dda2a38a77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1575591215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1575591215
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3880085420
Short name T146
Test name
Test status
Simulation time 48924456217 ps
CPU time 635.61 seconds
Started Jul 27 05:48:54 PM PDT 24
Finished Jul 27 05:59:29 PM PDT 24
Peak memory 199828 kb
Host smart-a0010063-6208-49d5-af80-9a9174e3fe4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3880085420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3880085420
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3008524644
Short name T185
Test name
Test status
Simulation time 843280138793 ps
CPU time 2592.71 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 06:32:06 PM PDT 24
Peak memory 207984 kb
Host smart-881a43aa-b889-4558-97e1-48ff5b709ff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3008524644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3008524644
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1419536330
Short name T366
Test name
Test status
Simulation time 4881904947 ps
CPU time 115.56 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:50:51 PM PDT 24
Peak memory 199812 kb
Host smart-0fd62c05-9023-4785-b576-740010f22b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419536330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1419536330
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2879598200
Short name T250
Test name
Test status
Simulation time 16292646 ps
CPU time 0.58 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:49:18 PM PDT 24
Peak memory 195720 kb
Host smart-80c07f39-8844-4e4d-a33f-5ce7af153aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879598200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2879598200
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1817740825
Short name T438
Test name
Test status
Simulation time 120251249 ps
CPU time 7.08 seconds
Started Jul 27 05:49:19 PM PDT 24
Finished Jul 27 05:49:26 PM PDT 24
Peak memory 199656 kb
Host smart-0e7ebdfc-92e1-4e6b-b6d9-6d1624671b0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817740825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1817740825
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3088155809
Short name T430
Test name
Test status
Simulation time 9475820043 ps
CPU time 38.04 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:49:55 PM PDT 24
Peak memory 199216 kb
Host smart-1001e3ec-b0bb-4325-8ef7-a5bb88446e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088155809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3088155809
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3729623204
Short name T223
Test name
Test status
Simulation time 3350057127 ps
CPU time 752.82 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 06:01:49 PM PDT 24
Peak memory 622724 kb
Host smart-d416eab7-8016-48fb-b6a2-8b9cd3b708ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729623204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3729623204
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1366481599
Short name T477
Test name
Test status
Simulation time 2405475994 ps
CPU time 12.61 seconds
Started Jul 27 05:49:25 PM PDT 24
Finished Jul 27 05:49:37 PM PDT 24
Peak memory 199640 kb
Host smart-4144567c-37b7-4594-b1e7-8a239b41283f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366481599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1366481599
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2526919770
Short name T521
Test name
Test status
Simulation time 645611103 ps
CPU time 12.06 seconds
Started Jul 27 05:49:23 PM PDT 24
Finished Jul 27 05:49:35 PM PDT 24
Peak memory 199700 kb
Host smart-9291a570-7b4d-4c5b-8d54-39c1a3146bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526919770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2526919770
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3364755364
Short name T442
Test name
Test status
Simulation time 5339568769 ps
CPU time 14.06 seconds
Started Jul 27 05:49:15 PM PDT 24
Finished Jul 27 05:49:29 PM PDT 24
Peak memory 199748 kb
Host smart-656851fd-8453-4ad2-87c9-2cd29b8ac39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364755364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3364755364
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2699270625
Short name T90
Test name
Test status
Simulation time 3630592321 ps
CPU time 192.84 seconds
Started Jul 27 05:49:14 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 247000 kb
Host smart-4cebd44f-e217-48e3-9e16-2a11921c281b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699270625 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2699270625
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2047806803
Short name T236
Test name
Test status
Simulation time 792466442 ps
CPU time 4.71 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:49:21 PM PDT 24
Peak memory 199704 kb
Host smart-3bc638a3-51e8-44f7-a3bd-98e687a1223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047806803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2047806803
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1862447427
Short name T298
Test name
Test status
Simulation time 12062320 ps
CPU time 0.59 seconds
Started Jul 27 05:49:25 PM PDT 24
Finished Jul 27 05:49:26 PM PDT 24
Peak memory 195060 kb
Host smart-b7f00b1c-a671-460e-8053-2c5f84b5c362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862447427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1862447427
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4202930065
Short name T203
Test name
Test status
Simulation time 510157135 ps
CPU time 29.09 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:49:46 PM PDT 24
Peak memory 199096 kb
Host smart-8e577ab6-749e-42fc-a3b7-080716054ab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202930065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4202930065
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2288562541
Short name T182
Test name
Test status
Simulation time 10753566679 ps
CPU time 38.85 seconds
Started Jul 27 05:49:17 PM PDT 24
Finished Jul 27 05:49:56 PM PDT 24
Peak memory 207964 kb
Host smart-ca412346-fefc-4a19-b62c-492cdeaa72ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288562541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2288562541
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3281670732
Short name T260
Test name
Test status
Simulation time 14615809395 ps
CPU time 144.57 seconds
Started Jul 27 05:49:16 PM PDT 24
Finished Jul 27 05:51:41 PM PDT 24
Peak memory 569576 kb
Host smart-717367e6-e711-458a-9db0-e960a00c721b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281670732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3281670732
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3896579511
Short name T411
Test name
Test status
Simulation time 66800740904 ps
CPU time 221.66 seconds
Started Jul 27 05:49:20 PM PDT 24
Finished Jul 27 05:53:02 PM PDT 24
Peak memory 199780 kb
Host smart-1777f6f9-18fc-4485-8e79-5e89a864e102
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896579511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3896579511
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.416437216
Short name T323
Test name
Test status
Simulation time 1610669588 ps
CPU time 12.54 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 05:49:37 PM PDT 24
Peak memory 199640 kb
Host smart-a9d4bd45-5942-47af-9f18-a8ef2af28e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416437216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.416437216
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2376231615
Short name T346
Test name
Test status
Simulation time 1514397700 ps
CPU time 5.38 seconds
Started Jul 27 05:49:18 PM PDT 24
Finished Jul 27 05:49:23 PM PDT 24
Peak memory 199712 kb
Host smart-89fbf019-c35b-4599-9187-20f0170896c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376231615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2376231615
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.530391207
Short name T53
Test name
Test status
Simulation time 129948875215 ps
CPU time 543.39 seconds
Started Jul 27 05:49:20 PM PDT 24
Finished Jul 27 05:58:24 PM PDT 24
Peak memory 479404 kb
Host smart-142f2472-01b0-4a5e-98e6-93d1bfe5d1a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530391207 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.530391207
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.161571582
Short name T88
Test name
Test status
Simulation time 6714430992 ps
CPU time 73.73 seconds
Started Jul 27 05:49:29 PM PDT 24
Finished Jul 27 05:50:43 PM PDT 24
Peak memory 199756 kb
Host smart-012d25ac-c8c7-4ccb-8baa-55da4e6ecc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161571582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.161571582
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1412555696
Short name T281
Test name
Test status
Simulation time 47370601 ps
CPU time 0.55 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 05:49:24 PM PDT 24
Peak memory 195692 kb
Host smart-c86832d7-9a01-490f-9d9b-0f9dc05bf8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412555696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1412555696
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3481232547
Short name T502
Test name
Test status
Simulation time 217911476 ps
CPU time 11.96 seconds
Started Jul 27 05:49:28 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 199584 kb
Host smart-cb578bfe-177e-4a0a-9c8c-98aba33e7363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481232547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3481232547
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2624853457
Short name T8
Test name
Test status
Simulation time 1401718039 ps
CPU time 43.54 seconds
Started Jul 27 05:49:30 PM PDT 24
Finished Jul 27 05:50:14 PM PDT 24
Peak memory 199732 kb
Host smart-465d8fe1-3eb6-4243-9706-96d510b58585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624853457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2624853457
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3902860838
Short name T64
Test name
Test status
Simulation time 30270879938 ps
CPU time 806.13 seconds
Started Jul 27 05:49:29 PM PDT 24
Finished Jul 27 06:02:55 PM PDT 24
Peak memory 682224 kb
Host smart-0b3efecf-7433-4d6f-bc35-06b440ba0b14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902860838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3902860838
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1653463818
Short name T214
Test name
Test status
Simulation time 4230772922 ps
CPU time 57.38 seconds
Started Jul 27 05:49:31 PM PDT 24
Finished Jul 27 05:50:28 PM PDT 24
Peak memory 199856 kb
Host smart-032aca97-bdb9-4875-b450-b2b37957dfd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653463818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1653463818
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.604113879
Short name T426
Test name
Test status
Simulation time 54885959506 ps
CPU time 67.41 seconds
Started Jul 27 05:49:20 PM PDT 24
Finished Jul 27 05:50:28 PM PDT 24
Peak memory 199840 kb
Host smart-aa515343-6711-4b0e-bc6b-0ca3c0040f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604113879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.604113879
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1562346067
Short name T65
Test name
Test status
Simulation time 835358702 ps
CPU time 4.61 seconds
Started Jul 27 05:49:21 PM PDT 24
Finished Jul 27 05:49:25 PM PDT 24
Peak memory 199744 kb
Host smart-09ed574d-b938-4741-8613-0134f5f54ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562346067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1562346067
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2742617769
Short name T451
Test name
Test status
Simulation time 378568728463 ps
CPU time 2036.55 seconds
Started Jul 27 05:49:29 PM PDT 24
Finished Jul 27 06:23:26 PM PDT 24
Peak memory 769424 kb
Host smart-f8fbb25c-4e56-4ab2-ab45-780853e1f31c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742617769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2742617769
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3385742493
Short name T172
Test name
Test status
Simulation time 7200105084 ps
CPU time 65.14 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:50:32 PM PDT 24
Peak memory 199800 kb
Host smart-71d90f98-087e-47d6-a764-96488c527ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385742493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3385742493
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1399209807
Short name T41
Test name
Test status
Simulation time 50331656 ps
CPU time 0.58 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 05:49:36 PM PDT 24
Peak memory 196320 kb
Host smart-d07539d7-e788-406d-a241-403e51025444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399209807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1399209807
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.597209112
Short name T143
Test name
Test status
Simulation time 2451878097 ps
CPU time 36.72 seconds
Started Jul 27 05:49:25 PM PDT 24
Finished Jul 27 05:50:02 PM PDT 24
Peak memory 199808 kb
Host smart-0f2baadc-c5cc-4e16-b19c-d0237f2608e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597209112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.597209112
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.161441728
Short name T458
Test name
Test status
Simulation time 7035873472 ps
CPU time 25.78 seconds
Started Jul 27 05:49:39 PM PDT 24
Finished Jul 27 05:50:05 PM PDT 24
Peak memory 199828 kb
Host smart-a16b06a4-c93b-4675-9cbf-6e31ef2f7c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161441728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.161441728
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.288283787
Short name T6
Test name
Test status
Simulation time 6008047852 ps
CPU time 1153.67 seconds
Started Jul 27 05:49:39 PM PDT 24
Finished Jul 27 06:08:53 PM PDT 24
Peak memory 782020 kb
Host smart-6ab072c8-b6a0-4bd1-a9be-f0df844213c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288283787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.288283787
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3102223379
Short name T440
Test name
Test status
Simulation time 26419546381 ps
CPU time 225.6 seconds
Started Jul 27 05:49:20 PM PDT 24
Finished Jul 27 05:53:05 PM PDT 24
Peak memory 199804 kb
Host smart-65dbc0c3-70d5-4ee3-b860-6de4124845b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102223379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3102223379
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1809634836
Short name T251
Test name
Test status
Simulation time 7379096310 ps
CPU time 104.73 seconds
Started Jul 27 05:49:40 PM PDT 24
Finished Jul 27 05:51:24 PM PDT 24
Peak memory 208004 kb
Host smart-988e85d1-678c-4900-830e-92d308e39116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809634836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1809634836
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3185115246
Short name T402
Test name
Test status
Simulation time 846104728 ps
CPU time 3.63 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 05:49:39 PM PDT 24
Peak memory 199644 kb
Host smart-ee859cec-7ea8-4b7d-928c-5fe6c85394b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185115246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3185115246
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2745155703
Short name T87
Test name
Test status
Simulation time 13268558520 ps
CPU time 233.56 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:53:26 PM PDT 24
Peak memory 199768 kb
Host smart-bf13efab-d8d6-4cb6-9a39-af809fcc9e81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745155703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2745155703
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1974148174
Short name T444
Test name
Test status
Simulation time 26657245941 ps
CPU time 88.04 seconds
Started Jul 27 05:49:29 PM PDT 24
Finished Jul 27 05:50:57 PM PDT 24
Peak memory 199856 kb
Host smart-67e3b47b-2987-4575-913f-05233de68bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974148174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1974148174
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1363651349
Short name T211
Test name
Test status
Simulation time 140677510 ps
CPU time 0.59 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:49:23 PM PDT 24
Peak memory 195716 kb
Host smart-4e94aff3-d0b4-4062-a127-883c8092ff6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363651349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1363651349
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3798684180
Short name T199
Test name
Test status
Simulation time 1926303483 ps
CPU time 76.59 seconds
Started Jul 27 05:49:34 PM PDT 24
Finished Jul 27 05:50:51 PM PDT 24
Peak memory 199652 kb
Host smart-5fc7a8c8-5e0d-4023-811f-0f877cc6f116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798684180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3798684180
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3576259827
Short name T453
Test name
Test status
Simulation time 9653578644 ps
CPU time 63.91 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:50:26 PM PDT 24
Peak memory 199812 kb
Host smart-48344c0d-0029-4841-bb2d-4d99a7da8fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576259827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3576259827
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1964724277
Short name T239
Test name
Test status
Simulation time 1565866840 ps
CPU time 231.94 seconds
Started Jul 27 05:49:25 PM PDT 24
Finished Jul 27 05:53:17 PM PDT 24
Peak memory 491880 kb
Host smart-ce8f2222-56c8-41f9-b743-9e53e9ef209c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964724277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1964724277
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3662260779
Short name T409
Test name
Test status
Simulation time 4155228356 ps
CPU time 12.43 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 05:49:47 PM PDT 24
Peak memory 199720 kb
Host smart-8f7900e4-bea4-48be-8d02-067bfa8cefb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662260779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3662260779
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3192469281
Short name T314
Test name
Test status
Simulation time 5082375686 ps
CPU time 69.46 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:50:31 PM PDT 24
Peak memory 199656 kb
Host smart-9ccd964f-a517-4563-8d80-ba243009ab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192469281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3192469281
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.391660425
Short name T418
Test name
Test status
Simulation time 492597700 ps
CPU time 5.34 seconds
Started Jul 27 05:49:34 PM PDT 24
Finished Jul 27 05:49:39 PM PDT 24
Peak memory 199688 kb
Host smart-157affb7-7fbb-4e57-a7b8-8c1dc38baad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391660425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.391660425
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4083498260
Short name T514
Test name
Test status
Simulation time 39119451833 ps
CPU time 111.07 seconds
Started Jul 27 05:49:29 PM PDT 24
Finished Jul 27 05:51:20 PM PDT 24
Peak memory 199796 kb
Host smart-1f5e6db6-9403-40b7-b90c-e2f7c31b9f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083498260 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4083498260
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3586493313
Short name T212
Test name
Test status
Simulation time 2903663313 ps
CPU time 39.48 seconds
Started Jul 27 05:49:25 PM PDT 24
Finished Jul 27 05:50:05 PM PDT 24
Peak memory 199808 kb
Host smart-5f2bc40f-2f53-4d45-a9c4-b1ec1cfa990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586493313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3586493313
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2356884220
Short name T505
Test name
Test status
Simulation time 22158629 ps
CPU time 0.59 seconds
Started Jul 27 05:49:46 PM PDT 24
Finished Jul 27 05:49:47 PM PDT 24
Peak memory 195692 kb
Host smart-050ffeaa-cead-4232-8f80-87656b4864b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356884220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2356884220
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3765210589
Short name T34
Test name
Test status
Simulation time 4508121187 ps
CPU time 63.25 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:50:25 PM PDT 24
Peak memory 199676 kb
Host smart-99647f92-5fe9-45aa-adbd-de5f1631e113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765210589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3765210589
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.764935063
Short name T262
Test name
Test status
Simulation time 767476040 ps
CPU time 3.14 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:49:25 PM PDT 24
Peak memory 199624 kb
Host smart-e409e968-7cc7-4639-baa5-435eab62249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764935063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.764935063
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2738530761
Short name T256
Test name
Test status
Simulation time 5412032063 ps
CPU time 240.78 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 628700 kb
Host smart-9ea4471d-ce6b-4d28-a5bc-6df48c89a35e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738530761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2738530761
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3936027661
Short name T147
Test name
Test status
Simulation time 46443856214 ps
CPU time 141.75 seconds
Started Jul 27 05:49:25 PM PDT 24
Finished Jul 27 05:51:47 PM PDT 24
Peak memory 199744 kb
Host smart-06dd5656-9184-4f21-896c-7387128e17f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936027661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3936027661
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.100871464
Short name T368
Test name
Test status
Simulation time 17268974401 ps
CPU time 110.17 seconds
Started Jul 27 05:49:23 PM PDT 24
Finished Jul 27 05:51:14 PM PDT 24
Peak memory 199688 kb
Host smart-dd6648c8-9f5a-416f-93cd-5d423369a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100871464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.100871464
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1772327598
Short name T336
Test name
Test status
Simulation time 5621478091 ps
CPU time 7.9 seconds
Started Jul 27 05:49:24 PM PDT 24
Finished Jul 27 05:49:32 PM PDT 24
Peak memory 199828 kb
Host smart-2b2ceec8-cd88-4742-ad85-f149ee3bd226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772327598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1772327598
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2976967843
Short name T202
Test name
Test status
Simulation time 49850092651 ps
CPU time 1804.25 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 06:19:26 PM PDT 24
Peak memory 783656 kb
Host smart-bf7d5fd8-22a7-498b-88b1-056c105b5ab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976967843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2976967843
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1937885396
Short name T419
Test name
Test status
Simulation time 2185743713 ps
CPU time 26.2 seconds
Started Jul 27 05:49:21 PM PDT 24
Finished Jul 27 05:49:47 PM PDT 24
Peak memory 199776 kb
Host smart-a68f863b-b2e9-4952-b7c5-085dbb5f916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937885396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1937885396
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1881562634
Short name T464
Test name
Test status
Simulation time 13090183 ps
CPU time 0.6 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:49:34 PM PDT 24
Peak memory 194692 kb
Host smart-58a6f947-11b6-4d0a-93d3-b2815f7a9c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881562634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1881562634
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3424702473
Short name T529
Test name
Test status
Simulation time 516926068 ps
CPU time 29.54 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:49:52 PM PDT 24
Peak memory 199680 kb
Host smart-e49fc2c6-202e-4f30-b88f-4717366854c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424702473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3424702473
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2175534716
Short name T391
Test name
Test status
Simulation time 3940598232 ps
CPU time 50.81 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 05:50:13 PM PDT 24
Peak memory 199816 kb
Host smart-f22627d4-c765-43dd-b7be-e9b34d142558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175534716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2175534716
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2299075815
Short name T395
Test name
Test status
Simulation time 3832744327 ps
CPU time 679.73 seconds
Started Jul 27 05:49:37 PM PDT 24
Finished Jul 27 06:00:57 PM PDT 24
Peak memory 688240 kb
Host smart-52314d45-be58-4ae1-b1c5-e944157bad3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299075815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2299075815
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1172445277
Short name T524
Test name
Test status
Simulation time 9318036566 ps
CPU time 168.81 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:52:22 PM PDT 24
Peak memory 199760 kb
Host smart-08017da0-0b3f-4420-ac7a-962cbe3d86b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172445277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1172445277
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3481830431
Short name T399
Test name
Test status
Simulation time 1733322836 ps
CPU time 101.37 seconds
Started Jul 27 05:49:50 PM PDT 24
Finished Jul 27 05:51:31 PM PDT 24
Peak memory 199684 kb
Host smart-1b9b2771-79eb-46b1-bcd7-9183de3eebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481830431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3481830431
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2314863833
Short name T277
Test name
Test status
Simulation time 439242608 ps
CPU time 10.48 seconds
Started Jul 27 05:49:34 PM PDT 24
Finished Jul 27 05:49:45 PM PDT 24
Peak memory 199740 kb
Host smart-58f8e27f-8bbf-487a-8f09-8f8f9c6fd080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314863833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2314863833
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.139664442
Short name T76
Test name
Test status
Simulation time 468686955787 ps
CPU time 2601.52 seconds
Started Jul 27 05:49:22 PM PDT 24
Finished Jul 27 06:32:44 PM PDT 24
Peak memory 767908 kb
Host smart-a6bedf7e-df05-4b64-8701-443c9966513d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139664442 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.139664442
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3034269027
Short name T217
Test name
Test status
Simulation time 32022027980 ps
CPU time 106.68 seconds
Started Jul 27 05:49:23 PM PDT 24
Finished Jul 27 05:51:10 PM PDT 24
Peak memory 199752 kb
Host smart-3013a74e-c0e4-4e6d-9e9d-6cfceb6066e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034269027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3034269027
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2208861647
Short name T496
Test name
Test status
Simulation time 87228273 ps
CPU time 0.6 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 05:49:43 PM PDT 24
Peak memory 196364 kb
Host smart-aafd1993-f609-44b1-b1b1-aa6b813e967f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208861647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2208861647
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2929546403
Short name T365
Test name
Test status
Simulation time 1288918314 ps
CPU time 75.83 seconds
Started Jul 27 05:49:28 PM PDT 24
Finished Jul 27 05:50:44 PM PDT 24
Peak memory 199896 kb
Host smart-49eb211a-aab6-4af1-882d-56a17aec8601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929546403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2929546403
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3732070950
Short name T274
Test name
Test status
Simulation time 6079205129 ps
CPU time 37.56 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:50:05 PM PDT 24
Peak memory 207904 kb
Host smart-006efbca-7084-4b0b-b671-10b687bebc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732070950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3732070950
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3978310294
Short name T173
Test name
Test status
Simulation time 4383597272 ps
CPU time 858.84 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 06:03:54 PM PDT 24
Peak memory 756136 kb
Host smart-95b25532-066e-415b-a0f7-f37a221bcb5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3978310294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3978310294
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3841730567
Short name T80
Test name
Test status
Simulation time 9689425893 ps
CPU time 122.72 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:51:30 PM PDT 24
Peak memory 199712 kb
Host smart-7d29236d-29d8-48c5-844d-7af97cf8e3ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841730567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3841730567
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.383666907
Short name T352
Test name
Test status
Simulation time 20575815092 ps
CPU time 130.61 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:51:43 PM PDT 24
Peak memory 207976 kb
Host smart-10fe4270-0a70-46bd-ac1e-abe1687298a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383666907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.383666907
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.832727816
Short name T187
Test name
Test status
Simulation time 4116660759 ps
CPU time 5.28 seconds
Started Jul 27 05:49:41 PM PDT 24
Finished Jul 27 05:49:46 PM PDT 24
Peak memory 199772 kb
Host smart-27658894-3387-4013-9c4a-75b1353eb8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832727816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.832727816
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.46966529
Short name T500
Test name
Test status
Simulation time 129759374003 ps
CPU time 2000.22 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 06:22:55 PM PDT 24
Peak memory 728428 kb
Host smart-afc62404-707e-4e11-8db7-31797ace4893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46966529 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.46966529
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.214806623
Short name T238
Test name
Test status
Simulation time 6820050596 ps
CPU time 87.83 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:51:01 PM PDT 24
Peak memory 199756 kb
Host smart-f80e045a-e965-4e49-8949-7dbfc2435de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214806623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.214806623
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.622683045
Short name T149
Test name
Test status
Simulation time 22141044 ps
CPU time 0.57 seconds
Started Jul 27 05:49:32 PM PDT 24
Finished Jul 27 05:49:33 PM PDT 24
Peak memory 195728 kb
Host smart-d481b6a0-aab6-416a-8297-2718ef2a76fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622683045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.622683045
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3902946681
Short name T432
Test name
Test status
Simulation time 3791753389 ps
CPU time 66.57 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 05:50:42 PM PDT 24
Peak memory 199716 kb
Host smart-37e88ff9-c71a-4113-9309-17d604f68b0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902946681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3902946681
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.103064783
Short name T527
Test name
Test status
Simulation time 9394801899 ps
CPU time 43.1 seconds
Started Jul 27 05:49:28 PM PDT 24
Finished Jul 27 05:50:11 PM PDT 24
Peak memory 199812 kb
Host smart-77495847-b296-4a06-8bb4-bcf68ab8bdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103064783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.103064783
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3792390370
Short name T329
Test name
Test status
Simulation time 35393293 ps
CPU time 0.88 seconds
Started Jul 27 05:49:28 PM PDT 24
Finished Jul 27 05:49:29 PM PDT 24
Peak memory 198652 kb
Host smart-624d68a3-3ddb-43ea-bfa6-0c6f8f01cace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792390370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3792390370
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1742275160
Short name T345
Test name
Test status
Simulation time 2219768100 ps
CPU time 63.94 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:50:31 PM PDT 24
Peak memory 199728 kb
Host smart-5e3ca5fe-658b-4a6d-aa43-7efaa76323c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742275160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1742275160
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3878759987
Short name T480
Test name
Test status
Simulation time 20608755642 ps
CPU time 170.83 seconds
Started Jul 27 05:49:37 PM PDT 24
Finished Jul 27 05:52:28 PM PDT 24
Peak memory 216076 kb
Host smart-2b2076e5-0f67-47fd-90d7-6c3430ac8a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878759987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3878759987
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.850713781
Short name T210
Test name
Test status
Simulation time 527298556 ps
CPU time 12.37 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 199708 kb
Host smart-9bc82ee3-a6b5-4a0f-a13a-2d66bea9d637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850713781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.850713781
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2898278143
Short name T290
Test name
Test status
Simulation time 9143371445 ps
CPU time 460.22 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:57:14 PM PDT 24
Peak memory 216156 kb
Host smart-e2e5cd3d-0112-454a-bc7f-8038bbce5346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898278143 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2898278143
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3419651486
Short name T344
Test name
Test status
Simulation time 1302703196 ps
CPU time 15.43 seconds
Started Jul 27 05:49:36 PM PDT 24
Finished Jul 27 05:49:52 PM PDT 24
Peak memory 199732 kb
Host smart-fdb13237-ce3f-446f-b2a2-ae39738f2e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419651486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3419651486
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1251598846
Short name T254
Test name
Test status
Simulation time 12821152 ps
CPU time 0.55 seconds
Started Jul 27 05:49:31 PM PDT 24
Finished Jul 27 05:49:32 PM PDT 24
Peak memory 194648 kb
Host smart-ae953b90-534c-4042-b604-0ce81fdf4a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251598846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1251598846
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1845559543
Short name T259
Test name
Test status
Simulation time 1450610637 ps
CPU time 50.44 seconds
Started Jul 27 05:49:34 PM PDT 24
Finished Jul 27 05:50:24 PM PDT 24
Peak memory 199736 kb
Host smart-a144c2a6-0ce3-4ade-bcfa-f50ba88506da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845559543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1845559543
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.516793446
Short name T434
Test name
Test status
Simulation time 1649725694 ps
CPU time 29.15 seconds
Started Jul 27 05:49:28 PM PDT 24
Finished Jul 27 05:49:57 PM PDT 24
Peak memory 199680 kb
Host smart-8dc3fb33-cb65-43a8-9b75-7c372bad297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516793446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.516793446
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3395606433
Short name T49
Test name
Test status
Simulation time 12801150131 ps
CPU time 973.44 seconds
Started Jul 27 05:49:36 PM PDT 24
Finished Jul 27 06:05:49 PM PDT 24
Peak memory 731772 kb
Host smart-ab7cc93f-f7d6-41c9-973e-a94da78f71e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395606433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3395606433
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2918268564
Short name T461
Test name
Test status
Simulation time 104126549554 ps
CPU time 131.97 seconds
Started Jul 27 05:49:31 PM PDT 24
Finished Jul 27 05:51:43 PM PDT 24
Peak memory 199712 kb
Host smart-29bb3909-f499-4b58-9603-80a1347e5fc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918268564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2918268564
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3044263188
Short name T520
Test name
Test status
Simulation time 13455945779 ps
CPU time 166.29 seconds
Started Jul 27 05:49:34 PM PDT 24
Finished Jul 27 05:52:20 PM PDT 24
Peak memory 216104 kb
Host smart-e2db7105-5560-479e-a6bc-9033b90428e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044263188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3044263188
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2613360725
Short name T424
Test name
Test status
Simulation time 2110418260 ps
CPU time 7.51 seconds
Started Jul 27 05:49:43 PM PDT 24
Finished Jul 27 05:49:50 PM PDT 24
Peak memory 199708 kb
Host smart-d49b3087-0804-4d3c-94a5-8b60e6fcc771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613360725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2613360725
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.58087542
Short name T228
Test name
Test status
Simulation time 7312956944 ps
CPU time 89.52 seconds
Started Jul 27 05:49:34 PM PDT 24
Finished Jul 27 05:51:04 PM PDT 24
Peak memory 199756 kb
Host smart-459fb2cc-4b3c-4372-9a58-2b185badda45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58087542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.58087542
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1857195914
Short name T245
Test name
Test status
Simulation time 14048407 ps
CPU time 0.64 seconds
Started Jul 27 05:48:54 PM PDT 24
Finished Jul 27 05:48:54 PM PDT 24
Peak memory 195804 kb
Host smart-b37ba031-3c6d-4b25-a04e-522d53803179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857195914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1857195914
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.531359616
Short name T176
Test name
Test status
Simulation time 2572730736 ps
CPU time 70.91 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:50:06 PM PDT 24
Peak memory 199760 kb
Host smart-bc9d4766-b69a-45fb-bbbc-d9f8cc053c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531359616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.531359616
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3979182008
Short name T144
Test name
Test status
Simulation time 82277809 ps
CPU time 1.86 seconds
Started Jul 27 05:48:57 PM PDT 24
Finished Jul 27 05:48:59 PM PDT 24
Peak memory 199536 kb
Host smart-02e2643a-c169-4ff8-bbe9-dcdce2637b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979182008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3979182008
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.310747073
Short name T510
Test name
Test status
Simulation time 9420112981 ps
CPU time 881.51 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 06:03:33 PM PDT 24
Peak memory 748596 kb
Host smart-3b3e1119-b47c-4899-a85f-6fa5d621b73b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=310747073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.310747073
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1544676099
Short name T397
Test name
Test status
Simulation time 7231566681 ps
CPU time 131 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:51:03 PM PDT 24
Peak memory 199796 kb
Host smart-8ebac2db-d73f-4475-9481-0cce67bf0795
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544676099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1544676099
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.4167004531
Short name T5
Test name
Test status
Simulation time 2882813764 ps
CPU time 18.64 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:49:11 PM PDT 24
Peak memory 199752 kb
Host smart-c4eb9187-42ca-4e7f-a228-dbdb5a1186c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167004531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.4167004531
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2224370790
Short name T46
Test name
Test status
Simulation time 115491808 ps
CPU time 1.11 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 05:48:54 PM PDT 24
Peak memory 219336 kb
Host smart-58cfc666-598b-4e8d-84c6-f1f675c2b360
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224370790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2224370790
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1532457006
Short name T522
Test name
Test status
Simulation time 1530031468 ps
CPU time 13.16 seconds
Started Jul 27 05:48:51 PM PDT 24
Finished Jul 27 05:49:04 PM PDT 24
Peak memory 199652 kb
Host smart-ec7e57ac-8250-43a0-b50e-5067468fd2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532457006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1532457006
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1028118577
Short name T62
Test name
Test status
Simulation time 184063068432 ps
CPU time 1588.65 seconds
Started Jul 27 05:48:54 PM PDT 24
Finished Jul 27 06:15:23 PM PDT 24
Peak memory 767152 kb
Host smart-164ca03d-e7ee-4a11-854d-8c7717a56183
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028118577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1028118577
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2921413528
Short name T317
Test name
Test status
Simulation time 7219152400 ps
CPU time 71.07 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:50:04 PM PDT 24
Peak memory 199788 kb
Host smart-e852dcb4-0cf4-4591-b3ba-53616ece813c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2921413528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2921413528
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.340558333
Short name T473
Test name
Test status
Simulation time 7678191451 ps
CPU time 98.19 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:50:32 PM PDT 24
Peak memory 199752 kb
Host smart-02fb6b6c-eff2-45f6-b9cf-704a78bd01e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=340558333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.340558333
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1680566007
Short name T312
Test name
Test status
Simulation time 63669147668 ps
CPU time 141.24 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:51:14 PM PDT 24
Peak memory 199812 kb
Host smart-1486dfe4-0c03-4989-99c5-555e0276b364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1680566007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1680566007
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2053034997
Short name T481
Test name
Test status
Simulation time 143220153417 ps
CPU time 622.99 seconds
Started Jul 27 05:48:54 PM PDT 24
Finished Jul 27 05:59:17 PM PDT 24
Peak memory 199828 kb
Host smart-e01e76d2-e228-4072-ad83-3a2ffc17ee04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2053034997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2053034997
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2192283112
Short name T134
Test name
Test status
Simulation time 140338382202 ps
CPU time 2562.77 seconds
Started Jul 27 05:48:52 PM PDT 24
Finished Jul 27 06:31:35 PM PDT 24
Peak memory 215312 kb
Host smart-c3721ca5-17fb-4912-8ceb-311e1c31cdcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2192283112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2192283112
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1279053281
Short name T492
Test name
Test status
Simulation time 154514878149 ps
CPU time 2192.54 seconds
Started Jul 27 05:48:54 PM PDT 24
Finished Jul 27 06:25:27 PM PDT 24
Peak memory 216044 kb
Host smart-6eeec324-66f4-4031-aa13-7d1ece43d32d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1279053281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1279053281
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2101374224
Short name T383
Test name
Test status
Simulation time 8568549088 ps
CPU time 45.23 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 199772 kb
Host smart-f677dd5b-1d80-469f-a8dd-9ccf32b4f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101374224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2101374224
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1038917320
Short name T420
Test name
Test status
Simulation time 27874856 ps
CPU time 0.61 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:49:27 PM PDT 24
Peak memory 196408 kb
Host smart-9960a39b-dc98-481b-8b57-a16e03fe141e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038917320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1038917320
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2588152988
Short name T392
Test name
Test status
Simulation time 324841655 ps
CPU time 19.28 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:49:47 PM PDT 24
Peak memory 199684 kb
Host smart-3bbed362-989e-49df-8637-55bd6fc45f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588152988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2588152988
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3234692446
Short name T224
Test name
Test status
Simulation time 1909947618 ps
CPU time 27.95 seconds
Started Jul 27 05:49:26 PM PDT 24
Finished Jul 27 05:49:54 PM PDT 24
Peak memory 199668 kb
Host smart-e9e95f29-1bdc-4feb-8bd5-ff57462ed73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234692446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3234692446
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3831725367
Short name T396
Test name
Test status
Simulation time 8821885348 ps
CPU time 619.63 seconds
Started Jul 27 05:49:37 PM PDT 24
Finished Jul 27 05:59:57 PM PDT 24
Peak memory 691880 kb
Host smart-eb19809a-dc95-41a7-86ec-42d903df21d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831725367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3831725367
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2174028156
Short name T457
Test name
Test status
Simulation time 3283987380 ps
CPU time 169.56 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:52:16 PM PDT 24
Peak memory 199668 kb
Host smart-9fc77712-3823-4610-8cdf-df9e8275331c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174028156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2174028156
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3354995290
Short name T526
Test name
Test status
Simulation time 7380049965 ps
CPU time 32.1 seconds
Started Jul 27 05:49:27 PM PDT 24
Finished Jul 27 05:49:59 PM PDT 24
Peak memory 199772 kb
Host smart-54d40e34-c159-4169-bbbf-2b907d070368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354995290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3354995290
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2159414104
Short name T118
Test name
Test status
Simulation time 410971927 ps
CPU time 1.74 seconds
Started Jul 27 05:49:39 PM PDT 24
Finished Jul 27 05:49:41 PM PDT 24
Peak memory 199660 kb
Host smart-59ab16f6-e00e-4d46-9392-f1f6e6e19ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159414104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2159414104
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1942013782
Short name T289
Test name
Test status
Simulation time 7146663862 ps
CPU time 27.81 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 05:50:03 PM PDT 24
Peak memory 199724 kb
Host smart-ff458d67-e505-4e4e-8d95-80a99fe32f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942013782 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1942013782
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.113472951
Short name T253
Test name
Test status
Simulation time 6314403322 ps
CPU time 114.72 seconds
Started Jul 27 05:49:30 PM PDT 24
Finished Jul 27 05:51:25 PM PDT 24
Peak memory 199740 kb
Host smart-f1ddf6cb-0576-4b22-8466-13551916b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113472951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.113472951
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1984609138
Short name T412
Test name
Test status
Simulation time 21739155 ps
CPU time 0.58 seconds
Started Jul 27 05:49:39 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 195708 kb
Host smart-e34bf377-44d5-4fd2-9d0a-390749a1c7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984609138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1984609138
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.667279402
Short name T17
Test name
Test status
Simulation time 8729703778 ps
CPU time 70.62 seconds
Started Jul 27 05:49:44 PM PDT 24
Finished Jul 27 05:50:54 PM PDT 24
Peak memory 215952 kb
Host smart-0d484a80-104e-4719-9e1a-8f57ed52b29e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667279402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.667279402
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3507912656
Short name T466
Test name
Test status
Simulation time 1618603105 ps
CPU time 23.16 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 05:50:05 PM PDT 24
Peak memory 199720 kb
Host smart-2bf58dc5-f36b-434d-8731-c7b7530b6b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507912656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3507912656
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1194355258
Short name T441
Test name
Test status
Simulation time 19405802662 ps
CPU time 730.28 seconds
Started Jul 27 05:49:34 PM PDT 24
Finished Jul 27 06:01:44 PM PDT 24
Peak memory 732984 kb
Host smart-eff5d0da-0a8b-453d-bc1f-d76841358eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194355258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1194355258
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1249710010
Short name T163
Test name
Test status
Simulation time 12751171506 ps
CPU time 160.89 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:52:14 PM PDT 24
Peak memory 199796 kb
Host smart-d1cb4856-514d-4a39-acfd-99cec5c312ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249710010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1249710010
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1788748126
Short name T157
Test name
Test status
Simulation time 10387672944 ps
CPU time 29.27 seconds
Started Jul 27 05:49:36 PM PDT 24
Finished Jul 27 05:50:05 PM PDT 24
Peak memory 199712 kb
Host smart-e258b49d-19e1-4e36-85bf-84f6ed8b8daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788748126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1788748126
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1036018328
Short name T206
Test name
Test status
Simulation time 1374879538 ps
CPU time 6.15 seconds
Started Jul 27 05:49:33 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 199748 kb
Host smart-f061decb-d733-4584-b5b8-843a33ab2faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036018328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1036018328
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2395238152
Short name T75
Test name
Test status
Simulation time 255468270098 ps
CPU time 3417.83 seconds
Started Jul 27 05:49:35 PM PDT 24
Finished Jul 27 06:46:33 PM PDT 24
Peak memory 808912 kb
Host smart-324d400f-3527-4465-bca9-ac5f9b43856c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395238152 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2395238152
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1474994060
Short name T261
Test name
Test status
Simulation time 2328719960 ps
CPU time 69.4 seconds
Started Jul 27 05:49:44 PM PDT 24
Finished Jul 27 05:50:53 PM PDT 24
Peak memory 199728 kb
Host smart-59998bc8-62cf-441f-86b1-8c1bf13dfe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474994060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1474994060
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2500667788
Short name T415
Test name
Test status
Simulation time 21718152 ps
CPU time 0.58 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:49:48 PM PDT 24
Peak memory 195440 kb
Host smart-0641ea31-5e9b-4d30-b52b-96a9f07c7a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500667788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2500667788
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1840946039
Short name T370
Test name
Test status
Simulation time 736506377 ps
CPU time 40.53 seconds
Started Jul 27 05:49:52 PM PDT 24
Finished Jul 27 05:50:32 PM PDT 24
Peak memory 199712 kb
Host smart-5f2b1c17-8933-403d-977c-ecdda1658ca8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840946039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1840946039
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3886204689
Short name T400
Test name
Test status
Simulation time 1190421434 ps
CPU time 44.8 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 05:50:27 PM PDT 24
Peak memory 199716 kb
Host smart-00d10f63-8fa5-46e1-b761-cbd532567f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886204689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3886204689
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3722652922
Short name T162
Test name
Test status
Simulation time 512145367 ps
CPU time 30.92 seconds
Started Jul 27 05:49:43 PM PDT 24
Finished Jul 27 05:50:14 PM PDT 24
Peak memory 251984 kb
Host smart-654437c2-353d-4a8f-8f01-d35c54b9e1ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722652922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3722652922
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.101493302
Short name T85
Test name
Test status
Simulation time 23935027926 ps
CPU time 203.54 seconds
Started Jul 27 05:49:47 PM PDT 24
Finished Jul 27 05:53:11 PM PDT 24
Peak memory 199720 kb
Host smart-87d4fe96-1844-439b-a638-143c62da665a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101493302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.101493302
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2159419456
Short name T468
Test name
Test status
Simulation time 1482735913 ps
CPU time 83.98 seconds
Started Jul 27 05:49:39 PM PDT 24
Finished Jul 27 05:51:03 PM PDT 24
Peak memory 199744 kb
Host smart-462986e5-bfce-4153-bcdb-8bcfef32a401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159419456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2159419456
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1917970067
Short name T68
Test name
Test status
Simulation time 270117220 ps
CPU time 12.19 seconds
Started Jul 27 05:49:41 PM PDT 24
Finished Jul 27 05:49:54 PM PDT 24
Peak memory 199696 kb
Host smart-15e14655-8a20-46b4-92b1-d4a7a37b9109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917970067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1917970067
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1445574802
Short name T335
Test name
Test status
Simulation time 54241453834 ps
CPU time 2359.73 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 06:29:03 PM PDT 24
Peak memory 795528 kb
Host smart-4691cca2-f2ba-45ca-ba7e-f9c5f6a7ce74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445574802 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1445574802
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.86724251
Short name T235
Test name
Test status
Simulation time 472109863 ps
CPU time 10.06 seconds
Started Jul 27 05:49:41 PM PDT 24
Finished Jul 27 05:49:52 PM PDT 24
Peak memory 199716 kb
Host smart-4ec12796-4c65-42bd-b763-14e1135a1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86724251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.86724251
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.237120411
Short name T455
Test name
Test status
Simulation time 44795874 ps
CPU time 0.59 seconds
Started Jul 27 05:49:53 PM PDT 24
Finished Jul 27 05:49:54 PM PDT 24
Peak memory 195748 kb
Host smart-42e55f44-6f95-4134-86d4-6b592cb35f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237120411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.237120411
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1070852180
Short name T525
Test name
Test status
Simulation time 3393530864 ps
CPU time 52.98 seconds
Started Jul 27 05:49:40 PM PDT 24
Finished Jul 27 05:50:33 PM PDT 24
Peak memory 199792 kb
Host smart-17dd7398-dc82-4cc9-b315-ce443238ed81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070852180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1070852180
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3079072018
Short name T184
Test name
Test status
Simulation time 22378980687 ps
CPU time 41.55 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:50:30 PM PDT 24
Peak memory 199784 kb
Host smart-8a5db129-c9f2-49a0-b331-ce3bf6918ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079072018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3079072018
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2968086226
Short name T379
Test name
Test status
Simulation time 16359314881 ps
CPU time 1698.34 seconds
Started Jul 27 05:49:49 PM PDT 24
Finished Jul 27 06:18:07 PM PDT 24
Peak memory 780128 kb
Host smart-0e572c93-f939-41f7-a131-43d15b92f7fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968086226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2968086226
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.4111554580
Short name T508
Test name
Test status
Simulation time 21530680229 ps
CPU time 73.81 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 05:50:56 PM PDT 24
Peak memory 199812 kb
Host smart-a8ab7c4e-c7d2-4d94-984c-d6ded7f2859e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111554580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.4111554580
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3316817465
Short name T285
Test name
Test status
Simulation time 12678937430 ps
CPU time 168.93 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 05:52:31 PM PDT 24
Peak memory 199800 kb
Host smart-2fd37ed9-0045-4f2b-a5ab-d179eb160cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316817465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3316817465
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2303232882
Short name T178
Test name
Test status
Simulation time 325636101 ps
CPU time 6.07 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:49:54 PM PDT 24
Peak memory 199684 kb
Host smart-2231974a-bee8-4bb1-9121-10cbe65c9d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303232882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2303232882
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3096813010
Short name T161
Test name
Test status
Simulation time 59334218092 ps
CPU time 272.95 seconds
Started Jul 27 05:49:46 PM PDT 24
Finished Jul 27 05:54:19 PM PDT 24
Peak memory 199780 kb
Host smart-0cde58d2-243e-4320-b53e-ae9441063049
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096813010 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3096813010
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3815852168
Short name T89
Test name
Test status
Simulation time 2413842125 ps
CPU time 10.33 seconds
Started Jul 27 05:49:42 PM PDT 24
Finished Jul 27 05:49:52 PM PDT 24
Peak memory 199828 kb
Host smart-f5544dc9-b08d-4850-88e4-e03555673e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815852168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3815852168
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.493386715
Short name T40
Test name
Test status
Simulation time 47783499 ps
CPU time 0.61 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:49:49 PM PDT 24
Peak memory 196424 kb
Host smart-c900b360-6d85-4c73-9def-ab88661a404c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493386715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.493386715
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2870742510
Short name T18
Test name
Test status
Simulation time 8315866062 ps
CPU time 106.56 seconds
Started Jul 27 05:49:54 PM PDT 24
Finished Jul 27 05:51:41 PM PDT 24
Peak memory 199640 kb
Host smart-1d42c34b-f043-41b6-874a-af4b1df26ac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870742510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2870742510
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.4101937887
Short name T357
Test name
Test status
Simulation time 8049008656 ps
CPU time 28.5 seconds
Started Jul 27 05:49:54 PM PDT 24
Finished Jul 27 05:50:22 PM PDT 24
Peak memory 207884 kb
Host smart-5c97c069-96ad-4dac-b27b-69adf841ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101937887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.4101937887
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.661654399
Short name T263
Test name
Test status
Simulation time 9357226759 ps
CPU time 836.07 seconds
Started Jul 27 05:49:53 PM PDT 24
Finished Jul 27 06:03:50 PM PDT 24
Peak memory 742668 kb
Host smart-daacca01-2ed8-4841-abbc-3a1e17784f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661654399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.661654399
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1534069047
Short name T394
Test name
Test status
Simulation time 30615270026 ps
CPU time 185.94 seconds
Started Jul 27 05:49:52 PM PDT 24
Finished Jul 27 05:52:58 PM PDT 24
Peak memory 199844 kb
Host smart-be3e6ffe-28db-48ae-a557-49371dc8be28
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534069047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1534069047
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.70916297
Short name T512
Test name
Test status
Simulation time 9274576143 ps
CPU time 53.07 seconds
Started Jul 27 05:49:47 PM PDT 24
Finished Jul 27 05:50:40 PM PDT 24
Peak memory 199804 kb
Host smart-4745b9b7-19f5-4589-a1bc-69d44e34e505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70916297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.70916297
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.829398954
Short name T523
Test name
Test status
Simulation time 1186664803 ps
CPU time 10.73 seconds
Started Jul 27 05:49:45 PM PDT 24
Finished Jul 27 05:49:56 PM PDT 24
Peak memory 199764 kb
Host smart-29206a7b-93b2-457b-a88a-4fef3d52af96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829398954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.829398954
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.387511721
Short name T73
Test name
Test status
Simulation time 88480197838 ps
CPU time 2561.59 seconds
Started Jul 27 05:49:52 PM PDT 24
Finished Jul 27 06:32:34 PM PDT 24
Peak memory 769180 kb
Host smart-c26b9b6f-3c5c-429f-b9d4-9fc3dd0f86f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387511721 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.387511721
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.356411853
Short name T328
Test name
Test status
Simulation time 3242831403 ps
CPU time 29.33 seconds
Started Jul 27 05:49:49 PM PDT 24
Finished Jul 27 05:50:18 PM PDT 24
Peak memory 199816 kb
Host smart-40a8d966-3406-45d3-bd88-fa796156c6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356411853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.356411853
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1149800498
Short name T232
Test name
Test status
Simulation time 15260957 ps
CPU time 0.59 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:49:49 PM PDT 24
Peak memory 194692 kb
Host smart-0afb593e-45de-4e0d-b828-c83027ee709d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149800498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1149800498
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3635734590
Short name T471
Test name
Test status
Simulation time 156633723 ps
CPU time 2.79 seconds
Started Jul 27 05:49:47 PM PDT 24
Finished Jul 27 05:49:50 PM PDT 24
Peak memory 199704 kb
Host smart-8c44b24b-9573-4518-81f1-6394df99b101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635734590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3635734590
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1983057499
Short name T358
Test name
Test status
Simulation time 1342357728 ps
CPU time 17.1 seconds
Started Jul 27 05:49:53 PM PDT 24
Finished Jul 27 05:50:11 PM PDT 24
Peak memory 199700 kb
Host smart-b55f6511-c722-405b-8704-90af6bee42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983057499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1983057499
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3827969648
Short name T152
Test name
Test status
Simulation time 766091247 ps
CPU time 152.35 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:52:21 PM PDT 24
Peak memory 435744 kb
Host smart-785372b8-f8bb-4828-b5f5-b335a001aedd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827969648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3827969648
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.978028133
Short name T168
Test name
Test status
Simulation time 10475210220 ps
CPU time 147.6 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:52:16 PM PDT 24
Peak memory 199736 kb
Host smart-fa703da5-3475-4e24-be9b-6285d5df12f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978028133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.978028133
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3987739777
Short name T302
Test name
Test status
Simulation time 1376679983 ps
CPU time 21.98 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:50:10 PM PDT 24
Peak memory 199708 kb
Host smart-aa85b815-a46c-45cc-ab53-406855767253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987739777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3987739777
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.80072243
Short name T330
Test name
Test status
Simulation time 4050136568 ps
CPU time 12.27 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:50:01 PM PDT 24
Peak memory 199836 kb
Host smart-40985f53-0aaa-4f36-b3bb-d1ba2c312bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80072243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.80072243
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.504600391
Short name T337
Test name
Test status
Simulation time 223250977566 ps
CPU time 627.23 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 06:00:16 PM PDT 24
Peak memory 433420 kb
Host smart-28d9ffea-64e9-4bfc-984e-6449c6add195
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504600391 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.504600391
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1368449852
Short name T273
Test name
Test status
Simulation time 35449659430 ps
CPU time 56.82 seconds
Started Jul 27 05:49:54 PM PDT 24
Finished Jul 27 05:50:51 PM PDT 24
Peak memory 199676 kb
Host smart-6b2da6e7-ee32-4083-b7bf-5485fba17927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368449852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1368449852
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.813061648
Short name T382
Test name
Test status
Simulation time 13092947 ps
CPU time 0.59 seconds
Started Jul 27 05:49:55 PM PDT 24
Finished Jul 27 05:49:55 PM PDT 24
Peak memory 195704 kb
Host smart-a9a5f012-5302-47bb-a617-86e1e9e319c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813061648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.813061648
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3372204980
Short name T135
Test name
Test status
Simulation time 7713907013 ps
CPU time 102.9 seconds
Started Jul 27 05:49:54 PM PDT 24
Finished Jul 27 05:51:37 PM PDT 24
Peak memory 207924 kb
Host smart-9a9103b7-aac5-437f-b9bc-581ed6aa0742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372204980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3372204980
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3509174163
Short name T237
Test name
Test status
Simulation time 4467249741 ps
CPU time 58.9 seconds
Started Jul 27 05:50:05 PM PDT 24
Finished Jul 27 05:51:04 PM PDT 24
Peak memory 199780 kb
Host smart-7e516c8c-3c0b-4bd2-aaad-e7d8c2f91609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509174163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3509174163
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3551582756
Short name T234
Test name
Test status
Simulation time 2455793952 ps
CPU time 454.99 seconds
Started Jul 27 05:50:02 PM PDT 24
Finished Jul 27 05:57:37 PM PDT 24
Peak memory 671100 kb
Host smart-3be3d939-51da-43c3-8d1f-f2f04b8fee0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551582756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3551582756
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3776421774
Short name T160
Test name
Test status
Simulation time 32243346656 ps
CPU time 95.59 seconds
Started Jul 27 05:50:05 PM PDT 24
Finished Jul 27 05:51:41 PM PDT 24
Peak memory 199756 kb
Host smart-4ba2c1dd-2211-41b8-8123-c90352f431df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776421774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3776421774
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3420729968
Short name T240
Test name
Test status
Simulation time 14277662105 ps
CPU time 207.94 seconds
Started Jul 27 05:49:47 PM PDT 24
Finished Jul 27 05:53:15 PM PDT 24
Peak memory 199836 kb
Host smart-e6999577-673e-4546-bf3a-05e20554f7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420729968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3420729968
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.350436584
Short name T517
Test name
Test status
Simulation time 400756107 ps
CPU time 7.06 seconds
Started Jul 27 05:49:48 PM PDT 24
Finished Jul 27 05:49:55 PM PDT 24
Peak memory 199704 kb
Host smart-3f709a6b-b764-46bf-ba81-4aac19739ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350436584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.350436584
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1417720030
Short name T443
Test name
Test status
Simulation time 28371657270 ps
CPU time 193.93 seconds
Started Jul 27 05:49:56 PM PDT 24
Finished Jul 27 05:53:10 PM PDT 24
Peak memory 199808 kb
Host smart-ce21ec1b-54d0-487e-9ed9-626dbe247876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417720030 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1417720030
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.72609740
Short name T94
Test name
Test status
Simulation time 16119372133 ps
CPU time 90.48 seconds
Started Jul 27 05:50:05 PM PDT 24
Finished Jul 27 05:51:36 PM PDT 24
Peak memory 199784 kb
Host smart-6b41c53a-d8cb-440a-bb28-e2f18f520d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72609740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.72609740
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.110661196
Short name T257
Test name
Test status
Simulation time 16071504 ps
CPU time 0.59 seconds
Started Jul 27 05:50:05 PM PDT 24
Finished Jul 27 05:50:06 PM PDT 24
Peak memory 195328 kb
Host smart-0ecb39a1-ed84-4428-82f2-591c81d6c1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110661196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.110661196
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2098700383
Short name T282
Test name
Test status
Simulation time 3290190123 ps
CPU time 47.38 seconds
Started Jul 27 05:49:55 PM PDT 24
Finished Jul 27 05:50:43 PM PDT 24
Peak memory 199736 kb
Host smart-04eb7c6d-7e31-46ea-98e2-94fa82a05b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098700383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2098700383
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2493056199
Short name T476
Test name
Test status
Simulation time 14360353816 ps
CPU time 46.81 seconds
Started Jul 27 05:49:55 PM PDT 24
Finished Jul 27 05:50:42 PM PDT 24
Peak memory 216084 kb
Host smart-57abcc53-63a3-4cf5-90fa-885cde9cf313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493056199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2493056199
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3927545172
Short name T338
Test name
Test status
Simulation time 3443249679 ps
CPU time 344.68 seconds
Started Jul 27 05:49:56 PM PDT 24
Finished Jul 27 05:55:41 PM PDT 24
Peak memory 656060 kb
Host smart-d2ea3843-4049-4b39-addf-266afe25c168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927545172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3927545172
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2222288557
Short name T265
Test name
Test status
Simulation time 2742255858 ps
CPU time 107.28 seconds
Started Jul 27 05:49:56 PM PDT 24
Finished Jul 27 05:51:43 PM PDT 24
Peak memory 199804 kb
Host smart-c0ebe12a-b7af-4f0b-9402-87f1ddaeaec5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222288557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2222288557
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1231191632
Short name T33
Test name
Test status
Simulation time 6621327101 ps
CPU time 56.69 seconds
Started Jul 27 05:49:55 PM PDT 24
Finished Jul 27 05:50:52 PM PDT 24
Peak memory 199820 kb
Host smart-00ba5992-02f2-4ba5-9266-417d6bc89527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231191632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1231191632
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1515401500
Short name T378
Test name
Test status
Simulation time 631149461 ps
CPU time 9.87 seconds
Started Jul 27 05:50:06 PM PDT 24
Finished Jul 27 05:50:16 PM PDT 24
Peak memory 199600 kb
Host smart-2d86c12d-dfb3-4663-b6f0-8bdbddced0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515401500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1515401500
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.151707149
Short name T515
Test name
Test status
Simulation time 72994816136 ps
CPU time 2066.41 seconds
Started Jul 27 05:49:56 PM PDT 24
Finished Jul 27 06:24:23 PM PDT 24
Peak memory 792060 kb
Host smart-4dbd4d94-c395-4523-92f6-4a6f254cbc2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151707149 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.151707149
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2846696959
Short name T449
Test name
Test status
Simulation time 538533747 ps
CPU time 14.45 seconds
Started Jul 27 05:50:05 PM PDT 24
Finished Jul 27 05:50:20 PM PDT 24
Peak memory 199688 kb
Host smart-4f00300a-2450-4447-8296-b53838abd06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846696959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2846696959
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.400522396
Short name T322
Test name
Test status
Simulation time 19190321 ps
CPU time 0.6 seconds
Started Jul 27 05:50:11 PM PDT 24
Finished Jul 27 05:50:12 PM PDT 24
Peak memory 195204 kb
Host smart-58a4b341-b595-44d6-8f02-a7040667de35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400522396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.400522396
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4064744862
Short name T154
Test name
Test status
Simulation time 2912816558 ps
CPU time 85.33 seconds
Started Jul 27 05:50:05 PM PDT 24
Finished Jul 27 05:51:30 PM PDT 24
Peak memory 199804 kb
Host smart-32132f95-6be8-438b-bd07-eba21106ca60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064744862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4064744862
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2884472864
Short name T475
Test name
Test status
Simulation time 1024024161 ps
CPU time 6.76 seconds
Started Jul 27 05:50:07 PM PDT 24
Finished Jul 27 05:50:14 PM PDT 24
Peak memory 199672 kb
Host smart-d6a2f5fa-c7bc-4924-b45d-e4d37613caeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884472864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2884472864
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4171578069
Short name T320
Test name
Test status
Simulation time 2593304577 ps
CPU time 482.67 seconds
Started Jul 27 05:50:06 PM PDT 24
Finished Jul 27 05:58:09 PM PDT 24
Peak memory 673600 kb
Host smart-1c45ae5b-69da-41f2-b8a6-e434c5758770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171578069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4171578069
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3411607775
Short name T269
Test name
Test status
Simulation time 1642223217 ps
CPU time 86.83 seconds
Started Jul 27 05:50:01 PM PDT 24
Finished Jul 27 05:51:28 PM PDT 24
Peak memory 199688 kb
Host smart-cb792215-97a6-4671-9203-48d8d006f948
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411607775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3411607775
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_smoke.3976667332
Short name T145
Test name
Test status
Simulation time 144808836 ps
CPU time 6.45 seconds
Started Jul 27 05:49:55 PM PDT 24
Finished Jul 27 05:50:01 PM PDT 24
Peak memory 199708 kb
Host smart-2d601b8b-a638-4632-a952-5a22c411349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976667332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3976667332
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2394840270
Short name T37
Test name
Test status
Simulation time 3911598249 ps
CPU time 219.03 seconds
Started Jul 27 05:50:07 PM PDT 24
Finished Jul 27 05:53:46 PM PDT 24
Peak memory 216084 kb
Host smart-c2c69226-e42e-4feb-95cc-c824b08c564b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394840270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2394840270
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.571107982
Short name T169
Test name
Test status
Simulation time 2405836881 ps
CPU time 39.9 seconds
Started Jul 27 05:50:01 PM PDT 24
Finished Jul 27 05:50:41 PM PDT 24
Peak memory 199784 kb
Host smart-8cebe4da-e873-4677-977d-9ec8e18d69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571107982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.571107982
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.764396877
Short name T159
Test name
Test status
Simulation time 33019419 ps
CPU time 0.58 seconds
Started Jul 27 05:50:00 PM PDT 24
Finished Jul 27 05:50:01 PM PDT 24
Peak memory 195324 kb
Host smart-9be961fe-ed8b-4fcd-a183-d81928a391ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764396877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.764396877
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.862778495
Short name T9
Test name
Test status
Simulation time 4949606478 ps
CPU time 75.07 seconds
Started Jul 27 05:50:02 PM PDT 24
Finished Jul 27 05:51:17 PM PDT 24
Peak memory 199700 kb
Host smart-f73b38c4-57d1-4bf3-9c63-974d35019cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862778495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.862778495
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3729692391
Short name T507
Test name
Test status
Simulation time 2605555777 ps
CPU time 70.83 seconds
Started Jul 27 05:50:03 PM PDT 24
Finished Jul 27 05:51:14 PM PDT 24
Peak memory 199760 kb
Host smart-1ed6e965-7c93-4338-bec7-e986e221648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729692391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3729692391
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3847628867
Short name T493
Test name
Test status
Simulation time 12890476592 ps
CPU time 607.43 seconds
Started Jul 27 05:50:05 PM PDT 24
Finished Jul 27 06:00:12 PM PDT 24
Peak memory 623576 kb
Host smart-51d355d9-2c54-4093-8ce8-f7a69abbc9e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847628867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3847628867
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3713582229
Short name T421
Test name
Test status
Simulation time 85674556232 ps
CPU time 206.93 seconds
Started Jul 27 05:50:02 PM PDT 24
Finished Jul 27 05:53:29 PM PDT 24
Peak memory 199772 kb
Host smart-1a0992fb-66d8-423b-8798-e23ada3c230f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713582229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3713582229
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1468903547
Short name T389
Test name
Test status
Simulation time 15697500245 ps
CPU time 137.04 seconds
Started Jul 27 05:50:02 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 199788 kb
Host smart-f24632bb-cffd-4924-ad34-01dcad50729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468903547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1468903547
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2793638258
Short name T275
Test name
Test status
Simulation time 413028228 ps
CPU time 7.77 seconds
Started Jul 27 05:50:02 PM PDT 24
Finished Jul 27 05:50:10 PM PDT 24
Peak memory 199632 kb
Host smart-17970db0-576e-49a6-9171-771b4a1a1298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793638258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2793638258
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1236660753
Short name T77
Test name
Test status
Simulation time 61260452675 ps
CPU time 891.78 seconds
Started Jul 27 05:50:02 PM PDT 24
Finished Jul 27 06:04:54 PM PDT 24
Peak memory 714412 kb
Host smart-cb9d5ce5-1f76-4549-943a-97a362c94c03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236660753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1236660753
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.93898823
Short name T92
Test name
Test status
Simulation time 3130974369 ps
CPU time 78.74 seconds
Started Jul 27 05:50:11 PM PDT 24
Finished Jul 27 05:51:30 PM PDT 24
Peak memory 199628 kb
Host smart-ada7593c-2320-4931-be79-241f11bfaa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93898823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.93898823
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2261441264
Short name T151
Test name
Test status
Simulation time 24039970 ps
CPU time 0.76 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:06 PM PDT 24
Peak memory 195660 kb
Host smart-491135e6-7dac-468b-a20b-3b1fe9b4bdcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261441264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2261441264
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3812993959
Short name T376
Test name
Test status
Simulation time 1122979233 ps
CPU time 62.4 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:49:55 PM PDT 24
Peak memory 199928 kb
Host smart-5e186b0c-ffcd-4ba0-af89-3715c6d66094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812993959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3812993959
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.85913604
Short name T233
Test name
Test status
Simulation time 4363457204 ps
CPU time 27.35 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:49:22 PM PDT 24
Peak memory 207984 kb
Host smart-da83f127-e562-45c5-ab4a-46ca1692e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85913604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.85913604
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2286175719
Short name T484
Test name
Test status
Simulation time 5663579284 ps
CPU time 1070.35 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 06:06:43 PM PDT 24
Peak memory 736768 kb
Host smart-122de67e-646a-4631-b0f7-ed92109033cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286175719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2286175719
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1676167380
Short name T81
Test name
Test status
Simulation time 9714621361 ps
CPU time 175.44 seconds
Started Jul 27 05:48:54 PM PDT 24
Finished Jul 27 05:51:49 PM PDT 24
Peak memory 199772 kb
Host smart-d8fd0dad-49ea-4b8c-84de-46101c0a1eae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676167380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1676167380
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1827376774
Short name T299
Test name
Test status
Simulation time 7657681671 ps
CPU time 143.71 seconds
Started Jul 27 05:48:53 PM PDT 24
Finished Jul 27 05:51:16 PM PDT 24
Peak memory 199968 kb
Host smart-aaad99ce-ef85-41e9-8f98-b0f2ca42203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827376774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1827376774
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.530198046
Short name T48
Test name
Test status
Simulation time 151779501 ps
CPU time 0.87 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:49:03 PM PDT 24
Peak memory 218184 kb
Host smart-57a91daa-90f3-4db3-8cae-31dbacc7fd6c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530198046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.530198046
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1102667532
Short name T410
Test name
Test status
Simulation time 89087349 ps
CPU time 4.29 seconds
Started Jul 27 05:48:55 PM PDT 24
Finished Jul 27 05:48:59 PM PDT 24
Peak memory 199716 kb
Host smart-f617889a-4c9c-43d0-b56b-53455f73a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102667532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1102667532
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2329104511
Short name T305
Test name
Test status
Simulation time 194120652 ps
CPU time 8.92 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:49:11 PM PDT 24
Peak memory 199672 kb
Host smart-8b6f6c8d-31b8-49de-8756-b4f26a053ac9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329104511 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2329104511
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3631712527
Short name T12
Test name
Test status
Simulation time 893656233761 ps
CPU time 6143.8 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 07:31:26 PM PDT 24
Peak memory 831236 kb
Host smart-5737d24e-07c1-4cc1-bc21-2c3f13c95e0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631712527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3631712527
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.981979353
Short name T429
Test name
Test status
Simulation time 7392569300 ps
CPU time 44.48 seconds
Started Jul 27 05:49:00 PM PDT 24
Finished Jul 27 05:49:44 PM PDT 24
Peak memory 199776 kb
Host smart-0a1ca049-d227-4b40-9ef4-10c5fa9ed740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=981979353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.981979353
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.4036300295
Short name T359
Test name
Test status
Simulation time 2489034755 ps
CPU time 96.26 seconds
Started Jul 27 05:48:59 PM PDT 24
Finished Jul 27 05:50:36 PM PDT 24
Peak memory 199760 kb
Host smart-6f6d40e4-b59b-4333-af9e-a4cba71314da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4036300295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.4036300295
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.608189429
Short name T350
Test name
Test status
Simulation time 8340877408 ps
CPU time 129.95 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:51:15 PM PDT 24
Peak memory 199860 kb
Host smart-e636436a-34da-4b7c-bd80-55410cbca293
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=608189429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.608189429
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1301275664
Short name T450
Test name
Test status
Simulation time 47998510290 ps
CPU time 626.62 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:59:29 PM PDT 24
Peak memory 199784 kb
Host smart-6a50d4d3-ac03-40c7-bb8f-58a18ce04501
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1301275664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1301275664
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2860742634
Short name T150
Test name
Test status
Simulation time 202833825465 ps
CPU time 2484.44 seconds
Started Jul 27 05:49:06 PM PDT 24
Finished Jul 27 06:30:31 PM PDT 24
Peak memory 216076 kb
Host smart-b4997aac-1855-46aa-b3f8-645b587a794e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2860742634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2860742634
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1660496186
Short name T7
Test name
Test status
Simulation time 39728774600 ps
CPU time 2188.13 seconds
Started Jul 27 05:49:04 PM PDT 24
Finished Jul 27 06:25:33 PM PDT 24
Peak memory 215380 kb
Host smart-bca4b660-87c6-4106-b099-057d885493de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1660496186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1660496186
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3199853244
Short name T121
Test name
Test status
Simulation time 4509972808 ps
CPU time 93.5 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:50:37 PM PDT 24
Peak memory 199732 kb
Host smart-717e0e65-3465-4ba0-8dcc-91bba2ee0540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199853244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3199853244
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1534417887
Short name T309
Test name
Test status
Simulation time 59351492 ps
CPU time 0.61 seconds
Started Jul 27 05:50:11 PM PDT 24
Finished Jul 27 05:50:12 PM PDT 24
Peak memory 195720 kb
Host smart-d8d40bf3-7fcb-4ddf-a725-fe6cb6ea2083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534417887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1534417887
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1019455362
Short name T252
Test name
Test status
Simulation time 3928010759 ps
CPU time 58.56 seconds
Started Jul 27 05:50:04 PM PDT 24
Finished Jul 27 05:51:03 PM PDT 24
Peak memory 216116 kb
Host smart-314781f1-e692-4ac4-b1b8-6166794041f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019455362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1019455362
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4126569409
Short name T347
Test name
Test status
Simulation time 8675237378 ps
CPU time 42.67 seconds
Started Jul 27 05:50:03 PM PDT 24
Finished Jul 27 05:50:45 PM PDT 24
Peak memory 199772 kb
Host smart-89c95cdd-cf4e-45ae-a588-bb1c10d3221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126569409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4126569409
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3950867932
Short name T244
Test name
Test status
Simulation time 205424569 ps
CPU time 11.06 seconds
Started Jul 27 05:50:01 PM PDT 24
Finished Jul 27 05:50:12 PM PDT 24
Peak memory 216196 kb
Host smart-7c035022-957f-4ea4-99cc-76092f8dab64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950867932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3950867932
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2473051152
Short name T437
Test name
Test status
Simulation time 8906376253 ps
CPU time 118.29 seconds
Started Jul 27 05:50:06 PM PDT 24
Finished Jul 27 05:52:04 PM PDT 24
Peak memory 199800 kb
Host smart-280904f7-e080-4877-a5f4-877b2e05e1bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473051152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2473051152
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.64017719
Short name T54
Test name
Test status
Simulation time 15111957922 ps
CPU time 69.22 seconds
Started Jul 27 05:50:07 PM PDT 24
Finished Jul 27 05:51:16 PM PDT 24
Peak memory 199716 kb
Host smart-33e2846a-d0e8-44de-8e41-755f558f2254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64017719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.64017719
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.13583905
Short name T490
Test name
Test status
Simulation time 326239759 ps
CPU time 4.78 seconds
Started Jul 27 05:50:06 PM PDT 24
Finished Jul 27 05:50:11 PM PDT 24
Peak memory 199660 kb
Host smart-58e72dba-b59f-4c49-b409-117fb0e9829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13583905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.13583905
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.4096342204
Short name T390
Test name
Test status
Simulation time 8790865533 ps
CPU time 462.32 seconds
Started Jul 27 05:50:10 PM PDT 24
Finished Jul 27 05:57:53 PM PDT 24
Peak memory 199736 kb
Host smart-0499d23f-cc97-4dee-8ee8-c91930acc911
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096342204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4096342204
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1029365403
Short name T82
Test name
Test status
Simulation time 13518019214 ps
CPU time 62.56 seconds
Started Jul 27 05:50:12 PM PDT 24
Finished Jul 27 05:51:15 PM PDT 24
Peak memory 199684 kb
Host smart-aa581cc8-5edc-4258-9745-df257808ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029365403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1029365403
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2037337475
Short name T156
Test name
Test status
Simulation time 51860078 ps
CPU time 0.56 seconds
Started Jul 27 05:50:08 PM PDT 24
Finished Jul 27 05:50:09 PM PDT 24
Peak memory 194624 kb
Host smart-ca040d1a-34ed-4ad6-b79a-fbf58ab1c48a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037337475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2037337475
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1597058234
Short name T459
Test name
Test status
Simulation time 12125870424 ps
CPU time 79.31 seconds
Started Jul 27 05:50:10 PM PDT 24
Finished Jul 27 05:51:29 PM PDT 24
Peak memory 199776 kb
Host smart-4a55881e-736f-4826-b37f-8410b62fe374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597058234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1597058234
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1797581565
Short name T174
Test name
Test status
Simulation time 4494912350 ps
CPU time 55.34 seconds
Started Jul 27 05:50:10 PM PDT 24
Finished Jul 27 05:51:05 PM PDT 24
Peak memory 199688 kb
Host smart-09a1573d-8224-412e-a634-2afddb7b5b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797581565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1797581565
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1420827567
Short name T331
Test name
Test status
Simulation time 380282567 ps
CPU time 60.7 seconds
Started Jul 27 05:50:11 PM PDT 24
Finished Jul 27 05:51:12 PM PDT 24
Peak memory 342212 kb
Host smart-2cca7842-6b66-47f9-9f12-ea4bdd2f2dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420827567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1420827567
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.4090857868
Short name T165
Test name
Test status
Simulation time 107950866108 ps
CPU time 66.6 seconds
Started Jul 27 05:50:10 PM PDT 24
Finished Jul 27 05:51:17 PM PDT 24
Peak memory 199796 kb
Host smart-d9a03125-1f74-4162-bf25-bf0812885fdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090857868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.4090857868
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3385916987
Short name T218
Test name
Test status
Simulation time 2366513485 ps
CPU time 137.17 seconds
Started Jul 27 05:50:09 PM PDT 24
Finished Jul 27 05:52:27 PM PDT 24
Peak memory 199732 kb
Host smart-1e73f4d3-bb95-4507-8a9d-c906b0afea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385916987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3385916987
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1240987206
Short name T499
Test name
Test status
Simulation time 200134661 ps
CPU time 3.99 seconds
Started Jul 27 05:50:11 PM PDT 24
Finished Jul 27 05:50:15 PM PDT 24
Peak memory 199712 kb
Host smart-b2794a69-9972-4d9a-a40e-162b568a2846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240987206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1240987206
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2574258875
Short name T230
Test name
Test status
Simulation time 554190685 ps
CPU time 9.52 seconds
Started Jul 27 05:50:09 PM PDT 24
Finished Jul 27 05:50:18 PM PDT 24
Peak memory 199728 kb
Host smart-8a5610e2-8af6-4302-8121-e762d1b5676b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574258875 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2574258875
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.142129138
Short name T158
Test name
Test status
Simulation time 257390077 ps
CPU time 4.37 seconds
Started Jul 27 05:50:08 PM PDT 24
Finished Jul 27 05:50:13 PM PDT 24
Peak memory 199664 kb
Host smart-59f02e64-19f2-4dda-8ae7-a19f529ffa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142129138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.142129138
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2648093705
Short name T188
Test name
Test status
Simulation time 55651448 ps
CPU time 0.56 seconds
Started Jul 27 05:50:16 PM PDT 24
Finished Jul 27 05:50:16 PM PDT 24
Peak memory 195316 kb
Host smart-838c8150-4d7e-4713-a46c-785d62cf2aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648093705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2648093705
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2090157025
Short name T198
Test name
Test status
Simulation time 3311384858 ps
CPU time 56.69 seconds
Started Jul 27 05:50:11 PM PDT 24
Finished Jul 27 05:51:08 PM PDT 24
Peak memory 199840 kb
Host smart-af4510ac-13e2-4ade-a114-5be48e8fc23f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090157025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2090157025
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.766303775
Short name T385
Test name
Test status
Simulation time 14655336572 ps
CPU time 31.13 seconds
Started Jul 27 05:50:12 PM PDT 24
Finished Jul 27 05:50:43 PM PDT 24
Peak memory 199752 kb
Host smart-d71a13bd-a6d4-4267-831e-434d484fdc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766303775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.766303775
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3462320714
Short name T195
Test name
Test status
Simulation time 2484465446 ps
CPU time 448.99 seconds
Started Jul 27 05:50:10 PM PDT 24
Finished Jul 27 05:57:39 PM PDT 24
Peak memory 678128 kb
Host smart-ec31dfa4-2daa-421a-9d23-78a0e2f5a236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3462320714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3462320714
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2323650419
Short name T140
Test name
Test status
Simulation time 16179365419 ps
CPU time 180.83 seconds
Started Jul 27 05:50:09 PM PDT 24
Finished Jul 27 05:53:10 PM PDT 24
Peak memory 199732 kb
Host smart-99db5490-8bdb-471c-9fd4-53df633e9957
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323650419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2323650419
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1654263447
Short name T478
Test name
Test status
Simulation time 7268410239 ps
CPU time 100.3 seconds
Started Jul 27 05:50:10 PM PDT 24
Finished Jul 27 05:51:50 PM PDT 24
Peak memory 199784 kb
Host smart-ae5719e8-3e13-4e75-8e22-82803e65274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654263447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1654263447
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2046778675
Short name T279
Test name
Test status
Simulation time 3802701712 ps
CPU time 11.04 seconds
Started Jul 27 05:50:12 PM PDT 24
Finished Jul 27 05:50:23 PM PDT 24
Peak memory 199728 kb
Host smart-b37acbca-08ad-4185-9d87-2b6c6b2d95f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046778675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2046778675
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.324936499
Short name T340
Test name
Test status
Simulation time 344398464457 ps
CPU time 2871.84 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 06:38:15 PM PDT 24
Peak memory 751112 kb
Host smart-60826353-0356-4238-806d-c0b149ba91f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324936499 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.324936499
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1695217628
Short name T495
Test name
Test status
Simulation time 1432535468 ps
CPU time 5.14 seconds
Started Jul 27 05:50:09 PM PDT 24
Finished Jul 27 05:50:14 PM PDT 24
Peak memory 199652 kb
Host smart-f6826e35-7555-4358-8606-132e001258f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695217628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1695217628
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.25049690
Short name T70
Test name
Test status
Simulation time 13180968 ps
CPU time 0.57 seconds
Started Jul 27 05:50:15 PM PDT 24
Finished Jul 27 05:50:15 PM PDT 24
Peak memory 194592 kb
Host smart-77424c8f-8f0f-4f1c-8f5d-4650a9b0cd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25049690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.25049690
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1040528888
Short name T491
Test name
Test status
Simulation time 5643423193 ps
CPU time 80.54 seconds
Started Jul 27 05:50:15 PM PDT 24
Finished Jul 27 05:51:35 PM PDT 24
Peak memory 199816 kb
Host smart-1a8445fe-2ae4-4aa9-9ab7-1671da06f437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040528888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1040528888
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1336797779
Short name T295
Test name
Test status
Simulation time 3833391047 ps
CPU time 26.42 seconds
Started Jul 27 05:50:14 PM PDT 24
Finished Jul 27 05:50:41 PM PDT 24
Peak memory 199720 kb
Host smart-7e0aec3e-e098-4ed8-9bbd-b186d7cce0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336797779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1336797779
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.508265825
Short name T183
Test name
Test status
Simulation time 20372844569 ps
CPU time 646.57 seconds
Started Jul 27 05:50:15 PM PDT 24
Finished Jul 27 06:01:01 PM PDT 24
Peak memory 720528 kb
Host smart-51bd8f0b-de88-47bb-bd3a-1bab0f076fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508265825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.508265825
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2196377942
Short name T14
Test name
Test status
Simulation time 18132699694 ps
CPU time 161.44 seconds
Started Jul 27 05:50:15 PM PDT 24
Finished Jul 27 05:52:56 PM PDT 24
Peak memory 199728 kb
Host smart-962ce652-e6ad-40f6-8738-3df8777272cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196377942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2196377942
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.593498128
Short name T494
Test name
Test status
Simulation time 1552013020 ps
CPU time 22.46 seconds
Started Jul 27 05:50:15 PM PDT 24
Finished Jul 27 05:50:38 PM PDT 24
Peak memory 199820 kb
Host smart-05c2a996-e51a-4a48-8c55-518309d1103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593498128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.593498128
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3378338506
Short name T194
Test name
Test status
Simulation time 328165335 ps
CPU time 5.97 seconds
Started Jul 27 05:50:16 PM PDT 24
Finished Jul 27 05:50:22 PM PDT 24
Peak memory 199768 kb
Host smart-78ca6f9a-1ca5-41f7-8251-2a260a208e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378338506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3378338506
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2985652111
Short name T401
Test name
Test status
Simulation time 80291495395 ps
CPU time 1750.98 seconds
Started Jul 27 05:50:16 PM PDT 24
Finished Jul 27 06:19:28 PM PDT 24
Peak memory 671248 kb
Host smart-d6dd53a6-2130-4e89-ad9c-fea23c345fcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985652111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2985652111
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1363652882
Short name T436
Test name
Test status
Simulation time 3340644078 ps
CPU time 138.2 seconds
Started Jul 27 05:50:22 PM PDT 24
Finished Jul 27 05:52:41 PM PDT 24
Peak memory 199740 kb
Host smart-438d8097-d5e6-4fcd-be70-9a5ad36f32e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363652882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1363652882
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1954161197
Short name T509
Test name
Test status
Simulation time 20119291 ps
CPU time 0.6 seconds
Started Jul 27 05:50:22 PM PDT 24
Finished Jul 27 05:50:23 PM PDT 24
Peak memory 195716 kb
Host smart-f4e8d3ca-b02f-4b57-8623-1d12a4eb0e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954161197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1954161197
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.764471337
Short name T428
Test name
Test status
Simulation time 719355373 ps
CPU time 42.9 seconds
Started Jul 27 05:50:25 PM PDT 24
Finished Jul 27 05:51:08 PM PDT 24
Peak memory 199748 kb
Host smart-fd3bd448-0d0e-419e-a33c-c3533e7ae5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764471337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.764471337
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4272821639
Short name T343
Test name
Test status
Simulation time 546572848 ps
CPU time 2.27 seconds
Started Jul 27 05:50:22 PM PDT 24
Finished Jul 27 05:50:25 PM PDT 24
Peak memory 199708 kb
Host smart-1b803202-5468-4a29-a814-8e2636525420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272821639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4272821639
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2600171414
Short name T293
Test name
Test status
Simulation time 3526936250 ps
CPU time 728.93 seconds
Started Jul 27 05:50:22 PM PDT 24
Finished Jul 27 06:02:31 PM PDT 24
Peak memory 742036 kb
Host smart-a817775c-61fa-4110-aa10-ab453c378e92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600171414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2600171414
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.481005072
Short name T486
Test name
Test status
Simulation time 4049597523 ps
CPU time 110.76 seconds
Started Jul 27 05:50:17 PM PDT 24
Finished Jul 27 05:52:08 PM PDT 24
Peak memory 199776 kb
Host smart-2a39fa55-c228-4514-83a9-e5c73835f5b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481005072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.481005072
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2475098695
Short name T454
Test name
Test status
Simulation time 28525426612 ps
CPU time 179.32 seconds
Started Jul 27 05:50:15 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 199796 kb
Host smart-9a4e8038-5bb0-4adf-ac49-1564753bdd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475098695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2475098695
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3512048417
Short name T327
Test name
Test status
Simulation time 1095609407 ps
CPU time 13.1 seconds
Started Jul 27 05:50:18 PM PDT 24
Finished Jul 27 05:50:31 PM PDT 24
Peak memory 199680 kb
Host smart-c0d9c437-ec46-4e3d-b344-8d76e8aff98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512048417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3512048417
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2174145902
Short name T74
Test name
Test status
Simulation time 454424814968 ps
CPU time 3056.76 seconds
Started Jul 27 05:50:15 PM PDT 24
Finished Jul 27 06:41:12 PM PDT 24
Peak memory 754984 kb
Host smart-8fe2f5d7-3d59-4f4f-8674-77712bda7c86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174145902 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2174145902
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.705989210
Short name T84
Test name
Test status
Simulation time 1033427933 ps
CPU time 18.51 seconds
Started Jul 27 05:50:25 PM PDT 24
Finished Jul 27 05:50:43 PM PDT 24
Peak memory 199772 kb
Host smart-6e1ca539-3dff-4ff1-9a3d-30b580beb2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705989210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.705989210
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.4088487594
Short name T28
Test name
Test status
Simulation time 32612494 ps
CPU time 0.57 seconds
Started Jul 27 05:50:21 PM PDT 24
Finished Jul 27 05:50:22 PM PDT 24
Peak memory 194688 kb
Host smart-d85bd960-6401-4e81-8326-50c69e9dbba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088487594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.4088487594
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.685580358
Short name T141
Test name
Test status
Simulation time 3858208529 ps
CPU time 57 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 05:51:20 PM PDT 24
Peak memory 199784 kb
Host smart-9fd49526-6d1a-4190-bbe6-a3bf037e100f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685580358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.685580358
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.716351662
Short name T208
Test name
Test status
Simulation time 909876966 ps
CPU time 13.61 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 05:50:37 PM PDT 24
Peak memory 199728 kb
Host smart-0cc55e0c-7f95-46ff-b769-3f6500aba2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716351662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.716351662
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.4146182132
Short name T258
Test name
Test status
Simulation time 843522729 ps
CPU time 134.88 seconds
Started Jul 27 05:50:22 PM PDT 24
Finished Jul 27 05:52:37 PM PDT 24
Peak memory 602700 kb
Host smart-f7e23b15-1be5-46c0-a543-0166c38cd355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146182132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4146182132
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2156946986
Short name T360
Test name
Test status
Simulation time 13287716451 ps
CPU time 84.76 seconds
Started Jul 27 05:50:24 PM PDT 24
Finished Jul 27 05:51:49 PM PDT 24
Peak memory 199820 kb
Host smart-be42e094-2647-4e23-9ac1-daf71ed54649
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156946986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2156946986
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3667450419
Short name T445
Test name
Test status
Simulation time 10818411637 ps
CPU time 122.58 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 05:52:26 PM PDT 24
Peak memory 199752 kb
Host smart-e4e36eb3-d073-4d81-8868-c460edd407fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667450419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3667450419
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.584105173
Short name T427
Test name
Test status
Simulation time 196529622 ps
CPU time 3.44 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 05:50:26 PM PDT 24
Peak memory 199772 kb
Host smart-21214127-c26d-44ff-8668-7e61bd814545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584105173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.584105173
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.154632559
Short name T207
Test name
Test status
Simulation time 9499425585 ps
CPU time 1177.73 seconds
Started Jul 27 05:50:22 PM PDT 24
Finished Jul 27 06:10:00 PM PDT 24
Peak memory 762228 kb
Host smart-79d59088-050b-419b-aa3e-e5b13bc51006
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154632559 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.154632559
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3347080895
Short name T119
Test name
Test status
Simulation time 351563240 ps
CPU time 11.86 seconds
Started Jul 27 05:50:24 PM PDT 24
Finished Jul 27 05:50:36 PM PDT 24
Peak memory 199676 kb
Host smart-b16aa416-10ab-4da7-9b74-5b05041760d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347080895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3347080895
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3802590965
Short name T166
Test name
Test status
Simulation time 20411247 ps
CPU time 0.63 seconds
Started Jul 27 05:50:32 PM PDT 24
Finished Jul 27 05:50:32 PM PDT 24
Peak memory 195356 kb
Host smart-882a5d2c-5a64-40ef-98c6-0c034e2b607f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802590965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3802590965
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3422242279
Short name T255
Test name
Test status
Simulation time 193487524 ps
CPU time 3.16 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 05:50:26 PM PDT 24
Peak memory 199664 kb
Host smart-0a9fa351-d9c4-4385-b65e-53a595a5e3c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422242279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3422242279
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.870129860
Short name T485
Test name
Test status
Simulation time 7257806711 ps
CPU time 49.57 seconds
Started Jul 27 05:50:25 PM PDT 24
Finished Jul 27 05:51:15 PM PDT 24
Peak memory 207940 kb
Host smart-4c4c0cf3-fb83-4db4-bc0b-fcf6db6be304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870129860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.870129860
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1306972245
Short name T51
Test name
Test status
Simulation time 22432518882 ps
CPU time 1064.2 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 06:08:08 PM PDT 24
Peak memory 716228 kb
Host smart-4a13d993-5efa-49c1-8c0a-890d1274f247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306972245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1306972245
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.298100343
Short name T530
Test name
Test status
Simulation time 15670998672 ps
CPU time 59.26 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 05:51:28 PM PDT 24
Peak memory 199680 kb
Host smart-8898bf21-b371-4b85-88bc-4ac067a7396f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298100343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.298100343
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3209645159
Short name T30
Test name
Test status
Simulation time 474968157 ps
CPU time 25.02 seconds
Started Jul 27 05:50:23 PM PDT 24
Finished Jul 27 05:50:48 PM PDT 24
Peak memory 199716 kb
Host smart-6a82e405-2c2b-4fd1-8280-96d38ef008c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209645159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3209645159
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3017483735
Short name T311
Test name
Test status
Simulation time 1575217752 ps
CPU time 15.75 seconds
Started Jul 27 05:50:24 PM PDT 24
Finished Jul 27 05:50:40 PM PDT 24
Peak memory 199720 kb
Host smart-9835dd16-27e8-45d6-b591-0771b9f687c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017483735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3017483735
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1704858909
Short name T452
Test name
Test status
Simulation time 25925361056 ps
CPU time 3774.72 seconds
Started Jul 27 05:50:27 PM PDT 24
Finished Jul 27 06:53:22 PM PDT 24
Peak memory 825716 kb
Host smart-76d3e976-55ab-4d33-827a-fe4acfc23ae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704858909 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1704858909
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1352155155
Short name T404
Test name
Test status
Simulation time 16057379208 ps
CPU time 108.89 seconds
Started Jul 27 05:50:30 PM PDT 24
Finished Jul 27 05:52:19 PM PDT 24
Peak memory 199752 kb
Host smart-4f1598e0-090d-4234-bc6e-b31ef66107bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352155155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1352155155
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3800582854
Short name T222
Test name
Test status
Simulation time 21122732 ps
CPU time 0.59 seconds
Started Jul 27 05:50:31 PM PDT 24
Finished Jul 27 05:50:32 PM PDT 24
Peak memory 196388 kb
Host smart-bc431a7d-e949-499b-82be-ac2b7d1d76f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800582854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3800582854
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3698569115
Short name T133
Test name
Test status
Simulation time 14145607771 ps
CPU time 105.02 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 05:52:13 PM PDT 24
Peak memory 216144 kb
Host smart-63422a07-860e-411e-91f6-200f420ea80a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698569115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3698569115
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4278202305
Short name T209
Test name
Test status
Simulation time 1266678693 ps
CPU time 22.59 seconds
Started Jul 27 05:50:30 PM PDT 24
Finished Jul 27 05:50:53 PM PDT 24
Peak memory 199684 kb
Host smart-4ebb24af-8136-4257-a48a-08c03a0c95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278202305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4278202305
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2091402777
Short name T318
Test name
Test status
Simulation time 42220747286 ps
CPU time 568.4 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:59:58 PM PDT 24
Peak memory 666688 kb
Host smart-f1d9abf9-9bbf-4207-a519-ae4206dd54b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091402777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2091402777
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3166049994
Short name T39
Test name
Test status
Simulation time 1253689324 ps
CPU time 35.12 seconds
Started Jul 27 05:50:31 PM PDT 24
Finished Jul 27 05:51:06 PM PDT 24
Peak memory 199680 kb
Host smart-2f75c0bc-8a32-4bdc-a4f2-980608755c8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166049994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3166049994
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.5301021
Short name T288
Test name
Test status
Simulation time 3095793505 ps
CPU time 165.11 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 05:53:14 PM PDT 24
Peak memory 199748 kb
Host smart-d4e5839f-34a8-4130-8f33-9d258c7e11ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5301021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.5301021
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3470868344
Short name T342
Test name
Test status
Simulation time 419388494 ps
CPU time 5.24 seconds
Started Jul 27 05:50:30 PM PDT 24
Finished Jul 27 05:50:35 PM PDT 24
Peak memory 199716 kb
Host smart-b8f93024-b2cf-491b-92c9-c3f86bb0985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470868344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3470868344
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1645373775
Short name T71
Test name
Test status
Simulation time 188126678972 ps
CPU time 2342.61 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 06:29:32 PM PDT 24
Peak memory 770276 kb
Host smart-6f73f464-a8a2-420f-b31c-129f6ba95269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645373775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1645373775
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2311403475
Short name T463
Test name
Test status
Simulation time 7220166413 ps
CPU time 132.12 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:52:42 PM PDT 24
Peak memory 199716 kb
Host smart-42cefc97-4278-4f46-ade2-f4d41348155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311403475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2311403475
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3796206191
Short name T196
Test name
Test status
Simulation time 50118260 ps
CPU time 0.6 seconds
Started Jul 27 05:50:30 PM PDT 24
Finished Jul 27 05:50:31 PM PDT 24
Peak memory 196364 kb
Host smart-def73107-250c-41dc-bea7-ad426f081967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796206191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3796206191
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3992399836
Short name T416
Test name
Test status
Simulation time 25140289134 ps
CPU time 91.26 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:52:00 PM PDT 24
Peak memory 215192 kb
Host smart-8fb29dee-75b0-42c5-96e1-10b6661c8976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3992399836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3992399836
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.12713721
Short name T267
Test name
Test status
Simulation time 560343163 ps
CPU time 2.52 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:50:31 PM PDT 24
Peak memory 199632 kb
Host smart-7a76cf61-c701-466f-8abc-7564f9a2d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12713721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.12713721
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2816172777
Short name T353
Test name
Test status
Simulation time 72912290 ps
CPU time 4.92 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 05:50:33 PM PDT 24
Peak memory 207944 kb
Host smart-89e19aaf-153e-4084-9e17-8d82e60a7b55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2816172777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2816172777
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2674721623
Short name T403
Test name
Test status
Simulation time 5082299946 ps
CPU time 40.57 seconds
Started Jul 27 05:50:30 PM PDT 24
Finished Jul 27 05:51:10 PM PDT 24
Peak memory 199776 kb
Host smart-c067a931-f2ea-4920-98e4-e2f4a365f421
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674721623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2674721623
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2674708673
Short name T388
Test name
Test status
Simulation time 8543029914 ps
CPU time 126.11 seconds
Started Jul 27 05:50:30 PM PDT 24
Finished Jul 27 05:52:37 PM PDT 24
Peak memory 199936 kb
Host smart-b61734a9-a1ad-4330-ae34-9354f81d2b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674708673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2674708673
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2929938835
Short name T246
Test name
Test status
Simulation time 165541904 ps
CPU time 7.27 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 05:50:35 PM PDT 24
Peak memory 199680 kb
Host smart-c07eda28-7f84-45ea-b74d-9728bc0dccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929938835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2929938835
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2261212324
Short name T25
Test name
Test status
Simulation time 28233370880 ps
CPU time 3636.73 seconds
Started Jul 27 05:50:31 PM PDT 24
Finished Jul 27 06:51:08 PM PDT 24
Peak memory 871456 kb
Host smart-b831a625-8ca4-4e5e-ad45-e7bda115c665
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261212324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2261212324
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1388983093
Short name T280
Test name
Test status
Simulation time 26883750503 ps
CPU time 127.46 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 05:52:36 PM PDT 24
Peak memory 199780 kb
Host smart-f238c2ec-e2d0-44c2-9aff-7cba8f8a6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388983093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1388983093
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3175258453
Short name T479
Test name
Test status
Simulation time 20124872 ps
CPU time 0.61 seconds
Started Jul 27 05:50:35 PM PDT 24
Finished Jul 27 05:50:36 PM PDT 24
Peak memory 196404 kb
Host smart-fe605c04-47e2-466f-8383-796bf855d2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175258453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3175258453
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.945863408
Short name T266
Test name
Test status
Simulation time 1683466155 ps
CPU time 47.08 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:51:16 PM PDT 24
Peak memory 199708 kb
Host smart-fa491f70-0742-4693-9838-e2b3350f7174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945863408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.945863408
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.766860465
Short name T435
Test name
Test status
Simulation time 671415586 ps
CPU time 12.14 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 05:50:41 PM PDT 24
Peak memory 199712 kb
Host smart-cd6ab679-7129-49c5-8849-dae945edd3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766860465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.766860465
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3580747064
Short name T180
Test name
Test status
Simulation time 24195813797 ps
CPU time 836.03 seconds
Started Jul 27 05:50:28 PM PDT 24
Finished Jul 27 06:04:25 PM PDT 24
Peak memory 685288 kb
Host smart-8a25dfc3-e820-4dfd-9eb0-1d90a4469cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580747064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3580747064
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2534159267
Short name T326
Test name
Test status
Simulation time 28666506323 ps
CPU time 102.43 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:52:11 PM PDT 24
Peak memory 199944 kb
Host smart-b8141880-417e-4db8-b859-1107b574d619
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534159267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2534159267
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1946070797
Short name T213
Test name
Test status
Simulation time 1623931413 ps
CPU time 84.5 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:51:54 PM PDT 24
Peak memory 199716 kb
Host smart-b4728870-b20b-4213-ad36-b4b1286a68a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946070797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1946070797
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.576158029
Short name T363
Test name
Test status
Simulation time 1098590242 ps
CPU time 12.73 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:50:41 PM PDT 24
Peak memory 199720 kb
Host smart-5e2bf239-ad0e-414f-bd3e-8e4a3a570874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576158029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.576158029
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2238317862
Short name T179
Test name
Test status
Simulation time 2284157571 ps
CPU time 119.82 seconds
Started Jul 27 05:50:35 PM PDT 24
Finished Jul 27 05:52:35 PM PDT 24
Peak memory 199800 kb
Host smart-327b693a-17b3-4d92-9ad0-c56c785f613f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238317862 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2238317862
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2911232075
Short name T313
Test name
Test status
Simulation time 6900224718 ps
CPU time 16.1 seconds
Started Jul 27 05:50:29 PM PDT 24
Finished Jul 27 05:50:45 PM PDT 24
Peak memory 199780 kb
Host smart-1202e1d7-a9ac-447e-bc60-9375a38f5b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911232075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2911232075
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2277120145
Short name T42
Test name
Test status
Simulation time 44283638 ps
CPU time 0.6 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 05:49:02 PM PDT 24
Peak memory 195720 kb
Host smart-aab109c6-4283-497f-8005-cdfab1e84c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277120145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2277120145
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3859998446
Short name T215
Test name
Test status
Simulation time 4937436926 ps
CPU time 32.92 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:49:35 PM PDT 24
Peak memory 199748 kb
Host smart-6cb2f5fb-0b91-439b-9ddf-009755c2bee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859998446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3859998446
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2682757835
Short name T373
Test name
Test status
Simulation time 342229615 ps
CPU time 5.26 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:49:09 PM PDT 24
Peak memory 199708 kb
Host smart-40e62239-1464-4a53-9296-983501676bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682757835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2682757835
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3538566128
Short name T139
Test name
Test status
Simulation time 22541025819 ps
CPU time 1027 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 06:06:08 PM PDT 24
Peak memory 699436 kb
Host smart-c71c54fd-ab6c-420e-a81e-83a76890c318
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538566128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3538566128
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.94125681
Short name T377
Test name
Test status
Simulation time 4340175811 ps
CPU time 141.64 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:51:24 PM PDT 24
Peak memory 199728 kb
Host smart-1094fc1a-6d35-4e53-8f9c-47f0b3b37cae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94125681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.94125681
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.205996976
Short name T425
Test name
Test status
Simulation time 2781993488 ps
CPU time 167.37 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:51:53 PM PDT 24
Peak memory 216004 kb
Host smart-ff7268f3-64f9-4ec3-b314-47a5a65af183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205996976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.205996976
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1862806944
Short name T472
Test name
Test status
Simulation time 195741206 ps
CPU time 2.88 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 05:49:04 PM PDT 24
Peak memory 199684 kb
Host smart-81303ef9-dcfd-4576-9add-c7071e46d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862806944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1862806944
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3666175656
Short name T201
Test name
Test status
Simulation time 68984968799 ps
CPU time 2088.62 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 06:23:51 PM PDT 24
Peak memory 721972 kb
Host smart-57bb72e5-c722-450b-8f8f-3893ddb716b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666175656 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3666175656
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.869565833
Short name T221
Test name
Test status
Simulation time 12437132201 ps
CPU time 157.69 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:51:41 PM PDT 24
Peak memory 199700 kb
Host smart-d100326e-9960-483c-867a-240d378e3dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869565833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.869565833
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1037934642
Short name T170
Test name
Test status
Simulation time 17335716 ps
CPU time 0.59 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:49:03 PM PDT 24
Peak memory 194708 kb
Host smart-06dd3c0f-47f3-4025-a64e-45875bf837a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037934642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1037934642
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.167630918
Short name T511
Test name
Test status
Simulation time 3799994518 ps
CPU time 99.14 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:50:42 PM PDT 24
Peak memory 199500 kb
Host smart-8e47ca60-03dc-4797-abf0-e1d1d74664b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167630918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.167630918
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4154469955
Short name T349
Test name
Test status
Simulation time 1800052278 ps
CPU time 33.93 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:49:36 PM PDT 24
Peak memory 199764 kb
Host smart-a20b15a7-37e3-479e-9d81-3ed5ce76f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154469955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4154469955
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2767341298
Short name T334
Test name
Test status
Simulation time 4338394589 ps
CPU time 584.33 seconds
Started Jul 27 05:49:04 PM PDT 24
Finished Jul 27 05:58:48 PM PDT 24
Peak memory 665992 kb
Host smart-c207b7a8-8723-4b43-84a8-639dc67246d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767341298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2767341298
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1937105307
Short name T29
Test name
Test status
Simulation time 6705411270 ps
CPU time 86.56 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:50:30 PM PDT 24
Peak memory 199752 kb
Host smart-4fcf3fe3-acf0-4efe-a1fc-1a025410942a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937105307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1937105307
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1068555775
Short name T431
Test name
Test status
Simulation time 1541549623 ps
CPU time 84.9 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:50:27 PM PDT 24
Peak memory 199680 kb
Host smart-cce7f552-8edc-4793-9670-e10ea448d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068555775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1068555775
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1607413853
Short name T506
Test name
Test status
Simulation time 277773879 ps
CPU time 12.95 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:18 PM PDT 24
Peak memory 199680 kb
Host smart-edfaba8c-0a2e-4782-9b6f-9a5b75da4d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607413853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1607413853
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3031284257
Short name T294
Test name
Test status
Simulation time 47457507418 ps
CPU time 1456.83 seconds
Started Jul 27 05:49:00 PM PDT 24
Finished Jul 27 06:13:17 PM PDT 24
Peak memory 722776 kb
Host smart-36ec27f3-879c-4a5f-932e-908deae2e938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031284257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3031284257
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2877321687
Short name T26
Test name
Test status
Simulation time 31391081328 ps
CPU time 3910.72 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 06:54:13 PM PDT 24
Peak memory 810600 kb
Host smart-a89f6b71-f97c-4a6f-bd8c-eb92bf87e806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877321687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2877321687
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3456757017
Short name T448
Test name
Test status
Simulation time 3892765203 ps
CPU time 13.54 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 05:49:15 PM PDT 24
Peak memory 199800 kb
Host smart-f6a316bd-9e6e-4930-a4d4-2f0b89b85670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456757017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3456757017
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1452795471
Short name T423
Test name
Test status
Simulation time 13598572 ps
CPU time 0.69 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:06 PM PDT 24
Peak memory 196396 kb
Host smart-88d68b54-542f-451c-8808-9c57a4e120f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452795471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1452795471
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1794858535
Short name T456
Test name
Test status
Simulation time 863440084 ps
CPU time 49.78 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 05:49:51 PM PDT 24
Peak memory 199732 kb
Host smart-5f46f78f-7b9e-431e-8c92-1d98825e4a27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794858535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1794858535
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1033835794
Short name T3
Test name
Test status
Simulation time 1773708832 ps
CPU time 17.39 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:49:21 PM PDT 24
Peak memory 199740 kb
Host smart-d41cbe66-530b-4810-bb31-d13631b8d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033835794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1033835794
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.900740616
Short name T384
Test name
Test status
Simulation time 4795195013 ps
CPU time 456.34 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:56:40 PM PDT 24
Peak memory 657144 kb
Host smart-0fedfe97-8473-4670-82d4-6400498382e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900740616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.900740616
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3874309197
Short name T69
Test name
Test status
Simulation time 5616637842 ps
CPU time 70.42 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:50:14 PM PDT 24
Peak memory 199796 kb
Host smart-7150f739-eaec-4ba0-8cfb-9566eb0d529e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874309197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3874309197
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1772364289
Short name T216
Test name
Test status
Simulation time 19995232496 ps
CPU time 199.55 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:52:23 PM PDT 24
Peak memory 199800 kb
Host smart-155f6c93-9e95-44be-9a84-5b88cef9658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772364289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1772364289
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.372393508
Short name T355
Test name
Test status
Simulation time 916009612 ps
CPU time 8.01 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:49:10 PM PDT 24
Peak memory 199712 kb
Host smart-35332ea8-6bd0-4408-b6dd-4c272414701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372393508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.372393508
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1301366270
Short name T43
Test name
Test status
Simulation time 222655779170 ps
CPU time 3052.32 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 06:39:56 PM PDT 24
Peak memory 735988 kb
Host smart-51a87680-dbd5-4bfe-9b48-d384430c933a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301366270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1301366270
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2467627416
Short name T60
Test name
Test status
Simulation time 190838433489 ps
CPU time 3522.8 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 06:47:45 PM PDT 24
Peak memory 681056 kb
Host smart-c738ccbe-7436-4404-829d-15347dabe166
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467627416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2467627416
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.339523383
Short name T15
Test name
Test status
Simulation time 7152765739 ps
CPU time 62.18 seconds
Started Jul 27 05:49:04 PM PDT 24
Finished Jul 27 05:50:07 PM PDT 24
Peak memory 199684 kb
Host smart-6969db1c-e1df-45e9-bfc3-28c4d83537c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339523383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.339523383
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2470775947
Short name T205
Test name
Test status
Simulation time 43134309 ps
CPU time 0.61 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:06 PM PDT 24
Peak memory 195752 kb
Host smart-2a666f8e-ac25-4599-baa6-5e439b0a2f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470775947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2470775947
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2115978923
Short name T142
Test name
Test status
Simulation time 2519973809 ps
CPU time 39.16 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:49:42 PM PDT 24
Peak memory 199780 kb
Host smart-0bcb1fb3-748d-4508-8066-bb90de2baecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115978923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2115978923
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1900450025
Short name T148
Test name
Test status
Simulation time 5706831439 ps
CPU time 27.28 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:32 PM PDT 24
Peak memory 199728 kb
Host smart-8e7bfa71-7351-4826-9f53-dfbdc5da9b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900450025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1900450025
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.68272512
Short name T241
Test name
Test status
Simulation time 3937272940 ps
CPU time 750.45 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 06:01:34 PM PDT 24
Peak memory 660500 kb
Host smart-3be38b28-08a6-4026-82f5-1b838477a654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68272512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.68272512
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3858337545
Short name T321
Test name
Test status
Simulation time 1253959741 ps
CPU time 70.42 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:50:15 PM PDT 24
Peak memory 199660 kb
Host smart-05180f1f-c845-4054-be58-cd44fb6492e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858337545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3858337545
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1173924281
Short name T27
Test name
Test status
Simulation time 18892940033 ps
CPU time 131.89 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 05:51:13 PM PDT 24
Peak memory 199828 kb
Host smart-9d9ed33c-c3d3-49b1-8669-57e6ace1318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173924281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1173924281
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1808797645
Short name T533
Test name
Test status
Simulation time 234412584 ps
CPU time 3.31 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:49:05 PM PDT 24
Peak memory 199652 kb
Host smart-c3276454-c1b1-49f6-8b01-f4b9621b3b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808797645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1808797645
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2972367688
Short name T361
Test name
Test status
Simulation time 99125382776 ps
CPU time 1138.63 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 06:08:00 PM PDT 24
Peak memory 699684 kb
Host smart-97ed3665-4468-4b4c-aee6-7c45fdaa8d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972367688 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2972367688
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4127420698
Short name T13
Test name
Test status
Simulation time 339175758963 ps
CPU time 5639.22 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 07:23:01 PM PDT 24
Peak memory 824300 kb
Host smart-cb42be1e-45a3-4046-ad5a-be1d03d4b2d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127420698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.4127420698
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2217124132
Short name T190
Test name
Test status
Simulation time 34655309904 ps
CPU time 100.76 seconds
Started Jul 27 05:49:00 PM PDT 24
Finished Jul 27 05:50:41 PM PDT 24
Peak memory 199780 kb
Host smart-3889c247-03f8-422f-9882-4564d6a80546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217124132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2217124132
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2992309155
Short name T83
Test name
Test status
Simulation time 12384705 ps
CPU time 0.61 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 05:49:01 PM PDT 24
Peak memory 195684 kb
Host smart-9ba7e406-45c2-4068-8dfe-89867eb8e041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992309155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2992309155
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3957286493
Short name T272
Test name
Test status
Simulation time 3356748751 ps
CPU time 94.4 seconds
Started Jul 27 05:49:01 PM PDT 24
Finished Jul 27 05:50:36 PM PDT 24
Peak memory 199840 kb
Host smart-d02fe655-7d3d-4b9a-bb03-5976b9dfce33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3957286493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3957286493
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1185638686
Short name T138
Test name
Test status
Simulation time 815351186 ps
CPU time 21.41 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:27 PM PDT 24
Peak memory 199760 kb
Host smart-5f222f89-fe19-4f72-91dc-6cf812046244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185638686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1185638686
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2353793972
Short name T226
Test name
Test status
Simulation time 63849379 ps
CPU time 0.85 seconds
Started Jul 27 05:48:59 PM PDT 24
Finished Jul 27 05:49:00 PM PDT 24
Peak memory 198444 kb
Host smart-2338cd9f-0871-49c8-85ad-21712c5c8b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2353793972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2353793972
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3977558230
Short name T268
Test name
Test status
Simulation time 17969253793 ps
CPU time 111.46 seconds
Started Jul 27 05:49:03 PM PDT 24
Finished Jul 27 05:50:55 PM PDT 24
Peak memory 199760 kb
Host smart-96bfcdf6-9c70-4c04-907a-b9ba56e02aba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977558230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3977558230
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2590512237
Short name T398
Test name
Test status
Simulation time 17598561673 ps
CPU time 55.93 seconds
Started Jul 27 05:49:04 PM PDT 24
Finished Jul 27 05:50:00 PM PDT 24
Peak memory 199784 kb
Host smart-20e1d3af-19a7-4973-b7a1-03e236bbe27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590512237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2590512237
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1611121513
Short name T79
Test name
Test status
Simulation time 167545851 ps
CPU time 3.19 seconds
Started Jul 27 05:49:05 PM PDT 24
Finished Jul 27 05:49:08 PM PDT 24
Peak memory 199720 kb
Host smart-5b157421-c54e-452e-99d8-f3b6c5cfbca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611121513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1611121513
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1347233345
Short name T433
Test name
Test status
Simulation time 59279283793 ps
CPU time 1812.2 seconds
Started Jul 27 05:49:08 PM PDT 24
Finished Jul 27 06:19:21 PM PDT 24
Peak memory 688856 kb
Host smart-75f434da-3739-44d2-ac4f-fa6c07f7fa58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347233345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1347233345
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2751722213
Short name T16
Test name
Test status
Simulation time 329184393609 ps
CPU time 2355.65 seconds
Started Jul 27 05:49:04 PM PDT 24
Finished Jul 27 06:28:20 PM PDT 24
Peak memory 757080 kb
Host smart-d6738e40-529d-40c4-8733-8fc96cbf66d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751722213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2751722213
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2153253720
Short name T93
Test name
Test status
Simulation time 74487378284 ps
CPU time 105.77 seconds
Started Jul 27 05:49:02 PM PDT 24
Finished Jul 27 05:50:48 PM PDT 24
Peak memory 199784 kb
Host smart-16049c59-246c-457a-b28e-01261358ea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153253720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2153253720
Directory /workspace/9.hmac_wipe_secret/latest
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