Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18187429	1			T2	36944		T3	11074		T7	20757
all_values[1]	18187429	1			T2	36944		T3	11074		T7	20757
all_values[2]	18187429	1			T2	36944		T3	11074		T7	20757

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

288132

1

T2

216

T4

335

T10

107

auto[1]

54274155

1

T2

110616

T3

33222

T7

62271

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46492925

1

T2

94130

T3

23308

T7

51935

auto[1]

8069362

1

T2

16702

T3

9914

T7

10336

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98998	1			T2	106		T4	110		T24	4
all_values[0]	auto[0]	auto[1]	360	1			T2	2		T4	3		T24	3
all_values[0]	auto[1]	auto[0]	18068034	1			T2	36819		T3	11073		T7	20532
all_values[0]	auto[1]	auto[1]	20037	1			T2	17		T3	1		T7	225
all_values[1]	auto[0]	auto[0]	114038	1			T2	108		T4	220		T24	637
all_values[1]	auto[0]	auto[1]	197	1			T4	1		T24	2		T5	2
all_values[1]	auto[1]	auto[0]	18072849	1			T2	36836		T3	11074		T7	20757
all_values[1]	auto[1]	auto[1]	345	1			T4	1		T24	5		T21	5
all_values[2]	auto[0]	auto[0]	38519	1			T10	107		T9	46		T24	2
all_values[2]	auto[0]	auto[1]	36020	1			T4	1		T9	147		T24	6
all_values[2]	auto[1]	auto[0]	10100487	1			T2	20261		T3	1161		T7	10646
all_values[2]	auto[1]	auto[1]	8012403	1			T2	16683		T3	9913		T7	10111