Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141891

1

T3

14

T4

2796

T8

24

auto[1]

129044

1

T2

56

T3

8

T7

208

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	103474	1			T2	13		T3	10		T4	1867
len_1026_2046	9463	1			T4	46		T24	63		T5	237
len_514_1022	3887	1			T4	18		T9	1		T19	1
len_2_510	3413	1			T4	22		T10	1		T24	31
len_2056	174	1			T4	2		T10	1		T139	3
len_2048	644	1			T4	3		T24	4		T5	2
len_2040	166	1			T82	1		T90	2		T140	2
len_1032	208	1			T4	8		T139	4		T82	2
len_1024	1818	1			T7	104		T4	3		T10	4
len_1016	173	1			T4	2		T95	5		T139	4
len_520	186	1			T4	1		T10	3		T24	2
len_512	405	1			T4	1		T10	1		T24	3
len_504	208	1			T4	2		T96	1		T90	5
len_8	981	1			T2	15		T4	6		T24	32
len_0	10269	1			T3	1		T4	9		T8	3

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

88

1

T5

1

T50

2

T90

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	56164	1			T3	7		T4	1333		T8	11
auto[0]	len_1026_2046	4293	1			T4	23		T24	50		T5	231
auto[0]	len_514_1022	2525	1			T4	12		T9	1		T19	1
auto[0]	len_2_510	2083	1			T4	13		T10	1		T24	22
auto[0]	len_2056	92	1			T10	1		T82	4		T90	2
auto[0]	len_2048	389	1			T4	1		T24	3		T5	1
auto[0]	len_2040	85	1			T90	2		T140	2		T84	1
auto[0]	len_1032	102	1			T4	3		T139	1		T82	2
auto[0]	len_1024	282	1			T4	2		T24	1		T5	2
auto[0]	len_1016	99	1			T4	2		T95	2		T139	1
auto[0]	len_520	95	1			T4	1		T10	3		T24	1
auto[0]	len_512	264	1			T10	1		T24	1		T5	5
auto[0]	len_504	143	1			T4	2		T90	1		T11	1
auto[0]	len_8	21	1			T141	2		T142	2		T102	1
auto[0]	len_0	4310	1			T4	6		T8	1		T10	1
auto[1]	len_2050_plus	47310	1			T2	13		T3	3		T4	534
auto[1]	len_1026_2046	5170	1			T4	23		T24	13		T5	6
auto[1]	len_514_1022	1362	1			T4	6		T24	31		T5	3
auto[1]	len_2_510	1330	1			T4	9		T24	9		T5	4
auto[1]	len_2056	82	1			T4	2		T139	3		T82	2
auto[1]	len_2048	255	1			T4	2		T24	1		T5	1
auto[1]	len_2040	81	1			T82	1		T143	1		T144	4
auto[1]	len_1032	106	1			T4	5		T139	3		T90	2
auto[1]	len_1024	1536	1			T7	104		T4	1		T10	4
auto[1]	len_1016	74	1			T95	3		T139	3		T82	3
auto[1]	len_520	91	1			T24	1		T90	1		T11	2
auto[1]	len_512	141	1			T4	1		T24	2		T5	1
auto[1]	len_504	65	1			T96	1		T90	4		T11	1
auto[1]	len_8	960	1			T2	15		T4	6		T24	32
auto[1]	len_0	5959	1			T3	1		T4	3		T8	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

49

1

T79

2

T145

2

T49

1

auto[1]

len_upper

39

1

T5

1

T50

2

T90

1