Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4509901

1

T2

7825

T3

530

T7

5315

auto[1]

2897236

1

T2

10495

T3

325

T4

33342

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2831211

1

T2

10336

T3

359

T4

18029

auto[1]

4575926

1

T2

7984

T3

496

T7

5315

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3499446

1

T3

838

T4

12191

T8

3715

auto[1]

3907691

1

T2

18320

T3

17

T7

5315

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4596851

1

T2

7514

T3

325

T7

5315

auto[1]

2810286

1

T2

10806

T3

530

T4

22685

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6620390	1			T2	16220		T3	854		T7	4522
fifo_depth[1]	127822	1			T2	385		T3	1		T7	176
fifo_depth[2]	103894	1			T2	354		T7	169		T4	305
fifo_depth[3]	82589	1			T2	357		T7	175		T4	85
fifo_depth[4]	72845	1			T2	318		T7	138		T4	116
fifo_depth[5]	56059	1			T2	283		T7	90		T4	21
fifo_depth[6]	44636	1			T2	196		T7	37		T4	28
fifo_depth[7]	29080	1			T2	114		T7	8		T4	10

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

786747

1

T2

2100

T3

1

T7

793

auto[1]

6620390

1

T2

16220

T3

854

T7

4522

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7394160

1

T2

18320

T3

855

T7

5315

auto[1]

12977

1

T24

1374

T21

664

T26

55

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

31974

1

T10

4

T24

505

T5

49

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

29762

1

T4

23

T8

49

T9

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

34989

1

T4

4

T9

114

T19

163

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

32602

1

T4

57

T9

67

T19

132

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

198996

1

T4

57

T19

91

T24

115

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

51511

1

T4

8

T8

200

T9

49

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37014

1

T3

1

T4

39

T8

269

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

36489

1

T4

142

T9

37

T24

469

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46560

1

T4

53

T19

95

T24

2051

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

40969

1

T2

597

T4

25

T10

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44667

1

T2

181

T4

118

T8

529

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

44946

1

T2

524

T4

111

T8

24

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38828

1

T7

793

T4

188

T24

1410

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34280

1

T4

15

T8

60

T19

94

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44173

1

T2

798

T4

281

T9

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38987

1

T4

75

T8

196

T24

603

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

200225

1

T4

1230

T8

1

T10

49

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

178821

1

T3

353

T4

947

T8

284

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

185733

1

T3

3

T4

1476

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

191824

1

T4

1667

T8

1

T9

1138

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1688829

1

T4

872

T8

3

T9

11

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

188275

1

T3

174

T4

156

T8

1334

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

208003

1

T3

306

T4

976

T8

1303

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

204399

1

T3

1

T4

4537

T8

270

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

422593

1

T2

782

T3

1

T4

2520

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

410620

1

T2

1998

T3

1

T4

200

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

465421

1

T2

2771

T3

1

T4

4690

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

469505

1

T2

3483

T4

4908

T8

453

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

510726

1

T2

1299

T3

1

T7

4522

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

436932

1

T2

3149

T4

952

T8

452

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

438120

1

T2

1683

T3

12

T4

5399

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

420364

1

T2

1055

T3

1

T4

8862

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

231833

1

T4

1230

T8

1

T10

53

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

207488

1

T3

353

T4

970

T8

333

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

220363

1

T3

3

T4

1480

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

223429

1

T4

1724

T8

1

T9

1205

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1887490

1

T4

929

T8

3

T9

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

237119

1

T3

174

T4

164

T8

1534

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

243549

1

T3

307

T4

1015

T8

1572

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

239847

1

T3

1

T4

4679

T8

270

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

467869

1

T2

782

T3

1

T4

2573

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

451310

1

T2

2595

T3

1

T4

225

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

509714

1

T2

2952

T3

1

T4

4808

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

514021

1

T2

4007

T4

5019

T8

477

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

549017

1

T2

1299

T3

1

T7

5315

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

470852

1

T2

3149

T4

967

T8

512

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

481097

1

T2

2481

T3

12

T4

5680

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

459162

1

T2

1055

T3

1

T4

8937

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

366

1

T21

52

T146

34

T147

54

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1095

1

T21

54

T146

55

T23

35

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

359

1

T26

9

T12

7

T148

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

997

1

T24

57

T26

4

T12

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

335

1

T21

9

T26

17

T146

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2667

1

T24

557

T21

8

T12

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1468

1

T24

37

T26

7

T146

71

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1041

1

T21

29

T26

7

T12

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1284

1

T24

422

T21

255

T146

13

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

279

1

T26

7

T12

74

T146

10

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

374

1

T24

5

T21

10

T26

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

430

1

T24

8

T146

1

T148

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

537

1

T24

170

T21

6

T12

64

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

360

1

T24

118

T12

11

T146

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1196

1

T21

234

T146

87

T23

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

189

1

T21

7

T149

14

T150

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

200225

1

T4

1230

T8

1

T10

49

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

178821

1

T3

353

T4

947

T8

284

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

185733

1

T3

3

T4

1476

T8

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

191824

1

T4

1667

T8

1

T9

1138

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1688829

1

T4

872

T8

3

T9

11

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

188275

1

T3

174

T4

156

T8

1334

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

208003

1

T3

306

T4

976

T8

1303

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

204399

1

T3

1

T4

4537

T8

270

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

422593

1

T2

782

T3

1

T4

2520

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

410620

1

T2

1998

T3

1

T4

200

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

465421

1

T2

2771

T3

1

T4

4690

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

469505

1

T2

3483

T4

4908

T8

453

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

510726

1

T2

1299

T3

1

T7

4522

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

436932

1

T2

3149

T4

952

T8

452

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

438120

1

T2

1683

T3

12

T4

5399

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

420364

1

T2

1055

T3

1

T4

8862

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3941

1

T10

1

T24

19

T5

34

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3667

1

T4

14

T8

24

T9

11

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4221

1

T4

1

T9

74

T19

23

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3577

1

T4

36

T9

38

T19

20

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

49529

1

T4

10

T19

16

T24

20

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4117

1

T4

4

T8

83

T9

29

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4138

1

T3

1

T4

16

T8

55

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4605

1

T4

111

T9

19

T24

22

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6548

1

T4

16

T19

14

T24

161

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5553

1

T2

102

T4

2

T10

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6723

1

T2

43

T4

25

T8

92

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6775

1

T2

90

T4

45

T8

11

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7313

1

T7

176

T4

99

T24

13

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5080

1

T4

8

T8

13

T19

16

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5878

1

T2

150

T4

166

T9

15

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6157

1

T4

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43

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83

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22

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21

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28

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37

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49

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22

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15

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167

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1

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13

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78

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1

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23

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26

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1

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8

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1

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20

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1

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1

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68

fifo_depth[5]

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1

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15

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61

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19

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41

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35

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6

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23

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1

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12

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101

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1

T2

91

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1

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19

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11

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70

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1

T2

74

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1

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22

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1

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21

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1

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83

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14

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6

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1

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43

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6

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1

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T24

48

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12

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16

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29

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4

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2

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18

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12

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85

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1

T2

67

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4

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59

fifo_depth[6]

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1

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48

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1

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33

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37

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17

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2

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12

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6

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52

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61

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16

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18

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15

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19

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35

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28

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1

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7

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17

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1

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14

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20

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2

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1

T8

12

T24

8

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1

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1

T4

1

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4

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20

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1

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9

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31

T21

15

fifo_depth[7]

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1

T2

46

T19

12

T24

147

fifo_depth[7]

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1

T2

5

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8

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33

fifo_depth[7]

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1

T2

37

T4

1

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12

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1

T7

8

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10

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1

T19

5

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2

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5

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1

T2

26

T19

7

T24

21

fifo_depth[7]

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1

T24

52

T99

12

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1