Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18187429	1			T2	36944		T3	11074		T7	20757
all_pins[1]	18187429	1			T2	36944		T3	11074		T7	20757
all_pins[2]	18187429	1			T2	36944		T3	11074		T7	20757

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	46528654	1			T2	94132		T3	23308		T7	51935
values[0x1]	8033633	1			T2	16700		T3	9914		T7	10336
transitions[0x0=>0x1]	8033458	1			T2	16700		T3	9914		T7	10336
transitions[0x1=>0x0]	8033473	1			T2	16700		T3	9914		T7	10336

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18166578	1			T2	36927		T3	11073		T7	20532
all_pins[0]	values[0x1]	20851	1			T2	17		T3	1		T7	225
all_pins[0]	transitions[0x0=>0x1]	20778	1			T2	17		T3	1		T7	225
all_pins[0]	transitions[0x1=>0x0]	8012345	1			T2	16683		T3	9913		T7	10111
all_pins[1]	values[0x0]	18187050	1			T2	36944		T3	11074		T7	20757
all_pins[1]	values[0x1]	379	1			T4	1		T24	5		T21	6
all_pins[1]	transitions[0x0=>0x1]	325	1			T4	1		T24	5		T21	6
all_pins[1]	transitions[0x1=>0x0]	20797	1			T2	17		T3	1		T7	225
all_pins[2]	values[0x0]	10175026	1			T2	20261		T3	1161		T7	10646
all_pins[2]	values[0x1]	8012403	1			T2	16683		T3	9913		T7	10111
all_pins[2]	transitions[0x0=>0x1]	8012355	1			T2	16683		T3	9913		T7	10111
all_pins[2]	transitions[0x1=>0x0]	331	1			T4	1		T24	5		T21	6