Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 958 1 T4 4 T24 10 T5 4
all_values[1] 958 1 T4 4 T24 10 T5 4
all_values[2] 958 1 T4 4 T24 10 T5 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1438 1 T4 8 T24 21 T5 5
auto[1] 1436 1 T4 4 T24 9 T5 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1067 1 T4 3 T24 9 T5 4
auto[1] 1807 1 T4 9 T24 21 T5 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1661 1 T4 6 T24 18 T5 5
auto[1] 1213 1 T4 6 T24 12 T5 7


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 185 1 T4 1 T24 4 T5 1
all_values[0] auto[0] auto[0] auto[1] 81 1 T4 1 T24 2 T82 1
all_values[0] auto[0] auto[1] auto[0] 194 1 T24 2 T82 3 T90 9
all_values[0] auto[0] auto[1] auto[1] 94 1 T82 6 T90 1 T11 2
all_values[0] auto[1] auto[0] auto[1] 201 1 T4 2 T24 1 T82 5
all_values[0] auto[1] auto[1] auto[1] 203 1 T24 1 T5 3 T82 6
all_values[1] auto[0] auto[0] auto[0] 152 1 T24 2 T5 1 T82 3
all_values[1] auto[0] auto[0] auto[1] 126 1 T4 1 T24 3 T5 1
all_values[1] auto[0] auto[1] auto[0] 155 1 T82 2 T90 4 T127 5
all_values[1] auto[0] auto[1] auto[1] 121 1 T4 1 T24 1 T82 5
all_values[1] auto[1] auto[0] auto[1] 202 1 T4 1 T24 3 T5 2
all_values[1] auto[1] auto[1] auto[1] 202 1 T4 1 T24 1 T82 8
all_values[2] auto[0] auto[0] auto[0] 201 1 T4 1 T82 7 T90 6
all_values[2] auto[0] auto[0] auto[1] 79 1 T24 2 T82 1 T90 2
all_values[2] auto[0] auto[1] auto[0] 180 1 T4 1 T24 1 T5 2
all_values[2] auto[0] auto[1] auto[1] 93 1 T24 1 T82 6 T90 2
all_values[2] auto[1] auto[0] auto[1] 211 1 T4 1 T24 4 T82 4
all_values[2] auto[1] auto[1] auto[1] 194 1 T4 1 T24 2 T5 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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