Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4436	1			T2	6		T3	1		T4	31
sha2_none	4392	1			T2	10		T3	2		T4	34
sha2_512	7678	1			T2	4		T7	225		T4	32
sha2_384	7440	1			T2	8		T3	6		T4	32
sha2_256	6579	1			T2	12		T3	3		T4	52

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19093

1

T2

20

T3

5

T7

225

auto[1]

11836

1

T2

20

T3

7

T4

105

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11611

1

T2

18

T3

6

T4

90

auto[1]

19318

1

T2

22

T3

6

T7

225

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15913

1

T2

40

T3

5

T7

225

disabled

15016

1

T3

7

T4

89

T8

14

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4830	1			T2	7		T3	3		T4	22
key_none	7772	1			T2	4		T3	2		T4	29
key_1024	4565	1			T2	3		T7	225		T4	27
key_512	3900	1			T2	4		T4	39		T8	3
key_384	3516	1			T2	5		T3	1		T4	27
key_256	3190	1			T2	6		T3	2		T4	16
key_128	3063	1			T2	11		T3	3		T4	24

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19199

1

T2

19

T3

6

T7

225

auto[1]

11730

1

T2

21

T3

6

T4

87

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

30713

1

T2

40

T3

11

T7

225

disabled

216

1

T3

1

T8

5

T24

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1606

1

T2

4

T4

13

T10

1

enabled

auto[0]

auto[0]

auto[1]

1578

1

T2

2

T3

1

T4

9

enabled

auto[0]

auto[1]

auto[0]

1646

1

T2

4

T4

11

T8

6

enabled

auto[0]

auto[1]

auto[1]

1720

1

T2

8

T4

14

T8

3

enabled

auto[1]

auto[0]

auto[0]

4360

1

T2

6

T3

1

T7

225

enabled

auto[1]

auto[0]

auto[1]

1605

1

T2

8

T4

10

T8

3

enabled

auto[1]

auto[1]

auto[0]

1763

1

T2

5

T3

1

T4

10

enabled

auto[1]

auto[1]

auto[1]

1635

1

T2

3

T3

2

T4

14

disabled

auto[0]

auto[0]

auto[0]

1250

1

T4

8

T8

1

T10

3

disabled

auto[0]

auto[0]

auto[1]

1317

1

T3

2

T4

5

T8

1

disabled

auto[0]

auto[1]

auto[0]

1211

1

T3

3

T4

13

T8

1

disabled

auto[0]

auto[1]

auto[1]

1283

1

T4

17

T9

3

T19

4

disabled

auto[1]

auto[0]

auto[0]

6093

1

T4

12

T8

1

T9

1

disabled

auto[1]

auto[0]

auto[1]

1284

1

T3

1

T4

8

T8

4

disabled

auto[1]

auto[1]

auto[0]

1270

1

T3

1

T4

16

T8

2

disabled

auto[1]

auto[1]

auto[1]

1308

1

T4

10

T8

4

T10

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15828

1

T2

40

T3

5

T7

225

enabled

disabled

85

1

T8

3

T21

1

T138

3

disabled

disabled

131

1

T3

1

T8

2

T24

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14885

1

T3

6

T4

89

T8

12

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1144	1			T2	2		T3	1		T4	2
key_invalid	sha2_none	874	1			T2	3		T4	4		T8	1
key_invalid	sha2_512	836	1			T4	7		T10	1		T9	6
key_invalid	sha2_384	885	1			T3	2		T4	1		T10	3
key_invalid	sha2_256	980	1			T2	2		T4	8		T8	3
key_none	sha2_invalid	528	1			T4	5		T8	1		T19	1
key_none	sha2_none	545	1			T2	1		T4	6		T8	2
key_none	sha2_512	2564	1			T2	1		T4	4		T8	3
key_none	sha2_384	2499	1			T2	1		T3	1		T4	6
key_none	sha2_256	1595	1			T2	1		T3	1		T4	7
key_1024	sha2_invalid	549	1			T4	4		T8	1		T19	3
key_1024	sha2_none	609	1			T4	5		T9	4		T24	11
key_1024	sha2_512	1769	1			T7	225		T4	6		T9	2
key_1024	sha2_384	955	1			T2	1		T4	4		T8	3
key_512	sha2_invalid	575	1			T2	1		T4	5		T8	1
key_512	sha2_none	593	1			T2	1		T4	4		T19	2
key_512	sha2_512	618	1			T4	8		T8	1		T9	1
key_512	sha2_384	1219	1			T2	2		T4	12		T8	1
key_512	sha2_256	842	1			T4	9		T9	1		T19	1
key_384	sha2_invalid	563	1			T2	1		T4	7		T8	1
key_384	sha2_none	549	1			T2	1		T4	8		T24	6
key_384	sha2_512	638	1			T2	1		T8	1		T9	1
key_384	sha2_384	599	1			T3	1		T4	2		T24	9
key_384	sha2_256	1111	1			T2	2		T4	9		T24	7
key_256	sha2_invalid	525	1			T2	1		T4	2		T9	1
key_256	sha2_none	606	1			T2	2		T3	1		T4	2
key_256	sha2_512	649	1			T2	1		T4	1		T8	2
key_256	sha2_384	593	1			T2	1		T3	1		T4	2
key_256	sha2_256	775	1			T2	1		T4	9		T24	8
key_128	sha2_invalid	530	1			T2	1		T4	6		T8	1
key_128	sha2_none	597	1			T2	2		T3	1		T4	5
key_128	sha2_512	595	1			T2	1		T4	6		T9	1
key_128	sha2_384	669	1			T2	3		T4	5		T8	3
key_128	sha2_256	622	1			T2	4		T3	2		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

635

1

T2

2

T4

8

T9

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1144	1			T2	2		T3	1		T4	2
key_invalid	sha2_none	874	1			T2	3		T4	4		T8	1
key_invalid	sha2_512	836	1			T4	7		T10	1		T9	6
key_invalid	sha2_384	885	1			T3	2		T4	1		T10	3
key_invalid	sha2_256	980	1			T2	2		T4	8		T8	3
key_none	sha2_invalid	528	1			T4	5		T8	1		T19	1
key_none	sha2_none	545	1			T2	1		T4	6		T8	2
key_none	sha2_512	2564	1			T2	1		T4	4		T8	3
key_none	sha2_384	2499	1			T2	1		T3	1		T4	6
key_none	sha2_256	1595	1			T2	1		T3	1		T4	7
key_1024	sha2_invalid	549	1			T4	4		T8	1		T19	3
key_1024	sha2_none	609	1			T4	5		T9	4		T24	11
key_1024	sha2_512	1769	1			T7	225		T4	6		T9	2
key_1024	sha2_384	955	1			T2	1		T4	4		T8	3
key_1024	sha2_256	635	1			T2	2		T4	8		T9	2
key_512	sha2_invalid	575	1			T2	1		T4	5		T8	1
key_512	sha2_none	593	1			T2	1		T4	4		T19	2
key_512	sha2_512	618	1			T4	8		T8	1		T9	1
key_512	sha2_384	1219	1			T2	2		T4	12		T8	1
key_512	sha2_256	842	1			T4	9		T9	1		T19	1
key_384	sha2_invalid	563	1			T2	1		T4	7		T8	1
key_384	sha2_none	549	1			T2	1		T4	8		T24	6
key_384	sha2_512	638	1			T2	1		T8	1		T9	1
key_384	sha2_384	599	1			T3	1		T4	2		T24	9
key_384	sha2_256	1111	1			T2	2		T4	9		T24	7
key_256	sha2_invalid	525	1			T2	1		T4	2		T9	1
key_256	sha2_none	606	1			T2	2		T3	1		T4	2
key_256	sha2_512	649	1			T2	1		T4	1		T8	2
key_256	sha2_384	593	1			T2	1		T3	1		T4	2
key_256	sha2_256	775	1			T2	1		T4	9		T24	8
key_128	sha2_invalid	530	1			T2	1		T4	6		T8	1
key_128	sha2_none	597	1			T2	2		T3	1		T4	5
key_128	sha2_512	595	1			T2	1		T4	6		T9	1
key_128	sha2_384	669	1			T2	3		T4	5		T8	3
key_128	sha2_256	622	1			T2	4		T3	2		T4	2