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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 660
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T122 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1772170880 Jul 28 05:02:35 PM PDT 24 Jul 28 05:02:37 PM PDT 24 34818934 ps
T531 /workspace/coverage/cover_reg_top/34.hmac_intr_test.230305810 Jul 28 05:02:41 PM PDT 24 Jul 28 05:02:42 PM PDT 24 24844770 ps
T532 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2140582951 Jul 28 05:02:33 PM PDT 24 Jul 28 05:02:36 PM PDT 24 718089443 ps
T69 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1681599544 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:33 PM PDT 24 286422175 ps
T533 /workspace/coverage/cover_reg_top/45.hmac_intr_test.4087219268 Jul 28 05:02:48 PM PDT 24 Jul 28 05:02:49 PM PDT 24 37301114 ps
T534 /workspace/coverage/cover_reg_top/15.hmac_intr_test.71295011 Jul 28 05:02:32 PM PDT 24 Jul 28 05:02:32 PM PDT 24 29995364 ps
T535 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1986262933 Jul 28 05:02:34 PM PDT 24 Jul 28 05:02:37 PM PDT 24 193171850 ps
T107 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.218092331 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:30 PM PDT 24 92727222 ps
T123 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3133164859 Jul 28 05:02:23 PM PDT 24 Jul 28 05:02:24 PM PDT 24 16080251 ps
T536 /workspace/coverage/cover_reg_top/6.hmac_intr_test.494415077 Jul 28 05:02:30 PM PDT 24 Jul 28 05:02:31 PM PDT 24 20841705 ps
T70 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1717258564 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:30 PM PDT 24 286697101 ps
T537 /workspace/coverage/cover_reg_top/12.hmac_intr_test.8341203 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:29 PM PDT 24 31803244 ps
T538 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3491903301 Jul 28 05:02:17 PM PDT 24 Jul 28 05:02:20 PM PDT 24 353987301 ps
T539 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3083946769 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:32 PM PDT 24 15453196 ps
T540 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1987927310 Jul 28 05:02:35 PM PDT 24 Jul 28 05:02:36 PM PDT 24 54623910 ps
T124 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1354825541 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:27 PM PDT 24 267809568 ps
T108 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1390340626 Jul 28 05:02:19 PM PDT 24 Jul 28 05:02:20 PM PDT 24 127758166 ps
T541 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1329170071 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:27 PM PDT 24 317105191 ps
T542 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1212279590 Jul 28 05:02:40 PM PDT 24 Jul 28 05:02:43 PM PDT 24 241633458 ps
T543 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1308110048 Jul 28 05:02:07 PM PDT 24 Jul 28 05:02:08 PM PDT 24 92152245 ps
T544 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3660428515 Jul 28 05:02:35 PM PDT 24 Jul 28 05:02:37 PM PDT 24 342018514 ps
T71 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2436468389 Jul 28 05:02:34 PM PDT 24 Jul 28 05:02:36 PM PDT 24 190025254 ps
T545 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1017211803 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:29 PM PDT 24 14480054 ps
T546 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4034720194 Jul 28 05:02:20 PM PDT 24 Jul 28 05:05:05 PM PDT 24 16941648350 ps
T547 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2476360185 Jul 28 05:02:37 PM PDT 24 Jul 28 05:02:37 PM PDT 24 18228171 ps
T109 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1729998946 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:25 PM PDT 24 211522292 ps
T131 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3536876746 Jul 28 05:02:32 PM PDT 24 Jul 28 05:02:36 PM PDT 24 467144933 ps
T548 /workspace/coverage/cover_reg_top/40.hmac_intr_test.694559847 Jul 28 05:02:51 PM PDT 24 Jul 28 05:02:51 PM PDT 24 13456760 ps
T135 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2348858171 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:39 PM PDT 24 415058589 ps
T549 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4254509451 Jul 28 05:02:37 PM PDT 24 Jul 28 05:02:38 PM PDT 24 44537934 ps
T550 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2825729104 Jul 28 05:02:54 PM PDT 24 Jul 28 05:02:58 PM PDT 24 669021525 ps
T551 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2178049992 Jul 28 05:02:53 PM PDT 24 Jul 28 05:02:54 PM PDT 24 21299835 ps
T552 /workspace/coverage/cover_reg_top/10.hmac_intr_test.403385422 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:37 PM PDT 24 50543421 ps
T125 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.486949858 Jul 28 05:03:07 PM PDT 24 Jul 28 05:03:09 PM PDT 24 96398668 ps
T553 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3979784383 Jul 28 05:02:33 PM PDT 24 Jul 28 05:02:35 PM PDT 24 138267886 ps
T554 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.255912100 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:32 PM PDT 24 205051347 ps
T555 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2284645619 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:31 PM PDT 24 20566233 ps
T556 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2597415053 Jul 28 05:02:15 PM PDT 24 Jul 28 05:02:17 PM PDT 24 30307332 ps
T557 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1731918636 Jul 28 05:02:21 PM PDT 24 Jul 28 05:02:22 PM PDT 24 73740305 ps
T558 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.224530153 Jul 28 05:02:41 PM PDT 24 Jul 28 05:02:43 PM PDT 24 75327403 ps
T132 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1207361305 Jul 28 05:02:30 PM PDT 24 Jul 28 05:02:32 PM PDT 24 90431496 ps
T559 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4283668711 Jul 28 05:02:30 PM PDT 24 Jul 28 05:02:31 PM PDT 24 61524428 ps
T560 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3239314751 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:25 PM PDT 24 11443187 ps
T110 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2271504551 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:32 PM PDT 24 69353175 ps
T561 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1851006636 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:29 PM PDT 24 20868225 ps
T128 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.232252864 Jul 28 05:02:40 PM PDT 24 Jul 28 05:02:44 PM PDT 24 278501985 ps
T562 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4227599490 Jul 28 05:02:16 PM PDT 24 Jul 28 05:02:17 PM PDT 24 77542820 ps
T563 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2178307108 Jul 28 05:03:04 PM PDT 24 Jul 28 05:03:05 PM PDT 24 14810338 ps
T137 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1186714416 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:33 PM PDT 24 498167577 ps
T111 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1378702977 Jul 28 05:02:23 PM PDT 24 Jul 28 05:02:29 PM PDT 24 559168954 ps
T564 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3529921426 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:30 PM PDT 24 72933220 ps
T565 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3411704193 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:38 PM PDT 24 65732249 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4020613483 Jul 28 05:02:19 PM PDT 24 Jul 28 05:02:20 PM PDT 24 26979685 ps
T566 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3110711691 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:30 PM PDT 24 85993726 ps
T567 /workspace/coverage/cover_reg_top/11.hmac_intr_test.170070904 Jul 28 05:02:37 PM PDT 24 Jul 28 05:02:38 PM PDT 24 51050172 ps
T568 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1604260871 Jul 28 05:02:13 PM PDT 24 Jul 28 05:02:15 PM PDT 24 116418986 ps
T126 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3976397190 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:30 PM PDT 24 44908288 ps
T113 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1122127442 Jul 28 05:02:54 PM PDT 24 Jul 28 05:02:55 PM PDT 24 35370411 ps
T114 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1925737134 Jul 28 05:02:27 PM PDT 24 Jul 28 05:02:32 PM PDT 24 206057920 ps
T569 /workspace/coverage/cover_reg_top/16.hmac_intr_test.492447746 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:30 PM PDT 24 15264042 ps
T570 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2297149737 Jul 28 05:02:30 PM PDT 24 Jul 28 05:02:34 PM PDT 24 890117792 ps
T133 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2682765042 Jul 28 05:02:04 PM PDT 24 Jul 28 05:02:06 PM PDT 24 100912420 ps
T571 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2083507957 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:14 PM PDT 24 270911382 ps
T572 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3877211249 Jul 28 05:02:41 PM PDT 24 Jul 28 05:02:43 PM PDT 24 60578551 ps
T573 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3035657424 Jul 28 05:02:27 PM PDT 24 Jul 28 05:02:28 PM PDT 24 54036099 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1968415116 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:38 PM PDT 24 408930474 ps
T575 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1598773955 Jul 28 05:02:33 PM PDT 24 Jul 28 05:02:34 PM PDT 24 22516304 ps
T129 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.4057373650 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:35 PM PDT 24 239961430 ps
T576 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2891751127 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:30 PM PDT 24 16479303 ps
T577 /workspace/coverage/cover_reg_top/43.hmac_intr_test.4187833418 Jul 28 05:02:50 PM PDT 24 Jul 28 05:02:50 PM PDT 24 12175989 ps
T578 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1229525252 Jul 28 05:02:25 PM PDT 24 Jul 28 05:02:26 PM PDT 24 57471867 ps
T579 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4157032370 Jul 28 05:02:15 PM PDT 24 Jul 28 05:02:18 PM PDT 24 45959476 ps
T580 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4047137688 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:33 PM PDT 24 64092866 ps
T581 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2980394878 Jul 28 05:02:38 PM PDT 24 Jul 28 05:02:39 PM PDT 24 20483398 ps
T582 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1861455675 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:34 PM PDT 24 672990746 ps
T583 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2121511981 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:25 PM PDT 24 34750750 ps
T584 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3738686119 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:29 PM PDT 24 66461846 ps
T585 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2120116588 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:37 PM PDT 24 28110828 ps
T586 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.616676840 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:38 PM PDT 24 45757045 ps
T587 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1338026241 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:30 PM PDT 24 496669494 ps
T136 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.629991341 Jul 28 05:02:34 PM PDT 24 Jul 28 05:02:37 PM PDT 24 184985856 ps
T588 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.349669745 Jul 28 05:02:30 PM PDT 24 Jul 28 05:22:48 PM PDT 24 167690914612 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2897088832 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:27 PM PDT 24 150258881 ps
T134 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1240647062 Jul 28 05:02:32 PM PDT 24 Jul 28 05:02:36 PM PDT 24 455679570 ps
T590 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3159347255 Jul 28 05:02:41 PM PDT 24 Jul 28 05:02:42 PM PDT 24 101115960 ps
T591 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1892630444 Jul 28 05:02:37 PM PDT 24 Jul 28 05:02:37 PM PDT 24 11382220 ps
T115 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.584912473 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:27 PM PDT 24 111113448 ps
T592 /workspace/coverage/cover_reg_top/35.hmac_intr_test.205929300 Jul 28 05:02:41 PM PDT 24 Jul 28 05:02:42 PM PDT 24 12331847 ps
T593 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4017310986 Jul 28 05:02:35 PM PDT 24 Jul 28 05:02:36 PM PDT 24 78307983 ps
T594 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3962292576 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:24 PM PDT 24 11040171 ps
T595 /workspace/coverage/cover_reg_top/38.hmac_intr_test.919293265 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:36 PM PDT 24 11498989 ps
T596 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1908778459 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:29 PM PDT 24 169832540 ps
T597 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3153124696 Jul 28 05:02:44 PM PDT 24 Jul 28 05:02:45 PM PDT 24 12840247 ps
T598 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.305296605 Jul 28 05:02:34 PM PDT 24 Jul 28 05:02:36 PM PDT 24 208822533 ps
T599 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2104528606 Jul 28 05:02:37 PM PDT 24 Jul 28 05:02:40 PM PDT 24 106870752 ps
T600 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3370041258 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:31 PM PDT 24 484234224 ps
T116 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.358774400 Jul 28 05:02:18 PM PDT 24 Jul 28 05:02:30 PM PDT 24 4376110399 ps
T118 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.292621937 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:30 PM PDT 24 521093405 ps
T601 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4288386379 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:28 PM PDT 24 722005923 ps
T602 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3869024362 Jul 28 05:02:49 PM PDT 24 Jul 28 05:02:52 PM PDT 24 43755113 ps
T117 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2297782336 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:27 PM PDT 24 18396419 ps
T603 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3213264658 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:31 PM PDT 24 29475302 ps
T604 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1479067185 Jul 28 05:02:32 PM PDT 24 Jul 28 05:26:15 PM PDT 24 275498338745 ps
T605 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.988420776 Jul 28 05:02:16 PM PDT 24 Jul 28 05:02:17 PM PDT 24 230108055 ps
T606 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.874521014 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:30 PM PDT 24 83269611 ps
T607 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2534213722 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:39 PM PDT 24 752082136 ps
T608 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3795036756 Jul 28 05:02:33 PM PDT 24 Jul 28 05:02:34 PM PDT 24 55101800 ps
T609 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3345712714 Jul 28 05:02:32 PM PDT 24 Jul 28 05:02:34 PM PDT 24 84840817 ps
T610 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.497889260 Jul 28 05:02:35 PM PDT 24 Jul 28 05:02:37 PM PDT 24 62332894 ps
T611 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3936139817 Jul 28 05:02:25 PM PDT 24 Jul 28 05:02:26 PM PDT 24 24153697 ps
T612 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1040269097 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:24 PM PDT 24 360693577 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.508231243 Jul 28 05:02:34 PM PDT 24 Jul 28 05:02:36 PM PDT 24 75314246 ps
T614 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2279909090 Jul 28 05:02:23 PM PDT 24 Jul 28 05:02:24 PM PDT 24 27875384 ps
T615 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2768178541 Jul 28 05:02:17 PM PDT 24 Jul 28 05:02:25 PM PDT 24 665300158 ps
T616 /workspace/coverage/cover_reg_top/8.hmac_intr_test.588207891 Jul 28 05:02:34 PM PDT 24 Jul 28 05:02:34 PM PDT 24 23814858 ps
T617 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3105533664 Jul 28 05:02:23 PM PDT 24 Jul 28 05:02:23 PM PDT 24 15976380 ps
T618 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3010480515 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:34 PM PDT 24 60945715 ps
T619 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3032333299 Jul 28 05:02:25 PM PDT 24 Jul 28 05:02:42 PM PDT 24 1093634712 ps
T620 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2409499816 Jul 28 05:02:27 PM PDT 24 Jul 28 05:02:27 PM PDT 24 36499547 ps
T621 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3853803546 Jul 28 05:02:30 PM PDT 24 Jul 28 05:02:31 PM PDT 24 22114680 ps
T622 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3934550150 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:25 PM PDT 24 15569335 ps
T130 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.131573879 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:32 PM PDT 24 202682867 ps
T623 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3135105525 Jul 28 05:02:38 PM PDT 24 Jul 28 05:02:39 PM PDT 24 14201644 ps
T624 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1191707111 Jul 28 05:02:39 PM PDT 24 Jul 28 05:02:39 PM PDT 24 11332668 ps
T625 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2605222895 Jul 28 05:02:14 PM PDT 24 Jul 28 05:02:15 PM PDT 24 37014044 ps
T626 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4041022043 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:33 PM PDT 24 51400769 ps
T627 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2254284301 Jul 28 05:02:51 PM PDT 24 Jul 28 05:02:51 PM PDT 24 159120488 ps
T628 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3195380986 Jul 28 05:02:27 PM PDT 24 Jul 28 05:02:31 PM PDT 24 282657297 ps
T629 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3740444079 Jul 28 05:02:32 PM PDT 24 Jul 28 05:02:33 PM PDT 24 17898706 ps
T630 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.394173467 Jul 28 05:02:43 PM PDT 24 Jul 28 05:02:47 PM PDT 24 169450391 ps
T631 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.127307847 Jul 28 05:02:17 PM PDT 24 Jul 28 05:02:21 PM PDT 24 162701262 ps
T632 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1607181869 Jul 28 05:02:37 PM PDT 24 Jul 28 05:02:37 PM PDT 24 27879876 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3449182053 Jul 28 05:02:14 PM PDT 24 Jul 28 05:02:15 PM PDT 24 116630389 ps
T634 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.936716250 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:29 PM PDT 24 13108556 ps
T635 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3648430670 Jul 28 05:02:35 PM PDT 24 Jul 28 05:02:38 PM PDT 24 151151173 ps
T636 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4176744071 Jul 28 05:02:24 PM PDT 24 Jul 28 05:02:26 PM PDT 24 43885840 ps
T637 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3107490153 Jul 28 05:02:12 PM PDT 24 Jul 28 05:02:13 PM PDT 24 189970446 ps
T638 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.849622319 Jul 28 05:02:56 PM PDT 24 Jul 28 05:03:01 PM PDT 24 284490530 ps
T639 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4191454906 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:30 PM PDT 24 479225961 ps
T640 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1333943258 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:33 PM PDT 24 191952722 ps
T641 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2616670104 Jul 28 05:02:25 PM PDT 24 Jul 28 05:02:26 PM PDT 24 13369017 ps
T642 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1443271037 Jul 28 05:02:25 PM PDT 24 Jul 28 05:02:26 PM PDT 24 65688753 ps
T643 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1385356685 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:37 PM PDT 24 17487122 ps
T644 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1638484295 Jul 28 05:02:28 PM PDT 24 Jul 28 05:02:30 PM PDT 24 94953492 ps
T645 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4214068672 Jul 28 05:02:29 PM PDT 24 Jul 28 05:02:30 PM PDT 24 38536559 ps
T646 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2886104799 Jul 28 05:02:26 PM PDT 24 Jul 28 05:02:28 PM PDT 24 67155656 ps
T647 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.354746250 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:35 PM PDT 24 270390164 ps
T648 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.154454032 Jul 28 05:02:31 PM PDT 24 Jul 28 05:02:32 PM PDT 24 98281572 ps
T649 /workspace/coverage/cover_reg_top/21.hmac_intr_test.255622817 Jul 28 05:02:42 PM PDT 24 Jul 28 05:02:43 PM PDT 24 14673579 ps
T650 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3549025866 Jul 28 05:02:39 PM PDT 24 Jul 28 05:02:39 PM PDT 24 16717995 ps
T651 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.886662819 Jul 28 05:02:23 PM PDT 24 Jul 28 05:02:33 PM PDT 24 1433547210 ps
T652 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4094681582 Jul 28 05:02:22 PM PDT 24 Jul 28 05:02:24 PM PDT 24 104270140 ps
T653 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1833590963 Jul 28 05:02:14 PM PDT 24 Jul 28 05:02:14 PM PDT 24 34287687 ps
T654 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4279177810 Jul 28 05:03:01 PM PDT 24 Jul 28 05:03:02 PM PDT 24 31842491 ps
T655 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4079553032 Jul 28 05:02:45 PM PDT 24 Jul 28 05:02:48 PM PDT 24 103308362 ps
T656 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3738198484 Jul 28 05:02:35 PM PDT 24 Jul 28 05:02:36 PM PDT 24 40953333 ps
T657 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3687950452 Jul 28 05:02:16 PM PDT 24 Jul 28 05:02:22 PM PDT 24 115470357 ps
T658 /workspace/coverage/cover_reg_top/47.hmac_intr_test.765300941 Jul 28 05:02:48 PM PDT 24 Jul 28 05:02:49 PM PDT 24 15199363 ps
T659 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2542973130 Jul 28 05:02:36 PM PDT 24 Jul 28 05:02:36 PM PDT 24 66646541 ps
T660 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2644400262 Jul 28 05:02:42 PM PDT 24 Jul 28 05:02:43 PM PDT 24 12765478 ps

Test location /workspace/coverage/default/15.hmac_stress_all.2513778995
Short name T4
Test name
Test status
Simulation time 116648643756 ps
CPU time 1068.91 seconds
Started Jul 28 07:14:52 PM PDT 24
Finished Jul 28 07:32:41 PM PDT 24
Peak memory 737884 kb
Host smart-ac92e8ed-a4c3-4441-a456-d09ade71c948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513778995 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2513778995
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all.283606931
Short name T5
Test name
Test status
Simulation time 131039926892 ps
CPU time 1817.82 seconds
Started Jul 28 07:14:14 PM PDT 24
Finished Jul 28 07:44:32 PM PDT 24
Peak memory 771752 kb
Host smart-2958086e-a5e1-4849-9218-d925a9b53b2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283606931 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.283606931
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2138509318
Short name T15
Test name
Test status
Simulation time 315894317647 ps
CPU time 5817.22 seconds
Started Jul 28 07:14:20 PM PDT 24
Finished Jul 28 08:51:18 PM PDT 24
Peak memory 818648 kb
Host smart-9fedfeee-c142-40e1-bafb-64c1504bfed9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138509318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2138509318
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_stress_all.397225930
Short name T24
Test name
Test status
Simulation time 87524240547 ps
CPU time 2564.05 seconds
Started Jul 28 07:15:33 PM PDT 24
Finished Jul 28 07:58:18 PM PDT 24
Peak memory 720448 kb
Host smart-aefae284-bb53-4e2d-ad7b-e6d5eb317200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397225930 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.397225930
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3536876746
Short name T131
Test name
Test status
Simulation time 467144933 ps
CPU time 3.97 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 199888 kb
Host smart-4100663e-e723-41c6-9b08-77a15042ea94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536876746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3536876746
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3961149697
Short name T25
Test name
Test status
Simulation time 56945565034 ps
CPU time 1238.92 seconds
Started Jul 28 07:14:02 PM PDT 24
Finished Jul 28 07:34:42 PM PDT 24
Peak memory 685752 kb
Host smart-d6053be3-8a4d-4008-9d2a-4a8b2901d4a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3961149697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3961149697
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1640554016
Short name T166
Test name
Test status
Simulation time 148187442 ps
CPU time 0.6 seconds
Started Jul 28 07:13:54 PM PDT 24
Finished Jul 28 07:13:55 PM PDT 24
Peak memory 195660 kb
Host smart-679b5b1e-7cce-413c-8f07-c48851d46675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640554016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1640554016
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2062617213
Short name T82
Test name
Test status
Simulation time 67848801169 ps
CPU time 1245.76 seconds
Started Jul 28 07:14:56 PM PDT 24
Finished Jul 28 07:35:42 PM PDT 24
Peak memory 675644 kb
Host smart-645b6a19-e2ba-42bd-a7b3-cca01dcbe91b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062617213 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2062617213
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1390340626
Short name T108
Test name
Test status
Simulation time 127758166 ps
CPU time 0.96 seconds
Started Jul 28 05:02:19 PM PDT 24
Finished Jul 28 05:02:20 PM PDT 24
Peak memory 199628 kb
Host smart-89ae456d-efda-49a0-b168-d932c20db027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390340626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1390340626
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.741416372
Short name T14
Test name
Test status
Simulation time 62425927486 ps
CPU time 750.01 seconds
Started Jul 28 07:14:00 PM PDT 24
Finished Jul 28 07:26:31 PM PDT 24
Peak memory 258544 kb
Host smart-58cfc41d-5191-4145-ae31-1b89b3b927bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741416372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.741416372
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.819294925
Short name T58
Test name
Test status
Simulation time 82913287 ps
CPU time 1 seconds
Started Jul 28 07:13:43 PM PDT 24
Finished Jul 28 07:13:44 PM PDT 24
Peak memory 219196 kb
Host smart-1028379f-9d8a-49db-925b-0b0fa293eafc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819294925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.819294925
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.232252864
Short name T128
Test name
Test status
Simulation time 278501985 ps
CPU time 4.42 seconds
Started Jul 28 05:02:40 PM PDT 24
Finished Jul 28 05:02:44 PM PDT 24
Peak memory 200020 kb
Host smart-b36298b1-f1ff-4ec9-b112-e472b078717f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232252864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.232252864
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1026879333
Short name T21
Test name
Test status
Simulation time 3787329363 ps
CPU time 206.06 seconds
Started Jul 28 07:16:31 PM PDT 24
Finished Jul 28 07:19:57 PM PDT 24
Peak memory 199684 kb
Host smart-1e03f5a5-843c-4b8e-913b-f0ea987a06a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026879333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1026879333
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2087690883
Short name T90
Test name
Test status
Simulation time 57911775112 ps
CPU time 1055.71 seconds
Started Jul 28 07:17:03 PM PDT 24
Finished Jul 28 07:34:39 PM PDT 24
Peak memory 216112 kb
Host smart-4bc0d379-77fb-4db1-b8bb-11ce144cbe44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087690883 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2087690883
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2608897566
Short name T85
Test name
Test status
Simulation time 310146100544 ps
CPU time 2605.35 seconds
Started Jul 28 07:16:43 PM PDT 24
Finished Jul 28 08:00:08 PM PDT 24
Peak memory 771764 kb
Host smart-a93a9b12-933e-4a97-9b5b-b749356429a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608897566 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2608897566
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2104528606
Short name T599
Test name
Test status
Simulation time 106870752 ps
CPU time 2.82 seconds
Started Jul 28 05:02:37 PM PDT 24
Finished Jul 28 05:02:40 PM PDT 24
Peak memory 199800 kb
Host smart-c2bdec5c-7322-4362-b31f-80755cc3d799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104528606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2104528606
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2623336801
Short name T18
Test name
Test status
Simulation time 91913572791 ps
CPU time 452.4 seconds
Started Jul 28 07:13:54 PM PDT 24
Finished Jul 28 07:21:26 PM PDT 24
Peak memory 357612 kb
Host smart-bedca804-d83e-45d3-9686-7e512fe7a464
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623336801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2623336801
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3010480515
Short name T618
Test name
Test status
Simulation time 60945715 ps
CPU time 3.02 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 199780 kb
Host smart-d77fe2d4-4940-4fbd-b802-9d0b9684170a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010480515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3010480515
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3032333299
Short name T619
Test name
Test status
Simulation time 1093634712 ps
CPU time 16.16 seconds
Started Jul 28 05:02:25 PM PDT 24
Finished Jul 28 05:02:42 PM PDT 24
Peak memory 199912 kb
Host smart-5cfcea17-2aff-4bf4-8725-b6f86635d91a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032333299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3032333299
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1833590963
Short name T653
Test name
Test status
Simulation time 34287687 ps
CPU time 0.73 seconds
Started Jul 28 05:02:14 PM PDT 24
Finished Jul 28 05:02:14 PM PDT 24
Peak memory 197868 kb
Host smart-7caa45a4-7eca-4576-a352-0c8d83c7827b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833590963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1833590963
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2897088832
Short name T589
Test name
Test status
Simulation time 150258881 ps
CPU time 1.1 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:27 PM PDT 24
Peak memory 199836 kb
Host smart-fa6c30fd-23e6-43c1-91b5-df240480cd5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897088832 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2897088832
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1308110048
Short name T543
Test name
Test status
Simulation time 92152245 ps
CPU time 0.8 seconds
Started Jul 28 05:02:07 PM PDT 24
Finished Jul 28 05:02:08 PM PDT 24
Peak memory 198672 kb
Host smart-abedd539-6c96-494d-ab27-eabbab04ef15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308110048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1308110048
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2616670104
Short name T641
Test name
Test status
Simulation time 13369017 ps
CPU time 0.6 seconds
Started Jul 28 05:02:25 PM PDT 24
Finished Jul 28 05:02:26 PM PDT 24
Peak memory 194672 kb
Host smart-ef9c804f-dc98-43ef-99ba-a9b99436b3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616670104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2616670104
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3976397190
Short name T126
Test name
Test status
Simulation time 44908288 ps
CPU time 1.1 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199876 kb
Host smart-421b0780-582b-4b17-ab4b-7debeef49482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976397190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3976397190
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4227599490
Short name T562
Test name
Test status
Simulation time 77542820 ps
CPU time 1.75 seconds
Started Jul 28 05:02:16 PM PDT 24
Finished Jul 28 05:02:17 PM PDT 24
Peak memory 199844 kb
Host smart-6f74d8d2-c20f-48cd-8be1-b68d635c25df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227599490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.4227599490
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2682765042
Short name T133
Test name
Test status
Simulation time 100912420 ps
CPU time 1.87 seconds
Started Jul 28 05:02:04 PM PDT 24
Finished Jul 28 05:02:06 PM PDT 24
Peak memory 199848 kb
Host smart-150fd636-25de-42bc-90a0-7dbbe929999d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682765042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2682765042
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.292621937
Short name T118
Test name
Test status
Simulation time 521093405 ps
CPU time 3.31 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199832 kb
Host smart-4bc2c3f2-43aa-4e5e-b260-484bdcbad172
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292621937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.292621937
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.358774400
Short name T116
Test name
Test status
Simulation time 4376110399 ps
CPU time 11.23 seconds
Started Jul 28 05:02:18 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199880 kb
Host smart-9305e48f-4783-4d6a-9b9d-8e02f553914f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358774400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.358774400
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4020613483
Short name T112
Test name
Test status
Simulation time 26979685 ps
CPU time 0.89 seconds
Started Jul 28 05:02:19 PM PDT 24
Finished Jul 28 05:02:20 PM PDT 24
Peak memory 198928 kb
Host smart-77941c82-1377-45c3-882d-c66bb46319fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020613483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4020613483
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4157032370
Short name T579
Test name
Test status
Simulation time 45959476 ps
CPU time 2.83 seconds
Started Jul 28 05:02:15 PM PDT 24
Finished Jul 28 05:02:18 PM PDT 24
Peak memory 208092 kb
Host smart-8a329fc2-c178-411a-9acd-0987bd223eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157032370 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4157032370
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3107490153
Short name T637
Test name
Test status
Simulation time 189970446 ps
CPU time 0.62 seconds
Started Jul 28 05:02:12 PM PDT 24
Finished Jul 28 05:02:13 PM PDT 24
Peak memory 194784 kb
Host smart-819ba16c-0143-46f4-918f-c8ffb2c6c6a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107490153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3107490153
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1968415116
Short name T574
Test name
Test status
Simulation time 408930474 ps
CPU time 2.18 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:38 PM PDT 24
Peak memory 199856 kb
Host smart-17134fb4-a2ea-4e59-9d35-f542769d7f9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968415116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1968415116
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.508231243
Short name T613
Test name
Test status
Simulation time 75314246 ps
CPU time 1.71 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 199856 kb
Host smart-19c13165-33b0-4ead-beba-82167a9d9bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508231243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.508231243
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1207361305
Short name T132
Test name
Test status
Simulation time 90431496 ps
CPU time 1.81 seconds
Started Jul 28 05:02:30 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 199784 kb
Host smart-238cf0b2-7d15-4bff-8306-53a7281e1b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207361305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1207361305
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3491903301
Short name T538
Test name
Test status
Simulation time 353987301 ps
CPU time 2.54 seconds
Started Jul 28 05:02:17 PM PDT 24
Finished Jul 28 05:02:20 PM PDT 24
Peak memory 199988 kb
Host smart-c2aba31a-7b00-419f-8239-947a0aafa2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491903301 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3491903301
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2297782336
Short name T117
Test name
Test status
Simulation time 18396419 ps
CPU time 0.89 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:27 PM PDT 24
Peak memory 199508 kb
Host smart-f7fb88c5-3110-4dd0-8f2e-95ce6f63c5f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297782336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2297782336
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.403385422
Short name T552
Test name
Test status
Simulation time 50543421 ps
CPU time 0.57 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 194736 kb
Host smart-966a9b4c-597f-477f-9b08-e888e128dd03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403385422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.403385422
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.486949858
Short name T125
Test name
Test status
Simulation time 96398668 ps
CPU time 1.52 seconds
Started Jul 28 05:03:07 PM PDT 24
Finished Jul 28 05:03:09 PM PDT 24
Peak memory 199892 kb
Host smart-936683e9-7660-4632-8f13-d3a75d2965c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486949858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.486949858
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.127307847
Short name T631
Test name
Test status
Simulation time 162701262 ps
CPU time 4.16 seconds
Started Jul 28 05:02:17 PM PDT 24
Finished Jul 28 05:02:21 PM PDT 24
Peak memory 199832 kb
Host smart-384b22fa-8663-4269-8ded-5c410dde87c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127307847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.127307847
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3411704193
Short name T565
Test name
Test status
Simulation time 65732249 ps
CPU time 2.22 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:38 PM PDT 24
Peak memory 208048 kb
Host smart-e8cefca1-8e92-43cd-877a-2547e8f77744
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411704193 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3411704193
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3549025866
Short name T650
Test name
Test status
Simulation time 16717995 ps
CPU time 0.78 seconds
Started Jul 28 05:02:39 PM PDT 24
Finished Jul 28 05:02:39 PM PDT 24
Peak memory 199580 kb
Host smart-280c9ce0-22fe-49b2-92a5-0cb3785a21d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549025866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3549025866
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.170070904
Short name T567
Test name
Test status
Simulation time 51050172 ps
CPU time 0.56 seconds
Started Jul 28 05:02:37 PM PDT 24
Finished Jul 28 05:02:38 PM PDT 24
Peak memory 194836 kb
Host smart-460d3807-39a2-4be3-a801-f76984bba44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170070904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.170070904
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.305296605
Short name T598
Test name
Test status
Simulation time 208822533 ps
CPU time 1.78 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 200008 kb
Host smart-30ea37b6-042b-43b0-b391-72fec866ff18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305296605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.305296605
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2297149737
Short name T570
Test name
Test status
Simulation time 890117792 ps
CPU time 3.9 seconds
Started Jul 28 05:02:30 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 199728 kb
Host smart-16f7c4bb-1aa3-4b77-84b8-767e3c651855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297149737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2297149737
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1186714416
Short name T137
Test name
Test status
Simulation time 498167577 ps
CPU time 3.84 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 199744 kb
Host smart-2a0e32c2-f062-47fa-b21a-2dd93521c1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186714416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1186714416
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3110711691
Short name T566
Test name
Test status
Simulation time 85993726 ps
CPU time 2.14 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199840 kb
Host smart-c7981ee0-e194-45c7-b7a3-41990096f5ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110711691 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3110711691
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3133164859
Short name T123
Test name
Test status
Simulation time 16080251 ps
CPU time 0.81 seconds
Started Jul 28 05:02:23 PM PDT 24
Finished Jul 28 05:02:24 PM PDT 24
Peak memory 199292 kb
Host smart-abf45624-0406-42c7-bbe7-edc5c7215db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133164859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3133164859
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.8341203
Short name T537
Test name
Test status
Simulation time 31803244 ps
CPU time 0.55 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:29 PM PDT 24
Peak memory 194680 kb
Host smart-0b61d72a-7d0d-4290-9370-d94339fc2270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8341203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.8341203
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1772170880
Short name T122
Test name
Test status
Simulation time 34818934 ps
CPU time 1.55 seconds
Started Jul 28 05:02:35 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 199820 kb
Host smart-089fcc6b-7470-4a6b-9687-4272727797c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772170880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1772170880
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4288386379
Short name T601
Test name
Test status
Simulation time 722005923 ps
CPU time 3.95 seconds
Started Jul 28 05:02:24 PM PDT 24
Finished Jul 28 05:02:28 PM PDT 24
Peak memory 199752 kb
Host smart-981cb8a1-c8ec-4f4e-aafb-8c5099e3e491
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288386379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.4288386379
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1240647062
Short name T134
Test name
Test status
Simulation time 455679570 ps
CPU time 3.89 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 199816 kb
Host smart-dcdd7fe2-71ae-415d-ae4c-1f6e511c0305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240647062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1240647062
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1908778459
Short name T596
Test name
Test status
Simulation time 169832540 ps
CPU time 1.25 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:29 PM PDT 24
Peak memory 199744 kb
Host smart-de86c64a-e873-4c83-8c12-9f5bc15243cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908778459 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1908778459
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2279909090
Short name T614
Test name
Test status
Simulation time 27875384 ps
CPU time 0.98 seconds
Started Jul 28 05:02:23 PM PDT 24
Finished Jul 28 05:02:24 PM PDT 24
Peak memory 199404 kb
Host smart-d1618302-0af7-406d-a3f2-931680f668c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279909090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2279909090
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3795036756
Short name T608
Test name
Test status
Simulation time 55101800 ps
CPU time 0.58 seconds
Started Jul 28 05:02:33 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 194720 kb
Host smart-66f62ca5-b8a4-463f-8933-3abe1f113928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795036756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3795036756
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1354825541
Short name T124
Test name
Test status
Simulation time 267809568 ps
CPU time 1.23 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:27 PM PDT 24
Peak memory 199224 kb
Host smart-4317b3bb-758d-4f87-9dfb-0d7efe85efe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354825541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1354825541
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2140582951
Short name T532
Test name
Test status
Simulation time 718089443 ps
CPU time 3.14 seconds
Started Jul 28 05:02:33 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 199840 kb
Host smart-92e1425c-b73c-48a5-a22f-2bcd5c829e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140582951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2140582951
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1717258564
Short name T70
Test name
Test status
Simulation time 286697101 ps
CPU time 4.13 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199796 kb
Host smart-aebeabb0-a42c-496c-90e6-7e85e6bfee4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717258564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1717258564
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1479067185
Short name T604
Test name
Test status
Simulation time 275498338745 ps
CPU time 1422.67 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:26:15 PM PDT 24
Peak memory 222388 kb
Host smart-102c41d5-e6b1-48e0-8110-cceb46dd0d6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479067185 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1479067185
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2644400262
Short name T660
Test name
Test status
Simulation time 12765478 ps
CPU time 0.69 seconds
Started Jul 28 05:02:42 PM PDT 24
Finished Jul 28 05:02:43 PM PDT 24
Peak memory 197612 kb
Host smart-95fa91dc-6c55-45b9-ad2f-d3dc475c630e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644400262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2644400262
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2120116588
Short name T585
Test name
Test status
Simulation time 28110828 ps
CPU time 0.57 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 194744 kb
Host smart-002bdaf0-b7d5-430d-8309-087c32501ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120116588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2120116588
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3738686119
Short name T584
Test name
Test status
Simulation time 66461846 ps
CPU time 1.59 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:29 PM PDT 24
Peak memory 199808 kb
Host smart-a8230782-e9bc-4af7-aa8d-a95c0a1b87e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738686119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3738686119
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.224530153
Short name T558
Test name
Test status
Simulation time 75327403 ps
CPU time 1.61 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:02:43 PM PDT 24
Peak memory 200068 kb
Host smart-bcaaf1da-3ad1-43e5-ae03-62b127c185f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224530153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.224530153
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3979784383
Short name T553
Test name
Test status
Simulation time 138267886 ps
CPU time 1.74 seconds
Started Jul 28 05:02:33 PM PDT 24
Finished Jul 28 05:02:35 PM PDT 24
Peak memory 199932 kb
Host smart-ea31a71a-0763-455b-a274-32b610ba1307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979784383 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3979784383
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.779236852
Short name T105
Test name
Test status
Simulation time 32000442 ps
CPU time 0.71 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 197552 kb
Host smart-b74c6abb-fa0d-4d2c-b5e5-e92ac048f14e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779236852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.779236852
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.71295011
Short name T534
Test name
Test status
Simulation time 29995364 ps
CPU time 0.62 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 195036 kb
Host smart-be0c3c30-c7c5-40e6-be8b-f77dfec6e8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71295011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.71295011
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3869024362
Short name T602
Test name
Test status
Simulation time 43755113 ps
CPU time 2.09 seconds
Started Jul 28 05:02:49 PM PDT 24
Finished Jul 28 05:02:52 PM PDT 24
Peak memory 199792 kb
Host smart-7f54520e-4b73-4286-8f50-7dbcc6cf23c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869024362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3869024362
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2825729104
Short name T550
Test name
Test status
Simulation time 669021525 ps
CPU time 3.76 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:02:58 PM PDT 24
Peak memory 199796 kb
Host smart-5ea33468-61f9-441a-8c41-c1907343f926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825729104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2825729104
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.629991341
Short name T136
Test name
Test status
Simulation time 184985856 ps
CPU time 3.08 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 199816 kb
Host smart-db1ba484-a895-4df9-8692-6d704e0cd8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629991341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.629991341
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.4283668711
Short name T559
Test name
Test status
Simulation time 61524428 ps
CPU time 1.09 seconds
Started Jul 28 05:02:30 PM PDT 24
Finished Jul 28 05:02:31 PM PDT 24
Peak memory 199716 kb
Host smart-8b954c87-df45-4286-bbfb-f2ed8080c4f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283668711 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.4283668711
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3135105525
Short name T623
Test name
Test status
Simulation time 14201644 ps
CPU time 0.66 seconds
Started Jul 28 05:02:38 PM PDT 24
Finished Jul 28 05:02:39 PM PDT 24
Peak memory 197568 kb
Host smart-706f49cf-34c7-4af3-989a-8ccd435cc2f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135105525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3135105525
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.492447746
Short name T569
Test name
Test status
Simulation time 15264042 ps
CPU time 0.57 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 194660 kb
Host smart-40368441-b362-4171-9cfe-406a25a68ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492447746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.492447746
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.497889260
Short name T610
Test name
Test status
Simulation time 62332894 ps
CPU time 1.55 seconds
Started Jul 28 05:02:35 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 199908 kb
Host smart-0d181de1-a952-4f02-9420-7e6856fb5e18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497889260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.497889260
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.354746250
Short name T647
Test name
Test status
Simulation time 270390164 ps
CPU time 3.57 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:35 PM PDT 24
Peak memory 199840 kb
Host smart-e65b2465-12dd-475e-bda1-7d371181b1b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354746250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.354746250
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.849622319
Short name T638
Test name
Test status
Simulation time 284490530 ps
CPU time 4.68 seconds
Started Jul 28 05:02:56 PM PDT 24
Finished Jul 28 05:03:01 PM PDT 24
Peak memory 199852 kb
Host smart-f80d2aa0-c5ab-4159-817f-947b5e709176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849622319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.849622319
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4254509451
Short name T549
Test name
Test status
Simulation time 44537934 ps
CPU time 1.29 seconds
Started Jul 28 05:02:37 PM PDT 24
Finished Jul 28 05:02:38 PM PDT 24
Peak memory 199776 kb
Host smart-4b0eca7d-055d-4e94-b2e0-4d8b116ce358
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254509451 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4254509451
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.874521014
Short name T606
Test name
Test status
Simulation time 83269611 ps
CPU time 0.83 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199620 kb
Host smart-d94b0ab6-0cc0-4f83-b908-b01af3e83dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874521014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.874521014
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2409499816
Short name T620
Test name
Test status
Simulation time 36499547 ps
CPU time 0.56 seconds
Started Jul 28 05:02:27 PM PDT 24
Finished Jul 28 05:02:27 PM PDT 24
Peak memory 194800 kb
Host smart-a31cdeea-4696-453d-8381-259f537be045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409499816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2409499816
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3035657424
Short name T573
Test name
Test status
Simulation time 54036099 ps
CPU time 1.11 seconds
Started Jul 28 05:02:27 PM PDT 24
Finished Jul 28 05:02:28 PM PDT 24
Peak memory 199476 kb
Host smart-1b83bbd8-d64f-404c-8432-54b54a0d55ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035657424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3035657424
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1212279590
Short name T542
Test name
Test status
Simulation time 241633458 ps
CPU time 3.04 seconds
Started Jul 28 05:02:40 PM PDT 24
Finished Jul 28 05:02:43 PM PDT 24
Peak memory 199876 kb
Host smart-a9e57c8b-15d8-45ad-951a-778d19c40332
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212279590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1212279590
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2348858171
Short name T135
Test name
Test status
Simulation time 415058589 ps
CPU time 2.92 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:39 PM PDT 24
Peak memory 199884 kb
Host smart-7d30c2b6-783d-41b4-8855-468e92fcd187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348858171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2348858171
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3877211249
Short name T572
Test name
Test status
Simulation time 60578551 ps
CPU time 1.77 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:02:43 PM PDT 24
Peak memory 199872 kb
Host smart-46651fb9-4a40-417f-ab48-2e5465684664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877211249 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3877211249
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3740444079
Short name T629
Test name
Test status
Simulation time 17898706 ps
CPU time 0.7 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 197788 kb
Host smart-0ac66dd6-aed6-416d-9dc0-8bbf2e8f1cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740444079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3740444079
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3936139817
Short name T611
Test name
Test status
Simulation time 24153697 ps
CPU time 0.59 seconds
Started Jul 28 05:02:25 PM PDT 24
Finished Jul 28 05:02:26 PM PDT 24
Peak memory 194812 kb
Host smart-73e679b9-351a-497f-a6f7-e52e5431dccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936139817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3936139817
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4017310986
Short name T593
Test name
Test status
Simulation time 78307983 ps
CPU time 1.11 seconds
Started Jul 28 05:02:35 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 199728 kb
Host smart-68d1690b-2fbb-44d3-9489-42e9a3cde8d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017310986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.4017310986
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4041022043
Short name T626
Test name
Test status
Simulation time 51400769 ps
CPU time 1.36 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 199928 kb
Host smart-e692a7b5-a460-462b-8d9c-435fecebbc33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041022043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4041022043
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2534213722
Short name T607
Test name
Test status
Simulation time 752082136 ps
CPU time 3.23 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:39 PM PDT 24
Peak memory 199948 kb
Host smart-3069682f-fb9c-4876-a206-b1efc7197822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534213722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2534213722
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3660428515
Short name T544
Test name
Test status
Simulation time 342018514 ps
CPU time 2.26 seconds
Started Jul 28 05:02:35 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 199872 kb
Host smart-bb6054f8-3dde-4af4-b3d4-946a51c00fee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660428515 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3660428515
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1122127442
Short name T113
Test name
Test status
Simulation time 35370411 ps
CPU time 0.93 seconds
Started Jul 28 05:02:54 PM PDT 24
Finished Jul 28 05:02:55 PM PDT 24
Peak memory 199588 kb
Host smart-8fa0c720-c23f-495f-ba5d-0585b0ef97a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122127442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1122127442
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1851006636
Short name T561
Test name
Test status
Simulation time 20868225 ps
CPU time 0.56 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:29 PM PDT 24
Peak memory 194652 kb
Host smart-861e595c-34fc-4dc5-b0aa-a2add81e548a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851006636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1851006636
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3648430670
Short name T635
Test name
Test status
Simulation time 151151173 ps
CPU time 2.02 seconds
Started Jul 28 05:02:35 PM PDT 24
Finished Jul 28 05:02:38 PM PDT 24
Peak memory 199828 kb
Host smart-79e21c6e-295f-4e06-8a30-80c46f8aa52d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648430670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3648430670
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.255912100
Short name T554
Test name
Test status
Simulation time 205051347 ps
CPU time 3.44 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 199788 kb
Host smart-315c1578-ef00-409e-96db-19be7f601db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255912100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.255912100
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1638484295
Short name T644
Test name
Test status
Simulation time 94953492 ps
CPU time 1.83 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199832 kb
Host smart-d0feba82-b88c-4930-b392-2bd5865ccca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638484295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1638484295
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1925737134
Short name T114
Test name
Test status
Simulation time 206057920 ps
CPU time 5.48 seconds
Started Jul 28 05:02:27 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 199832 kb
Host smart-a80dc4bf-96bb-4b64-b674-a4d8c94bb27a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925737134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1925737134
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3687950452
Short name T657
Test name
Test status
Simulation time 115470357 ps
CPU time 5.15 seconds
Started Jul 28 05:02:16 PM PDT 24
Finished Jul 28 05:02:22 PM PDT 24
Peak memory 198460 kb
Host smart-cc2ee2b7-cd99-4796-8440-1efdd20134cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687950452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3687950452
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2271504551
Short name T110
Test name
Test status
Simulation time 69353175 ps
CPU time 0.99 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 199400 kb
Host smart-b484a4a3-40e6-4359-8729-09fcb1353e59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271504551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2271504551
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4176744071
Short name T636
Test name
Test status
Simulation time 43885840 ps
CPU time 1.22 seconds
Started Jul 28 05:02:24 PM PDT 24
Finished Jul 28 05:02:26 PM PDT 24
Peak memory 199652 kb
Host smart-2c3f657a-e2ba-462c-9503-dc9afb499e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176744071 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4176744071
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3449182053
Short name T633
Test name
Test status
Simulation time 116630389 ps
CPU time 0.81 seconds
Started Jul 28 05:02:14 PM PDT 24
Finished Jul 28 05:02:15 PM PDT 24
Peak memory 199128 kb
Host smart-05a9b9ee-ef75-494e-a639-6412efc9f55a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449182053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3449182053
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2605222895
Short name T625
Test name
Test status
Simulation time 37014044 ps
CPU time 0.58 seconds
Started Jul 28 05:02:14 PM PDT 24
Finished Jul 28 05:02:15 PM PDT 24
Peak memory 194764 kb
Host smart-f4661839-51ef-4c70-8d55-54d2e30fa7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605222895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2605222895
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2083507957
Short name T571
Test name
Test status
Simulation time 270911382 ps
CPU time 1.72 seconds
Started Jul 28 05:02:12 PM PDT 24
Finished Jul 28 05:02:14 PM PDT 24
Peak memory 200072 kb
Host smart-8c41badb-51d9-4396-a830-19331466ef2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083507957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2083507957
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.988420776
Short name T605
Test name
Test status
Simulation time 230108055 ps
CPU time 1.49 seconds
Started Jul 28 05:02:16 PM PDT 24
Finished Jul 28 05:02:17 PM PDT 24
Peak memory 199824 kb
Host smart-d279cab8-d1a7-446c-9fc9-138b9635fa75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988420776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.988420776
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2178049992
Short name T551
Test name
Test status
Simulation time 21299835 ps
CPU time 0.57 seconds
Started Jul 28 05:02:53 PM PDT 24
Finished Jul 28 05:02:54 PM PDT 24
Peak memory 194860 kb
Host smart-337e1deb-3b1c-4d23-84bf-1845eef7933e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178049992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2178049992
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.255622817
Short name T649
Test name
Test status
Simulation time 14673579 ps
CPU time 0.57 seconds
Started Jul 28 05:02:42 PM PDT 24
Finished Jul 28 05:02:43 PM PDT 24
Peak memory 194680 kb
Host smart-3281d18e-b42d-48e1-ac7b-c4ec694a8aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255622817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.255622817
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1598773955
Short name T575
Test name
Test status
Simulation time 22516304 ps
CPU time 0.61 seconds
Started Jul 28 05:02:33 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 194728 kb
Host smart-4964c217-44f6-4d4b-bf4d-b6f3ba968213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598773955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1598773955
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1892630444
Short name T591
Test name
Test status
Simulation time 11382220 ps
CPU time 0.59 seconds
Started Jul 28 05:02:37 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 194728 kb
Host smart-82b7eb9b-92db-4e4d-b047-5f3fc0edf97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892630444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1892630444
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3853803546
Short name T621
Test name
Test status
Simulation time 22114680 ps
CPU time 0.56 seconds
Started Jul 28 05:02:30 PM PDT 24
Finished Jul 28 05:02:31 PM PDT 24
Peak memory 194680 kb
Host smart-a9d0bea8-e819-4b8c-b7a2-2930945d0a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853803546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3853803546
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3529921426
Short name T564
Test name
Test status
Simulation time 72933220 ps
CPU time 0.56 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 194684 kb
Host smart-f3b63b6e-cc02-4d42-965a-132d779321a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529921426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3529921426
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2891751127
Short name T576
Test name
Test status
Simulation time 16479303 ps
CPU time 0.57 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 194760 kb
Host smart-4247f867-cb9b-4c22-ba41-bfb71fd3fbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891751127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2891751127
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2254284301
Short name T627
Test name
Test status
Simulation time 159120488 ps
CPU time 0.61 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:51 PM PDT 24
Peak memory 194828 kb
Host smart-4ea98b64-3c5e-41ee-b627-8aea32e810ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254284301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2254284301
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2284645619
Short name T555
Test name
Test status
Simulation time 20566233 ps
CPU time 0.6 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:31 PM PDT 24
Peak memory 194928 kb
Host smart-c731d735-c132-4717-9d6d-d3191fc2893b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284645619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2284645619
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1385356685
Short name T643
Test name
Test status
Simulation time 17487122 ps
CPU time 0.56 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 194732 kb
Host smart-64e6960a-1896-4f04-82d8-94c2718e2e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385356685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1385356685
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2768178541
Short name T615
Test name
Test status
Simulation time 665300158 ps
CPU time 7.96 seconds
Started Jul 28 05:02:17 PM PDT 24
Finished Jul 28 05:02:25 PM PDT 24
Peak memory 199840 kb
Host smart-5972b422-9c8e-4312-a68b-1edd0b7d2ce9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768178541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2768178541
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.886662819
Short name T651
Test name
Test status
Simulation time 1433547210 ps
CPU time 9.92 seconds
Started Jul 28 05:02:23 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 199820 kb
Host smart-2f7f5d9b-7de3-49a2-a4be-dc099a0f00fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886662819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.886662819
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.218092331
Short name T107
Test name
Test status
Simulation time 92727222 ps
CPU time 0.85 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199048 kb
Host smart-01537598-97d8-4529-a6b9-2cdb620c0248
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218092331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.218092331
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2597415053
Short name T556
Test name
Test status
Simulation time 30307332 ps
CPU time 1.82 seconds
Started Jul 28 05:02:15 PM PDT 24
Finished Jul 28 05:02:17 PM PDT 24
Peak memory 199932 kb
Host smart-06be0b62-61f6-417d-98fd-ccf0adfb9a70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597415053 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2597415053
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1229525252
Short name T578
Test name
Test status
Simulation time 57471867 ps
CPU time 0.7 seconds
Started Jul 28 05:02:25 PM PDT 24
Finished Jul 28 05:02:26 PM PDT 24
Peak memory 197836 kb
Host smart-5d93b909-1831-4c10-81ba-3537200a5d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229525252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1229525252
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3239314751
Short name T560
Test name
Test status
Simulation time 11443187 ps
CPU time 0.62 seconds
Started Jul 28 05:02:24 PM PDT 24
Finished Jul 28 05:02:25 PM PDT 24
Peak memory 194752 kb
Host smart-82bd6610-e45d-4eab-8dc8-1a8021af0ab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239314751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3239314751
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.97782071
Short name T121
Test name
Test status
Simulation time 108834191 ps
CPU time 1.67 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:28 PM PDT 24
Peak memory 199740 kb
Host smart-f0cbc907-bd2e-48d2-9f9b-27858e126f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97782071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_o
utstanding.97782071
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1329170071
Short name T541
Test name
Test status
Simulation time 317105191 ps
CPU time 3.55 seconds
Started Jul 28 05:02:24 PM PDT 24
Finished Jul 28 05:02:27 PM PDT 24
Peak memory 199752 kb
Host smart-d13c84c4-3f9a-46b9-91a2-1fbe4a24b204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329170071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1329170071
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1333943258
Short name T640
Test name
Test status
Simulation time 191952722 ps
CPU time 1.89 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 199844 kb
Host smart-926bff42-1a2f-4a42-9e62-ad936b6236b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333943258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1333943258
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4214068672
Short name T645
Test name
Test status
Simulation time 38536559 ps
CPU time 0.59 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 194760 kb
Host smart-b5bef5f4-578e-407f-a527-81342208488b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214068672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4214068672
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3083946769
Short name T539
Test name
Test status
Simulation time 15453196 ps
CPU time 0.57 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 194664 kb
Host smart-fe65844a-2c1c-44da-b616-e468aa9bb284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083946769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3083946769
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1607181869
Short name T632
Test name
Test status
Simulation time 27879876 ps
CPU time 0.56 seconds
Started Jul 28 05:02:37 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 194820 kb
Host smart-94685e7d-925d-4505-b225-ea214a138f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607181869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1607181869
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3153124696
Short name T597
Test name
Test status
Simulation time 12840247 ps
CPU time 0.61 seconds
Started Jul 28 05:02:44 PM PDT 24
Finished Jul 28 05:02:45 PM PDT 24
Peak memory 194792 kb
Host smart-86d0f59f-435e-4750-8086-43aec0cb7478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153124696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3153124696
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.230305810
Short name T531
Test name
Test status
Simulation time 24844770 ps
CPU time 0.6 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:02:42 PM PDT 24
Peak memory 194804 kb
Host smart-236e3974-248b-4095-a9db-e6883339efdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230305810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.230305810
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.205929300
Short name T592
Test name
Test status
Simulation time 12331847 ps
CPU time 0.59 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:02:42 PM PDT 24
Peak memory 194784 kb
Host smart-dc64308b-744d-4c39-a896-916ba76af4cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205929300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.205929300
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1191707111
Short name T624
Test name
Test status
Simulation time 11332668 ps
CPU time 0.59 seconds
Started Jul 28 05:02:39 PM PDT 24
Finished Jul 28 05:02:39 PM PDT 24
Peak memory 194688 kb
Host smart-35f1fb71-9719-4add-9ba3-d0c8f2fb911d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191707111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1191707111
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1987927310
Short name T540
Test name
Test status
Simulation time 54623910 ps
CPU time 0.59 seconds
Started Jul 28 05:02:35 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 194804 kb
Host smart-6e1dfc49-f689-487f-bdaa-d62e72ff6b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987927310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1987927310
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.919293265
Short name T595
Test name
Test status
Simulation time 11498989 ps
CPU time 0.61 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 194672 kb
Host smart-4b777b42-c2b6-422b-88a3-b6138bf77ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919293265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.919293265
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2980394878
Short name T581
Test name
Test status
Simulation time 20483398 ps
CPU time 0.57 seconds
Started Jul 28 05:02:38 PM PDT 24
Finished Jul 28 05:02:39 PM PDT 24
Peak memory 194824 kb
Host smart-691f980e-d86d-4e54-a5b9-4c74702e4ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980394878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2980394878
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1729998946
Short name T109
Test name
Test status
Simulation time 211522292 ps
CPU time 2.98 seconds
Started Jul 28 05:02:22 PM PDT 24
Finished Jul 28 05:02:25 PM PDT 24
Peak memory 199764 kb
Host smart-bd909d97-6d85-44c6-ab2f-b84e38aa3201
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729998946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1729998946
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1378702977
Short name T111
Test name
Test status
Simulation time 559168954 ps
CPU time 5.83 seconds
Started Jul 28 05:02:23 PM PDT 24
Finished Jul 28 05:02:29 PM PDT 24
Peak memory 199808 kb
Host smart-3157c2f9-7888-4007-bfb0-133bdb333434
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378702977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1378702977
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.584912473
Short name T115
Test name
Test status
Simulation time 111113448 ps
CPU time 0.92 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:27 PM PDT 24
Peak memory 199012 kb
Host smart-adec3fa7-a8c0-4630-88ca-cba5197aca3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584912473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.584912473
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1731918636
Short name T557
Test name
Test status
Simulation time 73740305 ps
CPU time 1.31 seconds
Started Jul 28 05:02:21 PM PDT 24
Finished Jul 28 05:02:22 PM PDT 24
Peak memory 199840 kb
Host smart-fe28882d-e924-42a7-b7d0-fa53270284e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731918636 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1731918636
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2074368943
Short name T106
Test name
Test status
Simulation time 18927876 ps
CPU time 0.88 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 199524 kb
Host smart-a21acf63-c2a8-46bc-aaa3-bcfe110d101b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074368943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2074368943
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1017211803
Short name T545
Test name
Test status
Simulation time 14480054 ps
CPU time 0.63 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:29 PM PDT 24
Peak memory 194716 kb
Host smart-0f86a8b5-f6da-4175-a840-6884c0addba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017211803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1017211803
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4094681582
Short name T652
Test name
Test status
Simulation time 104270140 ps
CPU time 1.68 seconds
Started Jul 28 05:02:22 PM PDT 24
Finished Jul 28 05:02:24 PM PDT 24
Peak memory 199804 kb
Host smart-47f9ab04-1884-486d-a459-433deab19c47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094681582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4094681582
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1861455675
Short name T582
Test name
Test status
Simulation time 672990746 ps
CPU time 2.87 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 199736 kb
Host smart-71b82dd8-3e98-41a8-8409-fdc470386047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861455675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1861455675
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1681599544
Short name T69
Test name
Test status
Simulation time 286422175 ps
CPU time 4.48 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 199868 kb
Host smart-183da1f0-acff-4710-9025-2684fe7039ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681599544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1681599544
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.694559847
Short name T548
Test name
Test status
Simulation time 13456760 ps
CPU time 0.6 seconds
Started Jul 28 05:02:51 PM PDT 24
Finished Jul 28 05:02:51 PM PDT 24
Peak memory 194740 kb
Host smart-33f9819a-e5bc-4343-965c-be298e524a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694559847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.694559847
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2178307108
Short name T563
Test name
Test status
Simulation time 14810338 ps
CPU time 0.58 seconds
Started Jul 28 05:03:04 PM PDT 24
Finished Jul 28 05:03:05 PM PDT 24
Peak memory 194704 kb
Host smart-0855d228-2141-4c5e-a88c-ecefe9f3ade9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178307108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2178307108
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4279177810
Short name T654
Test name
Test status
Simulation time 31842491 ps
CPU time 0.57 seconds
Started Jul 28 05:03:01 PM PDT 24
Finished Jul 28 05:03:02 PM PDT 24
Peak memory 194672 kb
Host smart-a957c361-7d9a-4415-af17-918cdd76b83f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279177810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4279177810
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.4187833418
Short name T577
Test name
Test status
Simulation time 12175989 ps
CPU time 0.61 seconds
Started Jul 28 05:02:50 PM PDT 24
Finished Jul 28 05:02:50 PM PDT 24
Peak memory 194816 kb
Host smart-4725cf3d-c984-4419-b509-c2018589e2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187833418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4187833418
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2542973130
Short name T659
Test name
Test status
Simulation time 66646541 ps
CPU time 0.58 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 194804 kb
Host smart-45217976-5830-4881-8225-935dd723f9e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542973130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2542973130
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.4087219268
Short name T533
Test name
Test status
Simulation time 37301114 ps
CPU time 0.56 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:49 PM PDT 24
Peak memory 194664 kb
Host smart-efa91575-7ad0-4dd5-a2d7-3d8d5c215a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087219268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4087219268
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2476360185
Short name T547
Test name
Test status
Simulation time 18228171 ps
CPU time 0.56 seconds
Started Jul 28 05:02:37 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 194636 kb
Host smart-ff3e32bc-0c54-4da3-8b24-95eb41c84fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476360185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2476360185
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.765300941
Short name T658
Test name
Test status
Simulation time 15199363 ps
CPU time 0.59 seconds
Started Jul 28 05:02:48 PM PDT 24
Finished Jul 28 05:02:49 PM PDT 24
Peak memory 194744 kb
Host smart-c20e8b65-7298-4bc9-81be-f67d33ea1ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765300941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.765300941
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3738198484
Short name T656
Test name
Test status
Simulation time 40953333 ps
CPU time 0.6 seconds
Started Jul 28 05:02:35 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 194684 kb
Host smart-c020760f-9bf0-4ddc-9564-9cde4ce95573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738198484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3738198484
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3159347255
Short name T590
Test name
Test status
Simulation time 101115960 ps
CPU time 0.57 seconds
Started Jul 28 05:02:41 PM PDT 24
Finished Jul 28 05:02:42 PM PDT 24
Peak memory 194692 kb
Host smart-15708d73-d4bf-4f0d-8ae7-1587138924c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159347255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3159347255
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3370041258
Short name T600
Test name
Test status
Simulation time 484234224 ps
CPU time 2.24 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:31 PM PDT 24
Peak memory 199856 kb
Host smart-73e1f679-e7bd-41c7-96d8-34ec5825783a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370041258 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3370041258
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.936716250
Short name T634
Test name
Test status
Simulation time 13108556 ps
CPU time 0.71 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:29 PM PDT 24
Peak memory 198392 kb
Host smart-3b0d06e1-3d30-4b54-b491-4828128ac218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936716250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.936716250
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3962292576
Short name T594
Test name
Test status
Simulation time 11040171 ps
CPU time 0.57 seconds
Started Jul 28 05:02:24 PM PDT 24
Finished Jul 28 05:02:24 PM PDT 24
Peak memory 194708 kb
Host smart-9d171a28-074d-45cb-84b7-2831e2d7b497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962292576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3962292576
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4275249437
Short name T120
Test name
Test status
Simulation time 95604202 ps
CPU time 1.75 seconds
Started Jul 28 05:02:14 PM PDT 24
Finished Jul 28 05:02:16 PM PDT 24
Peak memory 199764 kb
Host smart-22078d60-6af8-4f64-ab36-6496aa665e92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275249437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4275249437
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3195380986
Short name T628
Test name
Test status
Simulation time 282657297 ps
CPU time 3.75 seconds
Started Jul 28 05:02:27 PM PDT 24
Finished Jul 28 05:02:31 PM PDT 24
Peak memory 199840 kb
Host smart-a2e097dc-6220-4541-be9f-25a5901af474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195380986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3195380986
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1604260871
Short name T568
Test name
Test status
Simulation time 116418986 ps
CPU time 1.88 seconds
Started Jul 28 05:02:13 PM PDT 24
Finished Jul 28 05:02:15 PM PDT 24
Peak memory 199824 kb
Host smart-bdbb5b1c-ef81-4b56-97e9-1d21a26cee96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604260871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1604260871
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.4079553032
Short name T655
Test name
Test status
Simulation time 103308362 ps
CPU time 2.55 seconds
Started Jul 28 05:02:45 PM PDT 24
Finished Jul 28 05:02:48 PM PDT 24
Peak memory 199944 kb
Host smart-ecd3cab7-1b89-46c2-a941-0b6e89ab1cc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079553032 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.4079553032
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1443271037
Short name T642
Test name
Test status
Simulation time 65688753 ps
CPU time 0.94 seconds
Started Jul 28 05:02:25 PM PDT 24
Finished Jul 28 05:02:26 PM PDT 24
Peak memory 199416 kb
Host smart-f639ae5f-de6e-4982-9bdf-6d85b6630cb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443271037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1443271037
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.494415077
Short name T536
Test name
Test status
Simulation time 20841705 ps
CPU time 0.6 seconds
Started Jul 28 05:02:30 PM PDT 24
Finished Jul 28 05:02:31 PM PDT 24
Peak memory 194768 kb
Host smart-cd915e94-5ddf-4c14-a01a-c7b5b72d8b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494415077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.494415077
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1040269097
Short name T612
Test name
Test status
Simulation time 360693577 ps
CPU time 1.63 seconds
Started Jul 28 05:02:22 PM PDT 24
Finished Jul 28 05:02:24 PM PDT 24
Peak memory 199828 kb
Host smart-325f9aca-0576-4058-9ced-5275b4ed937e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040269097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1040269097
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1338026241
Short name T587
Test name
Test status
Simulation time 496669494 ps
CPU time 1.82 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199872 kb
Host smart-c371d1a6-3003-4677-bb33-504f25c0b5db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338026241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1338026241
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.4057373650
Short name T129
Test name
Test status
Simulation time 239961430 ps
CPU time 3.76 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:35 PM PDT 24
Peak memory 199756 kb
Host smart-0dd2f524-cbe4-469a-8e0b-20fab71e23bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057373650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.4057373650
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.349669745
Short name T588
Test name
Test status
Simulation time 167690914612 ps
CPU time 1217.77 seconds
Started Jul 28 05:02:30 PM PDT 24
Finished Jul 28 05:22:48 PM PDT 24
Peak memory 226780 kb
Host smart-445826d2-ac01-453c-8458-45ac9da07560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349669745 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.349669745
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3105533664
Short name T617
Test name
Test status
Simulation time 15976380 ps
CPU time 0.7 seconds
Started Jul 28 05:02:23 PM PDT 24
Finished Jul 28 05:02:23 PM PDT 24
Peak memory 198116 kb
Host smart-8b7503ee-0d72-4f8b-a35b-62f03338f0ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105533664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3105533664
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2121511981
Short name T583
Test name
Test status
Simulation time 34750750 ps
CPU time 0.54 seconds
Started Jul 28 05:02:24 PM PDT 24
Finished Jul 28 05:02:25 PM PDT 24
Peak memory 194740 kb
Host smart-61e745ea-e9f0-4f51-a5a7-a60d06cf3582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121511981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2121511981
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.616676840
Short name T586
Test name
Test status
Simulation time 45757045 ps
CPU time 1.17 seconds
Started Jul 28 05:02:36 PM PDT 24
Finished Jul 28 05:02:38 PM PDT 24
Peak memory 199812 kb
Host smart-d65689f1-76ee-40a0-b7dd-a3681f8c1bf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616676840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.616676840
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.394173467
Short name T630
Test name
Test status
Simulation time 169450391 ps
CPU time 3.46 seconds
Started Jul 28 05:02:43 PM PDT 24
Finished Jul 28 05:02:47 PM PDT 24
Peak memory 199888 kb
Host smart-aac42e58-e300-4f16-8a23-be97e7b32b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394173467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.394173467
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.131573879
Short name T130
Test name
Test status
Simulation time 202682867 ps
CPU time 3.24 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 199868 kb
Host smart-af7ccf36-511f-4052-9e50-d2e201c0cac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131573879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.131573879
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2886104799
Short name T646
Test name
Test status
Simulation time 67155656 ps
CPU time 1.91 seconds
Started Jul 28 05:02:26 PM PDT 24
Finished Jul 28 05:02:28 PM PDT 24
Peak memory 200028 kb
Host smart-343b3375-a7f8-4540-bdc5-2646ac68cf79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886104799 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2886104799
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3213264658
Short name T603
Test name
Test status
Simulation time 29475302 ps
CPU time 0.96 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:31 PM PDT 24
Peak memory 199844 kb
Host smart-02334245-939b-4673-a525-f92ec52a8135
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213264658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3213264658
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.588207891
Short name T616
Test name
Test status
Simulation time 23814858 ps
CPU time 0.6 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 194728 kb
Host smart-3341287e-4c38-4b77-9d29-f93b6a058ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588207891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.588207891
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1826305736
Short name T119
Test name
Test status
Simulation time 170534803 ps
CPU time 2.36 seconds
Started Jul 28 05:02:20 PM PDT 24
Finished Jul 28 05:02:23 PM PDT 24
Peak memory 199888 kb
Host smart-53080c86-04e1-488e-9d4d-3faef7e497da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826305736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1826305736
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1986262933
Short name T535
Test name
Test status
Simulation time 193171850 ps
CPU time 2.73 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:02:37 PM PDT 24
Peak memory 199864 kb
Host smart-0a05c406-be44-438e-9a1a-2e8a93daf0d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986262933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1986262933
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3345712714
Short name T609
Test name
Test status
Simulation time 84840817 ps
CPU time 1.66 seconds
Started Jul 28 05:02:32 PM PDT 24
Finished Jul 28 05:02:34 PM PDT 24
Peak memory 199848 kb
Host smart-9247f47d-8fe5-47ea-a0ef-d8fde302e161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345712714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3345712714
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4034720194
Short name T546
Test name
Test status
Simulation time 16941648350 ps
CPU time 165.23 seconds
Started Jul 28 05:02:20 PM PDT 24
Finished Jul 28 05:05:05 PM PDT 24
Peak memory 215804 kb
Host smart-90d1e13c-a820-45e6-a2ef-153a942fd999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034720194 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.4034720194
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.154454032
Short name T648
Test name
Test status
Simulation time 98281572 ps
CPU time 0.81 seconds
Started Jul 28 05:02:31 PM PDT 24
Finished Jul 28 05:02:32 PM PDT 24
Peak memory 199104 kb
Host smart-7bf5bc35-6da6-486c-bd67-bad243862a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154454032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.154454032
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3934550150
Short name T622
Test name
Test status
Simulation time 15569335 ps
CPU time 0.61 seconds
Started Jul 28 05:02:24 PM PDT 24
Finished Jul 28 05:02:25 PM PDT 24
Peak memory 194752 kb
Host smart-02392078-5cf4-41a9-bea2-301d1adf6463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934550150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3934550150
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4191454906
Short name T639
Test name
Test status
Simulation time 479225961 ps
CPU time 1.81 seconds
Started Jul 28 05:02:28 PM PDT 24
Finished Jul 28 05:02:30 PM PDT 24
Peak memory 199780 kb
Host smart-7913eec5-66b3-433b-b4be-8de057e886c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191454906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4191454906
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4047137688
Short name T580
Test name
Test status
Simulation time 64092866 ps
CPU time 3.17 seconds
Started Jul 28 05:02:29 PM PDT 24
Finished Jul 28 05:02:33 PM PDT 24
Peak memory 199940 kb
Host smart-b3c43a37-6e72-4ae5-8717-848653ae2a68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047137688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4047137688
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2436468389
Short name T71
Test name
Test status
Simulation time 190025254 ps
CPU time 1.75 seconds
Started Jul 28 05:02:34 PM PDT 24
Finished Jul 28 05:02:36 PM PDT 24
Peak memory 199892 kb
Host smart-92a92b56-727d-44a5-8915-4a3a938ca007
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436468389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2436468389
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2241580463
Short name T36
Test name
Test status
Simulation time 27566947 ps
CPU time 0.56 seconds
Started Jul 28 07:13:43 PM PDT 24
Finished Jul 28 07:13:44 PM PDT 24
Peak memory 195656 kb
Host smart-08240d60-6379-4891-90b8-cf7bf75bddd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241580463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2241580463
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2569930549
Short name T473
Test name
Test status
Simulation time 340106923 ps
CPU time 17.89 seconds
Started Jul 28 07:13:39 PM PDT 24
Finished Jul 28 07:13:57 PM PDT 24
Peak memory 199632 kb
Host smart-0a1d1c1f-07cc-4df3-9f7a-c426322fb600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569930549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2569930549
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.98949779
Short name T252
Test name
Test status
Simulation time 5088897299 ps
CPU time 14.29 seconds
Started Jul 28 07:13:43 PM PDT 24
Finished Jul 28 07:13:58 PM PDT 24
Peak memory 199720 kb
Host smart-bcbb4a9a-7f32-4bf7-b28c-5e8aa51f47e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98949779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.98949779
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.318746318
Short name T164
Test name
Test status
Simulation time 5363258593 ps
CPU time 290.39 seconds
Started Jul 28 07:13:37 PM PDT 24
Finished Jul 28 07:18:28 PM PDT 24
Peak memory 498288 kb
Host smart-4069aad8-348c-46cb-baa0-e88aefb0bdb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318746318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.318746318
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1663746347
Short name T360
Test name
Test status
Simulation time 10964059845 ps
CPU time 114.53 seconds
Started Jul 28 07:13:44 PM PDT 24
Finished Jul 28 07:15:39 PM PDT 24
Peak memory 199700 kb
Host smart-3d4bf792-91e9-4289-a6d2-d7b4bbf28e3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663746347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1663746347
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3327839774
Short name T309
Test name
Test status
Simulation time 3834442341 ps
CPU time 105.5 seconds
Started Jul 28 07:13:44 PM PDT 24
Finished Jul 28 07:15:29 PM PDT 24
Peak memory 199764 kb
Host smart-6367e7b5-481d-4647-a532-73f7dff61976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327839774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3327839774
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3040317137
Short name T215
Test name
Test status
Simulation time 260735067 ps
CPU time 3.74 seconds
Started Jul 28 07:13:38 PM PDT 24
Finished Jul 28 07:13:42 PM PDT 24
Peak memory 199568 kb
Host smart-1536f045-99c9-4a08-a7f4-11c9f30877a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040317137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3040317137
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.4077246324
Short name T514
Test name
Test status
Simulation time 130459524437 ps
CPU time 550.17 seconds
Started Jul 28 07:13:43 PM PDT 24
Finished Jul 28 07:22:53 PM PDT 24
Peak memory 199732 kb
Host smart-9a01958f-049a-46ba-9e87-50e68ad2c712
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077246324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.4077246324
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3229059257
Short name T13
Test name
Test status
Simulation time 57664221477 ps
CPU time 1037.98 seconds
Started Jul 28 07:13:41 PM PDT 24
Finished Jul 28 07:31:00 PM PDT 24
Peak memory 707036 kb
Host smart-aad865d6-6d1f-4313-9935-1f96717e108b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229059257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3229059257
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3192166868
Short name T493
Test name
Test status
Simulation time 1578199763 ps
CPU time 62.21 seconds
Started Jul 28 07:13:43 PM PDT 24
Finished Jul 28 07:14:46 PM PDT 24
Peak memory 199636 kb
Host smart-9100886f-a1e2-4ccc-85ef-1384462cc752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3192166868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3192166868
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2275079122
Short name T78
Test name
Test status
Simulation time 8948916135 ps
CPU time 89.77 seconds
Started Jul 28 07:13:40 PM PDT 24
Finished Jul 28 07:15:10 PM PDT 24
Peak memory 199732 kb
Host smart-e9621853-142c-4af3-9562-e73b0b382332
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2275079122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2275079122
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3411905889
Short name T237
Test name
Test status
Simulation time 11880594145 ps
CPU time 107.3 seconds
Started Jul 28 07:13:44 PM PDT 24
Finished Jul 28 07:15:31 PM PDT 24
Peak memory 199748 kb
Host smart-b17a7912-e1ce-4f03-9505-ec6378bed32f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3411905889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3411905889
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2964061357
Short name T413
Test name
Test status
Simulation time 21663391503 ps
CPU time 600.19 seconds
Started Jul 28 07:13:44 PM PDT 24
Finished Jul 28 07:23:44 PM PDT 24
Peak memory 199768 kb
Host smart-33f0984a-47b6-4f1a-9172-28b600365900
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2964061357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2964061357
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3719183190
Short name T141
Test name
Test status
Simulation time 41050263006 ps
CPU time 2245.46 seconds
Started Jul 28 07:13:43 PM PDT 24
Finished Jul 28 07:51:09 PM PDT 24
Peak memory 215112 kb
Host smart-178a513b-9ec5-40eb-9198-759b2e5553ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3719183190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3719183190
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3040275304
Short name T263
Test name
Test status
Simulation time 172383929744 ps
CPU time 2344.94 seconds
Started Jul 28 07:13:44 PM PDT 24
Finished Jul 28 07:52:49 PM PDT 24
Peak memory 215264 kb
Host smart-0340ad10-e339-4406-843c-4b5b2906ec19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3040275304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3040275304
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1320590248
Short name T317
Test name
Test status
Simulation time 2627538439 ps
CPU time 6.57 seconds
Started Jul 28 07:13:40 PM PDT 24
Finished Jul 28 07:13:46 PM PDT 24
Peak memory 199800 kb
Host smart-e32a32dc-eff7-4564-87e4-77a1b574ea29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320590248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1320590248
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2843939960
Short name T530
Test name
Test status
Simulation time 20808685764 ps
CPU time 70.46 seconds
Started Jul 28 07:13:52 PM PDT 24
Finished Jul 28 07:15:02 PM PDT 24
Peak memory 216132 kb
Host smart-7b05deb2-4310-42c7-95db-8a8f3cac1b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843939960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2843939960
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1703974631
Short name T94
Test name
Test status
Simulation time 20832720 ps
CPU time 0.67 seconds
Started Jul 28 07:13:50 PM PDT 24
Finished Jul 28 07:13:51 PM PDT 24
Peak memory 197800 kb
Host smart-3ab8c7bb-6858-4b47-967c-337129ecfe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703974631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1703974631
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1752277486
Short name T178
Test name
Test status
Simulation time 10263630125 ps
CPU time 924.93 seconds
Started Jul 28 07:13:51 PM PDT 24
Finished Jul 28 07:29:16 PM PDT 24
Peak memory 708048 kb
Host smart-81088b26-c3d4-4eb1-81f1-4593cf7dcd1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752277486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1752277486
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3746238840
Short name T359
Test name
Test status
Simulation time 34796863563 ps
CPU time 212.69 seconds
Started Jul 28 07:13:49 PM PDT 24
Finished Jul 28 07:17:22 PM PDT 24
Peak memory 199756 kb
Host smart-50c43f88-1e07-4176-8459-c3215debfa5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746238840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3746238840
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3517231210
Short name T352
Test name
Test status
Simulation time 475722127 ps
CPU time 16.77 seconds
Started Jul 28 07:13:46 PM PDT 24
Finished Jul 28 07:14:03 PM PDT 24
Peak memory 199860 kb
Host smart-ab1d0e06-a91c-47fb-8353-daaa3e9189ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517231210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3517231210
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1579228613
Short name T59
Test name
Test status
Simulation time 58771471 ps
CPU time 0.92 seconds
Started Jul 28 07:13:56 PM PDT 24
Finished Jul 28 07:13:57 PM PDT 24
Peak memory 218136 kb
Host smart-0eb9e06b-0b4c-41ff-8b8a-e2c8efcd3668
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579228613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1579228613
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.4037821452
Short name T193
Test name
Test status
Simulation time 87098861 ps
CPU time 1.86 seconds
Started Jul 28 07:13:44 PM PDT 24
Finished Jul 28 07:13:46 PM PDT 24
Peak memory 199648 kb
Host smart-8f2eda62-65d5-43bf-bbe7-0a0da604879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037821452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4037821452
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.443522224
Short name T492
Test name
Test status
Simulation time 10563483579 ps
CPU time 1082.29 seconds
Started Jul 28 07:13:56 PM PDT 24
Finished Jul 28 07:31:58 PM PDT 24
Peak memory 645384 kb
Host smart-00029c95-89fe-4c72-9491-454e8612d3e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443522224 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.443522224
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.961879074
Short name T306
Test name
Test status
Simulation time 8550447764 ps
CPU time 68.87 seconds
Started Jul 28 07:13:51 PM PDT 24
Finished Jul 28 07:15:00 PM PDT 24
Peak memory 199780 kb
Host smart-9541b7fa-430f-4f43-8d37-437b728c5267
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=961879074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.961879074
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.780713860
Short name T435
Test name
Test status
Simulation time 5240834258 ps
CPU time 59.72 seconds
Started Jul 28 07:13:50 PM PDT 24
Finished Jul 28 07:14:49 PM PDT 24
Peak memory 199684 kb
Host smart-f2b13f50-5997-4181-bf86-e9aaf6a27bbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=780713860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.780713860
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1434656698
Short name T100
Test name
Test status
Simulation time 35791960655 ps
CPU time 140.09 seconds
Started Jul 28 07:13:54 PM PDT 24
Finished Jul 28 07:16:14 PM PDT 24
Peak memory 199704 kb
Host smart-a980cc77-b806-44e1-b3a5-321f4b6d7a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1434656698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1434656698
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1881122883
Short name T524
Test name
Test status
Simulation time 112563713928 ps
CPU time 552.8 seconds
Started Jul 28 07:13:50 PM PDT 24
Finished Jul 28 07:23:03 PM PDT 24
Peak memory 199704 kb
Host smart-df586e7e-2227-4a63-856a-e16739a69cca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1881122883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1881122883
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2568209762
Short name T329
Test name
Test status
Simulation time 816332662035 ps
CPU time 2584.99 seconds
Started Jul 28 07:13:51 PM PDT 24
Finished Jul 28 07:56:56 PM PDT 24
Peak memory 216168 kb
Host smart-53509788-55c4-4496-97d9-95319c9c4591
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2568209762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2568209762
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3526592967
Short name T438
Test name
Test status
Simulation time 761500390988 ps
CPU time 2510.55 seconds
Started Jul 28 07:13:48 PM PDT 24
Finished Jul 28 07:55:39 PM PDT 24
Peak memory 215276 kb
Host smart-801c3beb-61ec-43ad-9965-a856e2a3e0fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3526592967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3526592967
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2354188100
Short name T504
Test name
Test status
Simulation time 5244334809 ps
CPU time 19.67 seconds
Started Jul 28 07:13:51 PM PDT 24
Finished Jul 28 07:14:11 PM PDT 24
Peak memory 199692 kb
Host smart-6b6cf642-5ef7-45f9-a93a-5501a231e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354188100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2354188100
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2689804849
Short name T525
Test name
Test status
Simulation time 13894812 ps
CPU time 0.58 seconds
Started Jul 28 07:14:37 PM PDT 24
Finished Jul 28 07:14:37 PM PDT 24
Peak memory 194608 kb
Host smart-08b689d2-23ec-40ee-bc9c-ebf475aa8891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689804849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2689804849
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2126012658
Short name T364
Test name
Test status
Simulation time 6807223748 ps
CPU time 78.68 seconds
Started Jul 28 07:14:25 PM PDT 24
Finished Jul 28 07:15:44 PM PDT 24
Peak memory 216144 kb
Host smart-3bee7cc4-ea13-4c6f-819a-7958e761c6a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126012658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2126012658
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3765463922
Short name T318
Test name
Test status
Simulation time 3289737245 ps
CPU time 31.97 seconds
Started Jul 28 07:14:35 PM PDT 24
Finished Jul 28 07:15:07 PM PDT 24
Peak memory 199732 kb
Host smart-90d19e7d-2fa4-4d81-94d7-bb3ebb28e1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765463922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3765463922
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1229588719
Short name T422
Test name
Test status
Simulation time 19595958824 ps
CPU time 581.92 seconds
Started Jul 28 07:14:35 PM PDT 24
Finished Jul 28 07:24:17 PM PDT 24
Peak memory 614452 kb
Host smart-01eb70ea-45ad-4723-91f0-1c07d732bda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229588719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1229588719
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3547308927
Short name T457
Test name
Test status
Simulation time 4214222572 ps
CPU time 51.32 seconds
Started Jul 28 07:14:37 PM PDT 24
Finished Jul 28 07:15:28 PM PDT 24
Peak memory 199684 kb
Host smart-9bb22c5e-a1ef-47a8-a7b9-4d69a15d3803
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547308927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3547308927
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.313625812
Short name T186
Test name
Test status
Simulation time 805881901 ps
CPU time 45.51 seconds
Started Jul 28 07:14:28 PM PDT 24
Finished Jul 28 07:15:14 PM PDT 24
Peak memory 199672 kb
Host smart-ec4cfa06-5daa-4705-a1b2-ddf78b198249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313625812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.313625812
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3545705709
Short name T480
Test name
Test status
Simulation time 9569524784 ps
CPU time 13.66 seconds
Started Jul 28 07:14:33 PM PDT 24
Finished Jul 28 07:14:47 PM PDT 24
Peak memory 199716 kb
Host smart-1254ef34-b2a3-4ff6-9379-183b0490f4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545705709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3545705709
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1950974256
Short name T446
Test name
Test status
Simulation time 423755749959 ps
CPU time 1341.32 seconds
Started Jul 28 07:14:35 PM PDT 24
Finished Jul 28 07:36:57 PM PDT 24
Peak memory 199704 kb
Host smart-4241152d-5a80-4b56-9bd1-cb1d014bb5ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950974256 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1950974256
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1404839440
Short name T95
Test name
Test status
Simulation time 10074525118 ps
CPU time 81.22 seconds
Started Jul 28 07:14:36 PM PDT 24
Finished Jul 28 07:15:57 PM PDT 24
Peak memory 199720 kb
Host smart-9e47ddd4-4d2c-44ae-90f7-ce319fb16dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404839440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1404839440
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1275705884
Short name T310
Test name
Test status
Simulation time 19839624 ps
CPU time 0.58 seconds
Started Jul 28 07:14:40 PM PDT 24
Finished Jul 28 07:14:41 PM PDT 24
Peak memory 195292 kb
Host smart-40fe3fea-5653-4997-b7a6-4348e54a2ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275705884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1275705884
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.833872288
Short name T180
Test name
Test status
Simulation time 793710241 ps
CPU time 43.14 seconds
Started Jul 28 07:14:36 PM PDT 24
Finished Jul 28 07:15:20 PM PDT 24
Peak memory 199564 kb
Host smart-acf6de66-ca1c-4f33-a9bf-0ad46dccd061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833872288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.833872288
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3301810268
Short name T403
Test name
Test status
Simulation time 498688921 ps
CPU time 9.4 seconds
Started Jul 28 07:14:35 PM PDT 24
Finished Jul 28 07:14:45 PM PDT 24
Peak memory 199636 kb
Host smart-df0904e4-03b5-456b-afd3-fd30186b1268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301810268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3301810268
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2055586489
Short name T51
Test name
Test status
Simulation time 97908140228 ps
CPU time 1034.29 seconds
Started Jul 28 07:14:35 PM PDT 24
Finished Jul 28 07:31:50 PM PDT 24
Peak memory 701564 kb
Host smart-1f2e1a5b-ec63-4093-b6e1-46db46fd8a54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055586489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2055586489
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4208415118
Short name T424
Test name
Test status
Simulation time 3578092325 ps
CPU time 54.57 seconds
Started Jul 28 07:14:36 PM PDT 24
Finished Jul 28 07:15:31 PM PDT 24
Peak memory 199700 kb
Host smart-b9e16e38-d5db-4a9e-8891-8ac288f9a8ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208415118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4208415118
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3396102038
Short name T232
Test name
Test status
Simulation time 11487261226 ps
CPU time 152.24 seconds
Started Jul 28 07:14:38 PM PDT 24
Finished Jul 28 07:17:10 PM PDT 24
Peak memory 199652 kb
Host smart-38c89b95-6546-49c1-8583-3ccfb20c629b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396102038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3396102038
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2255870461
Short name T183
Test name
Test status
Simulation time 2050968169 ps
CPU time 1.84 seconds
Started Jul 28 07:14:36 PM PDT 24
Finished Jul 28 07:14:38 PM PDT 24
Peak memory 199656 kb
Host smart-2c05ba4e-b41e-4191-9bf2-787b4d8dd1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255870461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2255870461
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.677337911
Short name T146
Test name
Test status
Simulation time 42127665037 ps
CPU time 439.08 seconds
Started Jul 28 07:14:37 PM PDT 24
Finished Jul 28 07:21:56 PM PDT 24
Peak memory 199968 kb
Host smart-28715e1a-3e27-401f-9949-5951ef9e04ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677337911 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.677337911
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.941778469
Short name T529
Test name
Test status
Simulation time 3437603988 ps
CPU time 50.62 seconds
Started Jul 28 07:14:36 PM PDT 24
Finished Jul 28 07:15:27 PM PDT 24
Peak memory 199732 kb
Host smart-dea7ba19-c23c-4ba4-9b45-dbd68715aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941778469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.941778469
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1479590815
Short name T325
Test name
Test status
Simulation time 13885085 ps
CPU time 0.59 seconds
Started Jul 28 07:14:44 PM PDT 24
Finished Jul 28 07:14:45 PM PDT 24
Peak memory 195900 kb
Host smart-33f20964-b03b-4025-b50e-da6bf51f1312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479590815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1479590815
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4167706123
Short name T251
Test name
Test status
Simulation time 718701605 ps
CPU time 38.2 seconds
Started Jul 28 07:14:44 PM PDT 24
Finished Jul 28 07:15:22 PM PDT 24
Peak memory 199888 kb
Host smart-72d27a82-bb96-4499-a39c-2a35ecafdd6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4167706123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4167706123
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3463748388
Short name T448
Test name
Test status
Simulation time 1132981781 ps
CPU time 63.58 seconds
Started Jul 28 07:14:40 PM PDT 24
Finished Jul 28 07:15:44 PM PDT 24
Peak memory 199620 kb
Host smart-4a8ad56d-0480-4c01-9e16-dc8e80a47147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463748388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3463748388
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2612902536
Short name T382
Test name
Test status
Simulation time 1306082387 ps
CPU time 216.84 seconds
Started Jul 28 07:14:42 PM PDT 24
Finished Jul 28 07:18:19 PM PDT 24
Peak memory 434896 kb
Host smart-fd3e503e-0f0f-4ef1-a303-cb52a3ec9347
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612902536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2612902536
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1531526379
Short name T204
Test name
Test status
Simulation time 11225884981 ps
CPU time 131.62 seconds
Started Jul 28 07:14:43 PM PDT 24
Finished Jul 28 07:16:54 PM PDT 24
Peak memory 199692 kb
Host smart-9f80a818-913d-47ec-8401-dd9f3e29a654
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531526379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1531526379
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1416195816
Short name T219
Test name
Test status
Simulation time 17814169034 ps
CPU time 52.07 seconds
Started Jul 28 07:14:41 PM PDT 24
Finished Jul 28 07:15:33 PM PDT 24
Peak memory 199680 kb
Host smart-c7990a12-e4e8-4f2d-b91c-87c01cd1120f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416195816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1416195816
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.846696069
Short name T439
Test name
Test status
Simulation time 6395848899 ps
CPU time 16.56 seconds
Started Jul 28 07:14:39 PM PDT 24
Finished Jul 28 07:14:56 PM PDT 24
Peak memory 199732 kb
Host smart-a5fa29ab-2f33-409f-adff-317f31137427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846696069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.846696069
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2161862488
Short name T455
Test name
Test status
Simulation time 10833364231 ps
CPU time 1113.72 seconds
Started Jul 28 07:14:41 PM PDT 24
Finished Jul 28 07:33:15 PM PDT 24
Peak memory 756080 kb
Host smart-c22fd983-66a0-4fad-bdb1-b420a5e95d10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161862488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2161862488
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1751137731
Short name T185
Test name
Test status
Simulation time 40725900157 ps
CPU time 130.87 seconds
Started Jul 28 07:14:43 PM PDT 24
Finished Jul 28 07:16:54 PM PDT 24
Peak memory 199764 kb
Host smart-19d8f15c-9307-4410-920f-48458b4d5cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751137731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1751137731
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1929763467
Short name T290
Test name
Test status
Simulation time 57994076 ps
CPU time 0.61 seconds
Started Jul 28 07:14:39 PM PDT 24
Finished Jul 28 07:14:40 PM PDT 24
Peak memory 195580 kb
Host smart-b4f85e6f-c2f4-4657-853b-f316f8f60682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929763467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1929763467
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1890805568
Short name T478
Test name
Test status
Simulation time 2472526099 ps
CPU time 74.56 seconds
Started Jul 28 07:14:40 PM PDT 24
Finished Jul 28 07:15:55 PM PDT 24
Peak memory 199708 kb
Host smart-c7d15c9f-230b-42a7-bd13-5351907053f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890805568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1890805568
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2049378749
Short name T267
Test name
Test status
Simulation time 12632910174 ps
CPU time 14.87 seconds
Started Jul 28 07:14:42 PM PDT 24
Finished Jul 28 07:14:57 PM PDT 24
Peak memory 199752 kb
Host smart-88ef6451-93e6-4526-8637-6f44b2630383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049378749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2049378749
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2350525266
Short name T256
Test name
Test status
Simulation time 4961886480 ps
CPU time 160.13 seconds
Started Jul 28 07:14:40 PM PDT 24
Finished Jul 28 07:17:21 PM PDT 24
Peak memory 394900 kb
Host smart-026cd2bb-21df-49b6-861b-c851337fb63b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350525266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2350525266
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2676163577
Short name T476
Test name
Test status
Simulation time 311428423 ps
CPU time 17.88 seconds
Started Jul 28 07:14:40 PM PDT 24
Finished Jul 28 07:14:58 PM PDT 24
Peak memory 199616 kb
Host smart-a14347e5-730c-4abb-940d-faa9a641ea58
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676163577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2676163577
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.349669933
Short name T191
Test name
Test status
Simulation time 10277507943 ps
CPU time 180.17 seconds
Started Jul 28 07:14:44 PM PDT 24
Finished Jul 28 07:17:45 PM PDT 24
Peak memory 208196 kb
Host smart-2a5f0b9e-030e-4d9d-a978-6839b3eddfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349669933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.349669933
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.928506710
Short name T491
Test name
Test status
Simulation time 4491668651 ps
CPU time 15.59 seconds
Started Jul 28 07:14:40 PM PDT 24
Finished Jul 28 07:14:55 PM PDT 24
Peak memory 199680 kb
Host smart-6619b721-44da-432c-8da6-579b2aa9b510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928506710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.928506710
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3138687074
Short name T379
Test name
Test status
Simulation time 37174050675 ps
CPU time 598.09 seconds
Started Jul 28 07:14:44 PM PDT 24
Finished Jul 28 07:24:42 PM PDT 24
Peak memory 619720 kb
Host smart-83779f3f-64a7-4a53-a520-8c740f4aa85a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138687074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3138687074
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1998962265
Short name T311
Test name
Test status
Simulation time 1221198569 ps
CPU time 11.48 seconds
Started Jul 28 07:14:39 PM PDT 24
Finished Jul 28 07:14:51 PM PDT 24
Peak memory 199656 kb
Host smart-41edbb5f-1a49-4e47-ba9a-e00f35585d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998962265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1998962265
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1461243975
Short name T459
Test name
Test status
Simulation time 110247126 ps
CPU time 0.59 seconds
Started Jul 28 07:14:45 PM PDT 24
Finished Jul 28 07:14:45 PM PDT 24
Peak memory 195648 kb
Host smart-d93b027b-2d54-4061-8eef-74ff49cae7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461243975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1461243975
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3635846424
Short name T6
Test name
Test status
Simulation time 215784916 ps
CPU time 6.39 seconds
Started Jul 28 07:14:44 PM PDT 24
Finished Jul 28 07:14:51 PM PDT 24
Peak memory 199632 kb
Host smart-ef05fcde-98a6-4f6f-bd71-98d4292bf959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635846424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3635846424
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1386543163
Short name T426
Test name
Test status
Simulation time 4128132581 ps
CPU time 61.04 seconds
Started Jul 28 07:14:45 PM PDT 24
Finished Jul 28 07:15:46 PM PDT 24
Peak memory 199720 kb
Host smart-b8ac8c6d-6909-4650-be12-3ce9d76445e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386543163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1386543163
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2523956489
Short name T50
Test name
Test status
Simulation time 5847918297 ps
CPU time 1009.36 seconds
Started Jul 28 07:14:46 PM PDT 24
Finished Jul 28 07:31:36 PM PDT 24
Peak memory 760812 kb
Host smart-b9877add-6122-40cc-8d32-df9cc0ee2bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523956489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2523956489
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3474830329
Short name T181
Test name
Test status
Simulation time 36274833895 ps
CPU time 82.04 seconds
Started Jul 28 07:14:45 PM PDT 24
Finished Jul 28 07:16:07 PM PDT 24
Peak memory 199676 kb
Host smart-733721d5-2e3e-4cbb-9dc0-e6fef55efa81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474830329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3474830329
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2867444270
Short name T261
Test name
Test status
Simulation time 5747383037 ps
CPU time 166.95 seconds
Started Jul 28 07:14:41 PM PDT 24
Finished Jul 28 07:17:28 PM PDT 24
Peak memory 199684 kb
Host smart-25b97090-7668-48ee-a3de-030402e62bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867444270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2867444270
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1896336021
Short name T281
Test name
Test status
Simulation time 584426581 ps
CPU time 9.51 seconds
Started Jul 28 07:14:39 PM PDT 24
Finished Jul 28 07:14:49 PM PDT 24
Peak memory 199656 kb
Host smart-5076182a-ff8a-4e02-8d60-407ac6535ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896336021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1896336021
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1952790679
Short name T66
Test name
Test status
Simulation time 68986561629 ps
CPU time 2335.19 seconds
Started Jul 28 07:14:45 PM PDT 24
Finished Jul 28 07:53:41 PM PDT 24
Peak memory 774840 kb
Host smart-c0bb6057-451f-4096-b337-2aeffac8c928
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952790679 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1952790679
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3781401120
Short name T103
Test name
Test status
Simulation time 1317578177 ps
CPU time 62.09 seconds
Started Jul 28 07:14:46 PM PDT 24
Finished Jul 28 07:15:48 PM PDT 24
Peak memory 199624 kb
Host smart-ac96c703-c598-46b4-8826-43335c681906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781401120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3781401120
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.875043638
Short name T74
Test name
Test status
Simulation time 11411666 ps
CPU time 0.58 seconds
Started Jul 28 07:14:50 PM PDT 24
Finished Jul 28 07:14:51 PM PDT 24
Peak memory 194612 kb
Host smart-0a4968a1-d0ea-4c83-bc0b-af86f64eb9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875043638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.875043638
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1849043069
Short name T409
Test name
Test status
Simulation time 1937027705 ps
CPU time 27.38 seconds
Started Jul 28 07:14:46 PM PDT 24
Finished Jul 28 07:15:13 PM PDT 24
Peak memory 199632 kb
Host smart-494f49d2-1c84-407c-aabd-024f28e6d5b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849043069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1849043069
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.529061735
Short name T420
Test name
Test status
Simulation time 12232848144 ps
CPU time 53.74 seconds
Started Jul 28 07:14:50 PM PDT 24
Finished Jul 28 07:15:44 PM PDT 24
Peak memory 199656 kb
Host smart-b67183d6-01cb-4351-af44-91fb384d5fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529061735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.529061735
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.651734368
Short name T312
Test name
Test status
Simulation time 12933115648 ps
CPU time 1171.86 seconds
Started Jul 28 07:14:45 PM PDT 24
Finished Jul 28 07:34:17 PM PDT 24
Peak memory 746952 kb
Host smart-de70a062-fead-415d-9da0-ee66d0aeec7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651734368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.651734368
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2291173320
Short name T192
Test name
Test status
Simulation time 9358255946 ps
CPU time 25.16 seconds
Started Jul 28 07:14:50 PM PDT 24
Finished Jul 28 07:15:16 PM PDT 24
Peak memory 199732 kb
Host smart-cbb57583-1952-4799-af56-13228dcc262c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291173320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2291173320
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4267300070
Short name T34
Test name
Test status
Simulation time 1766508286 ps
CPU time 29.53 seconds
Started Jul 28 07:14:44 PM PDT 24
Finished Jul 28 07:15:14 PM PDT 24
Peak memory 199608 kb
Host smart-2d9b9b5d-afe2-4fe4-a2e6-c351b400b699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267300070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4267300070
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.261327141
Short name T374
Test name
Test status
Simulation time 783172372 ps
CPU time 2.76 seconds
Started Jul 28 07:14:45 PM PDT 24
Finished Jul 28 07:14:48 PM PDT 24
Peak memory 199644 kb
Host smart-d782c4b7-cf1c-43ca-a7f0-4aa75fd8e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261327141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.261327141
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3984367840
Short name T523
Test name
Test status
Simulation time 10291243209 ps
CPU time 124.41 seconds
Started Jul 28 07:14:52 PM PDT 24
Finished Jul 28 07:16:57 PM PDT 24
Peak memory 199720 kb
Host smart-996735ec-cc01-494a-8a5f-9874db47f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984367840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3984367840
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.629147509
Short name T168
Test name
Test status
Simulation time 14117483 ps
CPU time 0.58 seconds
Started Jul 28 07:14:53 PM PDT 24
Finished Jul 28 07:14:53 PM PDT 24
Peak memory 195668 kb
Host smart-20239fc7-7778-4aef-a75c-d1fcb2552b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629147509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.629147509
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.985984230
Short name T395
Test name
Test status
Simulation time 3205796664 ps
CPU time 28.69 seconds
Started Jul 28 07:14:57 PM PDT 24
Finished Jul 28 07:15:26 PM PDT 24
Peak memory 199704 kb
Host smart-a9dbe0c4-2214-4b65-a075-e629665a4329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985984230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.985984230
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3185948288
Short name T150
Test name
Test status
Simulation time 811519765 ps
CPU time 43.93 seconds
Started Jul 28 07:15:00 PM PDT 24
Finished Jul 28 07:15:44 PM PDT 24
Peak memory 199700 kb
Host smart-002c09cc-687e-42ea-8ff2-a89349b0f913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185948288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3185948288
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2122168593
Short name T202
Test name
Test status
Simulation time 12961718761 ps
CPU time 569.92 seconds
Started Jul 28 07:14:56 PM PDT 24
Finished Jul 28 07:24:26 PM PDT 24
Peak memory 673928 kb
Host smart-259a92e2-d8c7-4dc5-b2f4-2a9533000e47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122168593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2122168593
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2902968706
Short name T443
Test name
Test status
Simulation time 9103086604 ps
CPU time 144.22 seconds
Started Jul 28 07:14:53 PM PDT 24
Finished Jul 28 07:17:17 PM PDT 24
Peak memory 199692 kb
Host smart-164d8bcd-b20f-4149-986c-792498ffd6d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902968706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2902968706
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1506798567
Short name T199
Test name
Test status
Simulation time 2519133436 ps
CPU time 152.93 seconds
Started Jul 28 07:14:55 PM PDT 24
Finished Jul 28 07:17:28 PM PDT 24
Peak memory 199652 kb
Host smart-df84041d-748b-4357-8e6c-88d09c0d0191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506798567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1506798567
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2480061287
Short name T179
Test name
Test status
Simulation time 525368573 ps
CPU time 8.78 seconds
Started Jul 28 07:14:51 PM PDT 24
Finished Jul 28 07:15:00 PM PDT 24
Peak memory 199648 kb
Host smart-a2aabecd-7f88-4b64-aaaf-f399a0e41ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480061287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2480061287
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.215791792
Short name T456
Test name
Test status
Simulation time 40535118604 ps
CPU time 114.09 seconds
Started Jul 28 07:14:56 PM PDT 24
Finished Jul 28 07:16:51 PM PDT 24
Peak memory 199692 kb
Host smart-4db24fb7-c2e2-4570-9451-36d10eda000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215791792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.215791792
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3357220972
Short name T313
Test name
Test status
Simulation time 10424181 ps
CPU time 0.57 seconds
Started Jul 28 07:15:01 PM PDT 24
Finished Jul 28 07:15:01 PM PDT 24
Peak memory 194628 kb
Host smart-af1258f5-4176-489c-b0dc-5576d404aab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357220972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3357220972
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3999590395
Short name T307
Test name
Test status
Simulation time 553828709 ps
CPU time 30.33 seconds
Started Jul 28 07:15:00 PM PDT 24
Finished Jul 28 07:15:30 PM PDT 24
Peak memory 199636 kb
Host smart-9c41cfcf-9e76-4b33-a3ef-72b064c07eb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999590395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3999590395
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2972132397
Short name T292
Test name
Test status
Simulation time 13532008455 ps
CPU time 90.88 seconds
Started Jul 28 07:15:01 PM PDT 24
Finished Jul 28 07:16:32 PM PDT 24
Peak memory 199700 kb
Host smart-ca05727a-4bf8-439a-a151-9ce3403a1a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972132397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2972132397
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3359232530
Short name T258
Test name
Test status
Simulation time 3655603837 ps
CPU time 581.41 seconds
Started Jul 28 07:15:01 PM PDT 24
Finished Jul 28 07:24:42 PM PDT 24
Peak memory 723808 kb
Host smart-30969902-6189-4ead-85c0-2f0f47b4b710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359232530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3359232530
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3785533910
Short name T336
Test name
Test status
Simulation time 126259677683 ps
CPU time 167.78 seconds
Started Jul 28 07:15:03 PM PDT 24
Finished Jul 28 07:17:51 PM PDT 24
Peak memory 199736 kb
Host smart-2bcc1ccb-6a31-4eca-851b-35a163a451a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785533910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3785533910
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3975670764
Short name T218
Test name
Test status
Simulation time 12934582907 ps
CPU time 180.42 seconds
Started Jul 28 07:15:00 PM PDT 24
Finished Jul 28 07:18:01 PM PDT 24
Peak memory 199716 kb
Host smart-04f516bc-e554-4992-b333-7450cc216664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975670764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3975670764
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3906098391
Short name T43
Test name
Test status
Simulation time 958348525 ps
CPU time 5.95 seconds
Started Jul 28 07:14:57 PM PDT 24
Finished Jul 28 07:15:04 PM PDT 24
Peak memory 199636 kb
Host smart-4d9df02d-4811-4e44-95a3-d0bcf622969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906098391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3906098391
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2604415870
Short name T518
Test name
Test status
Simulation time 39745717949 ps
CPU time 501.86 seconds
Started Jul 28 07:15:01 PM PDT 24
Finished Jul 28 07:23:23 PM PDT 24
Peak memory 199692 kb
Host smart-db192089-8a18-4431-95f3-0cb590a94a82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604415870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2604415870
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4033972316
Short name T262
Test name
Test status
Simulation time 11973279582 ps
CPU time 36.95 seconds
Started Jul 28 07:15:03 PM PDT 24
Finished Jul 28 07:15:40 PM PDT 24
Peak memory 199744 kb
Host smart-48099d54-1817-428d-9e2a-dc40d59981c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033972316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4033972316
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1003082301
Short name T368
Test name
Test status
Simulation time 54019022 ps
CPU time 0.6 seconds
Started Jul 28 07:15:06 PM PDT 24
Finished Jul 28 07:15:06 PM PDT 24
Peak memory 195716 kb
Host smart-ab1b0ee1-003b-48c6-b249-8c8ad2c39015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003082301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1003082301
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2308781903
Short name T323
Test name
Test status
Simulation time 35848280 ps
CPU time 1.86 seconds
Started Jul 28 07:15:07 PM PDT 24
Finished Jul 28 07:15:09 PM PDT 24
Peak memory 199700 kb
Host smart-83c6f66b-4c7e-46b6-8e49-d5080e3e6b3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308781903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2308781903
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.884007575
Short name T230
Test name
Test status
Simulation time 4854950051 ps
CPU time 62.35 seconds
Started Jul 28 07:15:06 PM PDT 24
Finished Jul 28 07:16:08 PM PDT 24
Peak memory 199624 kb
Host smart-7dfb2abd-d3f9-475c-bff5-b41d90360af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884007575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.884007575
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.4096552625
Short name T268
Test name
Test status
Simulation time 7197593666 ps
CPU time 300.71 seconds
Started Jul 28 07:15:05 PM PDT 24
Finished Jul 28 07:20:06 PM PDT 24
Peak memory 466616 kb
Host smart-24165a5b-aa95-4c9a-a12d-23ccc0179924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4096552625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.4096552625
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2944291113
Short name T375
Test name
Test status
Simulation time 25594551 ps
CPU time 0.66 seconds
Started Jul 28 07:15:07 PM PDT 24
Finished Jul 28 07:15:07 PM PDT 24
Peak memory 196188 kb
Host smart-237c8969-fd31-45eb-9749-4dc773878a4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944291113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2944291113
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4291028187
Short name T452
Test name
Test status
Simulation time 1791043405 ps
CPU time 62.4 seconds
Started Jul 28 07:15:00 PM PDT 24
Finished Jul 28 07:16:02 PM PDT 24
Peak memory 199636 kb
Host smart-4cd49697-7afd-4ddd-b38f-c1505c0c332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291028187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4291028187
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2837739617
Short name T347
Test name
Test status
Simulation time 173177114 ps
CPU time 7.52 seconds
Started Jul 28 07:15:02 PM PDT 24
Finished Jul 28 07:15:10 PM PDT 24
Peak memory 199640 kb
Host smart-ee53bada-a6dd-496a-8d44-446d5cb5882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837739617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2837739617
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1655591409
Short name T16
Test name
Test status
Simulation time 122230508390 ps
CPU time 846.81 seconds
Started Jul 28 07:15:03 PM PDT 24
Finished Jul 28 07:29:09 PM PDT 24
Peak memory 711028 kb
Host smart-38d3c05f-8b04-468b-805e-b10ea3cd7587
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655591409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1655591409
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.835625011
Short name T44
Test name
Test status
Simulation time 19112265342 ps
CPU time 88.23 seconds
Started Jul 28 07:15:07 PM PDT 24
Finished Jul 28 07:16:35 PM PDT 24
Peak memory 199768 kb
Host smart-8ea9a888-6863-4928-86d8-5294d3ae81a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835625011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.835625011
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.87550090
Short name T64
Test name
Test status
Simulation time 16321464 ps
CPU time 0.6 seconds
Started Jul 28 07:15:10 PM PDT 24
Finished Jul 28 07:15:11 PM PDT 24
Peak memory 195584 kb
Host smart-6f0c9ec2-13f2-45e9-b2de-01c9396ee58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87550090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.87550090
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4263379563
Short name T470
Test name
Test status
Simulation time 1124018801 ps
CPU time 33.48 seconds
Started Jul 28 07:15:06 PM PDT 24
Finished Jul 28 07:15:40 PM PDT 24
Peak memory 199640 kb
Host smart-40e5742e-3968-44be-bdd6-beec07261789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263379563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4263379563
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.867974403
Short name T188
Test name
Test status
Simulation time 12085620451 ps
CPU time 37.54 seconds
Started Jul 28 07:15:07 PM PDT 24
Finished Jul 28 07:15:45 PM PDT 24
Peak memory 199732 kb
Host smart-1d7ca817-ebbc-46c3-bac0-9752532287cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867974403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.867974403
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4006435002
Short name T427
Test name
Test status
Simulation time 4401416112 ps
CPU time 831.34 seconds
Started Jul 28 07:15:06 PM PDT 24
Finished Jul 28 07:28:57 PM PDT 24
Peak memory 746412 kb
Host smart-0378deac-0142-4e7f-94f4-21275c2c76c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006435002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4006435002
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.260698388
Short name T321
Test name
Test status
Simulation time 946857076 ps
CPU time 4.77 seconds
Started Jul 28 07:15:11 PM PDT 24
Finished Jul 28 07:15:16 PM PDT 24
Peak memory 199560 kb
Host smart-0b39e860-2323-4a3a-aef0-bfd6ef44fe09
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260698388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.260698388
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.724394877
Short name T205
Test name
Test status
Simulation time 4714975698 ps
CPU time 60.33 seconds
Started Jul 28 07:15:06 PM PDT 24
Finished Jul 28 07:16:06 PM PDT 24
Peak memory 199792 kb
Host smart-ecf515d2-0407-4f25-bd2b-4357c9e95815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724394877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.724394877
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1289735618
Short name T506
Test name
Test status
Simulation time 1392617814 ps
CPU time 17.81 seconds
Started Jul 28 07:15:05 PM PDT 24
Finished Jul 28 07:15:23 PM PDT 24
Peak memory 199592 kb
Host smart-a828ecb2-6775-4522-8e21-2d1ee57f7acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289735618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1289735618
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1463361109
Short name T152
Test name
Test status
Simulation time 475671377 ps
CPU time 6.83 seconds
Started Jul 28 07:15:12 PM PDT 24
Finished Jul 28 07:15:18 PM PDT 24
Peak memory 199668 kb
Host smart-4a4c8c52-1fb4-4f25-b250-6ec48727ea22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463361109 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1463361109
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2219869594
Short name T495
Test name
Test status
Simulation time 1678199075 ps
CPU time 84.85 seconds
Started Jul 28 07:15:12 PM PDT 24
Finished Jul 28 07:16:37 PM PDT 24
Peak memory 199688 kb
Host smart-bab748c0-1ef6-4a53-a058-ea01ac329465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219869594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2219869594
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2251447483
Short name T297
Test name
Test status
Simulation time 46558480 ps
CPU time 0.58 seconds
Started Jul 28 07:14:00 PM PDT 24
Finished Jul 28 07:14:01 PM PDT 24
Peak memory 196340 kb
Host smart-76373859-2e0d-4041-8867-61bc54043bd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251447483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2251447483
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3215599234
Short name T381
Test name
Test status
Simulation time 2807463098 ps
CPU time 86.68 seconds
Started Jul 28 07:13:54 PM PDT 24
Finished Jul 28 07:15:21 PM PDT 24
Peak memory 199700 kb
Host smart-6925c6b9-7716-48e1-9891-4a57b5ce8d79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215599234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3215599234
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3104553587
Short name T26
Test name
Test status
Simulation time 1621888295 ps
CPU time 42.88 seconds
Started Jul 28 07:13:56 PM PDT 24
Finished Jul 28 07:14:39 PM PDT 24
Peak memory 199644 kb
Host smart-86938fdf-ee61-42f5-a5bf-f88f7e228182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104553587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3104553587
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3769887596
Short name T155
Test name
Test status
Simulation time 3837242620 ps
CPU time 127.19 seconds
Started Jul 28 07:13:53 PM PDT 24
Finished Jul 28 07:16:01 PM PDT 24
Peak memory 359876 kb
Host smart-3f30bbeb-72de-46cc-8187-5b3be7f86326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769887596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3769887596
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.685144795
Short name T198
Test name
Test status
Simulation time 4602922009 ps
CPU time 77.94 seconds
Started Jul 28 07:13:54 PM PDT 24
Finished Jul 28 07:15:12 PM PDT 24
Peak memory 199708 kb
Host smart-f8c01407-7287-4510-ad81-575e81fd29e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685144795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.685144795
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3014696193
Short name T346
Test name
Test status
Simulation time 20855135861 ps
CPU time 172.44 seconds
Started Jul 28 07:13:53 PM PDT 24
Finished Jul 28 07:16:46 PM PDT 24
Peak memory 199964 kb
Host smart-cde4c420-0ed4-4010-9adc-308e06e574db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014696193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3014696193
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2854296965
Short name T56
Test name
Test status
Simulation time 59538382 ps
CPU time 0.89 seconds
Started Jul 28 07:13:59 PM PDT 24
Finished Jul 28 07:14:00 PM PDT 24
Peak memory 218196 kb
Host smart-44487e2a-3f7b-456a-836c-dc43e40398f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854296965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2854296965
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2473149866
Short name T40
Test name
Test status
Simulation time 204000178 ps
CPU time 4.32 seconds
Started Jul 28 07:13:54 PM PDT 24
Finished Jul 28 07:13:58 PM PDT 24
Peak memory 199620 kb
Host smart-4a87efe8-7d86-42d5-974c-32d20e644539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473149866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2473149866
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1487690937
Short name T304
Test name
Test status
Simulation time 784892201593 ps
CPU time 1448.6 seconds
Started Jul 28 07:14:00 PM PDT 24
Finished Jul 28 07:38:09 PM PDT 24
Peak memory 766956 kb
Host smart-b3446848-a802-44a7-8e9d-86cdadb48dc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487690937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1487690937
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.919104952
Short name T502
Test name
Test status
Simulation time 2372309275 ps
CPU time 62.2 seconds
Started Jul 28 07:13:55 PM PDT 24
Finished Jul 28 07:14:57 PM PDT 24
Peak memory 199732 kb
Host smart-4f1359d2-3a2a-40bc-b7cf-56d995d81fbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=919104952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.919104952
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.795000394
Short name T466
Test name
Test status
Simulation time 9844708877 ps
CPU time 113.95 seconds
Started Jul 28 07:14:01 PM PDT 24
Finished Jul 28 07:15:55 PM PDT 24
Peak memory 199708 kb
Host smart-de91937c-7462-45d6-8ea7-296edaff6101
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=795000394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.795000394
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3091451562
Short name T7
Test name
Test status
Simulation time 11413905481 ps
CPU time 109.06 seconds
Started Jul 28 07:14:01 PM PDT 24
Finished Jul 28 07:15:50 PM PDT 24
Peak memory 199708 kb
Host smart-8dfead99-8c3c-4be4-9593-7c8d34bdf626
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3091451562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3091451562
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.626841644
Short name T460
Test name
Test status
Simulation time 10564497503 ps
CPU time 580.57 seconds
Started Jul 28 07:13:53 PM PDT 24
Finished Jul 28 07:23:34 PM PDT 24
Peak memory 199712 kb
Host smart-94849bf4-b20d-4138-ac0d-3cfab481775a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=626841644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.626841644
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2423223108
Short name T371
Test name
Test status
Simulation time 254662468697 ps
CPU time 2177.99 seconds
Started Jul 28 07:13:53 PM PDT 24
Finished Jul 28 07:50:12 PM PDT 24
Peak memory 216136 kb
Host smart-f1e55023-b45c-4ad3-a449-358c405842b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2423223108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2423223108
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2881505541
Short name T273
Test name
Test status
Simulation time 188440171599 ps
CPU time 2518.24 seconds
Started Jul 28 07:13:56 PM PDT 24
Finished Jul 28 07:55:55 PM PDT 24
Peak memory 215680 kb
Host smart-a97e2808-36a0-47ca-9d84-22239ff1fdfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2881505541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2881505541
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3582272218
Short name T434
Test name
Test status
Simulation time 1921248447 ps
CPU time 48.64 seconds
Started Jul 28 07:13:55 PM PDT 24
Finished Jul 28 07:14:44 PM PDT 24
Peak memory 199720 kb
Host smart-89ee9ddd-6bc2-4640-9750-162b590985d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582272218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3582272218
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1927412492
Short name T271
Test name
Test status
Simulation time 23617604 ps
CPU time 0.55 seconds
Started Jul 28 07:15:14 PM PDT 24
Finished Jul 28 07:15:15 PM PDT 24
Peak memory 195260 kb
Host smart-81d37fe7-63b2-4f16-be61-dd816a55e35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927412492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1927412492
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.588703926
Short name T295
Test name
Test status
Simulation time 6337028323 ps
CPU time 90.49 seconds
Started Jul 28 07:15:09 PM PDT 24
Finished Jul 28 07:16:40 PM PDT 24
Peak memory 199712 kb
Host smart-d36e96de-0372-46de-9ebc-ec771bf9ae14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588703926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.588703926
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3300909623
Short name T464
Test name
Test status
Simulation time 430066072 ps
CPU time 26.2 seconds
Started Jul 28 07:15:10 PM PDT 24
Finished Jul 28 07:15:37 PM PDT 24
Peak memory 199624 kb
Host smart-12ed2c1a-e43b-4b5b-bebc-d04aec9dad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300909623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3300909623
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3594767039
Short name T260
Test name
Test status
Simulation time 43033843207 ps
CPU time 934.64 seconds
Started Jul 28 07:15:09 PM PDT 24
Finished Jul 28 07:30:44 PM PDT 24
Peak memory 774044 kb
Host smart-02c21e69-5c56-4dfc-b206-2a418eabeb7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594767039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3594767039
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1535532537
Short name T481
Test name
Test status
Simulation time 6022855209 ps
CPU time 107.58 seconds
Started Jul 28 07:15:10 PM PDT 24
Finished Jul 28 07:16:58 PM PDT 24
Peak memory 199704 kb
Host smart-a8f3bd57-6692-4ff7-bf69-86bcd0dbeaf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535532537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1535532537
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1238646535
Short name T213
Test name
Test status
Simulation time 70557969062 ps
CPU time 158.9 seconds
Started Jul 28 07:15:08 PM PDT 24
Finished Jul 28 07:17:47 PM PDT 24
Peak memory 199724 kb
Host smart-cc6017c1-e808-4f5d-8681-cbdd0b5e5cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238646535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1238646535
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1292816175
Short name T187
Test name
Test status
Simulation time 882743750 ps
CPU time 9.57 seconds
Started Jul 28 07:15:10 PM PDT 24
Finished Jul 28 07:15:19 PM PDT 24
Peak memory 199616 kb
Host smart-db648da5-c1c0-4e85-8e6c-58fd70f5083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292816175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1292816175
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3643017456
Short name T440
Test name
Test status
Simulation time 16015427644 ps
CPU time 448.81 seconds
Started Jul 28 07:15:17 PM PDT 24
Finished Jul 28 07:22:46 PM PDT 24
Peak memory 486276 kb
Host smart-09692cc0-70ac-431a-b364-f97a3440cd83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643017456 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3643017456
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1531442384
Short name T236
Test name
Test status
Simulation time 3056036880 ps
CPU time 41.74 seconds
Started Jul 28 07:15:15 PM PDT 24
Finished Jul 28 07:15:57 PM PDT 24
Peak memory 199728 kb
Host smart-ba9f5fa8-77a2-442a-8e35-5cfac930070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531442384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1531442384
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.889200161
Short name T157
Test name
Test status
Simulation time 14183607 ps
CPU time 0.57 seconds
Started Jul 28 07:15:22 PM PDT 24
Finished Jul 28 07:15:22 PM PDT 24
Peak memory 194624 kb
Host smart-1ae9a4d8-093d-4142-9e3d-f3500ae6f5b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889200161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.889200161
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1693137535
Short name T497
Test name
Test status
Simulation time 4759449644 ps
CPU time 53.22 seconds
Started Jul 28 07:15:16 PM PDT 24
Finished Jul 28 07:16:09 PM PDT 24
Peak memory 199760 kb
Host smart-b63652f9-79e1-4234-ba0f-78d10c2237c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693137535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1693137535
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1639204009
Short name T167
Test name
Test status
Simulation time 14781803796 ps
CPU time 68.68 seconds
Started Jul 28 07:15:15 PM PDT 24
Finished Jul 28 07:16:24 PM PDT 24
Peak memory 199672 kb
Host smart-7d83cc04-4c13-41c2-a319-533e8cde99db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639204009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1639204009
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.513785984
Short name T350
Test name
Test status
Simulation time 13665209235 ps
CPU time 601.02 seconds
Started Jul 28 07:15:16 PM PDT 24
Finished Jul 28 07:25:17 PM PDT 24
Peak memory 685792 kb
Host smart-72252f64-1e8d-4f99-bbaa-1c311f3646ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513785984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.513785984
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1237963968
Short name T269
Test name
Test status
Simulation time 2110101928 ps
CPU time 7.47 seconds
Started Jul 28 07:15:15 PM PDT 24
Finished Jul 28 07:15:23 PM PDT 24
Peak memory 199596 kb
Host smart-e1784c09-8f0e-4e3b-bbdb-16b0b436da4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237963968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1237963968
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.441008158
Short name T496
Test name
Test status
Simulation time 11060451882 ps
CPU time 142.72 seconds
Started Jul 28 07:15:16 PM PDT 24
Finished Jul 28 07:17:39 PM PDT 24
Peak memory 199804 kb
Host smart-4b5b3f4f-82b7-4880-9d76-5d79d387d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441008158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.441008158
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.850497434
Short name T302
Test name
Test status
Simulation time 2342988195 ps
CPU time 7.77 seconds
Started Jul 28 07:15:17 PM PDT 24
Finished Jul 28 07:15:25 PM PDT 24
Peak memory 199692 kb
Host smart-1c071d3d-6c1a-45c7-a3ca-83d351857749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850497434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.850497434
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1949697317
Short name T449
Test name
Test status
Simulation time 72836721729 ps
CPU time 1089.87 seconds
Started Jul 28 07:15:17 PM PDT 24
Finished Jul 28 07:33:27 PM PDT 24
Peak memory 672976 kb
Host smart-39838205-b973-4de0-b781-849d527b4cef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949697317 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1949697317
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1650525869
Short name T369
Test name
Test status
Simulation time 19735574168 ps
CPU time 62.01 seconds
Started Jul 28 07:15:16 PM PDT 24
Finished Jul 28 07:16:18 PM PDT 24
Peak memory 199724 kb
Host smart-ee80e56f-37e6-48e2-b552-1d62066e9b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650525869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1650525869
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.969755159
Short name T354
Test name
Test status
Simulation time 18933275 ps
CPU time 0.59 seconds
Started Jul 28 07:15:23 PM PDT 24
Finished Jul 28 07:15:24 PM PDT 24
Peak memory 195652 kb
Host smart-85fc0a78-a8e2-49eb-b938-7f1f13b02f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969755159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.969755159
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3451309583
Short name T414
Test name
Test status
Simulation time 1188496776 ps
CPU time 65.27 seconds
Started Jul 28 07:15:21 PM PDT 24
Finished Jul 28 07:16:26 PM PDT 24
Peak memory 199688 kb
Host smart-48865436-9ae8-4c93-bc80-009746a571ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3451309583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3451309583
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3105148599
Short name T209
Test name
Test status
Simulation time 507591168 ps
CPU time 27.66 seconds
Started Jul 28 07:15:21 PM PDT 24
Finished Jul 28 07:15:49 PM PDT 24
Peak memory 199588 kb
Host smart-fe467e1a-9e1b-46f1-a5cc-21dfc73fcc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105148599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3105148599
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.443166324
Short name T52
Test name
Test status
Simulation time 15810301596 ps
CPU time 921.34 seconds
Started Jul 28 07:15:25 PM PDT 24
Finished Jul 28 07:30:46 PM PDT 24
Peak memory 731576 kb
Host smart-f2233ee6-8003-4dd5-8d71-8088c5582afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443166324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.443166324
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2708662654
Short name T45
Test name
Test status
Simulation time 4378575193 ps
CPU time 53.89 seconds
Started Jul 28 07:15:23 PM PDT 24
Finished Jul 28 07:16:17 PM PDT 24
Peak memory 199664 kb
Host smart-2f59a63c-aca7-480a-98b5-4a9ccc2f1bd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708662654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2708662654
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1943695660
Short name T89
Test name
Test status
Simulation time 9025083911 ps
CPU time 97.17 seconds
Started Jul 28 07:15:22 PM PDT 24
Finished Jul 28 07:16:59 PM PDT 24
Peak memory 199708 kb
Host smart-4f95c6af-a998-437c-bdae-6167d6d917ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943695660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1943695660
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2556766331
Short name T139
Test name
Test status
Simulation time 2159428540 ps
CPU time 14.09 seconds
Started Jul 28 07:15:23 PM PDT 24
Finished Jul 28 07:15:38 PM PDT 24
Peak memory 199680 kb
Host smart-aa3eb9f9-126e-4425-8104-47b425628694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556766331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2556766331
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1761351685
Short name T84
Test name
Test status
Simulation time 39142709008 ps
CPU time 502.43 seconds
Started Jul 28 07:15:23 PM PDT 24
Finished Jul 28 07:23:45 PM PDT 24
Peak memory 207936 kb
Host smart-afc2ef37-b837-4aea-9fb3-2ba58628a7a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761351685 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1761351685
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2930307134
Short name T299
Test name
Test status
Simulation time 599373414 ps
CPU time 9.04 seconds
Started Jul 28 07:15:22 PM PDT 24
Finished Jul 28 07:15:31 PM PDT 24
Peak memory 199596 kb
Host smart-0a7ade03-34a7-4804-bc3c-61bb684d6fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930307134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2930307134
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1602313039
Short name T300
Test name
Test status
Simulation time 14339599 ps
CPU time 0.61 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:15:28 PM PDT 24
Peak memory 195712 kb
Host smart-b57371e6-1438-4f4c-bf11-8f628c778f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602313039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1602313039
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.343905020
Short name T254
Test name
Test status
Simulation time 1028785614 ps
CPU time 27.31 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:15:55 PM PDT 24
Peak memory 199704 kb
Host smart-d89dc405-c050-463e-b535-5cce668ee7d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343905020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.343905020
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.47135573
Short name T429
Test name
Test status
Simulation time 12227572358 ps
CPU time 51.66 seconds
Started Jul 28 07:15:28 PM PDT 24
Finished Jul 28 07:16:20 PM PDT 24
Peak memory 199724 kb
Host smart-e269d03a-61c3-4852-8a7e-ded617bdf4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47135573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.47135573
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.86782629
Short name T338
Test name
Test status
Simulation time 1813107401 ps
CPU time 263.53 seconds
Started Jul 28 07:15:25 PM PDT 24
Finished Jul 28 07:19:49 PM PDT 24
Peak memory 632784 kb
Host smart-59b8e571-c947-48d1-b810-e4d6b547cfea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86782629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.86782629
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.214619188
Short name T423
Test name
Test status
Simulation time 4227098747 ps
CPU time 41.98 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:16:09 PM PDT 24
Peak memory 199672 kb
Host smart-60b50709-9df0-41ce-9fbc-356833067018
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214619188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.214619188
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4012727344
Short name T174
Test name
Test status
Simulation time 3384621426 ps
CPU time 44.98 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:16:12 PM PDT 24
Peak memory 199716 kb
Host smart-129b84b0-add1-49c7-8618-0ea5dd7e5474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012727344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4012727344
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1908523805
Short name T447
Test name
Test status
Simulation time 1839836492 ps
CPU time 14.72 seconds
Started Jul 28 07:15:25 PM PDT 24
Finished Jul 28 07:15:39 PM PDT 24
Peak memory 199648 kb
Host smart-6aa81338-5b07-4332-920f-2f816c8cdc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908523805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1908523805
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3269297775
Short name T259
Test name
Test status
Simulation time 192782476182 ps
CPU time 1957.14 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:48:05 PM PDT 24
Peak memory 770568 kb
Host smart-71c5d9c1-b05c-4b4c-ac49-d13f9fd48bcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269297775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3269297775
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.4206667599
Short name T67
Test name
Test status
Simulation time 2382551477 ps
CPU time 13.08 seconds
Started Jul 28 07:15:28 PM PDT 24
Finished Jul 28 07:15:41 PM PDT 24
Peak memory 199704 kb
Host smart-2c24bd11-9356-4b4a-8570-8b7ee379ad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206667599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4206667599
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3545807953
Short name T363
Test name
Test status
Simulation time 38383263 ps
CPU time 0.58 seconds
Started Jul 28 07:15:37 PM PDT 24
Finished Jul 28 07:15:37 PM PDT 24
Peak memory 195280 kb
Host smart-4ac6d28b-f98b-4b45-8387-183eba4f1ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545807953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3545807953
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2320107983
Short name T402
Test name
Test status
Simulation time 1139497642 ps
CPU time 66.47 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:16:34 PM PDT 24
Peak memory 199660 kb
Host smart-1388c7c5-67d9-489c-990d-f365cb2904d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320107983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2320107983
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.921719814
Short name T264
Test name
Test status
Simulation time 14982623023 ps
CPU time 50.02 seconds
Started Jul 28 07:16:04 PM PDT 24
Finished Jul 28 07:16:55 PM PDT 24
Peak memory 199716 kb
Host smart-68e66d77-e61a-4c56-90e4-f8e76373bbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921719814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.921719814
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4208040069
Short name T97
Test name
Test status
Simulation time 21551904 ps
CPU time 0.83 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:15:28 PM PDT 24
Peak memory 199524 kb
Host smart-df7e3293-603a-4e58-afa3-be67edfdfee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208040069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4208040069
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1614257026
Short name T475
Test name
Test status
Simulation time 2383679100 ps
CPU time 113.53 seconds
Started Jul 28 07:15:34 PM PDT 24
Finished Jul 28 07:17:27 PM PDT 24
Peak memory 199724 kb
Host smart-dad004e6-1c2f-4ccb-b155-fb51e1bbc9c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614257026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1614257026
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3383273037
Short name T212
Test name
Test status
Simulation time 1119898356 ps
CPU time 5.94 seconds
Started Jul 28 07:15:28 PM PDT 24
Finished Jul 28 07:15:34 PM PDT 24
Peak memory 199556 kb
Host smart-625f2f98-d8a9-46b8-b55f-5fbed1649fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383273037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3383273037
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3639153870
Short name T430
Test name
Test status
Simulation time 162458065 ps
CPU time 1.25 seconds
Started Jul 28 07:15:27 PM PDT 24
Finished Jul 28 07:15:28 PM PDT 24
Peak memory 199632 kb
Host smart-8463ffad-052c-4b71-a43e-fa2429b33f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639153870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3639153870
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2609147346
Short name T30
Test name
Test status
Simulation time 25244733690 ps
CPU time 285.94 seconds
Started Jul 28 07:15:29 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 199744 kb
Host smart-5a922733-d371-4567-a829-786d248706e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609147346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2609147346
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1588054196
Short name T101
Test name
Test status
Simulation time 9953007582 ps
CPU time 30.71 seconds
Started Jul 28 07:15:38 PM PDT 24
Finished Jul 28 07:16:09 PM PDT 24
Peak memory 199764 kb
Host smart-a0bc5595-60f6-4954-8fa9-0f14b51f84e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588054196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1588054196
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3196719053
Short name T241
Test name
Test status
Simulation time 42905460 ps
CPU time 0.61 seconds
Started Jul 28 07:15:38 PM PDT 24
Finished Jul 28 07:15:39 PM PDT 24
Peak memory 195660 kb
Host smart-cee06c64-93b2-4b1b-8d1c-e8670650a38f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196719053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3196719053
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.468971910
Short name T173
Test name
Test status
Simulation time 744552192 ps
CPU time 10.93 seconds
Started Jul 28 07:15:37 PM PDT 24
Finished Jul 28 07:15:48 PM PDT 24
Peak memory 199592 kb
Host smart-abf516d6-913c-4f44-855a-74ba3b79e82e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468971910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.468971910
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1471349556
Short name T286
Test name
Test status
Simulation time 314875367 ps
CPU time 6.13 seconds
Started Jul 28 07:15:41 PM PDT 24
Finished Jul 28 07:15:47 PM PDT 24
Peak memory 199520 kb
Host smart-195967c7-ce51-4aff-8b2d-a879b57eb7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471349556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1471349556
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3423777891
Short name T485
Test name
Test status
Simulation time 3889616766 ps
CPU time 345.72 seconds
Started Jul 28 07:15:37 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 640944 kb
Host smart-9581bfdd-1e8d-4339-86d1-bd9988d346ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423777891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3423777891
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2880405422
Short name T397
Test name
Test status
Simulation time 11440717703 ps
CPU time 139.26 seconds
Started Jul 28 07:15:37 PM PDT 24
Finished Jul 28 07:17:57 PM PDT 24
Peak memory 199756 kb
Host smart-aa1d0b33-7a93-4f7c-aa5e-4fa925c92c9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880405422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2880405422
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1306155238
Short name T288
Test name
Test status
Simulation time 2031206768 ps
CPU time 54.88 seconds
Started Jul 28 07:15:36 PM PDT 24
Finished Jul 28 07:16:31 PM PDT 24
Peak memory 199632 kb
Host smart-932290a5-a898-4437-965d-19138a196cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306155238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1306155238
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3514781696
Short name T370
Test name
Test status
Simulation time 3902168146 ps
CPU time 7.05 seconds
Started Jul 28 07:15:40 PM PDT 24
Finished Jul 28 07:15:47 PM PDT 24
Peak memory 199732 kb
Host smart-3832a121-1048-400a-8721-9af5d798d3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514781696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3514781696
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1546025677
Short name T425
Test name
Test status
Simulation time 11976088290 ps
CPU time 153.05 seconds
Started Jul 28 07:15:40 PM PDT 24
Finished Jul 28 07:18:13 PM PDT 24
Peak memory 199680 kb
Host smart-f511d388-cd76-4a03-8443-0811a1315943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546025677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1546025677
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3867614214
Short name T344
Test name
Test status
Simulation time 15696097 ps
CPU time 0.59 seconds
Started Jul 28 07:15:46 PM PDT 24
Finished Jul 28 07:15:47 PM PDT 24
Peak memory 196300 kb
Host smart-ed280d3c-6feb-4825-9274-510b96b9b725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867614214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3867614214
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.645531104
Short name T250
Test name
Test status
Simulation time 1489655945 ps
CPU time 34.45 seconds
Started Jul 28 07:15:37 PM PDT 24
Finished Jul 28 07:16:11 PM PDT 24
Peak memory 199656 kb
Host smart-601f98ec-a849-4bad-8ce8-edb798d5c2cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645531104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.645531104
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2414020128
Short name T65
Test name
Test status
Simulation time 2733237460 ps
CPU time 81.22 seconds
Started Jul 28 07:15:36 PM PDT 24
Finished Jul 28 07:16:57 PM PDT 24
Peak memory 199688 kb
Host smart-09682b7d-6d98-4533-9d41-9588e4b9e6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414020128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2414020128
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.856821973
Short name T378
Test name
Test status
Simulation time 31712742063 ps
CPU time 1379.91 seconds
Started Jul 28 07:15:37 PM PDT 24
Finished Jul 28 07:38:37 PM PDT 24
Peak memory 780420 kb
Host smart-dc4b58b6-f1bc-40da-b578-820fb410dd00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856821973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.856821973
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2298248474
Short name T357
Test name
Test status
Simulation time 653104521 ps
CPU time 35.12 seconds
Started Jul 28 07:15:34 PM PDT 24
Finished Jul 28 07:16:10 PM PDT 24
Peak memory 199840 kb
Host smart-431d155b-af3c-41ff-b94c-2341c6cea439
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298248474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2298248474
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1592781377
Short name T477
Test name
Test status
Simulation time 2665068046 ps
CPU time 38.09 seconds
Started Jul 28 07:15:43 PM PDT 24
Finished Jul 28 07:16:21 PM PDT 24
Peak memory 199760 kb
Host smart-be1b01d8-50a2-4ba7-a40c-763b2c68fcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592781377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1592781377
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3309805224
Short name T140
Test name
Test status
Simulation time 2817388042 ps
CPU time 8.26 seconds
Started Jul 28 07:15:40 PM PDT 24
Finished Jul 28 07:15:49 PM PDT 24
Peak memory 199680 kb
Host smart-861cfaa4-6909-4f57-b507-9940d6e0c977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309805224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3309805224
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1537563097
Short name T210
Test name
Test status
Simulation time 9253021670 ps
CPU time 255.23 seconds
Started Jul 28 07:15:39 PM PDT 24
Finished Jul 28 07:19:55 PM PDT 24
Peak memory 207956 kb
Host smart-ba206f32-73ae-4953-bce5-249132ceeb3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537563097 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1537563097
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2974889224
Short name T234
Test name
Test status
Simulation time 2273954142 ps
CPU time 73.57 seconds
Started Jul 28 07:15:38 PM PDT 24
Finished Jul 28 07:16:52 PM PDT 24
Peak memory 199688 kb
Host smart-d09c5332-8616-469e-b4bf-8d07cc275d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974889224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2974889224
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2127172750
Short name T201
Test name
Test status
Simulation time 23957878 ps
CPU time 0.63 seconds
Started Jul 28 07:15:49 PM PDT 24
Finished Jul 28 07:15:50 PM PDT 24
Peak memory 195616 kb
Host smart-1fd18a0e-747a-4cc2-9e5b-1995c0e30ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127172750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2127172750
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1562901180
Short name T349
Test name
Test status
Simulation time 2369214122 ps
CPU time 13.59 seconds
Started Jul 28 07:15:43 PM PDT 24
Finished Jul 28 07:15:57 PM PDT 24
Peak memory 199708 kb
Host smart-36533f09-de1e-4c6e-98f0-ada1bcfac2f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1562901180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1562901180
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3732107015
Short name T366
Test name
Test status
Simulation time 5953194411 ps
CPU time 38.78 seconds
Started Jul 28 07:15:43 PM PDT 24
Finished Jul 28 07:16:22 PM PDT 24
Peak memory 199656 kb
Host smart-d5a65477-5d65-4760-8e1c-ea3f078954aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732107015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3732107015
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3806434061
Short name T519
Test name
Test status
Simulation time 923040430 ps
CPU time 192.98 seconds
Started Jul 28 07:15:42 PM PDT 24
Finished Jul 28 07:18:55 PM PDT 24
Peak memory 649924 kb
Host smart-832be868-8a13-4e48-871a-0ff14c7ff0b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806434061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3806434061
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2579867581
Short name T521
Test name
Test status
Simulation time 1109701766 ps
CPU time 61.23 seconds
Started Jul 28 07:15:42 PM PDT 24
Finished Jul 28 07:16:43 PM PDT 24
Peak memory 199620 kb
Host smart-7f6d9330-9ea8-40bd-85ed-56702a1dba02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579867581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2579867581
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2288709685
Short name T314
Test name
Test status
Simulation time 16659703474 ps
CPU time 244.96 seconds
Started Jul 28 07:15:40 PM PDT 24
Finished Jul 28 07:19:45 PM PDT 24
Peak memory 208164 kb
Host smart-99778dc8-e462-425b-9890-9f47dd09286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288709685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2288709685
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4097749913
Short name T341
Test name
Test status
Simulation time 16310419 ps
CPU time 0.71 seconds
Started Jul 28 07:15:41 PM PDT 24
Finished Jul 28 07:15:41 PM PDT 24
Peak memory 196336 kb
Host smart-18f00e9e-b587-4ab2-bd1f-96419a4b1cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097749913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4097749913
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3937028077
Short name T501
Test name
Test status
Simulation time 171534596347 ps
CPU time 566.82 seconds
Started Jul 28 07:15:43 PM PDT 24
Finished Jul 28 07:25:10 PM PDT 24
Peak memory 199792 kb
Host smart-e0ece8f4-556a-499b-ab60-1a3a4d4635c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937028077 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3937028077
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1312890974
Short name T102
Test name
Test status
Simulation time 1958896324 ps
CPU time 100.55 seconds
Started Jul 28 07:15:49 PM PDT 24
Finished Jul 28 07:17:30 PM PDT 24
Peak memory 199384 kb
Host smart-4fcd24da-1d79-41a8-8770-b6846ea05f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312890974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1312890974
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2116230307
Short name T479
Test name
Test status
Simulation time 25252277 ps
CPU time 0.6 seconds
Started Jul 28 07:15:48 PM PDT 24
Finished Jul 28 07:15:49 PM PDT 24
Peak memory 194672 kb
Host smart-48e4a43e-286b-4214-845c-37d48ee7d01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116230307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2116230307
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1682481262
Short name T353
Test name
Test status
Simulation time 3524743003 ps
CPU time 50.53 seconds
Started Jul 28 07:15:46 PM PDT 24
Finished Jul 28 07:16:37 PM PDT 24
Peak memory 199696 kb
Host smart-13fccaf0-8502-40bc-88c2-038ef0fe8095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1682481262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1682481262
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2882814612
Short name T411
Test name
Test status
Simulation time 76252035 ps
CPU time 4.48 seconds
Started Jul 28 07:15:49 PM PDT 24
Finished Jul 28 07:15:54 PM PDT 24
Peak memory 199656 kb
Host smart-8c26baf8-3d70-472c-bd07-6763eb4e661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882814612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2882814612
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1410592789
Short name T324
Test name
Test status
Simulation time 295098509 ps
CPU time 45.04 seconds
Started Jul 28 07:15:48 PM PDT 24
Finished Jul 28 07:16:33 PM PDT 24
Peak memory 313884 kb
Host smart-4e718739-08ae-4a6c-9a14-4e7c11eaa2df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410592789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1410592789
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2933497741
Short name T469
Test name
Test status
Simulation time 1262436477 ps
CPU time 11.11 seconds
Started Jul 28 07:15:49 PM PDT 24
Finished Jul 28 07:16:00 PM PDT 24
Peak memory 199704 kb
Host smart-2a8e0321-00aa-4a9f-ba8c-0d4cdd391245
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933497741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2933497741
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1931292207
Short name T507
Test name
Test status
Simulation time 513086318 ps
CPU time 27.49 seconds
Started Jul 28 07:15:45 PM PDT 24
Finished Jul 28 07:16:13 PM PDT 24
Peak memory 199656 kb
Host smart-d5eba123-5f9f-44bf-97f0-ec4884b9865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931292207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1931292207
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1038503212
Short name T208
Test name
Test status
Simulation time 43677284 ps
CPU time 2 seconds
Started Jul 28 07:15:49 PM PDT 24
Finished Jul 28 07:15:51 PM PDT 24
Peak memory 199336 kb
Host smart-4bd07c69-e51d-4b74-94ad-8caad16a4faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038503212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1038503212
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.592358396
Short name T512
Test name
Test status
Simulation time 57036360993 ps
CPU time 1451.54 seconds
Started Jul 28 07:15:45 PM PDT 24
Finished Jul 28 07:39:57 PM PDT 24
Peak memory 706036 kb
Host smart-8cd1e58e-7ec9-4a91-8b4a-b2482a30751f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592358396 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.592358396
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.645941511
Short name T282
Test name
Test status
Simulation time 1889692373 ps
CPU time 34.79 seconds
Started Jul 28 07:15:50 PM PDT 24
Finished Jul 28 07:16:25 PM PDT 24
Peak memory 199656 kb
Host smart-502496ed-97b1-4de1-9877-aef5422fb57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645941511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.645941511
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2919038529
Short name T32
Test name
Test status
Simulation time 14442555 ps
CPU time 0.61 seconds
Started Jul 28 07:15:51 PM PDT 24
Finished Jul 28 07:15:52 PM PDT 24
Peak memory 196288 kb
Host smart-ddb8a599-324c-452e-bfe3-2de95fb8d466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919038529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2919038529
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.412618838
Short name T49
Test name
Test status
Simulation time 2228837924 ps
CPU time 60.63 seconds
Started Jul 28 07:15:53 PM PDT 24
Finished Jul 28 07:16:54 PM PDT 24
Peak memory 199668 kb
Host smart-1493caae-5aca-4c60-9158-dab0d4551403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412618838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.412618838
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.429511784
Short name T458
Test name
Test status
Simulation time 3531304766 ps
CPU time 48.25 seconds
Started Jul 28 07:15:52 PM PDT 24
Finished Jul 28 07:16:41 PM PDT 24
Peak memory 199712 kb
Host smart-6ef0990b-adb5-48c6-92d7-648e5e70e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429511784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.429511784
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3246917104
Short name T226
Test name
Test status
Simulation time 6744764504 ps
CPU time 312.87 seconds
Started Jul 28 07:15:51 PM PDT 24
Finished Jul 28 07:21:04 PM PDT 24
Peak memory 631260 kb
Host smart-ace763d9-aec8-4bab-a901-b88b39eeb9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246917104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3246917104
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4036945344
Short name T253
Test name
Test status
Simulation time 21913357292 ps
CPU time 135.87 seconds
Started Jul 28 07:15:51 PM PDT 24
Finished Jul 28 07:18:07 PM PDT 24
Peak memory 199676 kb
Host smart-7027340b-d2d8-4c67-9674-236c89335a02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036945344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4036945344
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1047066631
Short name T291
Test name
Test status
Simulation time 9236907353 ps
CPU time 83.08 seconds
Started Jul 28 07:15:48 PM PDT 24
Finished Jul 28 07:17:11 PM PDT 24
Peak memory 199744 kb
Host smart-c6a5305f-e632-493f-8ccd-17cfd5a11f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047066631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1047066631
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.225772199
Short name T143
Test name
Test status
Simulation time 954762817 ps
CPU time 12.8 seconds
Started Jul 28 07:15:45 PM PDT 24
Finished Jul 28 07:15:58 PM PDT 24
Peak memory 199648 kb
Host smart-cb7f9342-7350-4578-afa8-92e0469f4cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225772199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.225772199
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.4120627148
Short name T87
Test name
Test status
Simulation time 46515699066 ps
CPU time 298.15 seconds
Started Jul 28 07:15:53 PM PDT 24
Finished Jul 28 07:20:51 PM PDT 24
Peak memory 199680 kb
Host smart-b7943e5b-c571-4895-925e-ce687f9d38e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120627148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.4120627148
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4006825334
Short name T337
Test name
Test status
Simulation time 7978334268 ps
CPU time 131.09 seconds
Started Jul 28 07:15:53 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 199724 kb
Host smart-6b78d165-44be-4f17-9a03-2247b7793242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006825334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4006825334
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3925898785
Short name T247
Test name
Test status
Simulation time 42500029 ps
CPU time 0.58 seconds
Started Jul 28 07:14:04 PM PDT 24
Finished Jul 28 07:14:04 PM PDT 24
Peak memory 195272 kb
Host smart-f1d2de82-3778-4539-87da-390112489114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925898785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3925898785
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3008059728
Short name T28
Test name
Test status
Simulation time 2942214204 ps
CPU time 79.95 seconds
Started Jul 28 07:13:59 PM PDT 24
Finished Jul 28 07:15:20 PM PDT 24
Peak memory 199744 kb
Host smart-048405de-c4ae-475e-aede-87e7d7722203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008059728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3008059728
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.782525106
Short name T158
Test name
Test status
Simulation time 17270568178 ps
CPU time 65.8 seconds
Started Jul 28 07:14:00 PM PDT 24
Finished Jul 28 07:15:06 PM PDT 24
Peak memory 199736 kb
Host smart-4e97c11a-984d-41ce-a8bf-80f5d9a3c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782525106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.782525106
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2283734185
Short name T520
Test name
Test status
Simulation time 6428900962 ps
CPU time 432.28 seconds
Started Jul 28 07:14:01 PM PDT 24
Finished Jul 28 07:21:13 PM PDT 24
Peak memory 460196 kb
Host smart-9a42badf-cc7b-40a1-a8b5-c2b1466a0c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283734185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2283734185
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1683404190
Short name T326
Test name
Test status
Simulation time 2128068273 ps
CPU time 54.42 seconds
Started Jul 28 07:14:05 PM PDT 24
Finished Jul 28 07:14:59 PM PDT 24
Peak memory 199632 kb
Host smart-61351b7d-c4df-4471-90e2-50979923872a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683404190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1683404190
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3569579455
Short name T62
Test name
Test status
Simulation time 4596255028 ps
CPU time 18.87 seconds
Started Jul 28 07:14:01 PM PDT 24
Finished Jul 28 07:14:20 PM PDT 24
Peak memory 199744 kb
Host smart-d204f62c-123b-4209-b35e-cc35f45e12a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569579455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3569579455
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.819678300
Short name T55
Test name
Test status
Simulation time 200344400 ps
CPU time 1.04 seconds
Started Jul 28 07:14:04 PM PDT 24
Finished Jul 28 07:14:05 PM PDT 24
Peak memory 219380 kb
Host smart-aede470d-8c82-479a-9a27-86743429a34e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819678300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.819678300
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1401694120
Short name T298
Test name
Test status
Simulation time 34617224 ps
CPU time 1.69 seconds
Started Jul 28 07:14:01 PM PDT 24
Finished Jul 28 07:14:03 PM PDT 24
Peak memory 199584 kb
Host smart-eecadbbf-6205-428d-b3b4-066d70d249e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401694120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1401694120
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2262739110
Short name T220
Test name
Test status
Simulation time 8366205339 ps
CPU time 79.1 seconds
Started Jul 28 07:14:09 PM PDT 24
Finished Jul 28 07:15:29 PM PDT 24
Peak memory 199724 kb
Host smart-e49a70e8-0e4b-49fa-b19d-ccb16f48c9bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262739110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2262739110
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1217891445
Short name T522
Test name
Test status
Simulation time 1109103043 ps
CPU time 38.68 seconds
Started Jul 28 07:14:03 PM PDT 24
Finished Jul 28 07:14:42 PM PDT 24
Peak memory 199636 kb
Host smart-ad8a9c88-6a65-49fb-9d9a-8dd50cd27944
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1217891445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1217891445
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.300361308
Short name T239
Test name
Test status
Simulation time 6304248875 ps
CPU time 68.85 seconds
Started Jul 28 07:14:09 PM PDT 24
Finished Jul 28 07:15:18 PM PDT 24
Peak memory 199720 kb
Host smart-31258c22-b18a-4692-a1cc-8d549a6e1eb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=300361308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.300361308
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3955638925
Short name T38
Test name
Test status
Simulation time 2067022534 ps
CPU time 64.63 seconds
Started Jul 28 07:14:12 PM PDT 24
Finished Jul 28 07:15:17 PM PDT 24
Peak memory 199684 kb
Host smart-f351de28-efd1-4938-93ab-e14c921a83b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3955638925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3955638925
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2077037877
Short name T31
Test name
Test status
Simulation time 41564378232 ps
CPU time 528.77 seconds
Started Jul 28 07:13:57 PM PDT 24
Finished Jul 28 07:22:46 PM PDT 24
Peak memory 199724 kb
Host smart-76eaaf0f-4037-451f-9d4e-08b866bbaebb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2077037877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2077037877
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1863631009
Short name T142
Test name
Test status
Simulation time 242259502652 ps
CPU time 2231.66 seconds
Started Jul 28 07:14:00 PM PDT 24
Finished Jul 28 07:51:12 PM PDT 24
Peak memory 215148 kb
Host smart-d0fe59bc-eccb-49b3-9c74-0a46455150da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1863631009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1863631009
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.587443093
Short name T332
Test name
Test status
Simulation time 654760940070 ps
CPU time 2486.39 seconds
Started Jul 28 07:14:10 PM PDT 24
Finished Jul 28 07:55:37 PM PDT 24
Peak memory 216036 kb
Host smart-6b967978-92ed-42f9-a614-16d05069342d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=587443093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.587443093
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2307698179
Short name T406
Test name
Test status
Simulation time 4696813955 ps
CPU time 78.36 seconds
Started Jul 28 07:13:59 PM PDT 24
Finished Jul 28 07:15:18 PM PDT 24
Peak memory 199720 kb
Host smart-31880070-c5b3-46e6-b7ee-8c43fc81b65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307698179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2307698179
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2606314617
Short name T503
Test name
Test status
Simulation time 21337793 ps
CPU time 0.58 seconds
Started Jul 28 07:15:56 PM PDT 24
Finished Jul 28 07:15:56 PM PDT 24
Peak memory 195656 kb
Host smart-fb595727-e6fc-4abf-864e-5286f867b68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606314617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2606314617
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4241366816
Short name T396
Test name
Test status
Simulation time 1579053731 ps
CPU time 91.03 seconds
Started Jul 28 07:15:52 PM PDT 24
Finished Jul 28 07:17:23 PM PDT 24
Peak memory 199612 kb
Host smart-7342b304-af04-4c36-a233-93f2b9a8a637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4241366816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4241366816
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3531874823
Short name T149
Test name
Test status
Simulation time 2507614568 ps
CPU time 30.99 seconds
Started Jul 28 07:15:51 PM PDT 24
Finished Jul 28 07:16:22 PM PDT 24
Peak memory 199752 kb
Host smart-1c02be21-c9a9-43b2-b519-5a4030f2f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531874823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3531874823
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.789677910
Short name T233
Test name
Test status
Simulation time 1022600860 ps
CPU time 68.58 seconds
Started Jul 28 07:15:53 PM PDT 24
Finished Jul 28 07:17:02 PM PDT 24
Peak memory 341988 kb
Host smart-94559a86-5a52-43c9-be43-e893541ecba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789677910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.789677910
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1191138072
Short name T169
Test name
Test status
Simulation time 10579205065 ps
CPU time 85.75 seconds
Started Jul 28 07:15:49 PM PDT 24
Finished Jul 28 07:17:15 PM PDT 24
Peak memory 199940 kb
Host smart-1d611cc7-c1c1-4f79-8764-6f49448dcc95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191138072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1191138072
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.42217483
Short name T474
Test name
Test status
Simulation time 28718569219 ps
CPU time 97.58 seconds
Started Jul 28 07:15:52 PM PDT 24
Finished Jul 28 07:17:29 PM PDT 24
Peak memory 199688 kb
Host smart-2d924a0e-1038-49e6-b16d-638f36e5772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42217483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.42217483
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2780069797
Short name T483
Test name
Test status
Simulation time 2753923131 ps
CPU time 12.6 seconds
Started Jul 28 07:15:50 PM PDT 24
Finished Jul 28 07:16:03 PM PDT 24
Peak memory 199764 kb
Host smart-eac63d52-c074-4284-85f3-1f891baf0cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780069797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2780069797
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3136050367
Short name T206
Test name
Test status
Simulation time 7926017918 ps
CPU time 113.93 seconds
Started Jul 28 07:15:52 PM PDT 24
Finished Jul 28 07:17:46 PM PDT 24
Peak memory 199696 kb
Host smart-26ba492c-33e1-4857-a556-8a9c079bde57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136050367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3136050367
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1258345108
Short name T472
Test name
Test status
Simulation time 851844276 ps
CPU time 12.42 seconds
Started Jul 28 07:15:52 PM PDT 24
Finished Jul 28 07:16:04 PM PDT 24
Peak memory 199676 kb
Host smart-6e17bd41-8d0b-457d-b1c3-8298c52f925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258345108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1258345108
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2276794171
Short name T266
Test name
Test status
Simulation time 37927669 ps
CPU time 0.57 seconds
Started Jul 28 07:15:56 PM PDT 24
Finished Jul 28 07:15:57 PM PDT 24
Peak memory 195248 kb
Host smart-b2749d52-de99-419c-b5d0-9b70d4f15794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276794171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2276794171
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2422719244
Short name T228
Test name
Test status
Simulation time 7012619236 ps
CPU time 93.95 seconds
Started Jul 28 07:15:56 PM PDT 24
Finished Jul 28 07:17:30 PM PDT 24
Peak memory 199676 kb
Host smart-adfb1702-ddf0-47d5-a585-4c9d0463e8d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422719244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2422719244
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3244255212
Short name T494
Test name
Test status
Simulation time 359694274 ps
CPU time 10.12 seconds
Started Jul 28 07:15:58 PM PDT 24
Finished Jul 28 07:16:08 PM PDT 24
Peak memory 199704 kb
Host smart-3504e46f-d649-4898-987d-95832227d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244255212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3244255212
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1808676964
Short name T384
Test name
Test status
Simulation time 26845235527 ps
CPU time 1316.19 seconds
Started Jul 28 07:15:55 PM PDT 24
Finished Jul 28 07:37:52 PM PDT 24
Peak memory 710256 kb
Host smart-4d0d487d-b2d4-4765-af31-cc031864fbdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808676964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1808676964
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1942779996
Short name T330
Test name
Test status
Simulation time 1002850754 ps
CPU time 16.99 seconds
Started Jul 28 07:15:53 PM PDT 24
Finished Jul 28 07:16:10 PM PDT 24
Peak memory 199888 kb
Host smart-898f867e-ff3c-43e7-8bb6-93a243d8c487
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942779996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1942779996
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.295889877
Short name T276
Test name
Test status
Simulation time 52948825693 ps
CPU time 146.08 seconds
Started Jul 28 07:15:54 PM PDT 24
Finished Jul 28 07:18:20 PM PDT 24
Peak memory 216028 kb
Host smart-d72fb527-5cf8-432e-a0a1-1f6c16f2d575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295889877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.295889877
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.534577388
Short name T144
Test name
Test status
Simulation time 1051023834 ps
CPU time 11.71 seconds
Started Jul 28 07:15:55 PM PDT 24
Finished Jul 28 07:16:07 PM PDT 24
Peak memory 199648 kb
Host smart-d4f552c4-55e9-4e10-a296-e130446136cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534577388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.534577388
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3540457022
Short name T104
Test name
Test status
Simulation time 508058887783 ps
CPU time 2012.21 seconds
Started Jul 28 07:15:55 PM PDT 24
Finished Jul 28 07:49:28 PM PDT 24
Peak memory 657780 kb
Host smart-655e1137-8a50-4553-8af1-f413548922a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540457022 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3540457022
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2074254908
Short name T159
Test name
Test status
Simulation time 899452793 ps
CPU time 54.62 seconds
Started Jul 28 07:15:58 PM PDT 24
Finished Jul 28 07:16:53 PM PDT 24
Peak memory 199572 kb
Host smart-3cafcc18-ed71-40e1-b5d0-229ec84a814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074254908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2074254908
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.293471023
Short name T37
Test name
Test status
Simulation time 21030226 ps
CPU time 0.57 seconds
Started Jul 28 07:16:00 PM PDT 24
Finished Jul 28 07:16:01 PM PDT 24
Peak memory 195588 kb
Host smart-afe8feea-aae4-4e10-837c-06b4fe7fa0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293471023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.293471023
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.988582323
Short name T189
Test name
Test status
Simulation time 2273420988 ps
CPU time 70.91 seconds
Started Jul 28 07:15:56 PM PDT 24
Finished Jul 28 07:17:07 PM PDT 24
Peak memory 199712 kb
Host smart-1509d555-b136-4ce6-bad6-847c25e0667b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988582323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.988582323
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.22743764
Short name T231
Test name
Test status
Simulation time 3016015344 ps
CPU time 7.59 seconds
Started Jul 28 07:16:01 PM PDT 24
Finished Jul 28 07:16:09 PM PDT 24
Peak memory 199736 kb
Host smart-50f4207e-788b-4fd8-b1d4-2caa0112d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22743764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.22743764
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3268525645
Short name T197
Test name
Test status
Simulation time 12415935885 ps
CPU time 478.1 seconds
Started Jul 28 07:16:01 PM PDT 24
Finished Jul 28 07:23:59 PM PDT 24
Peak memory 628376 kb
Host smart-522f04f4-4231-48f6-adf8-3001ad71ed82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268525645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3268525645
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.4287519849
Short name T490
Test name
Test status
Simulation time 8837871816 ps
CPU time 87.56 seconds
Started Jul 28 07:16:01 PM PDT 24
Finished Jul 28 07:17:29 PM PDT 24
Peak memory 199636 kb
Host smart-5f3bda84-a5ba-46d4-9788-b367dddeb37a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287519849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4287519849
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3662468430
Short name T528
Test name
Test status
Simulation time 2589413996 ps
CPU time 144.44 seconds
Started Jul 28 07:16:00 PM PDT 24
Finished Jul 28 07:18:25 PM PDT 24
Peak memory 199712 kb
Host smart-ad90d1ce-25aa-4176-948c-d1f1979b346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662468430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3662468430
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1106988402
Short name T416
Test name
Test status
Simulation time 948233135 ps
CPU time 12.38 seconds
Started Jul 28 07:15:55 PM PDT 24
Finished Jul 28 07:16:07 PM PDT 24
Peak memory 199664 kb
Host smart-f71ca04c-0517-48ce-8f7c-d30b303af7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106988402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1106988402
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1445808476
Short name T216
Test name
Test status
Simulation time 30901675836 ps
CPU time 4634.98 seconds
Started Jul 28 07:16:02 PM PDT 24
Finished Jul 28 08:33:18 PM PDT 24
Peak memory 807124 kb
Host smart-831294b5-d87a-4502-b6a4-c4a5d372595b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445808476 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1445808476
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.485966490
Short name T277
Test name
Test status
Simulation time 1974767370 ps
CPU time 14.91 seconds
Started Jul 28 07:16:00 PM PDT 24
Finished Jul 28 07:16:15 PM PDT 24
Peak memory 199664 kb
Host smart-34181841-a3a2-49ee-ad47-a0f5f2963e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485966490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.485966490
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4255970813
Short name T46
Test name
Test status
Simulation time 13842703 ps
CPU time 0.6 seconds
Started Jul 28 07:16:06 PM PDT 24
Finished Jul 28 07:16:07 PM PDT 24
Peak memory 195712 kb
Host smart-c6360931-5644-4925-96b1-6c60a6cb80e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255970813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4255970813
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3518118379
Short name T80
Test name
Test status
Simulation time 3054406316 ps
CPU time 43.55 seconds
Started Jul 28 07:16:00 PM PDT 24
Finished Jul 28 07:16:44 PM PDT 24
Peak memory 199736 kb
Host smart-609c8d48-570a-4f93-9bc4-0078428aad72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518118379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3518118379
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1326177734
Short name T431
Test name
Test status
Simulation time 4553405015 ps
CPU time 51.75 seconds
Started Jul 28 07:16:00 PM PDT 24
Finished Jul 28 07:16:52 PM PDT 24
Peak memory 207872 kb
Host smart-2e4be4e9-8184-43f7-838f-9ea7eb6e88ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326177734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1326177734
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1888494137
Short name T468
Test name
Test status
Simulation time 2421567331 ps
CPU time 429.51 seconds
Started Jul 28 07:16:00 PM PDT 24
Finished Jul 28 07:23:10 PM PDT 24
Peak memory 643164 kb
Host smart-27fc95d3-aaa8-4d0a-8b86-769f81ad2dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888494137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1888494137
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2906463578
Short name T8
Test name
Test status
Simulation time 10260463688 ps
CPU time 285.35 seconds
Started Jul 28 07:16:03 PM PDT 24
Finished Jul 28 07:20:48 PM PDT 24
Peak memory 199612 kb
Host smart-45730f39-d39c-483c-ab57-6dd2e0653091
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906463578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2906463578
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3521936958
Short name T47
Test name
Test status
Simulation time 8240176350 ps
CPU time 69.39 seconds
Started Jul 28 07:16:01 PM PDT 24
Finished Jul 28 07:17:10 PM PDT 24
Peak memory 199688 kb
Host smart-df9811b1-df3e-4658-a53c-f48a9f4130b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521936958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3521936958
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.236919333
Short name T489
Test name
Test status
Simulation time 4955994716 ps
CPU time 11.69 seconds
Started Jul 28 07:16:02 PM PDT 24
Finished Jul 28 07:16:13 PM PDT 24
Peak memory 199748 kb
Host smart-5f2700ff-9cab-474f-aa57-c9348d9477f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236919333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.236919333
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2157166801
Short name T83
Test name
Test status
Simulation time 218846361878 ps
CPU time 688.63 seconds
Started Jul 28 07:16:05 PM PDT 24
Finished Jul 28 07:27:34 PM PDT 24
Peak memory 199780 kb
Host smart-2759abbf-46de-4f76-838c-c0c05513627a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157166801 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2157166801
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3903812963
Short name T76
Test name
Test status
Simulation time 1541941030 ps
CPU time 28.2 seconds
Started Jul 28 07:16:05 PM PDT 24
Finished Jul 28 07:16:33 PM PDT 24
Peak memory 199628 kb
Host smart-8c04cf5b-6f10-492c-951b-ea793c2fbfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903812963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3903812963
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2262176437
Short name T392
Test name
Test status
Simulation time 83412738 ps
CPU time 0.57 seconds
Started Jul 28 07:16:05 PM PDT 24
Finished Jul 28 07:16:06 PM PDT 24
Peak memory 194616 kb
Host smart-9a21f054-9d50-4fa0-95e4-cd4fff24abe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262176437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2262176437
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3365865441
Short name T444
Test name
Test status
Simulation time 2246457938 ps
CPU time 30.59 seconds
Started Jul 28 07:16:05 PM PDT 24
Finished Jul 28 07:16:36 PM PDT 24
Peak memory 199676 kb
Host smart-97dd21a7-cfbe-4486-bc84-7169f67e5651
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365865441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3365865441
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2239149994
Short name T462
Test name
Test status
Simulation time 14362191363 ps
CPU time 36.76 seconds
Started Jul 28 07:16:07 PM PDT 24
Finished Jul 28 07:16:43 PM PDT 24
Peak memory 199700 kb
Host smart-dc54d69e-956e-410d-999d-ffdceb5060fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239149994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2239149994
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2886531068
Short name T433
Test name
Test status
Simulation time 4407056433 ps
CPU time 840.57 seconds
Started Jul 28 07:16:01 PM PDT 24
Finished Jul 28 07:30:02 PM PDT 24
Peak memory 705248 kb
Host smart-85da7820-7435-4ec8-a2fe-b40d9bb04728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886531068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2886531068
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2554193287
Short name T53
Test name
Test status
Simulation time 5442545806 ps
CPU time 23.12 seconds
Started Jul 28 07:16:04 PM PDT 24
Finished Jul 28 07:16:27 PM PDT 24
Peak memory 199700 kb
Host smart-659ba794-21b3-427b-b33f-dd6541c1dba7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554193287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2554193287
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1338644718
Short name T160
Test name
Test status
Simulation time 1209176184 ps
CPU time 28.38 seconds
Started Jul 28 07:16:07 PM PDT 24
Finished Jul 28 07:16:35 PM PDT 24
Peak memory 199696 kb
Host smart-1f0a3c66-cefa-492d-935c-2f555d0478fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338644718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1338644718
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3258896222
Short name T510
Test name
Test status
Simulation time 1002957604 ps
CPU time 11.46 seconds
Started Jul 28 07:16:04 PM PDT 24
Finished Jul 28 07:16:16 PM PDT 24
Peak memory 199644 kb
Host smart-d2dd1c7b-9684-4056-8d68-fe88a4aab767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258896222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3258896222
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3655352555
Short name T526
Test name
Test status
Simulation time 854428678867 ps
CPU time 1393.53 seconds
Started Jul 28 07:16:05 PM PDT 24
Finished Jul 28 07:39:19 PM PDT 24
Peak memory 735336 kb
Host smart-638dbf30-b1bd-4d17-9631-9916366568b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655352555 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3655352555
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3541463662
Short name T244
Test name
Test status
Simulation time 388138832 ps
CPU time 21.58 seconds
Started Jul 28 07:16:04 PM PDT 24
Finished Jul 28 07:16:25 PM PDT 24
Peak memory 199632 kb
Host smart-f2fbff48-13a5-4459-8966-bf4f2bc8afb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541463662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3541463662
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4064567249
Short name T328
Test name
Test status
Simulation time 39011122 ps
CPU time 0.58 seconds
Started Jul 28 07:16:13 PM PDT 24
Finished Jul 28 07:16:14 PM PDT 24
Peak memory 195604 kb
Host smart-d8cc24a4-3700-4268-9a30-c460dc4c75de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064567249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4064567249
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2326803836
Short name T391
Test name
Test status
Simulation time 178827000 ps
CPU time 2.78 seconds
Started Jul 28 07:16:08 PM PDT 24
Finished Jul 28 07:16:11 PM PDT 24
Peak memory 199544 kb
Host smart-67fee2a1-343c-4ca6-b233-b4f1587cace0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326803836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2326803836
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2353993409
Short name T461
Test name
Test status
Simulation time 2949654389 ps
CPU time 45.45 seconds
Started Jul 28 07:16:10 PM PDT 24
Finished Jul 28 07:16:55 PM PDT 24
Peak memory 199688 kb
Host smart-92da414b-133a-4cb2-96bd-d06b2c36bb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353993409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2353993409
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2834267348
Short name T499
Test name
Test status
Simulation time 1039695606 ps
CPU time 191.2 seconds
Started Jul 28 07:16:06 PM PDT 24
Finished Jul 28 07:19:18 PM PDT 24
Peak memory 602244 kb
Host smart-044a9a40-2c23-411d-8727-dbd33ba98dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834267348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2834267348
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3183650542
Short name T393
Test name
Test status
Simulation time 15950810567 ps
CPU time 72.84 seconds
Started Jul 28 07:16:08 PM PDT 24
Finished Jul 28 07:17:21 PM PDT 24
Peak memory 199692 kb
Host smart-2f4ad9f2-05b1-46d6-8a02-eb8cd680de83
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183650542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3183650542
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3623637839
Short name T211
Test name
Test status
Simulation time 9833994051 ps
CPU time 159.31 seconds
Started Jul 28 07:16:09 PM PDT 24
Finished Jul 28 07:18:48 PM PDT 24
Peak memory 215936 kb
Host smart-d77efd67-bc34-4e7f-bc35-f3b69ac96ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623637839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3623637839
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1254345824
Short name T225
Test name
Test status
Simulation time 1448739605 ps
CPU time 17.61 seconds
Started Jul 28 07:16:08 PM PDT 24
Finished Jul 28 07:16:25 PM PDT 24
Peak memory 199568 kb
Host smart-28f4b99c-c482-4d6f-9a07-bfe2ce2eb8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254345824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1254345824
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.704794594
Short name T274
Test name
Test status
Simulation time 5453836845 ps
CPU time 74.94 seconds
Started Jul 28 07:16:10 PM PDT 24
Finished Jul 28 07:17:25 PM PDT 24
Peak memory 199720 kb
Host smart-22e4998d-c929-4b56-ad66-50079e1271b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704794594 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.704794594
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3898828398
Short name T255
Test name
Test status
Simulation time 1610341284 ps
CPU time 27.74 seconds
Started Jul 28 07:16:14 PM PDT 24
Finished Jul 28 07:16:42 PM PDT 24
Peak memory 199652 kb
Host smart-b06fc425-b9a9-409d-8f73-f4d4074498f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898828398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3898828398
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3764739726
Short name T245
Test name
Test status
Simulation time 12993490 ps
CPU time 0.61 seconds
Started Jul 28 07:16:19 PM PDT 24
Finished Jul 28 07:16:19 PM PDT 24
Peak memory 195656 kb
Host smart-c1c8b4d3-fe4c-4306-a751-2a072314821d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764739726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3764739726
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.4107967990
Short name T450
Test name
Test status
Simulation time 1623569369 ps
CPU time 92.69 seconds
Started Jul 28 07:16:15 PM PDT 24
Finished Jul 28 07:17:48 PM PDT 24
Peak memory 199632 kb
Host smart-20a0ec70-3b5a-4adc-8479-832014b17f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107967990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4107967990
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3166464305
Short name T516
Test name
Test status
Simulation time 788284394 ps
CPU time 4.27 seconds
Started Jul 28 07:16:12 PM PDT 24
Finished Jul 28 07:16:17 PM PDT 24
Peak memory 199612 kb
Host smart-2e48c90f-2832-495c-bc23-5d19224318ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166464305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3166464305
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2480263064
Short name T221
Test name
Test status
Simulation time 4045683263 ps
CPU time 787.56 seconds
Started Jul 28 07:16:16 PM PDT 24
Finished Jul 28 07:29:23 PM PDT 24
Peak memory 753656 kb
Host smart-c6eacd4e-7756-46e1-8f12-3c4612ff21e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480263064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2480263064
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3957572526
Short name T498
Test name
Test status
Simulation time 26078687037 ps
CPU time 116.44 seconds
Started Jul 28 07:16:14 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 199688 kb
Host smart-ea498d83-c891-4af8-b5ac-637188677f9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957572526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3957572526
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.4200064896
Short name T390
Test name
Test status
Simulation time 65836343305 ps
CPU time 199.29 seconds
Started Jul 28 07:16:12 PM PDT 24
Finished Jul 28 07:19:31 PM PDT 24
Peak memory 216080 kb
Host smart-a304e624-b7bf-433f-8080-b429d4cfa63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200064896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.4200064896
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.838617721
Short name T246
Test name
Test status
Simulation time 291320450 ps
CPU time 7.6 seconds
Started Jul 28 07:16:14 PM PDT 24
Finished Jul 28 07:16:22 PM PDT 24
Peak memory 199644 kb
Host smart-a6cb114d-98fd-41f8-91bd-3c985cfb6822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838617721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.838617721
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.451077880
Short name T373
Test name
Test status
Simulation time 1469328634 ps
CPU time 75.87 seconds
Started Jul 28 07:16:19 PM PDT 24
Finished Jul 28 07:17:35 PM PDT 24
Peak memory 199612 kb
Host smart-17f4b4bf-6b9b-4066-90d2-7069858241b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451077880 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.451077880
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3161827178
Short name T383
Test name
Test status
Simulation time 23817851104 ps
CPU time 91.28 seconds
Started Jul 28 07:16:18 PM PDT 24
Finished Jul 28 07:17:49 PM PDT 24
Peak memory 199808 kb
Host smart-9c1748ee-f5b2-4a39-98d5-596bf1d1c8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161827178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3161827178
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3071586877
Short name T372
Test name
Test status
Simulation time 13333159 ps
CPU time 0.59 seconds
Started Jul 28 07:16:23 PM PDT 24
Finished Jul 28 07:16:24 PM PDT 24
Peak memory 195696 kb
Host smart-fcb84759-663c-4f44-ae1d-02129d7e4104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071586877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3071586877
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3721438111
Short name T156
Test name
Test status
Simulation time 608793795 ps
CPU time 33.82 seconds
Started Jul 28 07:16:19 PM PDT 24
Finished Jul 28 07:16:53 PM PDT 24
Peak memory 199632 kb
Host smart-3fdf941d-de43-4027-8225-880de367bbcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721438111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3721438111
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1083454528
Short name T147
Test name
Test status
Simulation time 2632485799 ps
CPU time 28.58 seconds
Started Jul 28 07:16:19 PM PDT 24
Finished Jul 28 07:16:47 PM PDT 24
Peak memory 199744 kb
Host smart-7e822b43-e107-4e94-8bb7-8923635040bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083454528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1083454528
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1506502131
Short name T151
Test name
Test status
Simulation time 11781585192 ps
CPU time 1077.74 seconds
Started Jul 28 07:16:19 PM PDT 24
Finished Jul 28 07:34:17 PM PDT 24
Peak memory 704116 kb
Host smart-233ede06-cc0f-4198-b116-b63e017899b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506502131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1506502131
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3582847101
Short name T3
Test name
Test status
Simulation time 18243584963 ps
CPU time 62.32 seconds
Started Jul 28 07:16:19 PM PDT 24
Finished Jul 28 07:17:21 PM PDT 24
Peak memory 199760 kb
Host smart-80f18958-7b6f-4366-9388-88b07c1eb455
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582847101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3582847101
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.235352330
Short name T305
Test name
Test status
Simulation time 2089574622 ps
CPU time 30.57 seconds
Started Jul 28 07:16:17 PM PDT 24
Finished Jul 28 07:16:48 PM PDT 24
Peak memory 199616 kb
Host smart-42d55a3f-7486-4951-b554-a8c838e33c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235352330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.235352330
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.446976744
Short name T270
Test name
Test status
Simulation time 7114571138 ps
CPU time 16.17 seconds
Started Jul 28 07:16:18 PM PDT 24
Finished Jul 28 07:16:34 PM PDT 24
Peak memory 199776 kb
Host smart-0c000c29-ff2d-459a-a371-445c4dce78f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446976744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.446976744
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4135530210
Short name T93
Test name
Test status
Simulation time 110977045255 ps
CPU time 171.62 seconds
Started Jul 28 07:16:20 PM PDT 24
Finished Jul 28 07:19:11 PM PDT 24
Peak memory 216148 kb
Host smart-eeab4725-157c-4d03-8602-41c8dd87d88f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135530210 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4135530210
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1210771664
Short name T91
Test name
Test status
Simulation time 592506659 ps
CPU time 10.5 seconds
Started Jul 28 07:16:22 PM PDT 24
Finished Jul 28 07:16:32 PM PDT 24
Peak memory 199660 kb
Host smart-f7d569d8-2cc2-4c4a-af8f-09b644ab8cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210771664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1210771664
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1756643790
Short name T170
Test name
Test status
Simulation time 14695549 ps
CPU time 0.57 seconds
Started Jul 28 07:16:26 PM PDT 24
Finished Jul 28 07:16:27 PM PDT 24
Peak memory 194628 kb
Host smart-82d16f99-ef75-41f9-97d7-197b717ebcc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756643790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1756643790
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.824972205
Short name T240
Test name
Test status
Simulation time 4918802547 ps
CPU time 39.68 seconds
Started Jul 28 07:16:22 PM PDT 24
Finished Jul 28 07:17:02 PM PDT 24
Peak memory 199684 kb
Host smart-ab6224bf-e9d5-4b87-b72e-d476c6667b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824972205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.824972205
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2855741484
Short name T334
Test name
Test status
Simulation time 6085887347 ps
CPU time 62.92 seconds
Started Jul 28 07:16:25 PM PDT 24
Finished Jul 28 07:17:28 PM PDT 24
Peak memory 199716 kb
Host smart-5b1ac994-1c80-48b1-8671-c72c33a26039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855741484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2855741484
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3127505070
Short name T412
Test name
Test status
Simulation time 13167703666 ps
CPU time 1244.07 seconds
Started Jul 28 07:16:22 PM PDT 24
Finished Jul 28 07:37:06 PM PDT 24
Peak memory 700772 kb
Host smart-e7913b67-9647-4a29-ba14-2cb57892be67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127505070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3127505070
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.816266970
Short name T176
Test name
Test status
Simulation time 4578508387 ps
CPU time 51.98 seconds
Started Jul 28 07:16:21 PM PDT 24
Finished Jul 28 07:17:13 PM PDT 24
Peak memory 199672 kb
Host smart-686e1059-19c7-4cf6-b6a8-aaa38cb21de4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816266970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.816266970
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2754754310
Short name T296
Test name
Test status
Simulation time 10723139088 ps
CPU time 86.4 seconds
Started Jul 28 07:16:27 PM PDT 24
Finished Jul 28 07:17:54 PM PDT 24
Peak memory 199728 kb
Host smart-518bdc46-2a06-486a-83e9-88cf73c8d898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754754310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2754754310
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1081567224
Short name T410
Test name
Test status
Simulation time 1551998607 ps
CPU time 14.31 seconds
Started Jul 28 07:16:23 PM PDT 24
Finished Jul 28 07:16:37 PM PDT 24
Peak memory 199624 kb
Host smart-b70424f0-f3c2-4555-8cbc-cb06667901f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081567224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1081567224
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1070493820
Short name T127
Test name
Test status
Simulation time 26003733738 ps
CPU time 1230.38 seconds
Started Jul 28 07:16:23 PM PDT 24
Finished Jul 28 07:36:54 PM PDT 24
Peak memory 708392 kb
Host smart-5afcb75e-f34c-4341-87b7-668f81e2df25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070493820 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1070493820
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3064647912
Short name T81
Test name
Test status
Simulation time 41306558977 ps
CPU time 125.23 seconds
Started Jul 28 07:16:23 PM PDT 24
Finished Jul 28 07:18:29 PM PDT 24
Peak memory 199744 kb
Host smart-058a0865-0298-40f0-9719-3b3ce043d6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064647912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3064647912
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.932672538
Short name T200
Test name
Test status
Simulation time 13278831 ps
CPU time 0.6 seconds
Started Jul 28 07:16:27 PM PDT 24
Finished Jul 28 07:16:27 PM PDT 24
Peak memory 194656 kb
Host smart-01b89dd8-e799-42a1-bb94-4a9eef5e56b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932672538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.932672538
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3258261141
Short name T436
Test name
Test status
Simulation time 1515805888 ps
CPU time 42.37 seconds
Started Jul 28 07:16:26 PM PDT 24
Finished Jul 28 07:17:09 PM PDT 24
Peak memory 199624 kb
Host smart-12d6de9b-5551-40c9-ae44-523d5daa6499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258261141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3258261141
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3736530462
Short name T222
Test name
Test status
Simulation time 3693824761 ps
CPU time 47.34 seconds
Started Jul 28 07:16:27 PM PDT 24
Finished Jul 28 07:17:15 PM PDT 24
Peak memory 199688 kb
Host smart-9502e135-7043-44b8-b692-1e7a51d9ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736530462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3736530462
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2595682165
Short name T75
Test name
Test status
Simulation time 1417055410 ps
CPU time 299.76 seconds
Started Jul 28 07:16:26 PM PDT 24
Finished Jul 28 07:21:25 PM PDT 24
Peak memory 644864 kb
Host smart-8740111b-530e-4b2e-ab31-737361b84a12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595682165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2595682165
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2509121
Short name T154
Test name
Test status
Simulation time 35466635947 ps
CPU time 163.58 seconds
Started Jul 28 07:16:27 PM PDT 24
Finished Jul 28 07:19:11 PM PDT 24
Peak memory 199656 kb
Host smart-58762a6d-8d3d-477b-93b3-89d49c6e381c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2509121
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3745753344
Short name T229
Test name
Test status
Simulation time 8082084168 ps
CPU time 146.94 seconds
Started Jul 28 07:16:22 PM PDT 24
Finished Jul 28 07:18:50 PM PDT 24
Peak memory 207864 kb
Host smart-46f41d6d-cdc3-42d2-a2d2-958fc84f445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745753344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3745753344
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1371597410
Short name T214
Test name
Test status
Simulation time 1573184176 ps
CPU time 13.08 seconds
Started Jul 28 07:16:27 PM PDT 24
Finished Jul 28 07:16:40 PM PDT 24
Peak memory 199700 kb
Host smart-a7259ced-c8a5-494c-8ac6-8623dddeb4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371597410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1371597410
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1986763171
Short name T98
Test name
Test status
Simulation time 73091880036 ps
CPU time 467.31 seconds
Started Jul 28 07:16:28 PM PDT 24
Finished Jul 28 07:24:16 PM PDT 24
Peak memory 651664 kb
Host smart-0f5ee622-3ea8-4a1c-8d54-f31091e9cbc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986763171 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1986763171
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4190673304
Short name T195
Test name
Test status
Simulation time 193726321 ps
CPU time 10.43 seconds
Started Jul 28 07:16:26 PM PDT 24
Finished Jul 28 07:16:37 PM PDT 24
Peak memory 199556 kb
Host smart-34ad64d0-210a-4beb-87a6-769dfc1c6813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190673304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4190673304
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3981033468
Short name T54
Test name
Test status
Simulation time 21924142 ps
CPU time 0.59 seconds
Started Jul 28 07:14:13 PM PDT 24
Finished Jul 28 07:14:14 PM PDT 24
Peak memory 196288 kb
Host smart-7f1b23f4-7d57-4c5e-8c25-9f9edd3b6193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981033468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3981033468
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3482805611
Short name T356
Test name
Test status
Simulation time 7593036584 ps
CPU time 105.3 seconds
Started Jul 28 07:14:11 PM PDT 24
Finished Jul 28 07:15:56 PM PDT 24
Peak memory 199624 kb
Host smart-11ecc384-d26f-430a-a4df-f9d707f44237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482805611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3482805611
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3561429474
Short name T399
Test name
Test status
Simulation time 2701040915 ps
CPU time 34.08 seconds
Started Jul 28 07:14:08 PM PDT 24
Finished Jul 28 07:14:42 PM PDT 24
Peak memory 199716 kb
Host smart-2271edfa-c92a-48e6-940b-404d1de26f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561429474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3561429474
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.286608153
Short name T162
Test name
Test status
Simulation time 20283649975 ps
CPU time 953.94 seconds
Started Jul 28 07:14:12 PM PDT 24
Finished Jul 28 07:30:06 PM PDT 24
Peak memory 767040 kb
Host smart-f6554a6e-9661-4504-b3cd-0afc43e98f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286608153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.286608153
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2106340255
Short name T365
Test name
Test status
Simulation time 35393790560 ps
CPU time 142.32 seconds
Started Jul 28 07:14:13 PM PDT 24
Finished Jul 28 07:16:36 PM PDT 24
Peak memory 199728 kb
Host smart-383459a8-4f4d-4ace-b779-4f5f49fb24c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106340255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2106340255
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.253611335
Short name T367
Test name
Test status
Simulation time 5623735513 ps
CPU time 74.45 seconds
Started Jul 28 07:14:03 PM PDT 24
Finished Jul 28 07:15:18 PM PDT 24
Peak memory 199716 kb
Host smart-6091bcc5-ab8e-492d-bd03-6666c62801b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253611335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.253611335
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1252911171
Short name T57
Test name
Test status
Simulation time 140101252 ps
CPU time 1.05 seconds
Started Jul 28 07:14:11 PM PDT 24
Finished Jul 28 07:14:12 PM PDT 24
Peak memory 219216 kb
Host smart-faab06b2-94d6-4e58-bc73-87993e6cc90f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252911171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1252911171
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4204828193
Short name T29
Test name
Test status
Simulation time 453844244 ps
CPU time 5.83 seconds
Started Jul 28 07:14:05 PM PDT 24
Finished Jul 28 07:14:10 PM PDT 24
Peak memory 199620 kb
Host smart-e23de5f6-fb44-40bd-8cb5-defcf5cd62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204828193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4204828193
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1905617488
Short name T386
Test name
Test status
Simulation time 28631228308 ps
CPU time 2269.48 seconds
Started Jul 28 07:14:14 PM PDT 24
Finished Jul 28 07:52:03 PM PDT 24
Peak memory 759388 kb
Host smart-fbc6f650-37d2-4f81-a100-4b1ae7ef9acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905617488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1905617488
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3407264865
Short name T12
Test name
Test status
Simulation time 39141074436 ps
CPU time 2943.33 seconds
Started Jul 28 07:14:12 PM PDT 24
Finished Jul 28 08:03:15 PM PDT 24
Peak memory 734840 kb
Host smart-c229e5c4-f1ca-423f-80f4-6afed4314ac0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407264865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3407264865
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1409938594
Short name T454
Test name
Test status
Simulation time 5693156770 ps
CPU time 71.16 seconds
Started Jul 28 07:14:11 PM PDT 24
Finished Jul 28 07:15:22 PM PDT 24
Peak memory 199724 kb
Host smart-e31b00ff-c2e6-4afe-86f4-03e912f76dc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1409938594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1409938594
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.126553083
Short name T294
Test name
Test status
Simulation time 3903706266 ps
CPU time 57.61 seconds
Started Jul 28 07:14:13 PM PDT 24
Finished Jul 28 07:15:10 PM PDT 24
Peak memory 199724 kb
Host smart-7a0dddaa-3058-40a2-a397-d0c90e7a816d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=126553083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.126553083
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2698498852
Short name T419
Test name
Test status
Simulation time 15671722068 ps
CPU time 122.85 seconds
Started Jul 28 07:14:13 PM PDT 24
Finished Jul 28 07:16:16 PM PDT 24
Peak memory 199676 kb
Host smart-5f763278-22ec-4cee-9942-b625539baec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2698498852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2698498852
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.4208432153
Short name T303
Test name
Test status
Simulation time 55085239656 ps
CPU time 669.41 seconds
Started Jul 28 07:14:08 PM PDT 24
Finished Jul 28 07:25:18 PM PDT 24
Peak memory 199748 kb
Host smart-b406ca50-3279-4bbc-95f1-ea0cd444effc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4208432153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.4208432153
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3479594499
Short name T488
Test name
Test status
Simulation time 156737484002 ps
CPU time 2017.09 seconds
Started Jul 28 07:14:12 PM PDT 24
Finished Jul 28 07:47:49 PM PDT 24
Peak memory 216004 kb
Host smart-412dddfa-d6e0-468e-8841-fc43c0779d9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3479594499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3479594499
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1061327518
Short name T376
Test name
Test status
Simulation time 164878995653 ps
CPU time 2235.47 seconds
Started Jul 28 07:14:11 PM PDT 24
Finished Jul 28 07:51:27 PM PDT 24
Peak memory 216116 kb
Host smart-22aa2af7-4633-4988-aa90-051117a4bf95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1061327518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1061327518
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1626985040
Short name T172
Test name
Test status
Simulation time 4177922599 ps
CPU time 67.86 seconds
Started Jul 28 07:14:10 PM PDT 24
Finished Jul 28 07:15:18 PM PDT 24
Peak memory 199656 kb
Host smart-e24bf891-83b2-4a20-a28a-a7a9b44e8bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626985040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1626985040
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.963045122
Short name T287
Test name
Test status
Simulation time 31949215 ps
CPU time 0.57 seconds
Started Jul 28 07:16:31 PM PDT 24
Finished Jul 28 07:16:32 PM PDT 24
Peak memory 194636 kb
Host smart-3b9dc9d5-5b81-4b99-8216-9f31d6439805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963045122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.963045122
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1480320
Short name T407
Test name
Test status
Simulation time 1419481451 ps
CPU time 80.11 seconds
Started Jul 28 07:16:32 PM PDT 24
Finished Jul 28 07:17:52 PM PDT 24
Peak memory 199696 kb
Host smart-f5ac6f50-acb5-41d3-bc4b-f7ce4267f16b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1480320
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.617262406
Short name T48
Test name
Test status
Simulation time 573357399 ps
CPU time 25.93 seconds
Started Jul 28 07:16:32 PM PDT 24
Finished Jul 28 07:16:58 PM PDT 24
Peak memory 199692 kb
Host smart-e8fb644c-9913-4a92-9b07-9389e22237c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617262406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.617262406
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2621373108
Short name T463
Test name
Test status
Simulation time 22553986926 ps
CPU time 1210.01 seconds
Started Jul 28 07:16:31 PM PDT 24
Finished Jul 28 07:36:41 PM PDT 24
Peak memory 713016 kb
Host smart-2251dd1e-1b14-4f09-a1e2-7e21c9278553
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621373108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2621373108
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.501010873
Short name T283
Test name
Test status
Simulation time 1190273102 ps
CPU time 17.96 seconds
Started Jul 28 07:16:32 PM PDT 24
Finished Jul 28 07:16:50 PM PDT 24
Peak memory 199648 kb
Host smart-06a34e10-54c8-4e52-b017-ef7f78723d66
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501010873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.501010873
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3165787175
Short name T405
Test name
Test status
Simulation time 31516838317 ps
CPU time 156.48 seconds
Started Jul 28 07:16:32 PM PDT 24
Finished Jul 28 07:19:08 PM PDT 24
Peak memory 199772 kb
Host smart-f3180eff-40be-459e-bfbc-b1d034d740ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165787175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3165787175
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2275741685
Short name T171
Test name
Test status
Simulation time 1792640055 ps
CPU time 4.3 seconds
Started Jul 28 07:16:34 PM PDT 24
Finished Jul 28 07:16:38 PM PDT 24
Peak memory 199644 kb
Host smart-671615bd-7c16-49eb-b918-201f07c34dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275741685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2275741685
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1304864260
Short name T165
Test name
Test status
Simulation time 535255371 ps
CPU time 30.35 seconds
Started Jul 28 07:16:30 PM PDT 24
Finished Jul 28 07:17:01 PM PDT 24
Peak memory 199668 kb
Host smart-64a028a5-7c81-4607-91a6-de465699fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304864260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1304864260
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2447112356
Short name T442
Test name
Test status
Simulation time 12519637 ps
CPU time 0.58 seconds
Started Jul 28 07:16:36 PM PDT 24
Finished Jul 28 07:16:37 PM PDT 24
Peak memory 195676 kb
Host smart-24879a21-911b-4830-aa8c-1f060dbbe83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447112356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2447112356
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4282499752
Short name T184
Test name
Test status
Simulation time 34436160 ps
CPU time 1.87 seconds
Started Jul 28 07:16:30 PM PDT 24
Finished Jul 28 07:16:32 PM PDT 24
Peak memory 199648 kb
Host smart-5b206164-3deb-4ef4-aec7-f4ece52eccec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282499752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4282499752
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.545855737
Short name T203
Test name
Test status
Simulation time 2914276550 ps
CPU time 31.2 seconds
Started Jul 28 07:16:34 PM PDT 24
Finished Jul 28 07:17:05 PM PDT 24
Peak memory 199724 kb
Host smart-71089259-3d61-4dc2-ad35-11f6d117a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545855737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.545855737
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1946642831
Short name T327
Test name
Test status
Simulation time 2991972179 ps
CPU time 275.6 seconds
Started Jul 28 07:16:34 PM PDT 24
Finished Jul 28 07:21:10 PM PDT 24
Peak memory 469348 kb
Host smart-8caf11ff-a060-4520-9b56-c3efac53df5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946642831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1946642831
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2481901093
Short name T39
Test name
Test status
Simulation time 9153867816 ps
CPU time 53.11 seconds
Started Jul 28 07:16:35 PM PDT 24
Finished Jul 28 07:17:28 PM PDT 24
Peak memory 199648 kb
Host smart-04d8ac16-0f5f-4c29-b07d-19d77d4bd6f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481901093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2481901093
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3466029578
Short name T41
Test name
Test status
Simulation time 4351649327 ps
CPU time 56.11 seconds
Started Jul 28 07:16:34 PM PDT 24
Finished Jul 28 07:17:30 PM PDT 24
Peak memory 199728 kb
Host smart-a4a09548-b0ef-4f96-bcdf-2f2b8bd61e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466029578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3466029578
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.334416889
Short name T35
Test name
Test status
Simulation time 405757850 ps
CPU time 8.92 seconds
Started Jul 28 07:16:30 PM PDT 24
Finished Jul 28 07:16:39 PM PDT 24
Peak memory 199676 kb
Host smart-7047bea4-ee91-4b37-b27f-e2ff502fbcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334416889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.334416889
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2627484388
Short name T380
Test name
Test status
Simulation time 55351952013 ps
CPU time 246.24 seconds
Started Jul 28 07:16:38 PM PDT 24
Finished Jul 28 07:20:45 PM PDT 24
Peak memory 199676 kb
Host smart-d566efdd-6777-49be-b2ee-9003eb2a74b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627484388 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2627484388
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.78976731
Short name T19
Test name
Test status
Simulation time 2088533331 ps
CPU time 100.38 seconds
Started Jul 28 07:16:35 PM PDT 24
Finished Jul 28 07:18:15 PM PDT 24
Peak memory 199612 kb
Host smart-6d3004f3-fdd9-4f76-abc9-b1a657b5453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78976731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.78976731
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4042256049
Short name T331
Test name
Test status
Simulation time 80215442 ps
CPU time 0.59 seconds
Started Jul 28 07:16:43 PM PDT 24
Finished Jul 28 07:16:43 PM PDT 24
Peak memory 195668 kb
Host smart-1df7843e-11c1-480a-85bc-be3ca74dfb94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042256049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4042256049
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3171945528
Short name T249
Test name
Test status
Simulation time 209583914 ps
CPU time 12.27 seconds
Started Jul 28 07:16:38 PM PDT 24
Finished Jul 28 07:16:50 PM PDT 24
Peak memory 199628 kb
Host smart-abca2c4c-cdb5-4003-8cdc-2a788e3d0818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171945528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3171945528
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1848907863
Short name T63
Test name
Test status
Simulation time 586762706 ps
CPU time 6.17 seconds
Started Jul 28 07:16:41 PM PDT 24
Finished Jul 28 07:16:47 PM PDT 24
Peak memory 199568 kb
Host smart-71d58f34-b123-486b-9828-006e496445e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848907863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1848907863
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3425293000
Short name T465
Test name
Test status
Simulation time 3239100918 ps
CPU time 526.87 seconds
Started Jul 28 07:16:35 PM PDT 24
Finished Jul 28 07:25:22 PM PDT 24
Peak memory 519752 kb
Host smart-ddc0e802-0bfa-4f73-afdc-00dfac42a040
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425293000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3425293000
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.199608833
Short name T355
Test name
Test status
Simulation time 16652055648 ps
CPU time 113.8 seconds
Started Jul 28 07:16:40 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 199756 kb
Host smart-f754c78d-9d55-4002-b57e-3d0cd6cccdee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199608833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.199608833
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.799547528
Short name T527
Test name
Test status
Simulation time 3424660206 ps
CPU time 98.56 seconds
Started Jul 28 07:16:36 PM PDT 24
Finished Jul 28 07:18:14 PM PDT 24
Peak memory 207920 kb
Host smart-ce792c3f-f1a8-4fa7-aebf-3787d2d4c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799547528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.799547528
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3937164372
Short name T320
Test name
Test status
Simulation time 114795641 ps
CPU time 1.03 seconds
Started Jul 28 07:16:36 PM PDT 24
Finished Jul 28 07:16:37 PM PDT 24
Peak memory 199512 kb
Host smart-64a33140-7e5d-4c42-bc71-990bfa28a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937164372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3937164372
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3228152190
Short name T235
Test name
Test status
Simulation time 263148813522 ps
CPU time 5972.4 seconds
Started Jul 28 07:16:40 PM PDT 24
Finished Jul 28 08:56:13 PM PDT 24
Peak memory 872552 kb
Host smart-e38d6160-2d88-4c33-9119-23c8773b052f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228152190 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3228152190
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3891596582
Short name T9
Test name
Test status
Simulation time 31886981431 ps
CPU time 141.91 seconds
Started Jul 28 07:16:37 PM PDT 24
Finished Jul 28 07:18:59 PM PDT 24
Peak memory 199956 kb
Host smart-d5b1eaa8-2735-4bae-9bcc-6251e7f3e884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891596582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3891596582
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2394773286
Short name T1
Test name
Test status
Simulation time 27252003 ps
CPU time 0.56 seconds
Started Jul 28 07:16:44 PM PDT 24
Finished Jul 28 07:16:45 PM PDT 24
Peak memory 195280 kb
Host smart-c85c035e-438b-4def-a34c-fe4613979f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394773286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2394773286
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2355920537
Short name T22
Test name
Test status
Simulation time 2262877127 ps
CPU time 15.11 seconds
Started Jul 28 07:16:42 PM PDT 24
Finished Jul 28 07:16:57 PM PDT 24
Peak memory 199740 kb
Host smart-eaa8f4ab-860e-4e2d-8f5f-d0fa9c4a0f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355920537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2355920537
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3094345302
Short name T432
Test name
Test status
Simulation time 6879217137 ps
CPU time 7.73 seconds
Started Jul 28 07:16:44 PM PDT 24
Finished Jul 28 07:16:52 PM PDT 24
Peak memory 199636 kb
Host smart-e5d1c597-0eb3-4a2c-931a-dc9e82146c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094345302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3094345302
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2483547905
Short name T388
Test name
Test status
Simulation time 10181787489 ps
CPU time 800.45 seconds
Started Jul 28 07:16:46 PM PDT 24
Finished Jul 28 07:30:06 PM PDT 24
Peak memory 628028 kb
Host smart-229b44a5-0775-402c-aa28-9521b53b602e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483547905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2483547905
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.627741606
Short name T257
Test name
Test status
Simulation time 7131424991 ps
CPU time 58.64 seconds
Started Jul 28 07:16:45 PM PDT 24
Finished Jul 28 07:17:44 PM PDT 24
Peak memory 199736 kb
Host smart-e51a010f-a0b0-4e79-b289-d2c0d5644a36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627741606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.627741606
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.65752945
Short name T451
Test name
Test status
Simulation time 24462113589 ps
CPU time 105.97 seconds
Started Jul 28 07:16:40 PM PDT 24
Finished Jul 28 07:18:26 PM PDT 24
Peak memory 199728 kb
Host smart-b8ee71ff-6940-4a19-a754-adf40a8045d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65752945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.65752945
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3276812098
Short name T248
Test name
Test status
Simulation time 84045301 ps
CPU time 1.22 seconds
Started Jul 28 07:16:39 PM PDT 24
Finished Jul 28 07:16:41 PM PDT 24
Peak memory 199672 kb
Host smart-6500b27f-0a71-4bde-8528-9f46253e1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276812098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3276812098
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4145283252
Short name T511
Test name
Test status
Simulation time 193714014283 ps
CPU time 1223.49 seconds
Started Jul 28 07:16:47 PM PDT 24
Finished Jul 28 07:37:10 PM PDT 24
Peak memory 679336 kb
Host smart-82d6556b-3483-4838-b016-02e811fbf4e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145283252 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4145283252
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1504653378
Short name T343
Test name
Test status
Simulation time 6952616132 ps
CPU time 92.06 seconds
Started Jul 28 07:16:42 PM PDT 24
Finished Jul 28 07:18:14 PM PDT 24
Peak memory 199960 kb
Host smart-188e3bdb-9462-4ad1-adb7-d186a4bf90a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504653378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1504653378
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2164649833
Short name T486
Test name
Test status
Simulation time 13765198 ps
CPU time 0.58 seconds
Started Jul 28 07:16:43 PM PDT 24
Finished Jul 28 07:16:44 PM PDT 24
Peak memory 194608 kb
Host smart-9c22ebc1-d853-489c-908a-32a56bfb3e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164649833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2164649833
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2771784960
Short name T400
Test name
Test status
Simulation time 1116233269 ps
CPU time 29.52 seconds
Started Jul 28 07:16:45 PM PDT 24
Finished Jul 28 07:17:15 PM PDT 24
Peak memory 199660 kb
Host smart-4c41dfbb-33c7-476a-9db6-239651504cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771784960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2771784960
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.193344276
Short name T345
Test name
Test status
Simulation time 3474999425 ps
CPU time 46.83 seconds
Started Jul 28 07:16:43 PM PDT 24
Finished Jul 28 07:17:30 PM PDT 24
Peak memory 207944 kb
Host smart-e96711e2-de59-4390-afba-8053aecdd596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193344276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.193344276
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3009433715
Short name T421
Test name
Test status
Simulation time 448428196 ps
CPU time 60.42 seconds
Started Jul 28 07:16:45 PM PDT 24
Finished Jul 28 07:17:45 PM PDT 24
Peak memory 328208 kb
Host smart-fd6247c7-51d9-4a0f-8e0c-40f1113388e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009433715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3009433715
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.596150610
Short name T509
Test name
Test status
Simulation time 17667204386 ps
CPU time 228.2 seconds
Started Jul 28 07:16:45 PM PDT 24
Finished Jul 28 07:20:33 PM PDT 24
Peak memory 199708 kb
Host smart-16ce2f9a-c116-4d04-9651-be6fd155217a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596150610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.596150610
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.584194056
Short name T163
Test name
Test status
Simulation time 2612952206 ps
CPU time 141.88 seconds
Started Jul 28 07:16:45 PM PDT 24
Finished Jul 28 07:19:07 PM PDT 24
Peak memory 199628 kb
Host smart-0de7d3c0-adf6-4ac7-9d6b-6a6463d4dfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584194056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.584194056
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1688910474
Short name T398
Test name
Test status
Simulation time 2508915827 ps
CPU time 14.61 seconds
Started Jul 28 07:16:47 PM PDT 24
Finished Jul 28 07:17:02 PM PDT 24
Peak memory 199744 kb
Host smart-492aec78-4fe4-44e6-a1bb-f409b2b01b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688910474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1688910474
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.174115127
Short name T515
Test name
Test status
Simulation time 23266367170 ps
CPU time 109.6 seconds
Started Jul 28 07:16:44 PM PDT 24
Finished Jul 28 07:18:33 PM PDT 24
Peak memory 199708 kb
Host smart-a1e42911-c220-4e6a-b554-f10a8c0d5185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174115127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.174115127
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3515896548
Short name T441
Test name
Test status
Simulation time 85584927 ps
CPU time 0.58 seconds
Started Jul 28 07:16:53 PM PDT 24
Finished Jul 28 07:16:54 PM PDT 24
Peak memory 196332 kb
Host smart-c780b4cc-f347-4218-bde4-efe028b501eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515896548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3515896548
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.103113534
Short name T351
Test name
Test status
Simulation time 576667470 ps
CPU time 34.21 seconds
Started Jul 28 07:16:46 PM PDT 24
Finished Jul 28 07:17:21 PM PDT 24
Peak memory 199616 kb
Host smart-b7f7d19a-a6e9-4d2a-85cc-3b194a8c82ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103113534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.103113534
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1338905813
Short name T335
Test name
Test status
Simulation time 15996531375 ps
CPU time 47.52 seconds
Started Jul 28 07:16:48 PM PDT 24
Finished Jul 28 07:17:35 PM PDT 24
Peak memory 199732 kb
Host smart-d0249557-5609-4924-ac02-80586207190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338905813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1338905813
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2589764478
Short name T243
Test name
Test status
Simulation time 6541874418 ps
CPU time 370.94 seconds
Started Jul 28 07:16:48 PM PDT 24
Finished Jul 28 07:23:00 PM PDT 24
Peak memory 691548 kb
Host smart-903acb31-f91e-495e-a84b-81c3f18b8a2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589764478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2589764478
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1645227063
Short name T385
Test name
Test status
Simulation time 6782380073 ps
CPU time 158.1 seconds
Started Jul 28 07:16:49 PM PDT 24
Finished Jul 28 07:19:27 PM PDT 24
Peak memory 199712 kb
Host smart-1964ea31-d3ec-430b-91fb-051d23b2f902
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645227063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1645227063
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.574211993
Short name T145
Test name
Test status
Simulation time 4950239810 ps
CPU time 91 seconds
Started Jul 28 07:16:49 PM PDT 24
Finished Jul 28 07:18:20 PM PDT 24
Peak memory 199784 kb
Host smart-edfbd5bd-3128-4868-a59b-3d260806c2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574211993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.574211993
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3201521464
Short name T10
Test name
Test status
Simulation time 200676521 ps
CPU time 4.48 seconds
Started Jul 28 07:16:49 PM PDT 24
Finished Jul 28 07:16:53 PM PDT 24
Peak memory 199608 kb
Host smart-62c978b9-b088-4311-a32d-eab4c13075ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201521464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3201521464
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2112787906
Short name T285
Test name
Test status
Simulation time 80430741908 ps
CPU time 375.68 seconds
Started Jul 28 07:16:47 PM PDT 24
Finished Jul 28 07:23:03 PM PDT 24
Peak memory 199920 kb
Host smart-092c8d33-238e-451b-bb7a-c9a9af4b9266
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112787906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2112787906
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1769638771
Short name T42
Test name
Test status
Simulation time 7564397136 ps
CPU time 95.75 seconds
Started Jul 28 07:16:49 PM PDT 24
Finished Jul 28 07:18:25 PM PDT 24
Peak memory 199648 kb
Host smart-c79d7e7b-3e14-48a2-b808-c4e81cdbe952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769638771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1769638771
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2343654900
Short name T513
Test name
Test status
Simulation time 13860241 ps
CPU time 0.58 seconds
Started Jul 28 07:17:01 PM PDT 24
Finished Jul 28 07:17:01 PM PDT 24
Peak memory 194628 kb
Host smart-41e20e30-9e0d-4f67-a043-b1150849cb24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343654900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2343654900
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.47069079
Short name T280
Test name
Test status
Simulation time 1556477228 ps
CPU time 84.45 seconds
Started Jul 28 07:16:54 PM PDT 24
Finished Jul 28 07:18:18 PM PDT 24
Peak memory 199612 kb
Host smart-8814087f-b0ac-442e-ba24-b251d41ffe4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47069079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.47069079
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2663940372
Short name T428
Test name
Test status
Simulation time 4149186823 ps
CPU time 57.55 seconds
Started Jul 28 07:16:54 PM PDT 24
Finished Jul 28 07:17:51 PM PDT 24
Peak memory 199716 kb
Host smart-310eb2d3-a4a3-4a46-acbb-026bdf7956e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663940372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2663940372
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3175531426
Short name T517
Test name
Test status
Simulation time 14839947082 ps
CPU time 342.67 seconds
Started Jul 28 07:16:55 PM PDT 24
Finished Jul 28 07:22:37 PM PDT 24
Peak memory 703084 kb
Host smart-3855a151-bfaf-422a-b3d9-92746d5d2a94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175531426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3175531426
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3936854251
Short name T194
Test name
Test status
Simulation time 3404389770 ps
CPU time 44.94 seconds
Started Jul 28 07:16:55 PM PDT 24
Finished Jul 28 07:17:40 PM PDT 24
Peak memory 199628 kb
Host smart-1426ab93-7c37-4c9b-a8d2-9ddc2bd9a7de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936854251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3936854251
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.426326628
Short name T275
Test name
Test status
Simulation time 2893686887 ps
CPU time 9.15 seconds
Started Jul 28 07:16:56 PM PDT 24
Finished Jul 28 07:17:05 PM PDT 24
Peak memory 199684 kb
Host smart-66f40fda-9d63-4aa3-b137-b88a3da942d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426326628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.426326628
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3969715634
Short name T453
Test name
Test status
Simulation time 7190282360 ps
CPU time 16.11 seconds
Started Jul 28 07:16:53 PM PDT 24
Finished Jul 28 07:17:09 PM PDT 24
Peak memory 199712 kb
Host smart-e68944cd-fd62-4aa0-ab8b-073904aa45d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969715634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3969715634
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1138439559
Short name T86
Test name
Test status
Simulation time 242489669497 ps
CPU time 1450.64 seconds
Started Jul 28 07:16:59 PM PDT 24
Finished Jul 28 07:41:10 PM PDT 24
Peak memory 700628 kb
Host smart-5bf8be9f-8c2b-4612-b91b-3496dcefb5d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138439559 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1138439559
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2821079608
Short name T153
Test name
Test status
Simulation time 1913574447 ps
CPU time 23.48 seconds
Started Jul 28 07:17:02 PM PDT 24
Finished Jul 28 07:17:25 PM PDT 24
Peak memory 199668 kb
Host smart-9ab88a91-7218-4d99-8b35-ba7b92ed3c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821079608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2821079608
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2861580925
Short name T505
Test name
Test status
Simulation time 40295761 ps
CPU time 0.56 seconds
Started Jul 28 07:16:59 PM PDT 24
Finished Jul 28 07:16:59 PM PDT 24
Peak memory 195296 kb
Host smart-073eb658-d765-47c2-8e41-ab9375f6a3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861580925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2861580925
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1914537319
Short name T484
Test name
Test status
Simulation time 1915604901 ps
CPU time 28.26 seconds
Started Jul 28 07:16:58 PM PDT 24
Finished Jul 28 07:17:26 PM PDT 24
Peak memory 199556 kb
Host smart-38ffb307-ec04-418f-83c0-184acece8d75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914537319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1914537319
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3410599435
Short name T23
Test name
Test status
Simulation time 1938646287 ps
CPU time 52.63 seconds
Started Jul 28 07:17:01 PM PDT 24
Finished Jul 28 07:17:53 PM PDT 24
Peak memory 199736 kb
Host smart-ded540e3-21a4-4067-9886-93ec9d8e9e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410599435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3410599435
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.832328397
Short name T333
Test name
Test status
Simulation time 7265697005 ps
CPU time 275.6 seconds
Started Jul 28 07:16:58 PM PDT 24
Finished Jul 28 07:21:34 PM PDT 24
Peak memory 600996 kb
Host smart-4da847e8-747b-47cc-aeee-6f9a913abf65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832328397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.832328397
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1675302370
Short name T278
Test name
Test status
Simulation time 2230161470 ps
CPU time 124.53 seconds
Started Jul 28 07:17:00 PM PDT 24
Finished Jul 28 07:19:04 PM PDT 24
Peak memory 199728 kb
Host smart-944e0257-8e48-485f-bd29-9f3b1e2adece
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675302370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1675302370
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3678947504
Short name T340
Test name
Test status
Simulation time 1431535094 ps
CPU time 78.48 seconds
Started Jul 28 07:16:58 PM PDT 24
Finished Jul 28 07:18:16 PM PDT 24
Peak memory 199588 kb
Host smart-e57eb4a5-68c0-4d1c-bdd4-8b6d575e59be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678947504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3678947504
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2353049920
Short name T358
Test name
Test status
Simulation time 604895765 ps
CPU time 6.23 seconds
Started Jul 28 07:16:58 PM PDT 24
Finished Jul 28 07:17:05 PM PDT 24
Peak memory 199668 kb
Host smart-4377d6bf-996e-4fc2-ab6b-1decbdddd37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353049920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2353049920
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.48812886
Short name T322
Test name
Test status
Simulation time 57762706179 ps
CPU time 1107.32 seconds
Started Jul 28 07:16:59 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 620132 kb
Host smart-26436261-4e5f-44d7-a397-c890759d52f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48812886 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.48812886
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3171404533
Short name T99
Test name
Test status
Simulation time 679278856 ps
CPU time 27.24 seconds
Started Jul 28 07:17:00 PM PDT 24
Finished Jul 28 07:17:28 PM PDT 24
Peak memory 199708 kb
Host smart-f7eae5aa-312d-45ad-95d6-387f0f9583f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171404533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3171404533
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2154225862
Short name T33
Test name
Test status
Simulation time 28441291 ps
CPU time 0.62 seconds
Started Jul 28 07:17:09 PM PDT 24
Finished Jul 28 07:17:09 PM PDT 24
Peak memory 195588 kb
Host smart-5e36980f-c2e8-4055-812c-2609d05f6b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154225862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2154225862
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3832153441
Short name T417
Test name
Test status
Simulation time 3032230354 ps
CPU time 89.09 seconds
Started Jul 28 07:17:01 PM PDT 24
Finished Jul 28 07:18:30 PM PDT 24
Peak memory 199760 kb
Host smart-9f27fccf-86b0-4f3c-9a74-f70944e28cdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832153441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3832153441
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4121442384
Short name T362
Test name
Test status
Simulation time 2303157438 ps
CPU time 60.39 seconds
Started Jul 28 07:17:04 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 199684 kb
Host smart-ab9791ad-c75b-40c5-970a-4e89b66b45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121442384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4121442384
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3557485090
Short name T2
Test name
Test status
Simulation time 3071693274 ps
CPU time 498.84 seconds
Started Jul 28 07:17:03 PM PDT 24
Finished Jul 28 07:25:22 PM PDT 24
Peak memory 479392 kb
Host smart-3f80c87a-a505-4e07-8978-d74cc4a174be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557485090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3557485090
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.166314514
Short name T487
Test name
Test status
Simulation time 1631252318 ps
CPU time 8.43 seconds
Started Jul 28 07:17:05 PM PDT 24
Finished Jul 28 07:17:13 PM PDT 24
Peak memory 199576 kb
Host smart-75bd2acc-1f46-447f-bbc5-3800a7917628
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166314514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.166314514
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2757538175
Short name T394
Test name
Test status
Simulation time 8642197654 ps
CPU time 78.6 seconds
Started Jul 28 07:16:59 PM PDT 24
Finished Jul 28 07:18:18 PM PDT 24
Peak memory 199712 kb
Host smart-bee92758-347e-4373-b200-9c3ebf4350a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757538175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2757538175
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1409578547
Short name T96
Test name
Test status
Simulation time 103276429 ps
CPU time 1.57 seconds
Started Jul 28 07:16:59 PM PDT 24
Finished Jul 28 07:17:01 PM PDT 24
Peak memory 199640 kb
Host smart-e5ee7d3c-e800-4faf-af98-dd28259d26d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409578547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1409578547
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2763210427
Short name T289
Test name
Test status
Simulation time 23177450074 ps
CPU time 61.16 seconds
Started Jul 28 07:17:04 PM PDT 24
Finished Jul 28 07:18:05 PM PDT 24
Peak memory 199700 kb
Host smart-50242159-4cc8-4911-868f-bcd6b98c7e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763210427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2763210427
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2026973299
Short name T348
Test name
Test status
Simulation time 15329513 ps
CPU time 0.61 seconds
Started Jul 28 07:17:08 PM PDT 24
Finished Jul 28 07:17:08 PM PDT 24
Peak memory 196332 kb
Host smart-4711990b-5c00-4be0-a342-e3a613c74d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026973299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2026973299
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4120951604
Short name T471
Test name
Test status
Simulation time 126630593 ps
CPU time 3.65 seconds
Started Jul 28 07:17:08 PM PDT 24
Finished Jul 28 07:17:12 PM PDT 24
Peak memory 199684 kb
Host smart-0637cb73-6860-431c-ac23-c21cc4f7aab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120951604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4120951604
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3894457862
Short name T301
Test name
Test status
Simulation time 3046754692 ps
CPU time 31.69 seconds
Started Jul 28 07:17:09 PM PDT 24
Finished Jul 28 07:17:40 PM PDT 24
Peak memory 199732 kb
Host smart-13b9ea5d-2cff-45ef-b687-25f6ff9d075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894457862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3894457862
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.915141078
Short name T175
Test name
Test status
Simulation time 5268258165 ps
CPU time 745.54 seconds
Started Jul 28 07:17:07 PM PDT 24
Finished Jul 28 07:29:33 PM PDT 24
Peak memory 687548 kb
Host smart-3d021049-abe4-46e2-bdd9-712d0a980309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915141078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.915141078
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.296490725
Short name T223
Test name
Test status
Simulation time 15152526939 ps
CPU time 48.72 seconds
Started Jul 28 07:17:09 PM PDT 24
Finished Jul 28 07:17:58 PM PDT 24
Peak memory 199756 kb
Host smart-02662a13-f7b4-4d4f-86a5-48ef22ebf88d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296490725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.296490725
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3980278431
Short name T308
Test name
Test status
Simulation time 2131537020 ps
CPU time 119.53 seconds
Started Jul 28 07:17:10 PM PDT 24
Finished Jul 28 07:19:09 PM PDT 24
Peak memory 199600 kb
Host smart-620297a0-7fa3-4773-a045-5b7b5ef025e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980278431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3980278431
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3525903521
Short name T265
Test name
Test status
Simulation time 12882354131 ps
CPU time 12.58 seconds
Started Jul 28 07:17:07 PM PDT 24
Finished Jul 28 07:17:20 PM PDT 24
Peak memory 199668 kb
Host smart-f3b6fd94-3d5f-4c85-9cca-638ff83b0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525903521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3525903521
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2309899799
Short name T88
Test name
Test status
Simulation time 109472359936 ps
CPU time 2410.57 seconds
Started Jul 28 07:17:11 PM PDT 24
Finished Jul 28 07:57:22 PM PDT 24
Peak memory 777212 kb
Host smart-4a75fb79-e7a5-493d-8a94-68ae96f1c9a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309899799 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2309899799
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.950146730
Short name T68
Test name
Test status
Simulation time 34085507472 ps
CPU time 31.03 seconds
Started Jul 28 07:17:07 PM PDT 24
Finished Jul 28 07:17:39 PM PDT 24
Peak memory 199724 kb
Host smart-47a822e1-c7d1-4fb5-aef1-0c131d2c8d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950146730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.950146730
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1366045994
Short name T445
Test name
Test status
Simulation time 10293988 ps
CPU time 0.55 seconds
Started Jul 28 07:14:16 PM PDT 24
Finished Jul 28 07:14:16 PM PDT 24
Peak memory 195304 kb
Host smart-2c620779-06c3-4435-8912-737d025a6103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366045994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1366045994
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.4005492748
Short name T227
Test name
Test status
Simulation time 12374869206 ps
CPU time 41.97 seconds
Started Jul 28 07:14:12 PM PDT 24
Finished Jul 28 07:14:54 PM PDT 24
Peak memory 199728 kb
Host smart-cfed71d9-d14d-493f-b187-296d42b7725d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005492748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.4005492748
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1323857633
Short name T196
Test name
Test status
Simulation time 857191226 ps
CPU time 15.38 seconds
Started Jul 28 07:14:15 PM PDT 24
Finished Jul 28 07:14:30 PM PDT 24
Peak memory 199616 kb
Host smart-a5fb6d12-664a-40d1-bc8b-1d8ada0e830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323857633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1323857633
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.652781694
Short name T482
Test name
Test status
Simulation time 95703582 ps
CPU time 0.94 seconds
Started Jul 28 07:14:19 PM PDT 24
Finished Jul 28 07:14:20 PM PDT 24
Peak memory 199508 kb
Host smart-91d17020-7724-4623-a49f-09831e544177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652781694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.652781694
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3152351045
Short name T138
Test name
Test status
Simulation time 7810980096 ps
CPU time 91.28 seconds
Started Jul 28 07:14:16 PM PDT 24
Finished Jul 28 07:15:48 PM PDT 24
Peak memory 199700 kb
Host smart-cccd3c2b-70eb-43c0-91bc-6117809cec8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152351045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3152351045
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3967960932
Short name T224
Test name
Test status
Simulation time 47523451646 ps
CPU time 133.73 seconds
Started Jul 28 07:14:11 PM PDT 24
Finished Jul 28 07:16:25 PM PDT 24
Peak memory 215880 kb
Host smart-3524c13e-5c1a-4674-9ff5-c787ae3a4aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967960932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3967960932
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3735051289
Short name T401
Test name
Test status
Simulation time 1351952622 ps
CPU time 15.21 seconds
Started Jul 28 07:14:09 PM PDT 24
Finished Jul 28 07:14:24 PM PDT 24
Peak memory 199652 kb
Host smart-9f4ee9af-f1e4-4813-9a90-a022e4b4aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735051289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3735051289
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3377635496
Short name T11
Test name
Test status
Simulation time 67943746245 ps
CPU time 709.19 seconds
Started Jul 28 07:14:15 PM PDT 24
Finished Jul 28 07:26:04 PM PDT 24
Peak memory 685276 kb
Host smart-cb71e5ff-f139-4569-ac61-004e10718494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3377635496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3377635496
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2473591805
Short name T284
Test name
Test status
Simulation time 9008637974 ps
CPU time 40.09 seconds
Started Jul 28 07:14:15 PM PDT 24
Finished Jul 28 07:14:55 PM PDT 24
Peak memory 199764 kb
Host smart-b07111c1-8c25-4a81-b99a-682accc36941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473591805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2473591805
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4115747056
Short name T238
Test name
Test status
Simulation time 14682586 ps
CPU time 0.62 seconds
Started Jul 28 07:14:20 PM PDT 24
Finished Jul 28 07:14:21 PM PDT 24
Peak memory 196268 kb
Host smart-ec671647-ae31-415a-b224-4be05b6ec80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115747056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4115747056
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.331084852
Short name T217
Test name
Test status
Simulation time 828792896 ps
CPU time 44.94 seconds
Started Jul 28 07:14:16 PM PDT 24
Finished Jul 28 07:15:01 PM PDT 24
Peak memory 199640 kb
Host smart-d0840ef4-02f6-405d-8395-c7a1e38f4dd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331084852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.331084852
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1211419820
Short name T404
Test name
Test status
Simulation time 3822681365 ps
CPU time 35.38 seconds
Started Jul 28 07:14:15 PM PDT 24
Finished Jul 28 07:14:50 PM PDT 24
Peak memory 199696 kb
Host smart-0917e2f9-b128-4416-b129-92934bc4139d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211419820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1211419820
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1605181479
Short name T61
Test name
Test status
Simulation time 2276654872 ps
CPU time 235.5 seconds
Started Jul 28 07:14:17 PM PDT 24
Finished Jul 28 07:18:12 PM PDT 24
Peak memory 489040 kb
Host smart-9bab1cd9-8a58-4f00-b9a5-442ab9117d2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605181479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1605181479
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3787324475
Short name T377
Test name
Test status
Simulation time 18326447248 ps
CPU time 173.74 seconds
Started Jul 28 07:14:14 PM PDT 24
Finished Jul 28 07:17:08 PM PDT 24
Peak memory 199696 kb
Host smart-0fc9faf2-8b49-49ba-9e3b-1faa49875101
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787324475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3787324475
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3233380869
Short name T361
Test name
Test status
Simulation time 17042928913 ps
CPU time 147.7 seconds
Started Jul 28 07:14:15 PM PDT 24
Finished Jul 28 07:16:43 PM PDT 24
Peak memory 199692 kb
Host smart-e39e77b3-bf6f-489b-a465-118e24c504b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233380869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3233380869
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4034094293
Short name T467
Test name
Test status
Simulation time 421943117 ps
CPU time 7.09 seconds
Started Jul 28 07:14:16 PM PDT 24
Finished Jul 28 07:14:24 PM PDT 24
Peak memory 199628 kb
Host smart-f742123d-2ce2-4ed5-80c0-b1ffd116dc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034094293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4034094293
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1332336225
Short name T207
Test name
Test status
Simulation time 142919369455 ps
CPU time 2368.02 seconds
Started Jul 28 07:14:14 PM PDT 24
Finished Jul 28 07:53:43 PM PDT 24
Peak memory 762832 kb
Host smart-80179f08-d6c9-42a2-8090-0816085df379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332336225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1332336225
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1863621660
Short name T161
Test name
Test status
Simulation time 4316377725 ps
CPU time 77.88 seconds
Started Jul 28 07:14:17 PM PDT 24
Finished Jul 28 07:15:35 PM PDT 24
Peak memory 199772 kb
Host smart-febb95f0-96c1-4a3d-89c3-7e152a4b829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863621660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1863621660
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2789824311
Short name T315
Test name
Test status
Simulation time 12521658 ps
CPU time 0.57 seconds
Started Jul 28 07:14:20 PM PDT 24
Finished Jul 28 07:14:21 PM PDT 24
Peak memory 195672 kb
Host smart-3df568a4-c2fe-44a3-84d7-dfae8eb0b222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789824311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2789824311
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1309383012
Short name T508
Test name
Test status
Simulation time 453541438 ps
CPU time 22.44 seconds
Started Jul 28 07:14:19 PM PDT 24
Finished Jul 28 07:14:41 PM PDT 24
Peak memory 199608 kb
Host smart-be25d26a-22fa-471a-81bf-a7cea8c425c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309383012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1309383012
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3329567852
Short name T389
Test name
Test status
Simulation time 8889299041 ps
CPU time 59.03 seconds
Started Jul 28 07:14:21 PM PDT 24
Finished Jul 28 07:15:20 PM PDT 24
Peak memory 207968 kb
Host smart-423a319a-0375-4ed4-8fc1-cce24cbe575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329567852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3329567852
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.924684561
Short name T387
Test name
Test status
Simulation time 39177549335 ps
CPU time 768.71 seconds
Started Jul 28 07:14:18 PM PDT 24
Finished Jul 28 07:27:06 PM PDT 24
Peak memory 692736 kb
Host smart-776cd886-3caa-40fa-bc6f-19fabd7c470a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924684561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.924684561
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.678770596
Short name T182
Test name
Test status
Simulation time 9637449081 ps
CPU time 121.13 seconds
Started Jul 28 07:14:22 PM PDT 24
Finished Jul 28 07:16:24 PM PDT 24
Peak memory 199640 kb
Host smart-f076856d-cb30-4341-aa4e-786e53bd5030
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678770596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.678770596
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3348749051
Short name T418
Test name
Test status
Simulation time 16492762354 ps
CPU time 206.38 seconds
Started Jul 28 07:14:20 PM PDT 24
Finished Jul 28 07:17:46 PM PDT 24
Peak memory 216104 kb
Host smart-bbbedfb9-ae24-40f8-a7f5-99503554ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348749051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3348749051
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2116653272
Short name T500
Test name
Test status
Simulation time 607983174 ps
CPU time 7.89 seconds
Started Jul 28 07:14:22 PM PDT 24
Finished Jul 28 07:14:30 PM PDT 24
Peak memory 199620 kb
Host smart-abdda331-13c8-4bbf-8347-ebced6119f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116653272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2116653272
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3077558771
Short name T342
Test name
Test status
Simulation time 178586358945 ps
CPU time 1012.25 seconds
Started Jul 28 07:14:22 PM PDT 24
Finished Jul 28 07:31:15 PM PDT 24
Peak memory 692396 kb
Host smart-2536f4b4-125c-4f10-a17e-bc0a0c896f05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077558771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3077558771
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.798621006
Short name T17
Test name
Test status
Simulation time 58937074084 ps
CPU time 904.96 seconds
Started Jul 28 07:14:21 PM PDT 24
Finished Jul 28 07:29:26 PM PDT 24
Peak memory 216080 kb
Host smart-1224089d-2af0-4c60-9692-59d2874afef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798621006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.798621006
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1622705283
Short name T293
Test name
Test status
Simulation time 4151513242 ps
CPU time 71.82 seconds
Started Jul 28 07:14:19 PM PDT 24
Finished Jul 28 07:15:31 PM PDT 24
Peak memory 199696 kb
Host smart-0b9699c2-d3a5-4f5f-aed4-2fbf184f0a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622705283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1622705283
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.784791900
Short name T77
Test name
Test status
Simulation time 13266794 ps
CPU time 0.58 seconds
Started Jul 28 07:14:25 PM PDT 24
Finished Jul 28 07:14:25 PM PDT 24
Peak memory 195400 kb
Host smart-ae4ebde6-4899-4edf-a8a8-824f6596db94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784791900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.784791900
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2665237326
Short name T415
Test name
Test status
Simulation time 1611651684 ps
CPU time 96.87 seconds
Started Jul 28 07:14:27 PM PDT 24
Finished Jul 28 07:16:04 PM PDT 24
Peak memory 199648 kb
Host smart-a3ecd6b0-b503-4ed5-93cd-529370e5aa54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665237326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2665237326
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1835358976
Short name T148
Test name
Test status
Simulation time 1040253464 ps
CPU time 25.38 seconds
Started Jul 28 07:14:24 PM PDT 24
Finished Jul 28 07:14:50 PM PDT 24
Peak memory 199628 kb
Host smart-608a89d6-3a3c-411f-8201-e23c40a3fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835358976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1835358976
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1787130073
Short name T319
Test name
Test status
Simulation time 3220262292 ps
CPU time 606.96 seconds
Started Jul 28 07:14:27 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 618224 kb
Host smart-7e3496e4-77e9-45c8-b648-35260a53a83f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787130073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1787130073
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2711444605
Short name T339
Test name
Test status
Simulation time 595851120 ps
CPU time 32.94 seconds
Started Jul 28 07:14:23 PM PDT 24
Finished Jul 28 07:14:56 PM PDT 24
Peak memory 199864 kb
Host smart-46dbae5f-52df-45d7-9d3d-eadb3f642ede
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711444605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2711444605
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3810814173
Short name T79
Test name
Test status
Simulation time 15672467624 ps
CPU time 134.13 seconds
Started Jul 28 07:14:21 PM PDT 24
Finished Jul 28 07:16:35 PM PDT 24
Peak memory 199692 kb
Host smart-2a66a3fd-c9a0-4cdc-ae5a-45215312a162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810814173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3810814173
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1131928804
Short name T190
Test name
Test status
Simulation time 323021491 ps
CPU time 14.01 seconds
Started Jul 28 07:14:20 PM PDT 24
Finished Jul 28 07:14:34 PM PDT 24
Peak memory 199692 kb
Host smart-f95cd904-081f-41c9-b103-65f2e86cd9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131928804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1131928804
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3780456695
Short name T242
Test name
Test status
Simulation time 105320352842 ps
CPU time 266.52 seconds
Started Jul 28 07:14:24 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 216160 kb
Host smart-55de52c2-8b7a-42cf-9bd2-11a1c0c62705
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780456695 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3780456695
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.994617612
Short name T73
Test name
Test status
Simulation time 937118561779 ps
CPU time 3638.83 seconds
Started Jul 28 07:14:26 PM PDT 24
Finished Jul 28 08:15:05 PM PDT 24
Peak memory 781672 kb
Host smart-836a5877-d519-4fdd-ba1b-708a06c808b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994617612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.994617612
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2443565434
Short name T408
Test name
Test status
Simulation time 21525698017 ps
CPU time 168.65 seconds
Started Jul 28 07:14:28 PM PDT 24
Finished Jul 28 07:17:17 PM PDT 24
Peak memory 199716 kb
Host smart-fbd31c24-6295-4193-a97b-e4967e3d4652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443565434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2443565434
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1536761466
Short name T20
Test name
Test status
Simulation time 55515619 ps
CPU time 0.58 seconds
Started Jul 28 07:14:30 PM PDT 24
Finished Jul 28 07:14:31 PM PDT 24
Peak memory 195664 kb
Host smart-12ebb8be-c3eb-49a5-9289-e99d735c3f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536761466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1536761466
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.104974996
Short name T27
Test name
Test status
Simulation time 5638387678 ps
CPU time 22.12 seconds
Started Jul 28 07:14:28 PM PDT 24
Finished Jul 28 07:14:51 PM PDT 24
Peak memory 199760 kb
Host smart-6dad5048-4446-46e2-82a9-a84707f45e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104974996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.104974996
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.385642707
Short name T316
Test name
Test status
Simulation time 3387280866 ps
CPU time 42.93 seconds
Started Jul 28 07:14:32 PM PDT 24
Finished Jul 28 07:15:15 PM PDT 24
Peak memory 199656 kb
Host smart-eee4517f-3634-4589-a97f-46fb5fa2ec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385642707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.385642707
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3925226207
Short name T437
Test name
Test status
Simulation time 13296565907 ps
CPU time 634.69 seconds
Started Jul 28 07:14:33 PM PDT 24
Finished Jul 28 07:25:07 PM PDT 24
Peak memory 719716 kb
Host smart-8c595be0-8970-44f6-9c2f-159e75a762a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925226207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3925226207
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.911826024
Short name T279
Test name
Test status
Simulation time 2210066818 ps
CPU time 29.87 seconds
Started Jul 28 07:14:30 PM PDT 24
Finished Jul 28 07:15:00 PM PDT 24
Peak memory 199664 kb
Host smart-71c539f7-7988-4356-b03b-7aca95d16277
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911826024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.911826024
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2539140718
Short name T177
Test name
Test status
Simulation time 1401746915 ps
CPU time 85.29 seconds
Started Jul 28 07:14:28 PM PDT 24
Finished Jul 28 07:15:54 PM PDT 24
Peak memory 199676 kb
Host smart-133592b9-9fed-4ba2-a9fb-82051bd3b951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539140718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2539140718
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2543272473
Short name T272
Test name
Test status
Simulation time 2517330211 ps
CPU time 7.12 seconds
Started Jul 28 07:14:25 PM PDT 24
Finished Jul 28 07:14:32 PM PDT 24
Peak memory 199720 kb
Host smart-b86049d8-4bf3-455a-b2ce-9ec5da83094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543272473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2543272473
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1778772690
Short name T60
Test name
Test status
Simulation time 44795634079 ps
CPU time 1030.63 seconds
Started Jul 28 07:14:32 PM PDT 24
Finished Jul 28 07:31:43 PM PDT 24
Peak memory 647900 kb
Host smart-d2b5f034-d6e8-4593-bd2b-1cdd498c1e4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778772690 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1778772690
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2845344257
Short name T72
Test name
Test status
Simulation time 357466447723 ps
CPU time 1890.17 seconds
Started Jul 28 07:14:30 PM PDT 24
Finished Jul 28 07:46:00 PM PDT 24
Peak memory 690012 kb
Host smart-f0f2c62e-a389-493f-8d16-cd230266cb09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845344257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2845344257
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1747091539
Short name T92
Test name
Test status
Simulation time 2083058133 ps
CPU time 41.18 seconds
Started Jul 28 07:14:32 PM PDT 24
Finished Jul 28 07:15:13 PM PDT 24
Peak memory 199624 kb
Host smart-53ca0a08-21f7-4ab1-afdd-953f30fabc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747091539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1747091539
Directory /workspace/9.hmac_wipe_secret/latest
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