Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19993734	1			T1	26334		T2	3334		T3	10785
all_values[1]	19993734	1			T1	26334		T2	3334		T3	10785
all_values[2]	19993734	1			T1	26334		T2	3334		T3	10785

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279089

1

T3

1451

T15

2

T12

657

auto[1]

59702113

1

T1

79002

T2

10002

T3

30904

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51038859

1

T1

62476

T2

8796

T3

30544

auto[1]

8942343

1

T1

16526

T2

1206

T3

1811

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85440	1			T21	800		T45	42		T39	410
all_values[0]	auto[0]	auto[1]	414	1			T45	2		T7	3		T5	2
all_values[0]	auto[1]	auto[0]	19886289	1			T1	26329		T2	3299		T3	10767
all_values[0]	auto[1]	auto[1]	21591	1			T1	5		T2	35		T3	18
all_values[1]	auto[0]	auto[0]	101702	1			T15	2		T21	800		T45	96
all_values[1]	auto[0]	auto[1]	234	1			T7	2		T34	3		T64	3
all_values[1]	auto[1]	auto[0]	19891426	1			T1	26334		T2	3334		T3	10785
all_values[1]	auto[1]	auto[1]	372	1			T7	1		T34	3		T64	2
all_values[2]	auto[0]	auto[0]	50598	1			T3	1451		T12	657		T7	2
all_values[2]	auto[0]	auto[1]	40701	1			T7	2		T90	2		T34	1212
all_values[2]	auto[1]	auto[0]	11023404	1			T1	9813		T2	2163		T3	7541
all_values[2]	auto[1]	auto[1]	8879031	1			T1	16521		T2	1171		T3	1793