Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

153700

1

T1

24

T2

1754

T3

14

auto[1]

141122

1

T1

20

T2

1088

T3

10

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	114445	1			T1	12		T2	1001		T3	12
len_1026_2046	5854	1			T2	29		T4	11		T12	1
len_514_1022	4556	1			T2	88		T4	4		T15	1
len_2_510	3596	1			T2	12		T4	3		T15	1
len_2056	246	1			T8	1		T46	7		T140	6
len_2048	366	1			T1	5		T2	1		T4	1
len_2040	376	1			T46	3		T35	4		T141	2
len_1032	263	1			T34	1		T35	1		T140	4
len_1024	1787	1			T2	3		T86	1		T34	5
len_1016	248	1			T8	1		T34	3		T46	2
len_520	370	1			T34	2		T142	2		T35	4
len_512	398	1			T2	3		T4	1		T15	1
len_504	849	1			T15	1		T5	2		T143	1
len_8	1332	1			T7	7		T90	3		T34	6
len_0	12726	1			T1	5		T2	284		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

116

1

T39

1

T5

2

T128

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	60194	1			T1	7		T2	761		T3	7
auto[0]	len_1026_2046	3429	1			T2	19		T4	10		T12	1
auto[0]	len_514_1022	3219	1			T2	13		T4	3		T15	1
auto[0]	len_2_510	2354	1			T2	9		T4	2		T63	2
auto[0]	len_2056	126	1			T8	1		T46	5		T140	3
auto[0]	len_2048	228	1			T1	3		T2	1		T39	2
auto[0]	len_2040	111	1			T46	3		T35	2		T22	3
auto[0]	len_1032	146	1			T34	1		T35	1		T140	2
auto[0]	len_1024	296	1			T2	3		T86	1		T34	5
auto[0]	len_1016	135	1			T8	1		T34	2		T46	2
auto[0]	len_520	254	1			T34	1		T142	2		T35	4
auto[0]	len_512	236	1			T2	2		T15	1		T45	2
auto[0]	len_504	618	1			T15	1		T5	2		T143	1
auto[0]	len_8	23	1			T142	1		T143	1		T129	5
auto[0]	len_0	5482	1			T1	2		T2	69		T4	1
auto[1]	len_2050_plus	54251	1			T1	5		T2	240		T3	5
auto[1]	len_1026_2046	2425	1			T2	10		T4	1		T45	2
auto[1]	len_514_1022	1337	1			T2	75		T4	1		T45	1
auto[1]	len_2_510	1242	1			T2	3		T4	1		T15	1
auto[1]	len_2056	120	1			T46	2		T140	3		T141	2
auto[1]	len_2048	138	1			T1	2		T4	1		T34	2
auto[1]	len_2040	265	1			T35	2		T141	2		T22	2
auto[1]	len_1032	117	1			T140	2		T92	2		T99	3
auto[1]	len_1024	1491	1			T128	1		T46	2		T35	1
auto[1]	len_1016	113	1			T34	1		T141	1		T22	3
auto[1]	len_520	116	1			T34	1		T22	2		T80	1
auto[1]	len_512	162	1			T2	1		T4	1		T34	2
auto[1]	len_504	231	1			T35	1		T22	1		T129	1
auto[1]	len_8	1309	1			T7	7		T90	3		T34	6
auto[1]	len_0	7244	1			T1	3		T2	215		T15	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

57

1

T39

1

T5

2

T144

1

auto[1]

len_upper

59

1

T128

1

T22

4

T145

3