Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4937734

1

T1

1992

T2

3430

T3

2113

auto[1]

3245471

1

T1

5015

T2

2289

T3

3266

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3231353

1

T1

3166

T2

580

T3

1126

auto[1]

4951852

1

T1

3841

T2

5139

T3

4253

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3609658

1

T1

5047

T2

3496

T3

3966

auto[1]

4573547

1

T1

1960

T2

2223

T3

1413

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4972379

1

T1

4688

T2

3216

T3

2026

auto[1]

3210826

1

T1

2319

T2

2503

T3

3353

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	7385070	1			T1	6916		T2	5405		T3	4297
fifo_depth[1]	129643	1			T1	70		T2	77		T3	184
fifo_depth[2]	98577	1			T1	21		T2	101		T3	195
fifo_depth[3]	77519	1			T2	53		T3	162		T4	44
fifo_depth[4]	71575	1			T2	56		T3	177		T4	65
fifo_depth[5]	55767	1			T2	11		T3	154		T4	63
fifo_depth[6]	45125	1			T2	12		T3	108		T4	59
fifo_depth[7]	29620	1			T2	1		T3	56		T4	64

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

798135

1

T1

91

T2

314

T3

1082

auto[1]

7385070

1

T1

6916

T2

5405

T3

4297

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8170004

1

T1

7007

T2

5719

T3

5379

auto[1]

13201

1

T4

82

T23

321

T129

411

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

36560

1

T12

1

T13

1

T63

303

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

32322

1

T3

102

T12

1

T14

331

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

35987

1

T1

1

T2

4

T4

1716

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

39203

1

T2

23

T3

210

T4

145

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

168478

1

T2

113

T3

151

T12

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

32174

1

T2

55

T3

105

T12

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43027

1

T1

61

T2

15

T3

116

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

35749

1

T2

17

T3

240

T14

507

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49288

1

T4

91

T63

68

T39

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43781

1

T2

2

T20

1

T39

14

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50229

1

T2

4

T12

1

T45

25

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

50004

1

T1

14

T8

338

T89

373

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46018

1

T2

9

T3

67

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

47794

1

T2

19

T15

8

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44020

1

T1

15

T2

7

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

43501

1

T2

46

T3

91

T63

341

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

200182

1

T1

2

T2

39

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

192466

1

T1

1723

T2

78

T3

358

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

211090

1

T1

1010

T2

63

T4

38

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

222007

1

T2

133

T3

456

T4

40

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1756384

1

T1

7

T2

1529

T3

516

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

200182

1

T1

1

T2

574

T3

366

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

206308

1

T1

2242

T2

409

T3

753

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

197539

1

T2

444

T3

593

T14

1044

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

522102

1

T1

45

T2

35

T4

22

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

494093

1

T1

2

T2

112

T15

12

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

525715

1

T1

2

T2

87

T15

43

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

526324

1

T1

367

T4

42

T15

29

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

549805

1

T1

1

T2

142

T3

243

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

566105

1

T1

211

T2

723

T3

205

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

527186

1

T1

1302

T2

760

T3

180

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

487582

1

T1

1

T2

277

T3

627

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

236054

1

T1

2

T2

39

T12

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

224133

1

T1

1723

T2

78

T3

460

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

246378

1

T1

1011

T2

67

T4

1685

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

260769

1

T2

156

T3

666

T4

185

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1923949

1

T1

7

T2

1642

T3

667

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

230971

1

T1

1

T2

629

T3

471

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

246830

1

T1

2303

T2

424

T3

869

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

231234

1

T2

461

T3

833

T14

1551

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

570854

1

T1

45

T2

35

T4

100

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

537627

1

T1

2

T2

114

T20

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

575430

1

T1

2

T2

91

T15

43

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

575927

1

T1

381

T4

42

T15

29

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

595516

1

T1

1

T2

151

T3

310

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

613479

1

T1

211

T2

742

T3

205

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

570548

1

T1

1317

T2

767

T3

180

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

530305

1

T1

1

T2

323

T3

718

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

688

1

T23

146

T129

109

T144

88

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

655

1

T129

2

T146

1

T147

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

699

1

T4

69

T129

18

T144

23

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

441

1

T23

1

T129

7

T144

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

913

1

T23

29

T129

110

T144

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1385

1

T129

50

T146

546

T147

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2505

1

T129

87

T147

72

T148

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2054

1

T129

12

T146

65

T74

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

536

1

T4

13

T129

8

T146

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

247

1

T11

5

T149

64

T36

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

514

1

T144

20

T146

28

T150

233

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

401

1

T23

8

T74

28

T147

19

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

307

1

T129

8

T144

11

T150

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

420

1

T11

3

T149

94

T148

44

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

658

1

T11

100

T148

44

T151

70

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

778

1

T23

137

T144

50

T74

26

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

200182

1

T1

2

T2

39

T12

2

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

192466

1

T1

1723

T2

78

T3

358

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

211090

1

T1

1010

T2

63

T4

38

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

222007

1

T2

133

T3

456

T4

40

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1756384

1

T1

7

T2

1529

T3

516

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

200182

1

T1

1

T2

574

T3

366

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

206308

1

T1

2242

T2

409

T3

753

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

197539

1

T2

444

T3

593

T14

1044

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

522102

1

T1

45

T2

35

T4

22

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

494093

1

T1

2

T2

112

T15

12

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

525715

1

T1

2

T2

87

T15

43

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

526324

1

T1

367

T4

42

T15

29

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

549805

1

T1

1

T2

142

T3

243

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

566105

1

T1

211

T2

723

T3

205

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

527186

1

T1

1302

T2

760

T3

180

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

487582

1

T1

1

T2

277

T3

627

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3968

1

T63

46

T39

4

T7

20

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3812

1

T3

14

T14

85

T21

12

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4321

1

T1

1

T2

1

T4

10

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4875

1

T2

1

T3

32

T4

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

41833

1

T2

34

T3

25

T45

4

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4092

1

T2

11

T3

18

T21

37

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4327

1

T1

54

T2

1

T3

21

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

4067

1

T2

6

T3

39

T14

89

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

7318

1

T63

10

T39

3

T7

19

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6295

1

T20

1

T39

9

T8

17

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6661

1

T2

1

T45

6

T7

93

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

7845

1

T1

9

T8

47

T89

62

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8698

1

T2

2

T3

12

T63

115

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7851

1

T2

11

T15

1

T63

32

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6583

1

T1

6

T63

30

T7

100

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

7097

1

T2

9

T3

23

T63

65

fifo_depth[2]

auto[0]

auto[0]

auto[0]

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43

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66

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6

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56

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36

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30

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13

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18

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33

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45

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4

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4

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59

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54

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1

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5

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57

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15

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7

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1

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30

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16

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21

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7

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7

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7

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13

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3

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30

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21

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11

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27

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20

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10

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12

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1

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7

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15

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16

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21

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9