Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19993734	1			T1	26334		T2	3334		T3	10785
all_pins[1]	19993734	1			T1	26334		T2	3334		T3	10785
all_pins[2]	19993734	1			T1	26334		T2	3334		T3	10785

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51079319	1			T1	62476		T2	8795		T3	30543
values[0x1]	8901883	1			T1	16526		T2	1207		T3	1812
transitions[0x0=>0x1]	8901661	1			T1	16526		T2	1207		T3	1812
transitions[0x1=>0x0]	8901671	1			T1	16526		T2	1207		T3	1812

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19971284	1			T1	26329		T2	3298		T3	10766
all_pins[0]	values[0x1]	22450	1			T1	5		T2	36		T3	19
all_pins[0]	transitions[0x0=>0x1]	22366	1			T1	5		T2	36		T3	19
all_pins[0]	transitions[0x1=>0x0]	8878957	1			T1	16521		T2	1171		T3	1793
all_pins[1]	values[0x0]	19993332	1			T1	26334		T2	3334		T3	10785
all_pins[1]	values[0x1]	402	1			T7	1		T34	3		T64	2
all_pins[1]	transitions[0x0=>0x1]	333	1			T7	1		T34	1		T64	1
all_pins[1]	transitions[0x1=>0x0]	22381	1			T1	5		T2	36		T3	19
all_pins[2]	values[0x0]	11114703	1			T1	9813		T2	2163		T3	8992
all_pins[2]	values[0x1]	8879031	1			T1	16521		T2	1171		T3	1793
all_pins[2]	transitions[0x0=>0x1]	8878962	1			T1	16521		T2	1171		T3	1793
all_pins[2]	transitions[0x1=>0x0]	333	1			T7	1		T34	2		T23	4