Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1081 1 T7 4 T34 14 T64 10
all_values[1] 1081 1 T7 4 T34 14 T64 10
all_values[2] 1081 1 T7 4 T34 14 T64 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1633 1 T7 7 T34 19 T64 7
auto[1] 1610 1 T7 5 T34 23 T64 23


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1096 1 T7 4 T34 16 T64 8
auto[1] 2147 1 T7 8 T34 26 T64 22


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1827 1 T7 7 T34 24 T64 17
auto[1] 1416 1 T7 5 T34 18 T64 13


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 186 1 T34 4 T64 1 T80 2
all_values[0] auto[0] auto[0] auto[1] 117 1 T34 1 T64 2 T80 1
all_values[0] auto[0] auto[1] auto[0] 188 1 T7 2 T34 2 T64 2
all_values[0] auto[0] auto[1] auto[1] 112 1 T7 1 T34 1 T64 1
all_values[0] auto[1] auto[0] auto[1] 247 1 T7 1 T34 2 T64 2
all_values[0] auto[1] auto[1] auto[1] 231 1 T34 4 T64 2 T80 4
all_values[1] auto[0] auto[0] auto[0] 158 1 T34 1 T80 2 T81 1
all_values[1] auto[0] auto[0] auto[1] 144 1 T7 1 T34 3 T64 1
all_values[1] auto[0] auto[1] auto[0] 167 1 T34 3 T64 2 T80 1
all_values[1] auto[0] auto[1] auto[1] 133 1 T34 1 T64 2 T80 2
all_values[1] auto[1] auto[0] auto[1] 223 1 T7 2 T34 1 T129 7
all_values[1] auto[1] auto[1] auto[1] 256 1 T7 1 T34 5 T64 5
all_values[2] auto[0] auto[0] auto[0] 203 1 T7 1 T34 4 T80 6
all_values[2] auto[0] auto[0] auto[1] 131 1 T7 1 T34 1 T64 1
all_values[2] auto[0] auto[1] auto[0] 194 1 T7 1 T34 2 T64 3
all_values[2] auto[0] auto[1] auto[1] 94 1 T34 1 T64 2 T80 1
all_values[2] auto[1] auto[0] auto[1] 224 1 T7 1 T34 2 T129 10
all_values[2] auto[1] auto[1] auto[1] 235 1 T34 4 T64 4 T80 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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