Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4907	1			T1	10		T2	7		T3	2
sha2_none	4799	1			T1	2		T2	7		T3	2
sha2_512	8298	1			T1	5		T2	12		T3	7
sha2_384	8011	1			T1	7		T2	9		T3	3
sha2_256	7252	1			T1	5		T2	15		T3	3

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20522

1

T1

15

T2

27

T3

6

auto[1]

13195

1

T1

15

T2

24

T3

11

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13134

1

T1

13

T2

15

T3

4

auto[1]

20583

1

T1

17

T2

36

T3

13

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17557

1

T1

15

T2

24

T3

5

disabled

16160

1

T1

15

T2

27

T3

12

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5481	1			T1	9		T2	10		T3	2
key_none	8386	1			T2	9		T3	2		T4	3
key_1024	4859	1			T1	3		T2	7		T3	3
key_512	4219	1			T1	2		T2	4		T3	3
key_384	3819	1			T1	6		T2	5		T20	1
key_256	3480	1			T1	5		T2	10		T3	3
key_128	3383	1			T1	5		T2	6		T3	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20679

1

T1

19

T2

26

T3

6

auto[1]

13038

1

T1

11

T2

25

T3

11

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

33435

1

T1

28

T2

51

T3

17

disabled

282

1

T1

2

T8

3

T40

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1882

1

T1

3

T2

1

T4

2

enabled

auto[0]

auto[0]

auto[1]

1811

1

T1

1

T2

2

T20

1

enabled

auto[0]

auto[1]

auto[0]

1876

1

T2

3

T15

1

T12

4

enabled

auto[0]

auto[1]

auto[1]

1845

1

T1

2

T4

1

T15

2

enabled

auto[1]

auto[0]

auto[0]

4467

1

T1

1

T2

3

T3

1

enabled

auto[1]

auto[0]

auto[1]

1897

1

T1

3

T2

5

T3

1

enabled

auto[1]

auto[1]

auto[0]

1958

1

T1

4

T2

6

T3

1

enabled

auto[1]

auto[1]

auto[1]

1821

1

T1

1

T2

4

T3

2

disabled

auto[0]

auto[0]

auto[0]

1413

1

T1

1

T2

2

T12

3

disabled

auto[0]

auto[0]

auto[1]

1412

1

T1

3

T2

1

T3

1

disabled

auto[0]

auto[1]

auto[0]

1407

1

T1

3

T2

2

T4

3

disabled

auto[0]

auto[1]

auto[1]

1488

1

T2

4

T3

3

T4

2

disabled

auto[1]

auto[0]

auto[0]

6246

1

T1

2

T2

6

T3

2

disabled

auto[1]

auto[0]

auto[1]

1394

1

T1

1

T2

7

T3

1

disabled

auto[1]

auto[1]

auto[0]

1430

1

T1

5

T2

3

T3

2

disabled

auto[1]

auto[1]

auto[1]

1370

1

T2

2

T3

3

T14

4

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17453

1

T1

14

T2

24

T3

5

enabled

disabled

104

1

T1

1

T8

1

T34

7

disabled

disabled

178

1

T1

1

T8

2

T40

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15982

1

T1

14

T2

27

T3

12

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1382	1			T1	6		T2	1		T12	1
key_invalid	sha2_none	976	1			T2	2		T3	1		T4	2
key_invalid	sha2_512	979	1			T1	2		T3	1		T4	1
key_invalid	sha2_384	1019	1			T1	1		T2	2		T12	4
key_invalid	sha2_256	997	1			T2	4		T4	2		T15	1
key_none	sha2_invalid	630	1			T2	2		T7	3		T8	5
key_none	sha2_none	664	1			T3	1		T15	1		T12	2
key_none	sha2_512	2654	1			T2	1		T15	1		T14	1
key_none	sha2_384	2660	1			T2	1		T3	1		T4	1
key_none	sha2_256	1729	1			T2	5		T4	2		T12	1
key_1024	sha2_invalid	598	1			T2	2		T3	1		T12	3
key_1024	sha2_none	672	1			T1	1		T15	2		T45	1
key_1024	sha2_512	1831	1			T2	3		T4	1		T15	1
key_1024	sha2_384	962	1			T1	1		T2	2		T3	2
key_512	sha2_invalid	570	1			T1	1		T12	1		T13	1
key_512	sha2_none	608	1			T2	1		T12	1		T45	2
key_512	sha2_512	694	1			T2	3		T3	3		T12	1
key_512	sha2_384	1292	1			T1	1		T15	1		T13	1
key_512	sha2_256	1001	1			T12	1		T39	1		T7	4
key_384	sha2_invalid	566	1			T1	1		T2	1		T15	1
key_384	sha2_none	622	1			T1	1		T4	3		T12	1
key_384	sha2_512	726	1			T1	1		T2	1		T20	1
key_384	sha2_384	709	1			T1	1		T2	1		T13	2
key_384	sha2_256	1142	1			T1	2		T2	2		T12	1
key_256	sha2_invalid	551	1			T1	1		T15	1		T14	1
key_256	sha2_none	631	1			T2	3		T14	2		T63	1
key_256	sha2_512	688	1			T1	2		T2	2		T3	3
key_256	sha2_384	680	1			T1	1		T2	3		T4	1
key_256	sha2_256	877	1			T1	1		T2	2		T12	3
key_128	sha2_invalid	585	1			T1	1		T2	1		T15	1
key_128	sha2_none	611	1			T2	1		T13	1		T14	1
key_128	sha2_512	711	1			T2	2		T12	2		T13	1
key_128	sha2_384	676	1			T1	2		T14	1		T21	1
key_128	sha2_256	750	1			T1	1		T2	2		T3	3

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

735

1

T1

1

T12

2

T45

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1382	1			T1	6		T2	1		T12	1
key_invalid	sha2_none	976	1			T2	2		T3	1		T4	2
key_invalid	sha2_512	979	1			T1	2		T3	1		T4	1
key_invalid	sha2_384	1019	1			T1	1		T2	2		T12	4
key_invalid	sha2_256	997	1			T2	4		T4	2		T15	1
key_none	sha2_invalid	630	1			T2	2		T7	3		T8	5
key_none	sha2_none	664	1			T3	1		T15	1		T12	2
key_none	sha2_512	2654	1			T2	1		T15	1		T14	1
key_none	sha2_384	2660	1			T2	1		T3	1		T4	1
key_none	sha2_256	1729	1			T2	5		T4	2		T12	1
key_1024	sha2_invalid	598	1			T2	2		T3	1		T12	3
key_1024	sha2_none	672	1			T1	1		T15	2		T45	1
key_1024	sha2_512	1831	1			T2	3		T4	1		T15	1
key_1024	sha2_384	962	1			T1	1		T2	2		T3	2
key_1024	sha2_256	735	1			T1	1		T12	2		T45	1
key_512	sha2_invalid	570	1			T1	1		T12	1		T13	1
key_512	sha2_none	608	1			T2	1		T12	1		T45	2
key_512	sha2_512	694	1			T2	3		T3	3		T12	1
key_512	sha2_384	1292	1			T1	1		T15	1		T13	1
key_512	sha2_256	1001	1			T12	1		T39	1		T7	4
key_384	sha2_invalid	566	1			T1	1		T2	1		T15	1
key_384	sha2_none	622	1			T1	1		T4	3		T12	1
key_384	sha2_512	726	1			T1	1		T2	1		T20	1
key_384	sha2_384	709	1			T1	1		T2	1		T13	2
key_384	sha2_256	1142	1			T1	2		T2	2		T12	1
key_256	sha2_invalid	551	1			T1	1		T15	1		T14	1
key_256	sha2_none	631	1			T2	3		T14	2		T63	1
key_256	sha2_512	688	1			T1	2		T2	2		T3	3
key_256	sha2_384	680	1			T1	1		T2	3		T4	1
key_256	sha2_256	877	1			T1	1		T2	2		T12	3
key_128	sha2_invalid	585	1			T1	1		T2	1		T15	1
key_128	sha2_none	611	1			T2	1		T13	1		T14	1
key_128	sha2_512	711	1			T2	2		T12	2		T13	1
key_128	sha2_384	676	1			T1	2		T14	1		T21	1
key_128	sha2_256	750	1			T1	1		T2	2		T3	3