Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.52 95.26 97.33 100.00 94.12 98.12 97.97 99.85


Total test records in report: 660
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T538 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1014003685 Jul 29 06:51:59 PM PDT 24 Jul 29 06:52:02 PM PDT 24 339685221 ps
T114 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4158153792 Jul 29 06:51:54 PM PDT 24 Jul 29 06:51:55 PM PDT 24 32073234 ps
T121 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2190526461 Jul 29 06:51:57 PM PDT 24 Jul 29 06:51:59 PM PDT 24 65089326 ps
T539 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3409027959 Jul 29 06:51:54 PM PDT 24 Jul 29 06:51:55 PM PDT 24 43568471 ps
T540 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.254950846 Jul 29 06:52:02 PM PDT 24 Jul 29 06:52:05 PM PDT 24 87716084 ps
T541 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2132424330 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:12 PM PDT 24 31674013 ps
T542 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3688151739 Jul 29 06:52:09 PM PDT 24 Jul 29 06:52:09 PM PDT 24 11874300 ps
T543 /workspace/coverage/cover_reg_top/24.hmac_intr_test.646999760 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:13 PM PDT 24 18850288 ps
T104 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3588689062 Jul 29 06:52:04 PM PDT 24 Jul 29 06:52:05 PM PDT 24 56043204 ps
T544 /workspace/coverage/cover_reg_top/8.hmac_intr_test.497461925 Jul 29 06:51:50 PM PDT 24 Jul 29 06:51:51 PM PDT 24 16510675 ps
T105 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3854295620 Jul 29 06:51:58 PM PDT 24 Jul 29 06:51:59 PM PDT 24 64042387 ps
T122 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2951516121 Jul 29 06:52:09 PM PDT 24 Jul 29 06:52:11 PM PDT 24 130629738 ps
T545 /workspace/coverage/cover_reg_top/28.hmac_intr_test.840512195 Jul 29 06:52:10 PM PDT 24 Jul 29 06:52:10 PM PDT 24 16267682 ps
T546 /workspace/coverage/cover_reg_top/20.hmac_intr_test.207945410 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:13 PM PDT 24 41067517 ps
T547 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3842965727 Jul 29 06:51:55 PM PDT 24 Jul 29 06:51:55 PM PDT 24 22836987 ps
T548 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2364737313 Jul 29 06:51:58 PM PDT 24 Jul 29 06:51:59 PM PDT 24 125449827 ps
T123 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3462117114 Jul 29 06:52:06 PM PDT 24 Jul 29 06:52:07 PM PDT 24 22220579 ps
T549 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3901907981 Jul 29 06:52:09 PM PDT 24 Jul 29 06:52:10 PM PDT 24 12912453 ps
T124 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2919742468 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:53 PM PDT 24 227731753 ps
T550 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1910811225 Jul 29 06:51:32 PM PDT 24 Jul 29 06:51:33 PM PDT 24 43746851 ps
T106 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3849630222 Jul 29 06:51:34 PM PDT 24 Jul 29 06:51:35 PM PDT 24 44111581 ps
T125 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1865504061 Jul 29 06:51:59 PM PDT 24 Jul 29 06:52:01 PM PDT 24 34412972 ps
T551 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3023350940 Jul 29 06:52:10 PM PDT 24 Jul 29 06:52:11 PM PDT 24 106492958 ps
T552 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3685643002 Jul 29 06:51:34 PM PDT 24 Jul 29 06:51:37 PM PDT 24 374631610 ps
T126 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1929147472 Jul 29 06:51:56 PM PDT 24 Jul 29 06:51:58 PM PDT 24 126069300 ps
T127 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.804323744 Jul 29 06:52:03 PM PDT 24 Jul 29 06:52:04 PM PDT 24 31230351 ps
T553 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2133249478 Jul 29 06:51:53 PM PDT 24 Jul 29 06:51:55 PM PDT 24 238182695 ps
T554 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2191411861 Jul 29 06:51:57 PM PDT 24 Jul 29 06:51:58 PM PDT 24 16004047 ps
T555 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.544146025 Jul 29 06:51:56 PM PDT 24 Jul 29 06:51:59 PM PDT 24 61579687 ps
T60 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2785356878 Jul 29 06:51:58 PM PDT 24 Jul 29 06:52:02 PM PDT 24 867919607 ps
T556 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1116121630 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:36 PM PDT 24 15008315 ps
T557 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3874676627 Jul 29 06:52:10 PM PDT 24 Jul 29 06:52:11 PM PDT 24 23328968 ps
T558 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4019226018 Jul 29 06:51:53 PM PDT 24 Jul 29 06:51:54 PM PDT 24 20547942 ps
T61 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3541345631 Jul 29 06:51:36 PM PDT 24 Jul 29 06:51:38 PM PDT 24 53330576 ps
T62 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3556204099 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:38 PM PDT 24 653643185 ps
T559 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.554833262 Jul 29 06:51:52 PM PDT 24 Jul 29 06:51:53 PM PDT 24 108587374 ps
T560 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.717544895 Jul 29 06:52:09 PM PDT 24 Jul 29 06:52:12 PM PDT 24 219677519 ps
T561 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2034793670 Jul 29 06:51:58 PM PDT 24 Jul 29 06:52:01 PM PDT 24 562658837 ps
T562 /workspace/coverage/cover_reg_top/4.hmac_intr_test.409748649 Jul 29 06:51:36 PM PDT 24 Jul 29 06:51:37 PM PDT 24 48389225 ps
T563 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2073701768 Jul 29 06:52:00 PM PDT 24 Jul 29 06:52:02 PM PDT 24 144134735 ps
T564 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2260623136 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:37 PM PDT 24 528242327 ps
T565 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3286854152 Jul 29 06:52:02 PM PDT 24 Jul 29 06:52:04 PM PDT 24 270465349 ps
T566 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2425151408 Jul 29 06:51:27 PM PDT 24 Jul 29 06:51:28 PM PDT 24 26844729 ps
T567 /workspace/coverage/cover_reg_top/18.hmac_intr_test.651449725 Jul 29 06:52:01 PM PDT 24 Jul 29 06:52:02 PM PDT 24 209490084 ps
T568 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1118243410 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:54 PM PDT 24 54521339 ps
T569 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1000789905 Jul 29 06:52:14 PM PDT 24 Jul 29 06:52:15 PM PDT 24 14465031 ps
T570 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3830470332 Jul 29 06:52:15 PM PDT 24 Jul 29 06:52:15 PM PDT 24 61556934 ps
T571 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4048866331 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:35 PM PDT 24 154349210 ps
T572 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3450253812 Jul 29 06:51:56 PM PDT 24 Jul 29 06:51:58 PM PDT 24 179241180 ps
T573 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.468828293 Jul 29 06:52:02 PM PDT 24 Jul 29 06:52:04 PM PDT 24 192430697 ps
T574 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.985584968 Jul 29 06:51:53 PM PDT 24 Jul 29 06:51:55 PM PDT 24 67896409 ps
T575 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1735796878 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:52 PM PDT 24 88852376 ps
T576 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1114366260 Jul 29 06:52:03 PM PDT 24 Jul 29 06:52:05 PM PDT 24 522237545 ps
T577 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3507354488 Jul 29 06:52:11 PM PDT 24 Jul 29 06:52:12 PM PDT 24 18520194 ps
T107 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2948138954 Jul 29 06:52:09 PM PDT 24 Jul 29 06:52:10 PM PDT 24 14678985 ps
T578 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3141915120 Jul 29 06:51:37 PM PDT 24 Jul 29 06:51:39 PM PDT 24 204684802 ps
T108 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3494296322 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:34 PM PDT 24 20061375 ps
T579 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4242138500 Jul 29 06:51:36 PM PDT 24 Jul 29 06:51:36 PM PDT 24 14795879 ps
T132 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.709657630 Jul 29 06:52:02 PM PDT 24 Jul 29 06:52:07 PM PDT 24 501279850 ps
T580 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2140450303 Jul 29 06:51:39 PM PDT 24 Jul 29 06:51:40 PM PDT 24 33269215 ps
T581 /workspace/coverage/cover_reg_top/22.hmac_intr_test.4276207918 Jul 29 06:52:11 PM PDT 24 Jul 29 06:52:12 PM PDT 24 18229624 ps
T65 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3388453645 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:55 PM PDT 24 653885207 ps
T582 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2539856554 Jul 29 06:52:13 PM PDT 24 Jul 29 06:52:14 PM PDT 24 17231636 ps
T583 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.728708105 Jul 29 06:51:56 PM PDT 24 Jul 29 06:51:59 PM PDT 24 111993975 ps
T584 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.244534809 Jul 29 06:51:36 PM PDT 24 Jul 29 06:51:37 PM PDT 24 32575649 ps
T585 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3136969050 Jul 29 06:51:57 PM PDT 24 Jul 29 06:51:59 PM PDT 24 41644617 ps
T586 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1756360915 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:13 PM PDT 24 36899101 ps
T587 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1958754161 Jul 29 06:51:52 PM PDT 24 Jul 29 06:51:53 PM PDT 24 65246203 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2052830422 Jul 29 06:51:32 PM PDT 24 Jul 29 06:51:33 PM PDT 24 19480709 ps
T135 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1624705267 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:54 PM PDT 24 618268863 ps
T588 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1214851239 Jul 29 06:51:50 PM PDT 24 Jul 29 06:51:52 PM PDT 24 214008858 ps
T136 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1897111693 Jul 29 06:51:53 PM PDT 24 Jul 29 06:51:56 PM PDT 24 95149636 ps
T589 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.62294997 Jul 29 06:52:05 PM PDT 24 Jul 29 06:52:07 PM PDT 24 133940214 ps
T590 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3535055595 Jul 29 06:51:59 PM PDT 24 Jul 29 06:52:00 PM PDT 24 38520762 ps
T134 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1834912512 Jul 29 06:52:03 PM PDT 24 Jul 29 06:52:05 PM PDT 24 454038546 ps
T133 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.88389974 Jul 29 06:51:57 PM PDT 24 Jul 29 06:52:00 PM PDT 24 298004905 ps
T591 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2863034538 Jul 29 06:51:54 PM PDT 24 Jul 29 06:51:55 PM PDT 24 13808654 ps
T592 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3609871882 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:37 PM PDT 24 717058002 ps
T593 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.275522763 Jul 29 06:51:58 PM PDT 24 Jul 29 06:52:00 PM PDT 24 339019094 ps
T594 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3454385398 Jul 29 06:52:05 PM PDT 24 Jul 29 06:52:05 PM PDT 24 51154670 ps
T595 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2866733857 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:55 PM PDT 24 267186183 ps
T110 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2508859069 Jul 29 06:52:05 PM PDT 24 Jul 29 06:52:06 PM PDT 24 35123038 ps
T596 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3644901272 Jul 29 06:52:10 PM PDT 24 Jul 29 06:52:11 PM PDT 24 15533982 ps
T111 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3808995899 Jul 29 06:51:32 PM PDT 24 Jul 29 06:51:33 PM PDT 24 271181650 ps
T112 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.604358273 Jul 29 06:51:52 PM PDT 24 Jul 29 06:51:53 PM PDT 24 31303525 ps
T597 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3732656407 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:36 PM PDT 24 161884241 ps
T598 /workspace/coverage/cover_reg_top/19.hmac_intr_test.819253171 Jul 29 06:52:05 PM PDT 24 Jul 29 06:52:06 PM PDT 24 187159279 ps
T599 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3482816933 Jul 29 06:52:02 PM PDT 24 Jul 29 06:52:05 PM PDT 24 48130060 ps
T113 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2698714935 Jul 29 06:51:34 PM PDT 24 Jul 29 06:51:35 PM PDT 24 138142632 ps
T600 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4293223152 Jul 29 06:52:11 PM PDT 24 Jul 29 06:52:12 PM PDT 24 16151355 ps
T601 /workspace/coverage/cover_reg_top/7.hmac_intr_test.430923978 Jul 29 06:51:54 PM PDT 24 Jul 29 06:51:55 PM PDT 24 48544012 ps
T602 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1505771196 Jul 29 06:51:58 PM PDT 24 Jul 29 06:51:58 PM PDT 24 44443457 ps
T603 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1712702671 Jul 29 06:52:14 PM PDT 24 Jul 29 06:52:17 PM PDT 24 34257997 ps
T604 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.515011023 Jul 29 06:51:58 PM PDT 24 Jul 29 06:51:59 PM PDT 24 28297153 ps
T605 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2374935445 Jul 29 06:51:36 PM PDT 24 Jul 29 06:51:39 PM PDT 24 57243946 ps
T606 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1526116433 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:13 PM PDT 24 21328446 ps
T607 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3328139498 Jul 29 06:51:53 PM PDT 24 Jul 29 06:51:55 PM PDT 24 244122674 ps
T137 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1370994633 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:38 PM PDT 24 82190099 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.627623500 Jul 29 06:51:39 PM PDT 24 Jul 29 06:51:42 PM PDT 24 1619861963 ps
T609 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3930227333 Jul 29 06:52:00 PM PDT 24 Jul 29 06:52:01 PM PDT 24 46175002 ps
T610 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2345620192 Jul 29 06:51:54 PM PDT 24 Jul 29 06:51:55 PM PDT 24 25917221 ps
T115 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.909042103 Jul 29 06:51:56 PM PDT 24 Jul 29 06:51:57 PM PDT 24 21635926 ps
T611 /workspace/coverage/cover_reg_top/33.hmac_intr_test.263556385 Jul 29 06:52:11 PM PDT 24 Jul 29 06:52:11 PM PDT 24 28044496 ps
T612 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2503271520 Jul 29 06:51:58 PM PDT 24 Jul 29 06:52:00 PM PDT 24 612210184 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2816618695 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:34 PM PDT 24 58497862 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2600324470 Jul 29 06:52:07 PM PDT 24 Jul 29 06:52:07 PM PDT 24 79774357 ps
T615 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3471381522 Jul 29 06:52:03 PM PDT 24 Jul 29 06:52:05 PM PDT 24 135410536 ps
T616 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2055206939 Jul 29 06:52:13 PM PDT 24 Jul 29 06:52:14 PM PDT 24 73409356 ps
T617 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2392584768 Jul 29 06:52:13 PM PDT 24 Jul 29 06:52:14 PM PDT 24 25517154 ps
T618 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3616609755 Jul 29 06:52:03 PM PDT 24 Jul 29 06:52:04 PM PDT 24 41013696 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1235516075 Jul 29 06:51:58 PM PDT 24 Jul 29 06:52:03 PM PDT 24 438877472 ps
T620 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1641178677 Jul 29 06:51:56 PM PDT 24 Jul 29 07:07:19 PM PDT 24 264738036156 ps
T621 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.628278789 Jul 29 06:51:38 PM PDT 24 Jul 29 06:51:41 PM PDT 24 190618170 ps
T138 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2029906020 Jul 29 06:52:02 PM PDT 24 Jul 29 06:52:06 PM PDT 24 198937861 ps
T622 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1028687148 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:12 PM PDT 24 15167029 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4143199372 Jul 29 06:51:39 PM PDT 24 Jul 29 06:51:45 PM PDT 24 373896801 ps
T624 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.784771993 Jul 29 06:52:00 PM PDT 24 Jul 29 06:52:01 PM PDT 24 41927511 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3762502436 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:40 PM PDT 24 1794731953 ps
T626 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3044421873 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:37 PM PDT 24 35388190 ps
T627 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4283811542 Jul 29 06:52:14 PM PDT 24 Jul 29 06:52:14 PM PDT 24 17693896 ps
T66 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.977664933 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:56 PM PDT 24 282459474 ps
T628 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.318641949 Jul 29 06:51:30 PM PDT 24 Jul 29 06:51:41 PM PDT 24 2794926744 ps
T116 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3950200850 Jul 29 06:51:34 PM PDT 24 Jul 29 06:51:38 PM PDT 24 215151387 ps
T629 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.62622821 Jul 29 06:51:36 PM PDT 24 Jul 29 06:51:38 PM PDT 24 100749257 ps
T630 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2955102087 Jul 29 06:52:07 PM PDT 24 Jul 29 06:52:08 PM PDT 24 136208054 ps
T631 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1206195885 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:37 PM PDT 24 67270226 ps
T632 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1631886509 Jul 29 06:52:10 PM PDT 24 Jul 29 06:52:10 PM PDT 24 67283103 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.870343559 Jul 29 06:51:34 PM PDT 24 Jul 29 06:51:36 PM PDT 24 745450251 ps
T139 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1335563286 Jul 29 06:51:59 PM PDT 24 Jul 29 06:52:03 PM PDT 24 484045167 ps
T634 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.119982192 Jul 29 06:51:50 PM PDT 24 Jul 29 06:51:52 PM PDT 24 46465755 ps
T635 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2112257481 Jul 29 06:52:05 PM PDT 24 Jul 29 06:52:07 PM PDT 24 840979454 ps
T117 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3016002440 Jul 29 06:51:36 PM PDT 24 Jul 29 06:51:37 PM PDT 24 167629320 ps
T118 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.468619761 Jul 29 06:51:57 PM PDT 24 Jul 29 06:51:58 PM PDT 24 26627567 ps
T636 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1745385236 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:13 PM PDT 24 31017965 ps
T637 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1311659701 Jul 29 06:52:10 PM PDT 24 Jul 29 06:52:11 PM PDT 24 21899971 ps
T638 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2303718238 Jul 29 06:52:02 PM PDT 24 Jul 29 06:52:04 PM PDT 24 56756014 ps
T639 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1187130667 Jul 29 06:51:51 PM PDT 24 Jul 29 06:51:53 PM PDT 24 123129637 ps
T640 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3491746059 Jul 29 06:52:09 PM PDT 24 Jul 29 06:52:09 PM PDT 24 59595631 ps
T119 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1976089547 Jul 29 06:51:38 PM PDT 24 Jul 29 06:51:45 PM PDT 24 1569656055 ps
T641 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1749539266 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:34 PM PDT 24 23807205 ps
T642 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1877321596 Jul 29 06:52:05 PM PDT 24 Jul 29 06:52:06 PM PDT 24 35957238 ps
T643 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.808057406 Jul 29 06:51:50 PM PDT 24 Jul 29 06:51:52 PM PDT 24 428851206 ps
T644 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.844672891 Jul 29 06:51:57 PM PDT 24 Jul 29 06:51:58 PM PDT 24 14011197 ps
T645 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2923673834 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:36 PM PDT 24 571677945 ps
T646 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3959774574 Jul 29 06:51:34 PM PDT 24 Jul 29 06:51:43 PM PDT 24 9590611917 ps
T647 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3286835712 Jul 29 06:52:04 PM PDT 24 Jul 29 06:52:05 PM PDT 24 44051375 ps
T648 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1950514221 Jul 29 06:52:08 PM PDT 24 Jul 29 06:52:09 PM PDT 24 16770248 ps
T649 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1293070995 Jul 29 06:51:35 PM PDT 24 Jul 29 06:51:38 PM PDT 24 142513071 ps
T650 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3470831835 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:50 PM PDT 24 1642746324 ps
T651 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3049951826 Jul 29 06:51:58 PM PDT 24 Jul 29 06:52:00 PM PDT 24 186914323 ps
T652 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1278654000 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:34 PM PDT 24 43877284 ps
T653 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3404901387 Jul 29 06:52:10 PM PDT 24 Jul 29 06:52:11 PM PDT 24 45480336 ps
T654 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1577320721 Jul 29 06:51:24 PM PDT 24 Jul 29 06:51:27 PM PDT 24 340666044 ps
T655 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3419440829 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:13 PM PDT 24 10756684 ps
T656 /workspace/coverage/cover_reg_top/48.hmac_intr_test.643948293 Jul 29 06:52:12 PM PDT 24 Jul 29 06:52:13 PM PDT 24 38093156 ps
T657 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.982374156 Jul 29 06:51:57 PM PDT 24 Jul 29 06:51:57 PM PDT 24 24041429 ps
T658 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2520839819 Jul 29 06:51:29 PM PDT 24 Jul 29 06:51:30 PM PDT 24 80591692 ps
T67 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.509742085 Jul 29 06:51:39 PM PDT 24 Jul 29 06:51:41 PM PDT 24 621311857 ps
T659 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.304952384 Jul 29 06:51:58 PM PDT 24 Jul 29 06:52:03 PM PDT 24 487808700 ps
T660 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.466543981 Jul 29 06:51:33 PM PDT 24 Jul 29 06:51:39 PM PDT 24 118989006 ps

Test location /workspace/coverage/default/5.hmac_burst_wr.238518384
Short name T2
Test name
Test status
Simulation time 6039637293 ps
CPU time 67.5 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:23:30 PM PDT 24
Peak memory 199952 kb
Host smart-636aa55b-3185-48e4-ba91-c2e70cd4c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238518384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.238518384
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2284236864
Short name T7
Test name
Test status
Simulation time 125019095878 ps
CPU time 870.02 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:37:13 PM PDT 24
Peak memory 703028 kb
Host smart-178b401f-45d8-46f1-a6f1-a2e1fc9e86de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284236864 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2284236864
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1681169232
Short name T11
Test name
Test status
Simulation time 33118466055 ps
CPU time 3115.46 seconds
Started Jul 29 05:22:32 PM PDT 24
Finished Jul 29 06:14:28 PM PDT 24
Peak memory 807700 kb
Host smart-83ad9661-7173-449b-935a-426f3c9f4f83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681169232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1681169232
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3186872432
Short name T34
Test name
Test status
Simulation time 269877824683 ps
CPU time 1426.12 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:46:49 PM PDT 24
Peak memory 662776 kb
Host smart-fb06ce01-2036-4991-9e3e-d68e29b6e9b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186872432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3186872432
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2785356878
Short name T60
Test name
Test status
Simulation time 867919607 ps
CPU time 4.32 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:52:02 PM PDT 24
Peak memory 200096 kb
Host smart-cef1ed9c-e514-4e79-bd7a-f1c95f3d1061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785356878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2785356878
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1136642320
Short name T129
Test name
Test status
Simulation time 77323128731 ps
CPU time 2111.34 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:58:01 PM PDT 24
Peak memory 765508 kb
Host smart-55d9e5f8-487a-4011-9083-9f733656de46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136642320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1136642320
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1129608860
Short name T47
Test name
Test status
Simulation time 199411849 ps
CPU time 0.9 seconds
Started Jul 29 05:22:24 PM PDT 24
Finished Jul 29 05:22:25 PM PDT 24
Peak memory 218436 kb
Host smart-fa9be610-d7ca-4e45-a289-f7f33187ac12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129608860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1129608860
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2052830422
Short name T109
Test name
Test status
Simulation time 19480709 ps
CPU time 0.92 seconds
Started Jul 29 06:51:32 PM PDT 24
Finished Jul 29 06:51:33 PM PDT 24
Peak memory 199808 kb
Host smart-fb5a9521-946c-46be-996d-20c5d880bff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052830422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2052830422
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3140394833
Short name T16
Test name
Test status
Simulation time 4730628866 ps
CPU time 69.63 seconds
Started Jul 29 05:22:38 PM PDT 24
Finished Jul 29 05:23:47 PM PDT 24
Peak memory 200012 kb
Host smart-b4b50294-99bb-4de2-bd4f-4eb9e2643ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140394833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3140394833
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.988624786
Short name T23
Test name
Test status
Simulation time 2827274838 ps
CPU time 43.06 seconds
Started Jul 29 05:23:08 PM PDT 24
Finished Jul 29 05:23:51 PM PDT 24
Peak memory 199976 kb
Host smart-2dca596b-a3c2-42dc-bf5d-71c959fc8414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988624786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.988624786
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1508668948
Short name T78
Test name
Test status
Simulation time 384263845593 ps
CPU time 2365.35 seconds
Started Jul 29 05:24:18 PM PDT 24
Finished Jul 29 06:03:44 PM PDT 24
Peak memory 782388 kb
Host smart-99b22817-37e3-4487-afea-8ac679e8e850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508668948 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1508668948
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3162468722
Short name T42
Test name
Test status
Simulation time 12817531 ps
CPU time 0.57 seconds
Started Jul 29 05:22:34 PM PDT 24
Finished Jul 29 05:22:35 PM PDT 24
Peak memory 194816 kb
Host smart-77d51707-636f-416a-bcf8-3c489a66f556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162468722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3162468722
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1834912512
Short name T134
Test name
Test status
Simulation time 454038546 ps
CPU time 1.91 seconds
Started Jul 29 06:52:03 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 200132 kb
Host smart-d4a73de5-fe63-483a-bbc8-3350959ec4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834912512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1834912512
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2423083117
Short name T99
Test name
Test status
Simulation time 19168208557 ps
CPU time 252.29 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:27:01 PM PDT 24
Peak memory 199984 kb
Host smart-abd16436-afd6-4297-bdf5-8d1e4ad8a90c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423083117 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2423083117
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2190526461
Short name T121
Test name
Test status
Simulation time 65089326 ps
CPU time 1.58 seconds
Started Jul 29 06:51:57 PM PDT 24
Finished Jul 29 06:51:59 PM PDT 24
Peak memory 200120 kb
Host smart-40d92fdb-8430-4bfe-9f7e-9bdfa0a5fc5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190526461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2190526461
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.509742085
Short name T67
Test name
Test status
Simulation time 621311857 ps
CPU time 1.63 seconds
Started Jul 29 06:51:39 PM PDT 24
Finished Jul 29 06:51:41 PM PDT 24
Peak memory 200032 kb
Host smart-c204b144-a698-4947-8819-6f43e18012bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509742085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.509742085
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.4185208782
Short name T9
Test name
Test status
Simulation time 193345613940 ps
CPU time 2144.17 seconds
Started Jul 29 05:22:14 PM PDT 24
Finished Jul 29 05:57:58 PM PDT 24
Peak memory 656012 kb
Host smart-8b6a8aa8-0774-4002-8596-7fe91681efb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185208782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.4185208782
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2464487267
Short name T378
Test name
Test status
Simulation time 4990421979 ps
CPU time 62.5 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:23:52 PM PDT 24
Peak memory 199868 kb
Host smart-5c1d68ef-c1d5-46eb-a733-cd98a351ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464487267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2464487267
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3388453645
Short name T65
Test name
Test status
Simulation time 653885207 ps
CPU time 3.9 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 200128 kb
Host smart-57a79e04-ede7-4827-8cc0-d6c7ee14b83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388453645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3388453645
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.977664933
Short name T66
Test name
Test status
Simulation time 282459474 ps
CPU time 4.49 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:56 PM PDT 24
Peak memory 199964 kb
Host smart-f12a9ee0-1f75-4d65-a18b-f18ba67e6050
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977664933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.977664933
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.424235721
Short name T19
Test name
Test status
Simulation time 12994134012 ps
CPU time 196.82 seconds
Started Jul 29 05:22:24 PM PDT 24
Finished Jul 29 05:25:41 PM PDT 24
Peak memory 216412 kb
Host smart-4176df7d-63be-4311-86f7-7b11689b4e24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424235721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.424235721
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1577320721
Short name T654
Test name
Test status
Simulation time 340666044 ps
CPU time 3.13 seconds
Started Jul 29 06:51:24 PM PDT 24
Finished Jul 29 06:51:27 PM PDT 24
Peak memory 198884 kb
Host smart-1b8796a1-865f-457c-a568-dbae273fdcb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577320721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1577320721
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.318641949
Short name T628
Test name
Test status
Simulation time 2794926744 ps
CPU time 10.73 seconds
Started Jul 29 06:51:30 PM PDT 24
Finished Jul 29 06:51:41 PM PDT 24
Peak memory 199564 kb
Host smart-ced200d0-f57c-47c2-ac2d-ff2621958ee1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318641949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.318641949
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1116121630
Short name T556
Test name
Test status
Simulation time 15008315 ps
CPU time 0.73 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:36 PM PDT 24
Peak memory 198308 kb
Host smart-b776e968-fb17-49cb-a948-5478f0685738
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116121630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1116121630
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2374935445
Short name T605
Test name
Test status
Simulation time 57243946 ps
CPU time 2.59 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:39 PM PDT 24
Peak memory 208392 kb
Host smart-c4171715-2352-4e8b-a3e8-c1cf6be867c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374935445 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2374935445
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2520839819
Short name T658
Test name
Test status
Simulation time 80591692 ps
CPU time 0.93 seconds
Started Jul 29 06:51:29 PM PDT 24
Finished Jul 29 06:51:30 PM PDT 24
Peak memory 199724 kb
Host smart-47d126f0-4555-4cb3-97cb-5e368c636308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520839819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2520839819
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2140450303
Short name T580
Test name
Test status
Simulation time 33269215 ps
CPU time 0.61 seconds
Started Jul 29 06:51:39 PM PDT 24
Finished Jul 29 06:51:40 PM PDT 24
Peak memory 194908 kb
Host smart-dacc3bfd-28e4-47c5-ac08-12ecf30c541a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140450303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2140450303
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2260623136
Short name T564
Test name
Test status
Simulation time 528242327 ps
CPU time 1.27 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 199976 kb
Host smart-58af1701-1c87-43ff-b32d-fde2a1185fa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260623136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2260623136
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2425151408
Short name T566
Test name
Test status
Simulation time 26844729 ps
CPU time 1.46 seconds
Started Jul 29 06:51:27 PM PDT 24
Finished Jul 29 06:51:28 PM PDT 24
Peak memory 200144 kb
Host smart-3664acec-9ea7-4cde-8c93-6cd84dea5cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425151408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2425151408
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.627623500
Short name T608
Test name
Test status
Simulation time 1619861963 ps
CPU time 3.05 seconds
Started Jul 29 06:51:39 PM PDT 24
Finished Jul 29 06:51:42 PM PDT 24
Peak memory 199892 kb
Host smart-1aa9926c-0dba-49e4-881f-6b87f17ab5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627623500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.627623500
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3950200850
Short name T116
Test name
Test status
Simulation time 215151387 ps
CPU time 3.14 seconds
Started Jul 29 06:51:34 PM PDT 24
Finished Jul 29 06:51:38 PM PDT 24
Peak memory 200100 kb
Host smart-176da793-42b5-4915-a2d5-53f098f13c37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950200850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3950200850
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.466543981
Short name T660
Test name
Test status
Simulation time 118989006 ps
CPU time 5.04 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:39 PM PDT 24
Peak memory 200148 kb
Host smart-3093b338-3657-4fd8-ab88-e53c421b89d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466543981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.466543981
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2698714935
Short name T113
Test name
Test status
Simulation time 138142632 ps
CPU time 1 seconds
Started Jul 29 06:51:34 PM PDT 24
Finished Jul 29 06:51:35 PM PDT 24
Peak memory 199760 kb
Host smart-8bdb0621-c3b2-4e11-a6d0-8530e9a2b7ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698714935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2698714935
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.628278789
Short name T621
Test name
Test status
Simulation time 190618170 ps
CPU time 2.61 seconds
Started Jul 29 06:51:38 PM PDT 24
Finished Jul 29 06:51:41 PM PDT 24
Peak memory 200256 kb
Host smart-79892efa-863f-42a4-9dcc-60f222314faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628278789 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.628278789
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3494296322
Short name T108
Test name
Test status
Simulation time 20061375 ps
CPU time 0.68 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:34 PM PDT 24
Peak memory 198396 kb
Host smart-44109856-a84a-4df2-8e98-3f299a8ef827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494296322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3494296322
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1749539266
Short name T641
Test name
Test status
Simulation time 23807205 ps
CPU time 0.6 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:34 PM PDT 24
Peak memory 195148 kb
Host smart-4ccd17ea-ad64-40c4-ba1b-22948c69e52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749539266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1749539266
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3141915120
Short name T578
Test name
Test status
Simulation time 204684802 ps
CPU time 1.8 seconds
Started Jul 29 06:51:37 PM PDT 24
Finished Jul 29 06:51:39 PM PDT 24
Peak memory 200136 kb
Host smart-b4fda537-a1ff-4957-bb18-f24d60c037e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141915120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3141915120
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2816618695
Short name T613
Test name
Test status
Simulation time 58497862 ps
CPU time 1.41 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:34 PM PDT 24
Peak memory 200072 kb
Host smart-d6ffa9ed-75d4-4991-82c8-f116f9be7824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816618695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2816618695
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1293070995
Short name T649
Test name
Test status
Simulation time 142513071 ps
CPU time 2.91 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:38 PM PDT 24
Peak memory 200108 kb
Host smart-d89feb66-8760-4574-a0d9-5616302f4d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293070995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1293070995
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1641178677
Short name T620
Test name
Test status
Simulation time 264738036156 ps
CPU time 922.51 seconds
Started Jul 29 06:51:56 PM PDT 24
Finished Jul 29 07:07:19 PM PDT 24
Peak memory 224764 kb
Host smart-0cf9a3f5-207f-4860-9e8d-6acc67204692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641178677 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1641178677
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3854295620
Short name T105
Test name
Test status
Simulation time 64042387 ps
CPU time 0.69 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:51:59 PM PDT 24
Peak memory 198100 kb
Host smart-82a5f321-ef87-42d5-8b93-fa9589d7151f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854295620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3854295620
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2364737313
Short name T548
Test name
Test status
Simulation time 125449827 ps
CPU time 0.57 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:51:59 PM PDT 24
Peak memory 194972 kb
Host smart-ef8b3d9a-d52c-4664-83a5-3a791036bc15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364737313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2364737313
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.544146025
Short name T555
Test name
Test status
Simulation time 61579687 ps
CPU time 3.07 seconds
Started Jul 29 06:51:56 PM PDT 24
Finished Jul 29 06:51:59 PM PDT 24
Peak memory 200148 kb
Host smart-6c795700-2419-4364-a5a8-015988180bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544146025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.544146025
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2073701768
Short name T563
Test name
Test status
Simulation time 144134735 ps
CPU time 1.9 seconds
Started Jul 29 06:52:00 PM PDT 24
Finished Jul 29 06:52:02 PM PDT 24
Peak memory 199484 kb
Host smart-2c740680-5547-49dc-a12d-2b7acb9c4b2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073701768 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2073701768
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.982374156
Short name T657
Test name
Test status
Simulation time 24041429 ps
CPU time 0.69 seconds
Started Jul 29 06:51:57 PM PDT 24
Finished Jul 29 06:51:57 PM PDT 24
Peak memory 197828 kb
Host smart-ca310f01-248d-45cb-83a9-a4a3e94a15b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982374156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.982374156
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3930227333
Short name T609
Test name
Test status
Simulation time 46175002 ps
CPU time 0.6 seconds
Started Jul 29 06:52:00 PM PDT 24
Finished Jul 29 06:52:01 PM PDT 24
Peak memory 195012 kb
Host smart-349ce2fc-2eaa-4005-a167-d2cf66edacf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930227333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3930227333
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2034793670
Short name T561
Test name
Test status
Simulation time 562658837 ps
CPU time 2.43 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:52:01 PM PDT 24
Peak memory 200084 kb
Host smart-bfa14f7c-2bbd-448f-90b4-050162e6b09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034793670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2034793670
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.728708105
Short name T583
Test name
Test status
Simulation time 111993975 ps
CPU time 3.13 seconds
Started Jul 29 06:51:56 PM PDT 24
Finished Jul 29 06:51:59 PM PDT 24
Peak memory 200112 kb
Host smart-d4a1e121-3a5f-488b-8c35-8a16b0d5da40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728708105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.728708105
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.304952384
Short name T659
Test name
Test status
Simulation time 487808700 ps
CPU time 4.22 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:52:03 PM PDT 24
Peak memory 200220 kb
Host smart-d8b58a1d-e8d3-4a7a-a9c1-6a4cdfbae2c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304952384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.304952384
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2503271520
Short name T612
Test name
Test status
Simulation time 612210184 ps
CPU time 2.14 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:52:00 PM PDT 24
Peak memory 200064 kb
Host smart-737151df-528d-498b-b780-291d0e2987d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503271520 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2503271520
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.909042103
Short name T115
Test name
Test status
Simulation time 21635926 ps
CPU time 0.7 seconds
Started Jul 29 06:51:56 PM PDT 24
Finished Jul 29 06:51:57 PM PDT 24
Peak memory 197996 kb
Host smart-c42b1df8-109a-431a-a4f1-7335d7db26d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909042103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.909042103
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3535055595
Short name T590
Test name
Test status
Simulation time 38520762 ps
CPU time 0.66 seconds
Started Jul 29 06:51:59 PM PDT 24
Finished Jul 29 06:52:00 PM PDT 24
Peak memory 195220 kb
Host smart-6eb430e8-08e3-4430-9ce1-4aadd096d044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535055595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3535055595
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1865504061
Short name T125
Test name
Test status
Simulation time 34412972 ps
CPU time 1.65 seconds
Started Jul 29 06:51:59 PM PDT 24
Finished Jul 29 06:52:01 PM PDT 24
Peak memory 200148 kb
Host smart-92ee30b2-9677-4a07-a0b4-7be10d65a956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865504061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1865504061
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.515011023
Short name T604
Test name
Test status
Simulation time 28297153 ps
CPU time 1.43 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:51:59 PM PDT 24
Peak memory 200128 kb
Host smart-36d28e78-1fb9-4bef-91b1-dc3f18a92c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515011023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.515011023
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1335563286
Short name T139
Test name
Test status
Simulation time 484045167 ps
CPU time 3.96 seconds
Started Jul 29 06:51:59 PM PDT 24
Finished Jul 29 06:52:03 PM PDT 24
Peak memory 200152 kb
Host smart-37c8e66b-d0c4-4212-89b2-e27ef8764900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335563286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1335563286
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1014003685
Short name T538
Test name
Test status
Simulation time 339685221 ps
CPU time 2.45 seconds
Started Jul 29 06:51:59 PM PDT 24
Finished Jul 29 06:52:02 PM PDT 24
Peak memory 208420 kb
Host smart-523a9371-9100-478e-ba81-e28e0130832a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014003685 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1014003685
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.468619761
Short name T118
Test name
Test status
Simulation time 26627567 ps
CPU time 0.85 seconds
Started Jul 29 06:51:57 PM PDT 24
Finished Jul 29 06:51:58 PM PDT 24
Peak memory 199864 kb
Host smart-a476be2e-357c-4733-a089-56f1ee0562d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468619761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.468619761
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2191411861
Short name T554
Test name
Test status
Simulation time 16004047 ps
CPU time 0.61 seconds
Started Jul 29 06:51:57 PM PDT 24
Finished Jul 29 06:51:58 PM PDT 24
Peak memory 195176 kb
Host smart-7d57bd36-d60d-4fe4-a7a6-cd93a4601d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191411861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2191411861
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1929147472
Short name T126
Test name
Test status
Simulation time 126069300 ps
CPU time 1.61 seconds
Started Jul 29 06:51:56 PM PDT 24
Finished Jul 29 06:51:58 PM PDT 24
Peak memory 200128 kb
Host smart-0140a953-59e3-420f-8348-ec50994acbe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929147472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1929147472
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3450253812
Short name T572
Test name
Test status
Simulation time 179241180 ps
CPU time 1.96 seconds
Started Jul 29 06:51:56 PM PDT 24
Finished Jul 29 06:51:58 PM PDT 24
Peak memory 200184 kb
Host smart-73b26ee9-0cd7-48f4-a186-5dbe44294ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450253812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3450253812
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.88389974
Short name T133
Test name
Test status
Simulation time 298004905 ps
CPU time 2.73 seconds
Started Jul 29 06:51:57 PM PDT 24
Finished Jul 29 06:52:00 PM PDT 24
Peak memory 200204 kb
Host smart-60f15b1e-6291-4373-ba93-71c576759055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88389974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.88389974
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3136969050
Short name T585
Test name
Test status
Simulation time 41644617 ps
CPU time 1.36 seconds
Started Jul 29 06:51:57 PM PDT 24
Finished Jul 29 06:51:59 PM PDT 24
Peak memory 200132 kb
Host smart-21c9168f-e541-4736-90bb-83b95d0e70af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136969050 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3136969050
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.844672891
Short name T644
Test name
Test status
Simulation time 14011197 ps
CPU time 0.7 seconds
Started Jul 29 06:51:57 PM PDT 24
Finished Jul 29 06:51:58 PM PDT 24
Peak memory 198512 kb
Host smart-69e393a8-a3a4-4a66-a432-54c2c66c1700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844672891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.844672891
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1505771196
Short name T602
Test name
Test status
Simulation time 44443457 ps
CPU time 0.62 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:51:58 PM PDT 24
Peak memory 195088 kb
Host smart-62f13df0-e962-47f4-9148-6f3f4f0174ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505771196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1505771196
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.784771993
Short name T624
Test name
Test status
Simulation time 41927511 ps
CPU time 1.23 seconds
Started Jul 29 06:52:00 PM PDT 24
Finished Jul 29 06:52:01 PM PDT 24
Peak memory 199280 kb
Host smart-6bcff58c-4170-4753-81a3-9d9dbaf41ea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784771993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.784771993
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3049951826
Short name T651
Test name
Test status
Simulation time 186914323 ps
CPU time 2.51 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:52:00 PM PDT 24
Peak memory 200232 kb
Host smart-14dd9775-562c-44d5-bac1-0bd3526f56df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049951826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3049951826
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1235516075
Short name T619
Test name
Test status
Simulation time 438877472 ps
CPU time 4.4 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:52:03 PM PDT 24
Peak memory 200200 kb
Host smart-43ee79ff-6db4-45d4-b924-a2fd1f789e11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235516075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1235516075
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3286835712
Short name T647
Test name
Test status
Simulation time 44051375 ps
CPU time 1.56 seconds
Started Jul 29 06:52:04 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 200184 kb
Host smart-7b4b9eea-726d-44c0-b25d-4197954c013e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286835712 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3286835712
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2600324470
Short name T614
Test name
Test status
Simulation time 79774357 ps
CPU time 0.72 seconds
Started Jul 29 06:52:07 PM PDT 24
Finished Jul 29 06:52:07 PM PDT 24
Peak memory 198120 kb
Host smart-6df2b9d0-96ab-443d-9ae4-daacc1896fde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600324470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2600324470
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3901907981
Short name T549
Test name
Test status
Simulation time 12912453 ps
CPU time 0.59 seconds
Started Jul 29 06:52:09 PM PDT 24
Finished Jul 29 06:52:10 PM PDT 24
Peak memory 195148 kb
Host smart-26c7db7f-07c2-4796-9d7a-a046d0dbad9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901907981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3901907981
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3462117114
Short name T123
Test name
Test status
Simulation time 22220579 ps
CPU time 1.14 seconds
Started Jul 29 06:52:06 PM PDT 24
Finished Jul 29 06:52:07 PM PDT 24
Peak memory 198444 kb
Host smart-f18f20e4-4e54-4622-81b9-9ba0ea3b8271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462117114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3462117114
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.275522763
Short name T593
Test name
Test status
Simulation time 339019094 ps
CPU time 1.97 seconds
Started Jul 29 06:51:58 PM PDT 24
Finished Jul 29 06:52:00 PM PDT 24
Peak memory 200132 kb
Host smart-226e30d3-df45-460d-93b6-1e393340ba70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275522763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.275522763
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3471381522
Short name T615
Test name
Test status
Simulation time 135410536 ps
CPU time 1.74 seconds
Started Jul 29 06:52:03 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 200124 kb
Host smart-dbd49757-9cdb-4d31-b269-45966ac953ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471381522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3471381522
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.717544895
Short name T560
Test name
Test status
Simulation time 219677519 ps
CPU time 3.3 seconds
Started Jul 29 06:52:09 PM PDT 24
Finished Jul 29 06:52:12 PM PDT 24
Peak memory 208440 kb
Host smart-e975dd8b-264e-467e-9cdd-5cd130739dc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717544895 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.717544895
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.804323744
Short name T127
Test name
Test status
Simulation time 31230351 ps
CPU time 0.92 seconds
Started Jul 29 06:52:03 PM PDT 24
Finished Jul 29 06:52:04 PM PDT 24
Peak memory 199872 kb
Host smart-717e6041-dea0-4305-80bf-0758ae65279f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804323744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.804323744
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3454385398
Short name T594
Test name
Test status
Simulation time 51154670 ps
CPU time 0.59 seconds
Started Jul 29 06:52:05 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 195024 kb
Host smart-d0c6d91b-7e33-403c-bfc9-c18b6362e4e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454385398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3454385398
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.468828293
Short name T573
Test name
Test status
Simulation time 192430697 ps
CPU time 1.78 seconds
Started Jul 29 06:52:02 PM PDT 24
Finished Jul 29 06:52:04 PM PDT 24
Peak memory 200140 kb
Host smart-0bf980f0-eeb6-4a80-bcb0-43e55676d4e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468828293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.468828293
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3482816933
Short name T599
Test name
Test status
Simulation time 48130060 ps
CPU time 2.48 seconds
Started Jul 29 06:52:02 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 200116 kb
Host smart-d2745af0-1218-413d-8b40-581bedd98c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482816933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3482816933
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2303718238
Short name T638
Test name
Test status
Simulation time 56756014 ps
CPU time 1.71 seconds
Started Jul 29 06:52:02 PM PDT 24
Finished Jul 29 06:52:04 PM PDT 24
Peak memory 200128 kb
Host smart-8904d04b-2046-4933-89b2-4ce36db21e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303718238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2303718238
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.254950846
Short name T540
Test name
Test status
Simulation time 87716084 ps
CPU time 2.4 seconds
Started Jul 29 06:52:02 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 200136 kb
Host smart-e480ee29-0bda-4c57-948d-b009f14e301e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254950846 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.254950846
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2948138954
Short name T107
Test name
Test status
Simulation time 14678985 ps
CPU time 0.69 seconds
Started Jul 29 06:52:09 PM PDT 24
Finished Jul 29 06:52:10 PM PDT 24
Peak memory 197700 kb
Host smart-09f04538-0409-4bf3-9002-95ac16cf8b2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948138954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2948138954
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3616609755
Short name T618
Test name
Test status
Simulation time 41013696 ps
CPU time 0.6 seconds
Started Jul 29 06:52:03 PM PDT 24
Finished Jul 29 06:52:04 PM PDT 24
Peak memory 195180 kb
Host smart-6ddcb035-838b-4c24-b8db-37202833167e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616609755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3616609755
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1114366260
Short name T576
Test name
Test status
Simulation time 522237545 ps
CPU time 2.33 seconds
Started Jul 29 06:52:03 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 200188 kb
Host smart-6fd33f24-b7e5-4149-94ae-696cf4af29c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114366260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1114366260
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2112257481
Short name T635
Test name
Test status
Simulation time 840979454 ps
CPU time 1.83 seconds
Started Jul 29 06:52:05 PM PDT 24
Finished Jul 29 06:52:07 PM PDT 24
Peak memory 200108 kb
Host smart-0a2c4b04-0889-4103-9b7a-1cb38c348796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112257481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2112257481
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3286854152
Short name T565
Test name
Test status
Simulation time 270465349 ps
CPU time 1.94 seconds
Started Jul 29 06:52:02 PM PDT 24
Finished Jul 29 06:52:04 PM PDT 24
Peak memory 200024 kb
Host smart-0aebea35-52bd-4f3a-823b-e3353e73456f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286854152 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3286854152
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3588689062
Short name T104
Test name
Test status
Simulation time 56043204 ps
CPU time 0.91 seconds
Started Jul 29 06:52:04 PM PDT 24
Finished Jul 29 06:52:05 PM PDT 24
Peak memory 199892 kb
Host smart-68796887-39c4-4a02-b197-c25e5fb99013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588689062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3588689062
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.651449725
Short name T567
Test name
Test status
Simulation time 209490084 ps
CPU time 0.74 seconds
Started Jul 29 06:52:01 PM PDT 24
Finished Jul 29 06:52:02 PM PDT 24
Peak memory 195056 kb
Host smart-84a8d0b7-dbe7-4594-9614-4e639c46805e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651449725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.651449725
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2951516121
Short name T122
Test name
Test status
Simulation time 130629738 ps
CPU time 1.66 seconds
Started Jul 29 06:52:09 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 200032 kb
Host smart-2e879c32-bbec-41fb-9739-cb41e239bf29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951516121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2951516121
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2955102087
Short name T630
Test name
Test status
Simulation time 136208054 ps
CPU time 1.57 seconds
Started Jul 29 06:52:07 PM PDT 24
Finished Jul 29 06:52:08 PM PDT 24
Peak memory 200212 kb
Host smart-c61c3cb5-8531-4505-9778-c3c37d5a616b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955102087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2955102087
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.709657630
Short name T132
Test name
Test status
Simulation time 501279850 ps
CPU time 4.26 seconds
Started Jul 29 06:52:02 PM PDT 24
Finished Jul 29 06:52:07 PM PDT 24
Peak memory 200060 kb
Host smart-82eaac88-7332-4fa2-9e1a-c4a988c67a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709657630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.709657630
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1712702671
Short name T603
Test name
Test status
Simulation time 34257997 ps
CPU time 2.11 seconds
Started Jul 29 06:52:14 PM PDT 24
Finished Jul 29 06:52:17 PM PDT 24
Peak memory 200172 kb
Host smart-f0683a91-37ee-4b0e-a72a-33d642aab3e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712702671 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1712702671
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2508859069
Short name T110
Test name
Test status
Simulation time 35123038 ps
CPU time 0.97 seconds
Started Jul 29 06:52:05 PM PDT 24
Finished Jul 29 06:52:06 PM PDT 24
Peak memory 199980 kb
Host smart-b10115a5-1f01-4903-ba62-11a1d90631ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508859069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2508859069
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.819253171
Short name T598
Test name
Test status
Simulation time 187159279 ps
CPU time 0.6 seconds
Started Jul 29 06:52:05 PM PDT 24
Finished Jul 29 06:52:06 PM PDT 24
Peak memory 195020 kb
Host smart-33f7ea08-7b9e-4837-9d43-609e44ac687a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819253171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.819253171
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1877321596
Short name T642
Test name
Test status
Simulation time 35957238 ps
CPU time 1.66 seconds
Started Jul 29 06:52:05 PM PDT 24
Finished Jul 29 06:52:06 PM PDT 24
Peak memory 200116 kb
Host smart-630d15b7-ce17-42ca-b94b-2826037776b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877321596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1877321596
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.62294997
Short name T589
Test name
Test status
Simulation time 133940214 ps
CPU time 1.73 seconds
Started Jul 29 06:52:05 PM PDT 24
Finished Jul 29 06:52:07 PM PDT 24
Peak memory 200156 kb
Host smart-1c23534b-ab60-4f61-a5b0-07a30162f564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62294997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.62294997
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2029906020
Short name T138
Test name
Test status
Simulation time 198937861 ps
CPU time 3.95 seconds
Started Jul 29 06:52:02 PM PDT 24
Finished Jul 29 06:52:06 PM PDT 24
Peak memory 200012 kb
Host smart-f3fd2977-6e01-409c-a2a8-f660a659c406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029906020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2029906020
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3959774574
Short name T646
Test name
Test status
Simulation time 9590611917 ps
CPU time 8.88 seconds
Started Jul 29 06:51:34 PM PDT 24
Finished Jul 29 06:51:43 PM PDT 24
Peak memory 200176 kb
Host smart-e7d4be35-a44b-4339-a513-0b4f2476fba2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959774574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3959774574
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3470831835
Short name T650
Test name
Test status
Simulation time 1642746324 ps
CPU time 16.48 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:50 PM PDT 24
Peak memory 200108 kb
Host smart-37fddf19-e983-4c21-9809-fef0c89b7656
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470831835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3470831835
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1910811225
Short name T550
Test name
Test status
Simulation time 43746851 ps
CPU time 0.76 seconds
Started Jul 29 06:51:32 PM PDT 24
Finished Jul 29 06:51:33 PM PDT 24
Peak memory 198128 kb
Host smart-018a1b5a-9d8c-4622-9567-8645eb706c57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910811225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1910811225
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4048866331
Short name T571
Test name
Test status
Simulation time 154349210 ps
CPU time 1.27 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:35 PM PDT 24
Peak memory 200180 kb
Host smart-e42534af-2483-4d3a-840a-30ccd0a9fc6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048866331 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4048866331
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.244534809
Short name T584
Test name
Test status
Simulation time 32575649 ps
CPU time 0.93 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 199964 kb
Host smart-729d6514-3ad0-4f9c-b2f0-1dee9d08282f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244534809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.244534809
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1278654000
Short name T652
Test name
Test status
Simulation time 43877284 ps
CPU time 0.6 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:34 PM PDT 24
Peak memory 195140 kb
Host smart-23602570-caa6-485d-8bb3-5983a9d15235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278654000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1278654000
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.870343559
Short name T633
Test name
Test status
Simulation time 745450251 ps
CPU time 2.19 seconds
Started Jul 29 06:51:34 PM PDT 24
Finished Jul 29 06:51:36 PM PDT 24
Peak memory 200140 kb
Host smart-dd9c2b2b-96ff-4987-b0ce-51a001bdffa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870343559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.870343559
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2590370306
Short name T534
Test name
Test status
Simulation time 157848664 ps
CPU time 1.78 seconds
Started Jul 29 06:51:34 PM PDT 24
Finished Jul 29 06:51:36 PM PDT 24
Peak memory 200108 kb
Host smart-877227ea-f5c9-43b0-a28a-634a451dcbee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590370306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2590370306
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3556204099
Short name T62
Test name
Test status
Simulation time 653643185 ps
CPU time 3.04 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:38 PM PDT 24
Peak memory 200132 kb
Host smart-35f51cad-c26a-45fa-adaa-9d471b2cb564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556204099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3556204099
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.207945410
Short name T546
Test name
Test status
Simulation time 41067517 ps
CPU time 0.56 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:13 PM PDT 24
Peak memory 194968 kb
Host smart-232f00f3-5c8b-41b5-a932-f68b6f0e8b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207945410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.207945410
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1591010937
Short name T537
Test name
Test status
Simulation time 21737935 ps
CPU time 0.6 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 194968 kb
Host smart-8dd6ed09-6875-4148-a943-ed9372adc166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591010937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1591010937
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.4276207918
Short name T581
Test name
Test status
Simulation time 18229624 ps
CPU time 0.58 seconds
Started Jul 29 06:52:11 PM PDT 24
Finished Jul 29 06:52:12 PM PDT 24
Peak memory 195152 kb
Host smart-6ac3b12c-a651-4cd3-8e17-41cf0394d029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276207918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4276207918
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4293223152
Short name T600
Test name
Test status
Simulation time 16151355 ps
CPU time 0.6 seconds
Started Jul 29 06:52:11 PM PDT 24
Finished Jul 29 06:52:12 PM PDT 24
Peak memory 195112 kb
Host smart-fbbb4d50-3381-419c-b982-e08747413b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293223152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4293223152
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.646999760
Short name T543
Test name
Test status
Simulation time 18850288 ps
CPU time 0.62 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:13 PM PDT 24
Peak memory 195204 kb
Host smart-c2ada17e-b850-464c-b90b-0acbbfdf2145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646999760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.646999760
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3507354488
Short name T577
Test name
Test status
Simulation time 18520194 ps
CPU time 0.65 seconds
Started Jul 29 06:52:11 PM PDT 24
Finished Jul 29 06:52:12 PM PDT 24
Peak memory 194996 kb
Host smart-87353d61-0849-4d37-8053-0e5e96ac18a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507354488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3507354488
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3688151739
Short name T542
Test name
Test status
Simulation time 11874300 ps
CPU time 0.64 seconds
Started Jul 29 06:52:09 PM PDT 24
Finished Jul 29 06:52:09 PM PDT 24
Peak memory 195164 kb
Host smart-d631da55-b01a-4376-8315-acdd958b93fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688151739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3688151739
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1311659701
Short name T637
Test name
Test status
Simulation time 21899971 ps
CPU time 0.56 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 195000 kb
Host smart-376e35fd-291a-43cb-802a-f493211877b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311659701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1311659701
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.840512195
Short name T545
Test name
Test status
Simulation time 16267682 ps
CPU time 0.6 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:10 PM PDT 24
Peak memory 195072 kb
Host smart-5f78c65e-9841-49cf-8c9b-43ea92854556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840512195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.840512195
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1950514221
Short name T648
Test name
Test status
Simulation time 16770248 ps
CPU time 0.64 seconds
Started Jul 29 06:52:08 PM PDT 24
Finished Jul 29 06:52:09 PM PDT 24
Peak memory 195100 kb
Host smart-48ba906e-4f06-4954-9ea4-cf27140e9a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950514221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1950514221
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1972741255
Short name T535
Test name
Test status
Simulation time 704133922 ps
CPU time 3.25 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:39 PM PDT 24
Peak memory 200056 kb
Host smart-911af40b-2eda-4fe6-8d6a-65207fba9198
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972741255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1972741255
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4143199372
Short name T623
Test name
Test status
Simulation time 373896801 ps
CPU time 5.57 seconds
Started Jul 29 06:51:39 PM PDT 24
Finished Jul 29 06:51:45 PM PDT 24
Peak memory 200028 kb
Host smart-ed7ac337-ec82-440e-bc61-25996332b517
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143199372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.4143199372
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3016002440
Short name T117
Test name
Test status
Simulation time 167629320 ps
CPU time 1 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 199420 kb
Host smart-f816cd19-3b48-4fe6-b438-83f25d96b6eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016002440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3016002440
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3732656407
Short name T597
Test name
Test status
Simulation time 161884241 ps
CPU time 1.26 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:36 PM PDT 24
Peak memory 200004 kb
Host smart-d4f812d3-2147-4b60-945a-4565a54f854b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732656407 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3732656407
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4242138500
Short name T579
Test name
Test status
Simulation time 14795879 ps
CPU time 0.6 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:36 PM PDT 24
Peak memory 195024 kb
Host smart-69d11e12-b22f-4b16-9f41-8fd050d1dcec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242138500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4242138500
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3044421873
Short name T626
Test name
Test status
Simulation time 35388190 ps
CPU time 1.57 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 200216 kb
Host smart-f88e9bc3-31bf-40b2-81ec-fb6f366a1193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044421873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3044421873
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3609871882
Short name T592
Test name
Test status
Simulation time 717058002 ps
CPU time 3.26 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 200148 kb
Host smart-e737b602-a954-4cdb-b582-4d90859f4144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609871882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3609871882
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2132424330
Short name T541
Test name
Test status
Simulation time 31674013 ps
CPU time 0.61 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:12 PM PDT 24
Peak memory 194980 kb
Host smart-bb62d795-cc2b-4f1c-a40d-b91066b317a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132424330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2132424330
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1000789905
Short name T569
Test name
Test status
Simulation time 14465031 ps
CPU time 0.58 seconds
Started Jul 29 06:52:14 PM PDT 24
Finished Jul 29 06:52:15 PM PDT 24
Peak memory 195000 kb
Host smart-e62b7175-6e09-46ba-be36-139655be38a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000789905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1000789905
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3023350940
Short name T551
Test name
Test status
Simulation time 106492958 ps
CPU time 0.58 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 195204 kb
Host smart-da5c9fb7-6f96-4e8b-91a8-8bbdcdba9cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023350940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3023350940
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.263556385
Short name T611
Test name
Test status
Simulation time 28044496 ps
CPU time 0.59 seconds
Started Jul 29 06:52:11 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 194984 kb
Host smart-9ea9c215-8e09-4e18-9eb9-dde5965ab16c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263556385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.263556385
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1745385236
Short name T636
Test name
Test status
Simulation time 31017965 ps
CPU time 0.57 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:13 PM PDT 24
Peak memory 194996 kb
Host smart-956ab06a-acc4-4d38-b34a-f86e5e0111a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745385236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1745385236
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2392584768
Short name T617
Test name
Test status
Simulation time 25517154 ps
CPU time 0.63 seconds
Started Jul 29 06:52:13 PM PDT 24
Finished Jul 29 06:52:14 PM PDT 24
Peak memory 195244 kb
Host smart-2012e262-5c49-440f-9212-7e2241667678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392584768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2392584768
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4283811542
Short name T627
Test name
Test status
Simulation time 17693896 ps
CPU time 0.63 seconds
Started Jul 29 06:52:14 PM PDT 24
Finished Jul 29 06:52:14 PM PDT 24
Peak memory 194928 kb
Host smart-9a66a08d-db90-4dd0-93bd-d0ac0ef56510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283811542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4283811542
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1631886509
Short name T632
Test name
Test status
Simulation time 67283103 ps
CPU time 0.57 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:10 PM PDT 24
Peak memory 195068 kb
Host smart-bff2bb61-a696-4401-977e-5a91c296a33c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631886509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1631886509
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2539856554
Short name T582
Test name
Test status
Simulation time 17231636 ps
CPU time 0.6 seconds
Started Jul 29 06:52:13 PM PDT 24
Finished Jul 29 06:52:14 PM PDT 24
Peak memory 195044 kb
Host smart-88736779-2a99-42c1-93a5-3c750aa2eb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539856554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2539856554
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1028687148
Short name T622
Test name
Test status
Simulation time 15167029 ps
CPU time 0.56 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:12 PM PDT 24
Peak memory 194956 kb
Host smart-fb4d7099-6e13-437e-853e-40a41fd2f61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028687148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1028687148
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1976089547
Short name T119
Test name
Test status
Simulation time 1569656055 ps
CPU time 6.49 seconds
Started Jul 29 06:51:38 PM PDT 24
Finished Jul 29 06:51:45 PM PDT 24
Peak memory 200120 kb
Host smart-f53c742a-f808-45b0-bff1-5a2d105d58b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976089547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1976089547
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3762502436
Short name T625
Test name
Test status
Simulation time 1794731953 ps
CPU time 5.37 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:40 PM PDT 24
Peak memory 198380 kb
Host smart-2c431168-e735-4ba7-b7f7-ca2bdd1222f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762502436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3762502436
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3808995899
Short name T111
Test name
Test status
Simulation time 271181650 ps
CPU time 0.86 seconds
Started Jul 29 06:51:32 PM PDT 24
Finished Jul 29 06:51:33 PM PDT 24
Peak memory 199696 kb
Host smart-1d40fad8-f68a-44d9-a661-ac6730157193
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808995899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3808995899
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1206195885
Short name T631
Test name
Test status
Simulation time 67270226 ps
CPU time 1.87 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 200216 kb
Host smart-44fe5b8a-fd84-4ca3-a005-998716b42fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206195885 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1206195885
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3849630222
Short name T106
Test name
Test status
Simulation time 44111581 ps
CPU time 0.79 seconds
Started Jul 29 06:51:34 PM PDT 24
Finished Jul 29 06:51:35 PM PDT 24
Peak memory 199396 kb
Host smart-3ea65207-0fba-4947-bf69-03d66fd77a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849630222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3849630222
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.409748649
Short name T562
Test name
Test status
Simulation time 48389225 ps
CPU time 0.62 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 195136 kb
Host smart-bdce286f-5597-4422-ab2b-f2ed65c63a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409748649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.409748649
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.62622821
Short name T629
Test name
Test status
Simulation time 100749257 ps
CPU time 1.84 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:38 PM PDT 24
Peak memory 200148 kb
Host smart-6cffeed4-5dee-4f9c-801c-2ca5dfca11d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62622821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_o
utstanding.62622821
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3685643002
Short name T552
Test name
Test status
Simulation time 374631610 ps
CPU time 3.19 seconds
Started Jul 29 06:51:34 PM PDT 24
Finished Jul 29 06:51:37 PM PDT 24
Peak memory 200132 kb
Host smart-ba85b2e6-9296-4947-8506-20a8513e7f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685643002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3685643002
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3541345631
Short name T61
Test name
Test status
Simulation time 53330576 ps
CPU time 1.75 seconds
Started Jul 29 06:51:36 PM PDT 24
Finished Jul 29 06:51:38 PM PDT 24
Peak memory 200124 kb
Host smart-0eaf9ce9-e91c-4f7d-9507-2a866ccb1255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541345631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3541345631
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1756360915
Short name T586
Test name
Test status
Simulation time 36899101 ps
CPU time 0.62 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:13 PM PDT 24
Peak memory 195056 kb
Host smart-0c92acef-0e57-437b-8722-5edeb329e53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756360915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1756360915
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3419440829
Short name T655
Test name
Test status
Simulation time 10756684 ps
CPU time 0.6 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:13 PM PDT 24
Peak memory 194960 kb
Host smart-3271d1ed-2b74-46b4-956b-a36a84d9618d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419440829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3419440829
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2055206939
Short name T616
Test name
Test status
Simulation time 73409356 ps
CPU time 0.63 seconds
Started Jul 29 06:52:13 PM PDT 24
Finished Jul 29 06:52:14 PM PDT 24
Peak memory 195136 kb
Host smart-6474b433-05ca-4da0-aced-fca5a893bcc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055206939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2055206939
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1526116433
Short name T606
Test name
Test status
Simulation time 21328446 ps
CPU time 0.56 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:13 PM PDT 24
Peak memory 195016 kb
Host smart-809812b7-203a-4d6e-bd10-81e742295c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526116433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1526116433
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3874676627
Short name T557
Test name
Test status
Simulation time 23328968 ps
CPU time 0.64 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 195024 kb
Host smart-895ebbaf-3745-4735-9cba-80a4cc0ea4d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874676627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3874676627
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3404901387
Short name T653
Test name
Test status
Simulation time 45480336 ps
CPU time 0.59 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 194984 kb
Host smart-79e71911-0f55-40ad-b3d7-4aefd1150a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404901387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3404901387
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3830470332
Short name T570
Test name
Test status
Simulation time 61556934 ps
CPU time 0.62 seconds
Started Jul 29 06:52:15 PM PDT 24
Finished Jul 29 06:52:15 PM PDT 24
Peak memory 195044 kb
Host smart-a1f31afe-2c46-4bf9-8233-1a211cda1e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830470332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3830470332
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3491746059
Short name T640
Test name
Test status
Simulation time 59595631 ps
CPU time 0.59 seconds
Started Jul 29 06:52:09 PM PDT 24
Finished Jul 29 06:52:09 PM PDT 24
Peak memory 194952 kb
Host smart-88e4e655-8a00-421e-ac18-4479ccb3215a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491746059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3491746059
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.643948293
Short name T656
Test name
Test status
Simulation time 38093156 ps
CPU time 0.69 seconds
Started Jul 29 06:52:12 PM PDT 24
Finished Jul 29 06:52:13 PM PDT 24
Peak memory 195104 kb
Host smart-3f92b473-ee90-4fe3-be42-d8f55ef74550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643948293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.643948293
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3644901272
Short name T596
Test name
Test status
Simulation time 15533982 ps
CPU time 0.58 seconds
Started Jul 29 06:52:10 PM PDT 24
Finished Jul 29 06:52:11 PM PDT 24
Peak memory 194968 kb
Host smart-104c3e61-9bc6-4568-82d5-fbaacd346b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644901272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3644901272
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.808057406
Short name T643
Test name
Test status
Simulation time 428851206 ps
CPU time 2.29 seconds
Started Jul 29 06:51:50 PM PDT 24
Finished Jul 29 06:51:52 PM PDT 24
Peak memory 200068 kb
Host smart-e9316814-b99e-49aa-81fe-6f6e19bef9b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808057406 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.808057406
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3328139498
Short name T607
Test name
Test status
Simulation time 244122674 ps
CPU time 0.97 seconds
Started Jul 29 06:51:53 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 200036 kb
Host smart-0248fcc7-7a97-4b12-b79f-ab339f9bd2f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328139498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3328139498
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3409027959
Short name T539
Test name
Test status
Simulation time 43568471 ps
CPU time 0.59 seconds
Started Jul 29 06:51:54 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 195056 kb
Host smart-a4276351-0e54-4907-9cc4-b7d1c21d7fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409027959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3409027959
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1187130667
Short name T639
Test name
Test status
Simulation time 123129637 ps
CPU time 1.57 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:53 PM PDT 24
Peak memory 200124 kb
Host smart-9e5a6d33-bc2f-4407-a956-0c2a652bcd61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187130667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1187130667
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2923673834
Short name T645
Test name
Test status
Simulation time 571677945 ps
CPU time 3.23 seconds
Started Jul 29 06:51:33 PM PDT 24
Finished Jul 29 06:51:36 PM PDT 24
Peak memory 200124 kb
Host smart-66eed70d-ff5b-4d8a-8447-5a14fc37db7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923673834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2923673834
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1370994633
Short name T137
Test name
Test status
Simulation time 82190099 ps
CPU time 2.92 seconds
Started Jul 29 06:51:35 PM PDT 24
Finished Jul 29 06:51:38 PM PDT 24
Peak memory 200128 kb
Host smart-947d4730-a844-405c-aa71-7c9255de8ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370994633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1370994633
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2133249478
Short name T553
Test name
Test status
Simulation time 238182695 ps
CPU time 1.61 seconds
Started Jul 29 06:51:53 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 200108 kb
Host smart-cf697171-63c7-48af-9390-ee59cf282455
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133249478 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2133249478
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4019226018
Short name T558
Test name
Test status
Simulation time 20547942 ps
CPU time 0.92 seconds
Started Jul 29 06:51:53 PM PDT 24
Finished Jul 29 06:51:54 PM PDT 24
Peak memory 199972 kb
Host smart-17028729-4e50-4181-bf4c-bc6196296ac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019226018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4019226018
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2863034538
Short name T591
Test name
Test status
Simulation time 13808654 ps
CPU time 0.65 seconds
Started Jul 29 06:51:54 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 195116 kb
Host smart-02805313-e3ec-492f-8ea6-2e867062d048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863034538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2863034538
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2919742468
Short name T124
Test name
Test status
Simulation time 227731753 ps
CPU time 1.2 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:53 PM PDT 24
Peak memory 199904 kb
Host smart-681e0f06-2183-44bd-8420-f6f8daaf1f25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919742468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2919742468
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2866733857
Short name T595
Test name
Test status
Simulation time 267186183 ps
CPU time 3.98 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 200124 kb
Host smart-f11d2fc6-860d-4247-962d-57427aeb70b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866733857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2866733857
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1897111693
Short name T136
Test name
Test status
Simulation time 95149636 ps
CPU time 2.86 seconds
Started Jul 29 06:51:53 PM PDT 24
Finished Jul 29 06:51:56 PM PDT 24
Peak memory 200148 kb
Host smart-0470b1fc-04a8-43f7-9508-bbb089ca346b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897111693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1897111693
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.119982192
Short name T634
Test name
Test status
Simulation time 46465755 ps
CPU time 1.45 seconds
Started Jul 29 06:51:50 PM PDT 24
Finished Jul 29 06:51:52 PM PDT 24
Peak memory 200196 kb
Host smart-868a0014-b3b8-408b-9b15-1b82e3c6012c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119982192 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.119982192
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4158153792
Short name T114
Test name
Test status
Simulation time 32073234 ps
CPU time 0.94 seconds
Started Jul 29 06:51:54 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 199884 kb
Host smart-cf735a07-6810-43dd-a09e-45fbbda9e990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158153792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4158153792
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.430923978
Short name T601
Test name
Test status
Simulation time 48544012 ps
CPU time 0.61 seconds
Started Jul 29 06:51:54 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 195184 kb
Host smart-bee41e4b-78a9-4f1c-b422-37704a4bd080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430923978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.430923978
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1735796878
Short name T575
Test name
Test status
Simulation time 88852376 ps
CPU time 1.2 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:52 PM PDT 24
Peak memory 198688 kb
Host smart-969c7f02-b675-4f26-8613-cbfc215fea5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735796878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1735796878
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1214851239
Short name T588
Test name
Test status
Simulation time 214008858 ps
CPU time 1.27 seconds
Started Jul 29 06:51:50 PM PDT 24
Finished Jul 29 06:51:52 PM PDT 24
Peak memory 200188 kb
Host smart-3bd08e11-e443-4021-ba0b-bcc1b09a4781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214851239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1214851239
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1624705267
Short name T135
Test name
Test status
Simulation time 618268863 ps
CPU time 2.82 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:54 PM PDT 24
Peak memory 200144 kb
Host smart-6cdbff46-5054-44be-ab51-3e3bbeb63360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624705267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1624705267
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3355175690
Short name T536
Test name
Test status
Simulation time 53176984086 ps
CPU time 571.82 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 07:01:23 PM PDT 24
Peak memory 213240 kb
Host smart-962d8375-6e33-4a77-8241-520dd0acb9d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355175690 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3355175690
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.554833262
Short name T559
Test name
Test status
Simulation time 108587374 ps
CPU time 0.96 seconds
Started Jul 29 06:51:52 PM PDT 24
Finished Jul 29 06:51:53 PM PDT 24
Peak memory 199888 kb
Host smart-4f1d687c-4340-4e39-99f7-2d88936f634c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554833262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.554833262
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.497461925
Short name T544
Test name
Test status
Simulation time 16510675 ps
CPU time 0.62 seconds
Started Jul 29 06:51:50 PM PDT 24
Finished Jul 29 06:51:51 PM PDT 24
Peak memory 195024 kb
Host smart-fbb46586-00c4-404c-a692-4140e7319961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497461925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.497461925
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2345620192
Short name T610
Test name
Test status
Simulation time 25917221 ps
CPU time 1.21 seconds
Started Jul 29 06:51:54 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 200156 kb
Host smart-403c0c20-f0d2-4f0a-bba9-c4a861b928b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345620192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2345620192
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1958754161
Short name T587
Test name
Test status
Simulation time 65246203 ps
CPU time 1.46 seconds
Started Jul 29 06:51:52 PM PDT 24
Finished Jul 29 06:51:53 PM PDT 24
Peak memory 200108 kb
Host smart-4b6c2a52-00d9-4a76-b667-aa66c5aa1762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958754161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1958754161
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1118243410
Short name T568
Test name
Test status
Simulation time 54521339 ps
CPU time 3.57 seconds
Started Jul 29 06:51:51 PM PDT 24
Finished Jul 29 06:51:54 PM PDT 24
Peak memory 215380 kb
Host smart-7577c050-825f-41e8-b79f-a9961d2e422a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118243410 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1118243410
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.604358273
Short name T112
Test name
Test status
Simulation time 31303525 ps
CPU time 0.86 seconds
Started Jul 29 06:51:52 PM PDT 24
Finished Jul 29 06:51:53 PM PDT 24
Peak memory 199288 kb
Host smart-d5e24474-3717-4e30-a25e-105b11ebf82f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604358273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.604358273
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3842965727
Short name T547
Test name
Test status
Simulation time 22836987 ps
CPU time 0.58 seconds
Started Jul 29 06:51:55 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 195000 kb
Host smart-b6f7e535-7a30-4b4a-b3ef-1f84879f90c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842965727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3842965727
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2615344626
Short name T120
Test name
Test status
Simulation time 30782660 ps
CPU time 1.52 seconds
Started Jul 29 06:51:52 PM PDT 24
Finished Jul 29 06:51:54 PM PDT 24
Peak memory 200308 kb
Host smart-0ccce434-6b71-4279-8d19-f2765900806d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615344626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2615344626
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.985584968
Short name T574
Test name
Test status
Simulation time 67896409 ps
CPU time 1.83 seconds
Started Jul 29 06:51:53 PM PDT 24
Finished Jul 29 06:51:55 PM PDT 24
Peak memory 200080 kb
Host smart-c3a25fd4-1042-4dd5-830f-72f8c73b08bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985584968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.985584968
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3555461661
Short name T419
Test name
Test status
Simulation time 25263126 ps
CPU time 0.6 seconds
Started Jul 29 05:22:11 PM PDT 24
Finished Jul 29 05:22:12 PM PDT 24
Peak memory 196616 kb
Host smart-4ec681f1-26d3-49d8-ace7-8a9b85d7508f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555461661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3555461661
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3261092368
Short name T349
Test name
Test status
Simulation time 4451123415 ps
CPU time 87.49 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:23:40 PM PDT 24
Peak memory 199928 kb
Host smart-5f4bd5e9-78ef-4f71-ab3d-0d4354af4ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261092368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3261092368
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3553116597
Short name T45
Test name
Test status
Simulation time 25935948945 ps
CPU time 20.87 seconds
Started Jul 29 05:22:14 PM PDT 24
Finished Jul 29 05:22:35 PM PDT 24
Peak memory 199920 kb
Host smart-25fc4693-f3f4-4966-9dca-80b0a4f28f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553116597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3553116597
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3162011061
Short name T377
Test name
Test status
Simulation time 16148347931 ps
CPU time 886.05 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:37:01 PM PDT 24
Peak memory 734584 kb
Host smart-1718839e-3fca-41c9-8eff-c3916145808a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162011061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3162011061
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2561401436
Short name T402
Test name
Test status
Simulation time 5847262522 ps
CPU time 107.44 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:24:01 PM PDT 24
Peak memory 199980 kb
Host smart-842585ad-686b-4ba7-baf5-d7d33766a53e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561401436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2561401436
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3488494670
Short name T174
Test name
Test status
Simulation time 2097261177 ps
CPU time 117.4 seconds
Started Jul 29 05:22:09 PM PDT 24
Finished Jul 29 05:24:07 PM PDT 24
Peak memory 199908 kb
Host smart-70e7f7c3-ab5d-4f01-b16f-e8a54342d083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488494670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3488494670
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2029888628
Short name T49
Test name
Test status
Simulation time 78805976 ps
CPU time 0.98 seconds
Started Jul 29 05:22:11 PM PDT 24
Finished Jul 29 05:22:12 PM PDT 24
Peak memory 219632 kb
Host smart-4c4baa4e-e583-4aff-92ec-4c91fbc59844
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029888628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2029888628
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3276043275
Short name T521
Test name
Test status
Simulation time 141020169 ps
CPU time 2.43 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:22:15 PM PDT 24
Peak memory 199860 kb
Host smart-101e949f-1748-46ea-b872-3f84be97442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276043275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3276043275
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3568434645
Short name T376
Test name
Test status
Simulation time 219650159924 ps
CPU time 1612.73 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:49:08 PM PDT 24
Peak memory 784868 kb
Host smart-7d4fb42a-4016-481c-ab9d-912d2e5d2df2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568434645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3568434645
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.938161723
Short name T71
Test name
Test status
Simulation time 73938023635 ps
CPU time 2470.01 seconds
Started Jul 29 05:22:16 PM PDT 24
Finished Jul 29 06:03:26 PM PDT 24
Peak memory 764676 kb
Host smart-9a3b8ce9-58f8-42f7-91d4-e836db278f0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938161723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.938161723
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3483835413
Short name T325
Test name
Test status
Simulation time 2507820137 ps
CPU time 44.98 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:22:58 PM PDT 24
Peak memory 199912 kb
Host smart-7a73abcd-f530-4a94-beac-9dade6ebb961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3483835413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3483835413
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.786818255
Short name T162
Test name
Test status
Simulation time 6076753219 ps
CPU time 62.75 seconds
Started Jul 29 05:22:11 PM PDT 24
Finished Jul 29 05:23:14 PM PDT 24
Peak memory 199956 kb
Host smart-21f92c16-0f3e-4863-adb6-d43808aec0cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=786818255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.786818255
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3737527694
Short name T246
Test name
Test status
Simulation time 4481841829 ps
CPU time 66.06 seconds
Started Jul 29 05:22:09 PM PDT 24
Finished Jul 29 05:23:15 PM PDT 24
Peak memory 199976 kb
Host smart-2a3deef6-4439-45ae-9343-e16d807ec1c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3737527694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3737527694
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.175779481
Short name T469
Test name
Test status
Simulation time 72664998429 ps
CPU time 665.45 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:33:17 PM PDT 24
Peak memory 199996 kb
Host smart-39825813-2beb-4584-b92d-356ae8bb0386
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=175779481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.175779481
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.4086309874
Short name T73
Test name
Test status
Simulation time 393958719041 ps
CPU time 2476.36 seconds
Started Jul 29 05:22:08 PM PDT 24
Finished Jul 29 06:03:25 PM PDT 24
Peak memory 208080 kb
Host smart-33000413-00e4-4932-8547-d353aba49c71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4086309874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.4086309874
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2075532652
Short name T93
Test name
Test status
Simulation time 37844047183 ps
CPU time 2105.28 seconds
Started Jul 29 05:22:11 PM PDT 24
Finished Jul 29 05:57:17 PM PDT 24
Peak memory 216360 kb
Host smart-1e96afcd-4e3d-4bdb-b568-1f81a809d695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2075532652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2075532652
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1509806476
Short name T492
Test name
Test status
Simulation time 2791680401 ps
CPU time 51.15 seconds
Started Jul 29 05:22:10 PM PDT 24
Finished Jul 29 05:23:01 PM PDT 24
Peak memory 200024 kb
Host smart-b192339e-5817-4e25-90f2-b008edec70c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509806476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1509806476
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.879813215
Short name T436
Test name
Test status
Simulation time 17479951 ps
CPU time 0.6 seconds
Started Jul 29 05:22:16 PM PDT 24
Finished Jul 29 05:22:17 PM PDT 24
Peak memory 195840 kb
Host smart-9672180b-81f0-4501-88c8-c90150d2748a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879813215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.879813215
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2109206010
Short name T326
Test name
Test status
Simulation time 5370887778 ps
CPU time 92.5 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:23:48 PM PDT 24
Peak memory 216260 kb
Host smart-a85e32f5-32c9-4eab-9eec-e8344dbc8609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109206010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2109206010
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.297367078
Short name T147
Test name
Test status
Simulation time 1230362354 ps
CPU time 66.29 seconds
Started Jul 29 05:22:17 PM PDT 24
Finished Jul 29 05:23:24 PM PDT 24
Peak memory 200100 kb
Host smart-6180a5e1-14ba-48ef-aa80-78ad3f037da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297367078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.297367078
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1025853074
Short name T187
Test name
Test status
Simulation time 14625861396 ps
CPU time 664.76 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:33:17 PM PDT 24
Peak memory 642788 kb
Host smart-d631af61-636a-4e4a-b7fb-520526348f7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1025853074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1025853074
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1139524246
Short name T371
Test name
Test status
Simulation time 4185417639 ps
CPU time 59.51 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:23:11 PM PDT 24
Peak memory 200044 kb
Host smart-1db37712-35e4-414f-b0d2-141455378fc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139524246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1139524246
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1125404754
Short name T313
Test name
Test status
Simulation time 27000409910 ps
CPU time 129.31 seconds
Started Jul 29 05:22:17 PM PDT 24
Finished Jul 29 05:24:26 PM PDT 24
Peak memory 200176 kb
Host smart-4e206842-09cd-43ec-b008-e5bac76b5fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125404754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1125404754
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.621252474
Short name T50
Test name
Test status
Simulation time 192295280 ps
CPU time 0.81 seconds
Started Jul 29 05:22:16 PM PDT 24
Finished Jul 29 05:22:17 PM PDT 24
Peak memory 218440 kb
Host smart-7fa716a3-2b87-48f7-b0f9-9ee815fb74ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621252474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.621252474
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2184028283
Short name T267
Test name
Test status
Simulation time 2601578072 ps
CPU time 11.94 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:22:25 PM PDT 24
Peak memory 199980 kb
Host smart-001ca83d-a19d-4623-85fd-5d46c27257ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184028283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2184028283
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4040423716
Short name T502
Test name
Test status
Simulation time 108251005977 ps
CPU time 2591.03 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 06:05:27 PM PDT 24
Peak memory 791556 kb
Host smart-f88a0907-41c0-4f6d-b9c3-271144164f0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040423716 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4040423716
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3349742878
Short name T220
Test name
Test status
Simulation time 3314336363 ps
CPU time 42.3 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:22:55 PM PDT 24
Peak memory 199948 kb
Host smart-cdb1d6ef-dbeb-4e1f-b0d5-bf1658fa6a85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3349742878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3349742878
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.590811519
Short name T59
Test name
Test status
Simulation time 10893584273 ps
CPU time 59.72 seconds
Started Jul 29 05:22:11 PM PDT 24
Finished Jul 29 05:23:11 PM PDT 24
Peak memory 200008 kb
Host smart-7a07d67b-762a-49fa-b8ba-d14a29bbf677
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=590811519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.590811519
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.3166783287
Short name T423
Test name
Test status
Simulation time 31396148900 ps
CPU time 92.55 seconds
Started Jul 29 05:22:11 PM PDT 24
Finished Jul 29 05:23:44 PM PDT 24
Peak memory 199932 kb
Host smart-ce8dc944-4546-482d-9bfa-eb253658bc67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3166783287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3166783287
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3768853685
Short name T429
Test name
Test status
Simulation time 33605632716 ps
CPU time 539.02 seconds
Started Jul 29 05:22:09 PM PDT 24
Finished Jul 29 05:31:08 PM PDT 24
Peak memory 199988 kb
Host smart-95762a4a-361f-401c-b49e-92d2293158c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3768853685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3768853685
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1463488362
Short name T166
Test name
Test status
Simulation time 39043242876 ps
CPU time 2137.74 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:57:51 PM PDT 24
Peak memory 215580 kb
Host smart-c8d8e926-793a-4e58-b83c-1027f374e9f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1463488362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1463488362
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3047841955
Short name T439
Test name
Test status
Simulation time 146609766022 ps
CPU time 2067.41 seconds
Started Jul 29 05:22:10 PM PDT 24
Finished Jul 29 05:56:38 PM PDT 24
Peak memory 215568 kb
Host smart-9d6985e2-c323-4b4f-a1a4-8a25d45b73b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3047841955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3047841955
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2277131664
Short name T399
Test name
Test status
Simulation time 641822163 ps
CPU time 32.62 seconds
Started Jul 29 05:22:10 PM PDT 24
Finished Jul 29 05:22:43 PM PDT 24
Peak memory 199840 kb
Host smart-57ca3887-edb9-4a68-81e7-38f2dcebb0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277131664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2277131664
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4103225246
Short name T408
Test name
Test status
Simulation time 2595936558 ps
CPU time 35.8 seconds
Started Jul 29 05:22:35 PM PDT 24
Finished Jul 29 05:23:11 PM PDT 24
Peak memory 199920 kb
Host smart-16fe585e-0610-4145-bc33-4cfd4409b701
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103225246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4103225246
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.349268440
Short name T381
Test name
Test status
Simulation time 793222123 ps
CPU time 43.77 seconds
Started Jul 29 05:22:34 PM PDT 24
Finished Jul 29 05:23:18 PM PDT 24
Peak memory 199812 kb
Host smart-95ab22cc-ffff-457b-b44d-848310320541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349268440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.349268440
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1350794687
Short name T25
Test name
Test status
Simulation time 6504589601 ps
CPU time 583.22 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:32:20 PM PDT 24
Peak memory 643564 kb
Host smart-26c00c6f-879a-4af5-9d6b-dd52758f7b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350794687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1350794687
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.461284614
Short name T518
Test name
Test status
Simulation time 11184628520 ps
CPU time 155.35 seconds
Started Jul 29 05:22:31 PM PDT 24
Finished Jul 29 05:25:07 PM PDT 24
Peak memory 199984 kb
Host smart-a10b2138-cc7a-4e16-8299-b9d6e2182cb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461284614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.461284614
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1287990148
Short name T229
Test name
Test status
Simulation time 81319910515 ps
CPU time 96.77 seconds
Started Jul 29 05:22:34 PM PDT 24
Finished Jul 29 05:24:11 PM PDT 24
Peak memory 200412 kb
Host smart-46fa37f8-3c9f-436c-8a84-5d19ceda6a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287990148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1287990148
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3853673515
Short name T244
Test name
Test status
Simulation time 3381852002 ps
CPU time 10.7 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:22:48 PM PDT 24
Peak memory 199976 kb
Host smart-d41a9751-b378-43d7-b61f-4ab4da50e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853673515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3853673515
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2737550226
Short name T64
Test name
Test status
Simulation time 108550276 ps
CPU time 0.67 seconds
Started Jul 29 05:22:42 PM PDT 24
Finished Jul 29 05:22:43 PM PDT 24
Peak memory 195664 kb
Host smart-06605b1a-f855-4b8e-8617-925fb20176e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737550226 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2737550226
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3931617992
Short name T321
Test name
Test status
Simulation time 13675530641 ps
CPU time 62.98 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:23:46 PM PDT 24
Peak memory 199768 kb
Host smart-9ecf1828-5609-4b34-8500-3ce2b3d3ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931617992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3931617992
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2106104234
Short name T375
Test name
Test status
Simulation time 12219739 ps
CPU time 0.6 seconds
Started Jul 29 05:22:31 PM PDT 24
Finished Jul 29 05:22:32 PM PDT 24
Peak memory 195904 kb
Host smart-61c0573f-df30-42ca-9e64-aa3dd2f9398c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106104234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2106104234
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2993448342
Short name T175
Test name
Test status
Simulation time 3072565896 ps
CPU time 87.55 seconds
Started Jul 29 05:22:33 PM PDT 24
Finished Jul 29 05:24:01 PM PDT 24
Peak memory 199960 kb
Host smart-7b741e45-7733-4638-952f-731c90518ac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993448342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2993448342
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1510039672
Short name T28
Test name
Test status
Simulation time 1429524946 ps
CPU time 20.3 seconds
Started Jul 29 05:22:31 PM PDT 24
Finished Jul 29 05:22:52 PM PDT 24
Peak memory 199868 kb
Host smart-c2573b31-cf7b-4d60-a18d-ee571d452470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510039672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1510039672
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4164191672
Short name T409
Test name
Test status
Simulation time 3239187526 ps
CPU time 567.51 seconds
Started Jul 29 05:22:41 PM PDT 24
Finished Jul 29 05:32:09 PM PDT 24
Peak memory 713268 kb
Host smart-36e0d0bb-4cec-48ca-8b51-92e219eeeb16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164191672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4164191672
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3700559430
Short name T340
Test name
Test status
Simulation time 11444353162 ps
CPU time 207.26 seconds
Started Jul 29 05:22:36 PM PDT 24
Finished Jul 29 05:26:03 PM PDT 24
Peak memory 199992 kb
Host smart-a33a2f07-5abc-4360-b220-43ed7790a81f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700559430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3700559430
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1319102138
Short name T528
Test name
Test status
Simulation time 2191712729 ps
CPU time 92.23 seconds
Started Jul 29 05:22:32 PM PDT 24
Finished Jul 29 05:24:05 PM PDT 24
Peak memory 199924 kb
Host smart-b1b78926-a235-4d61-bce2-25bcece00803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319102138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1319102138
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2837936142
Short name T248
Test name
Test status
Simulation time 1635433767 ps
CPU time 6.22 seconds
Started Jul 29 05:22:42 PM PDT 24
Finished Jul 29 05:22:48 PM PDT 24
Peak memory 199836 kb
Host smart-78e9178f-7c7a-43da-a60e-a316e5aacf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837936142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2837936142
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.538379861
Short name T473
Test name
Test status
Simulation time 40072378864 ps
CPU time 1485.04 seconds
Started Jul 29 05:22:34 PM PDT 24
Finished Jul 29 05:47:20 PM PDT 24
Peak memory 705884 kb
Host smart-102f3adb-7e56-43dc-93b8-32cc3e6221a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538379861 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.538379861
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2662404939
Short name T155
Test name
Test status
Simulation time 112169479 ps
CPU time 2.31 seconds
Started Jul 29 05:22:42 PM PDT 24
Finished Jul 29 05:22:44 PM PDT 24
Peak memory 199780 kb
Host smart-b49ff8b6-1b1f-4aed-872f-62ef52a08fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662404939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2662404939
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3607028335
Short name T44
Test name
Test status
Simulation time 11212366 ps
CPU time 0.55 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:22:38 PM PDT 24
Peak memory 194872 kb
Host smart-bdb12080-73e2-4cc9-b685-eb49c7be8359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607028335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3607028335
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1494328344
Short name T525
Test name
Test status
Simulation time 3275809572 ps
CPU time 37.35 seconds
Started Jul 29 05:22:38 PM PDT 24
Finished Jul 29 05:23:16 PM PDT 24
Peak memory 199944 kb
Host smart-fabc2dba-dc88-485d-9543-61384c90f564
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494328344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1494328344
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1444696327
Short name T56
Test name
Test status
Simulation time 1623085357 ps
CPU time 5.85 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:22:43 PM PDT 24
Peak memory 199844 kb
Host smart-a09e7ce6-3903-4699-ade1-b74526e1125a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444696327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1444696327
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4062799396
Short name T315
Test name
Test status
Simulation time 48919455053 ps
CPU time 749.87 seconds
Started Jul 29 05:22:38 PM PDT 24
Finished Jul 29 05:35:08 PM PDT 24
Peak memory 605192 kb
Host smart-f0f00525-4d42-443f-afe7-5736ab2c8141
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062799396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4062799396
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1051097257
Short name T1
Test name
Test status
Simulation time 10760185402 ps
CPU time 138.94 seconds
Started Jul 29 05:22:46 PM PDT 24
Finished Jul 29 05:25:06 PM PDT 24
Peak memory 199740 kb
Host smart-37bc699e-4e4f-4096-87b6-58e91d210b46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051097257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1051097257
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2707639501
Short name T275
Test name
Test status
Simulation time 12381666418 ps
CPU time 56.9 seconds
Started Jul 29 05:22:42 PM PDT 24
Finished Jul 29 05:23:39 PM PDT 24
Peak memory 200016 kb
Host smart-c43d5844-44a6-48b0-8b9f-f57e75c0985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707639501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2707639501
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1364290827
Short name T421
Test name
Test status
Simulation time 104809538 ps
CPU time 1.63 seconds
Started Jul 29 05:22:33 PM PDT 24
Finished Jul 29 05:22:35 PM PDT 24
Peak memory 199852 kb
Host smart-ed8bc784-9fcf-4319-bd81-73567c29daf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364290827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1364290827
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.4193180436
Short name T82
Test name
Test status
Simulation time 710886261814 ps
CPU time 2284.27 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 06:00:41 PM PDT 24
Peak memory 733168 kb
Host smart-5c75ab2d-0465-445d-981a-216b473b0e88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193180436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4193180436
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.723516100
Short name T453
Test name
Test status
Simulation time 5516643062 ps
CPU time 72.03 seconds
Started Jul 29 05:22:44 PM PDT 24
Finished Jul 29 05:23:56 PM PDT 24
Peak memory 199772 kb
Host smart-4f7f9762-aa39-4b83-8f85-1df662310871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723516100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.723516100
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2070043805
Short name T281
Test name
Test status
Simulation time 119768152 ps
CPU time 0.58 seconds
Started Jul 29 05:22:41 PM PDT 24
Finished Jul 29 05:22:41 PM PDT 24
Peak memory 196556 kb
Host smart-14fa33ce-a802-472d-84c0-e3d54fcc63ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070043805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2070043805
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2498867102
Short name T156
Test name
Test status
Simulation time 2452564405 ps
CPU time 40.25 seconds
Started Jul 29 05:22:39 PM PDT 24
Finished Jul 29 05:23:19 PM PDT 24
Peak memory 216056 kb
Host smart-6abab6c5-3cbe-4055-adce-169eab689ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498867102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2498867102
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3306430074
Short name T55
Test name
Test status
Simulation time 89678557404 ps
CPU time 781.37 seconds
Started Jul 29 05:22:41 PM PDT 24
Finished Jul 29 05:35:42 PM PDT 24
Peak memory 693240 kb
Host smart-08747596-474b-4fa3-aaba-aca84ed0f9d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306430074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3306430074
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2249160022
Short name T290
Test name
Test status
Simulation time 8675082481 ps
CPU time 37.96 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:23:15 PM PDT 24
Peak memory 200008 kb
Host smart-b413a21a-1c54-44ea-be9e-25c36b869ee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249160022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2249160022
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.509283821
Short name T214
Test name
Test status
Simulation time 1785221313 ps
CPU time 98.86 seconds
Started Jul 29 05:22:41 PM PDT 24
Finished Jul 29 05:24:20 PM PDT 24
Peak memory 199824 kb
Host smart-4046a7a1-ce21-44eb-91e6-11b5baaf18c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509283821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.509283821
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.4078117257
Short name T165
Test name
Test status
Simulation time 58088518 ps
CPU time 2.44 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:22:40 PM PDT 24
Peak memory 199832 kb
Host smart-90bfb6f7-0e13-4464-b832-d6a6b8a024a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078117257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4078117257
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.504347334
Short name T363
Test name
Test status
Simulation time 765305299967 ps
CPU time 1630.55 seconds
Started Jul 29 05:22:38 PM PDT 24
Finished Jul 29 05:49:48 PM PDT 24
Peak memory 758768 kb
Host smart-2954b0dd-0d83-454f-9789-01992f096c36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504347334 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.504347334
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.888604755
Short name T225
Test name
Test status
Simulation time 892082519 ps
CPU time 40.41 seconds
Started Jul 29 05:22:38 PM PDT 24
Finished Jul 29 05:23:18 PM PDT 24
Peak memory 199788 kb
Host smart-ac2404a5-4eb1-4f5d-808c-155f2ab5718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888604755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.888604755
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.540851710
Short name T440
Test name
Test status
Simulation time 12165442 ps
CPU time 0.57 seconds
Started Jul 29 05:22:42 PM PDT 24
Finished Jul 29 05:22:42 PM PDT 24
Peak memory 195844 kb
Host smart-e8391659-2449-43c1-a3ea-de0d38c797a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540851710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.540851710
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.4136264532
Short name T505
Test name
Test status
Simulation time 856557889 ps
CPU time 33.84 seconds
Started Jul 29 05:22:39 PM PDT 24
Finished Jul 29 05:23:13 PM PDT 24
Peak memory 199740 kb
Host smart-5b5c4300-1a92-4b68-870c-f80193b80fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136264532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4136264532
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2524352052
Short name T258
Test name
Test status
Simulation time 1503595658 ps
CPU time 30.11 seconds
Started Jul 29 05:22:39 PM PDT 24
Finished Jul 29 05:23:09 PM PDT 24
Peak memory 199864 kb
Host smart-31d80fef-fa3a-4115-bf2b-af0e3d7bf76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524352052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2524352052
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3832628731
Short name T370
Test name
Test status
Simulation time 5622884245 ps
CPU time 220.17 seconds
Started Jul 29 05:22:45 PM PDT 24
Finished Jul 29 05:26:25 PM PDT 24
Peak memory 614108 kb
Host smart-504a1f0d-1af5-45f9-86b8-b4a0510d850a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832628731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3832628731
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2702266860
Short name T404
Test name
Test status
Simulation time 6374154947 ps
CPU time 70.68 seconds
Started Jul 29 05:22:44 PM PDT 24
Finished Jul 29 05:23:55 PM PDT 24
Peak memory 199928 kb
Host smart-39e3d597-c39e-49cf-9504-a203f60b46ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702266860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2702266860
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2407054760
Short name T385
Test name
Test status
Simulation time 22762137131 ps
CPU time 68.92 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:23:46 PM PDT 24
Peak memory 199952 kb
Host smart-3aaa808a-1eb8-4965-9015-64a8e5c6c86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407054760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2407054760
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1253066643
Short name T268
Test name
Test status
Simulation time 3058771774 ps
CPU time 12.8 seconds
Started Jul 29 05:22:41 PM PDT 24
Finished Jul 29 05:22:53 PM PDT 24
Peak memory 200128 kb
Host smart-b2b1de8f-3a03-4771-a49e-908b539a38db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253066643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1253066643
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2078187149
Short name T208
Test name
Test status
Simulation time 14521370929 ps
CPU time 41.07 seconds
Started Jul 29 05:22:42 PM PDT 24
Finished Jul 29 05:23:23 PM PDT 24
Peak memory 199984 kb
Host smart-af742956-6d8f-4c45-a5c7-7d62820dddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078187149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2078187149
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1041482183
Short name T41
Test name
Test status
Simulation time 13209930 ps
CPU time 0.59 seconds
Started Jul 29 05:22:45 PM PDT 24
Finished Jul 29 05:22:46 PM PDT 24
Peak memory 195564 kb
Host smart-4f1f00cd-3286-40ce-a213-af19206a4aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041482183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1041482183
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2943447409
Short name T311
Test name
Test status
Simulation time 5410256097 ps
CPU time 76.5 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:24:00 PM PDT 24
Peak memory 200208 kb
Host smart-c06b7363-21d8-42a2-b12b-15f9f57c4897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943447409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2943447409
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3965498142
Short name T420
Test name
Test status
Simulation time 7303221667 ps
CPU time 31.17 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:23:15 PM PDT 24
Peak memory 199944 kb
Host smart-27630d9e-2df8-42ab-bdf4-4273247c7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965498142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3965498142
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2792390405
Short name T460
Test name
Test status
Simulation time 1275421374 ps
CPU time 208.46 seconds
Started Jul 29 05:22:46 PM PDT 24
Finished Jul 29 05:26:14 PM PDT 24
Peak memory 443312 kb
Host smart-e6344dd3-d7ed-45e4-9484-2b32c8cefde3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792390405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2792390405
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.618022980
Short name T454
Test name
Test status
Simulation time 3140000860 ps
CPU time 84.81 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:24:08 PM PDT 24
Peak memory 199980 kb
Host smart-6189ce87-5529-41c3-a303-8f56db24ab13
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618022980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.618022980
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1792120589
Short name T488
Test name
Test status
Simulation time 24035912741 ps
CPU time 147.73 seconds
Started Jul 29 05:22:45 PM PDT 24
Finished Jul 29 05:25:13 PM PDT 24
Peak memory 199960 kb
Host smart-c7fe983b-3578-4f89-9a32-b70a27aa721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792120589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1792120589
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1064955670
Short name T352
Test name
Test status
Simulation time 3128802098 ps
CPU time 9.69 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:22:53 PM PDT 24
Peak memory 200016 kb
Host smart-7aeea59a-3474-4c31-9ec3-3756c7ced943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064955670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1064955670
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.558724531
Short name T81
Test name
Test status
Simulation time 132014357169 ps
CPU time 2818.93 seconds
Started Jul 29 05:22:42 PM PDT 24
Finished Jul 29 06:09:41 PM PDT 24
Peak memory 784120 kb
Host smart-7bbecc2e-b270-44d6-a875-0fb5ca9b0f48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558724531 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.558724531
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.455114556
Short name T233
Test name
Test status
Simulation time 310380912 ps
CPU time 5.72 seconds
Started Jul 29 05:22:46 PM PDT 24
Finished Jul 29 05:22:51 PM PDT 24
Peak memory 199716 kb
Host smart-d8c68013-f238-44d2-8934-08b254b886dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455114556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.455114556
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3698302191
Short name T219
Test name
Test status
Simulation time 94544053 ps
CPU time 0.56 seconds
Started Jul 29 05:22:50 PM PDT 24
Finished Jul 29 05:22:51 PM PDT 24
Peak memory 195904 kb
Host smart-24fcaa73-ff22-4765-8b40-d4bffdd7f49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698302191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3698302191
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3581006920
Short name T204
Test name
Test status
Simulation time 500558054 ps
CPU time 25.99 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:23:09 PM PDT 24
Peak memory 199840 kb
Host smart-22ff2ab4-78af-457d-85d9-a117e6df5096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581006920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3581006920
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3891590835
Short name T339
Test name
Test status
Simulation time 1005167050 ps
CPU time 20.26 seconds
Started Jul 29 05:22:44 PM PDT 24
Finished Jul 29 05:23:05 PM PDT 24
Peak memory 199784 kb
Host smart-b548e147-f173-4571-b317-5b85432185c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891590835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3891590835
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3780168978
Short name T157
Test name
Test status
Simulation time 1063552347 ps
CPU time 26.41 seconds
Started Jul 29 05:22:44 PM PDT 24
Finished Jul 29 05:23:10 PM PDT 24
Peak memory 246552 kb
Host smart-bd46517e-519f-4263-ba1e-b735ea215bf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780168978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3780168978
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2569464989
Short name T274
Test name
Test status
Simulation time 13745734084 ps
CPU time 174.99 seconds
Started Jul 29 05:22:47 PM PDT 24
Finished Jul 29 05:25:43 PM PDT 24
Peak memory 199984 kb
Host smart-04ec57d2-275a-440e-a030-87ec80c82dae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569464989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2569464989
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2457117067
Short name T317
Test name
Test status
Simulation time 5831620975 ps
CPU time 71.9 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:23:55 PM PDT 24
Peak memory 216252 kb
Host smart-92d575f9-49a7-4f6f-9417-29667729be4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457117067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2457117067
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4216851393
Short name T256
Test name
Test status
Simulation time 2964451512 ps
CPU time 16.46 seconds
Started Jul 29 05:22:43 PM PDT 24
Finished Jul 29 05:22:59 PM PDT 24
Peak memory 200144 kb
Host smart-cff8fed6-98ed-4be8-8b50-57199c8ab2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216851393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4216851393
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1781749105
Short name T314
Test name
Test status
Simulation time 136690010702 ps
CPU time 612.26 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:33:01 PM PDT 24
Peak memory 199884 kb
Host smart-4817e061-3d40-42b7-bb48-781a798c6e88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781749105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1781749105
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3599339969
Short name T231
Test name
Test status
Simulation time 11363137734 ps
CPU time 22.69 seconds
Started Jul 29 05:22:46 PM PDT 24
Finished Jul 29 05:23:09 PM PDT 24
Peak memory 200004 kb
Host smart-daa06a0b-deb9-4ef9-9a5d-41d025f80fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599339969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3599339969
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4139554446
Short name T261
Test name
Test status
Simulation time 50156261 ps
CPU time 0.56 seconds
Started Jul 29 05:22:48 PM PDT 24
Finished Jul 29 05:22:49 PM PDT 24
Peak memory 195868 kb
Host smart-f0adf08b-352a-4196-ac74-9bbbf5bb81bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139554446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4139554446
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.642025648
Short name T433
Test name
Test status
Simulation time 275557287 ps
CPU time 15.27 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:23:04 PM PDT 24
Peak memory 199848 kb
Host smart-08d1c636-73c3-4de7-b6cc-cbf65b34ed1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642025648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.642025648
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.97981371
Short name T391
Test name
Test status
Simulation time 6604135176 ps
CPU time 1227.97 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:43:17 PM PDT 24
Peak memory 762928 kb
Host smart-5464ebf5-0eb2-4748-926e-72dc6c4b7585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97981371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.97981371
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.369100722
Short name T236
Test name
Test status
Simulation time 6304111908 ps
CPU time 38.44 seconds
Started Jul 29 05:22:51 PM PDT 24
Finished Jul 29 05:23:30 PM PDT 24
Peak memory 200152 kb
Host smart-ff15fd31-4646-40bc-80b6-7bf9bcb28805
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369100722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.369100722
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3732347393
Short name T507
Test name
Test status
Simulation time 5714760752 ps
CPU time 46.78 seconds
Started Jul 29 05:22:50 PM PDT 24
Finished Jul 29 05:23:37 PM PDT 24
Peak memory 200008 kb
Host smart-cbbc86d2-740f-44bf-9e2c-e3f8e31f77cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732347393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3732347393
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1615033623
Short name T26
Test name
Test status
Simulation time 716843532 ps
CPU time 12.57 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:23:02 PM PDT 24
Peak memory 199888 kb
Host smart-2d588ab2-c1a1-41f2-a75f-a2400a872995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615033623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1615033623
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2856350149
Short name T335
Test name
Test status
Simulation time 2617459966 ps
CPU time 24.51 seconds
Started Jul 29 05:22:47 PM PDT 24
Finished Jul 29 05:23:12 PM PDT 24
Peak memory 200016 kb
Host smart-9b9cf064-b970-4737-8793-04217a1565bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856350149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2856350149
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1801357032
Short name T27
Test name
Test status
Simulation time 42646348 ps
CPU time 0.6 seconds
Started Jul 29 05:22:50 PM PDT 24
Finished Jul 29 05:22:50 PM PDT 24
Peak memory 195856 kb
Host smart-f6337262-68f4-42b8-8e7e-d91005f0783b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801357032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1801357032
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3037988417
Short name T154
Test name
Test status
Simulation time 186776584 ps
CPU time 3.01 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:23:02 PM PDT 24
Peak memory 199560 kb
Host smart-75f4dd29-d34b-4975-b1db-60e0c2e9bf3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037988417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3037988417
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3368325805
Short name T209
Test name
Test status
Simulation time 14520691851 ps
CPU time 49.69 seconds
Started Jul 29 05:22:47 PM PDT 24
Finished Jul 29 05:23:37 PM PDT 24
Peak memory 199976 kb
Host smart-45d7d5d6-f2ef-434d-99b6-5dfd518c961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368325805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3368325805
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1389095730
Short name T89
Test name
Test status
Simulation time 2760658795 ps
CPU time 266.73 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:27:26 PM PDT 24
Peak memory 477520 kb
Host smart-ea7852d1-82c8-42d0-a403-dc2798f5ac3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389095730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1389095730
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2400314492
Short name T515
Test name
Test status
Simulation time 4696662479 ps
CPU time 268.48 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:27:18 PM PDT 24
Peak memory 199968 kb
Host smart-0d3a54b1-f06a-4e44-971a-55bc1e24b3aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400314492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2400314492
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2190266578
Short name T203
Test name
Test status
Simulation time 4414888990 ps
CPU time 57.32 seconds
Started Jul 29 05:23:01 PM PDT 24
Finished Jul 29 05:23:58 PM PDT 24
Peak memory 199760 kb
Host smart-a8d61976-ccc9-40f2-bcd2-5633633692b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190266578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2190266578
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3041135568
Short name T98
Test name
Test status
Simulation time 1287436144 ps
CPU time 15.88 seconds
Started Jul 29 05:22:51 PM PDT 24
Finished Jul 29 05:23:07 PM PDT 24
Peak memory 199984 kb
Host smart-f24b4d72-71bd-4fbf-a634-96c414361b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041135568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3041135568
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2434359243
Short name T222
Test name
Test status
Simulation time 3102102540 ps
CPU time 73.5 seconds
Started Jul 29 05:22:50 PM PDT 24
Finished Jul 29 05:24:04 PM PDT 24
Peak memory 199964 kb
Host smart-43d255f7-dab2-44a9-b85e-3a6633c0f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434359243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2434359243
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3630216153
Short name T372
Test name
Test status
Simulation time 12643456 ps
CPU time 0.56 seconds
Started Jul 29 05:22:52 PM PDT 24
Finished Jul 29 05:22:52 PM PDT 24
Peak memory 194888 kb
Host smart-60f4ea7a-fd8a-48ac-a19c-06b6f6936279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630216153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3630216153
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1062305052
Short name T316
Test name
Test status
Simulation time 2951139550 ps
CPU time 78.87 seconds
Started Jul 29 05:22:48 PM PDT 24
Finished Jul 29 05:24:07 PM PDT 24
Peak memory 199952 kb
Host smart-8f14a0ee-216d-49b9-b512-08aad7fecaa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062305052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1062305052
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1092705029
Short name T495
Test name
Test status
Simulation time 1254544279 ps
CPU time 16.76 seconds
Started Jul 29 05:22:54 PM PDT 24
Finished Jul 29 05:23:11 PM PDT 24
Peak memory 199792 kb
Host smart-34883b73-0b1a-44d8-9ca1-4519a04f4ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092705029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1092705029
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2896201571
Short name T224
Test name
Test status
Simulation time 29498953688 ps
CPU time 1474.65 seconds
Started Jul 29 05:23:01 PM PDT 24
Finished Jul 29 05:47:36 PM PDT 24
Peak memory 795000 kb
Host smart-6ff0bc2e-b762-4b73-9cc4-cac9bce65cfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896201571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2896201571
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2348975510
Short name T431
Test name
Test status
Simulation time 6999942524 ps
CPU time 30.42 seconds
Started Jul 29 05:22:54 PM PDT 24
Finished Jul 29 05:23:24 PM PDT 24
Peak memory 199956 kb
Host smart-c68a7bf8-7e0a-4a13-9c15-5a6f4dc40fbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348975510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2348975510
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4149111975
Short name T169
Test name
Test status
Simulation time 24665924918 ps
CPU time 142.75 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:25:12 PM PDT 24
Peak memory 216264 kb
Host smart-ce333682-08e6-4166-a890-3752820ba8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149111975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4149111975
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1015614213
Short name T46
Test name
Test status
Simulation time 323644123 ps
CPU time 14.95 seconds
Started Jul 29 05:22:49 PM PDT 24
Finished Jul 29 05:23:04 PM PDT 24
Peak memory 199804 kb
Host smart-539471aa-e4c6-450a-a9df-106f02c9c614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015614213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1015614213
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2280416585
Short name T150
Test name
Test status
Simulation time 31427856282 ps
CPU time 1378.63 seconds
Started Jul 29 05:22:53 PM PDT 24
Finished Jul 29 05:45:52 PM PDT 24
Peak memory 658960 kb
Host smart-f436a721-7190-4c77-ba57-98248c3d48f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280416585 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2280416585
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2625095008
Short name T484
Test name
Test status
Simulation time 9547358915 ps
CPU time 47.07 seconds
Started Jul 29 05:22:52 PM PDT 24
Finished Jul 29 05:23:40 PM PDT 24
Peak memory 199960 kb
Host smart-8cc75f67-8cc8-4377-8626-b36e158f3d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625095008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2625095008
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.522911197
Short name T51
Test name
Test status
Simulation time 16624630 ps
CPU time 0.58 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:22:16 PM PDT 24
Peak memory 194892 kb
Host smart-418baeb4-933b-48b7-9f02-ac414ba51d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522911197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.522911197
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.677029327
Short name T332
Test name
Test status
Simulation time 851816033 ps
CPU time 23.78 seconds
Started Jul 29 05:22:25 PM PDT 24
Finished Jul 29 05:22:49 PM PDT 24
Peak memory 199800 kb
Host smart-e0ccb11c-0aaa-4242-a658-ec49e02ffada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677029327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.677029327
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1848033978
Short name T449
Test name
Test status
Simulation time 202915357 ps
CPU time 10.93 seconds
Started Jul 29 05:22:14 PM PDT 24
Finished Jul 29 05:22:25 PM PDT 24
Peak memory 199896 kb
Host smart-e0337d7e-abda-4608-8b51-ba55be56184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848033978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1848033978
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3041372823
Short name T211
Test name
Test status
Simulation time 10603813736 ps
CPU time 603.28 seconds
Started Jul 29 05:22:18 PM PDT 24
Finished Jul 29 05:32:22 PM PDT 24
Peak memory 714960 kb
Host smart-3e3d5837-5e56-4410-83be-354d7502df29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3041372823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3041372823
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.794248102
Short name T532
Test name
Test status
Simulation time 21968620800 ps
CPU time 195.57 seconds
Started Jul 29 05:22:18 PM PDT 24
Finished Jul 29 05:25:34 PM PDT 24
Peak memory 199980 kb
Host smart-316ffe87-09d6-4ffd-8911-15c566a14fb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794248102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.794248102
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.145249084
Short name T30
Test name
Test status
Simulation time 4064361306 ps
CPU time 73.83 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:23:29 PM PDT 24
Peak memory 199912 kb
Host smart-f2099685-84ea-4726-859a-285dbc27d597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145249084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.145249084
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.638134590
Short name T32
Test name
Test status
Simulation time 46393827 ps
CPU time 0.81 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:22:14 PM PDT 24
Peak memory 218524 kb
Host smart-454264c2-2645-4940-a2d5-4c4f1f6bd547
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638134590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.638134590
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2864980113
Short name T471
Test name
Test status
Simulation time 326726130 ps
CPU time 14.31 seconds
Started Jul 29 05:22:14 PM PDT 24
Finished Jul 29 05:22:28 PM PDT 24
Peak memory 199864 kb
Host smart-5fce3148-5a96-4ae1-8259-7001c5a6aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864980113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2864980113
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.780887074
Short name T8
Test name
Test status
Simulation time 19090698337 ps
CPU time 507.11 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:30:40 PM PDT 24
Peak memory 199984 kb
Host smart-8a95ea5c-b3d7-4e2e-8255-0fc201dabad1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780887074 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.780887074
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1675532531
Short name T10
Test name
Test status
Simulation time 293718784462 ps
CPU time 2046.19 seconds
Started Jul 29 05:22:14 PM PDT 24
Finished Jul 29 05:56:21 PM PDT 24
Peak memory 734932 kb
Host smart-dd54a1ba-0e4e-462e-82f3-9eb799544ff8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675532531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1675532531
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2519661810
Short name T412
Test name
Test status
Simulation time 6202122838 ps
CPU time 72.59 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:23:26 PM PDT 24
Peak memory 199912 kb
Host smart-fc7cd588-9fcc-470a-b478-697004276f21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2519661810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2519661810
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3372178774
Short name T298
Test name
Test status
Simulation time 12147409223 ps
CPU time 67.96 seconds
Started Jul 29 05:22:17 PM PDT 24
Finished Jul 29 05:23:25 PM PDT 24
Peak memory 199976 kb
Host smart-eb1a11ef-3854-403d-a240-ce2d110df64b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3372178774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3372178774
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.688239981
Short name T213
Test name
Test status
Simulation time 9013088876 ps
CPU time 77.78 seconds
Started Jul 29 05:22:12 PM PDT 24
Finished Jul 29 05:23:30 PM PDT 24
Peak memory 200012 kb
Host smart-ffae3e8b-1cb0-4d26-9a98-5de86966206e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=688239981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.688239981
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3548657226
Short name T194
Test name
Test status
Simulation time 361579534969 ps
CPU time 636.77 seconds
Started Jul 29 05:22:17 PM PDT 24
Finished Jul 29 05:32:54 PM PDT 24
Peak memory 200180 kb
Host smart-4057e135-7949-4569-8de0-a711e2ab9ae5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3548657226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3548657226
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2238746702
Short name T171
Test name
Test status
Simulation time 136297213880 ps
CPU time 1913.91 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:54:10 PM PDT 24
Peak memory 215296 kb
Host smart-ec8f3474-3b02-47b6-8d18-294cfdcd26a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2238746702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2238746702
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1433287911
Short name T143
Test name
Test status
Simulation time 129467509748 ps
CPU time 2163.84 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:58:17 PM PDT 24
Peak memory 215908 kb
Host smart-ecbd827b-3991-4602-92fe-b2df4d734a67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1433287911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1433287911
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4073815847
Short name T226
Test name
Test status
Simulation time 27884546576 ps
CPU time 121.78 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:24:15 PM PDT 24
Peak memory 199916 kb
Host smart-58b1c002-a1bc-40ec-a145-3dae3c0962f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073815847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4073815847
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1248746755
Short name T310
Test name
Test status
Simulation time 11376737 ps
CPU time 0.58 seconds
Started Jul 29 05:23:01 PM PDT 24
Finished Jul 29 05:23:01 PM PDT 24
Peak memory 195920 kb
Host smart-24f3f867-8818-43fa-a0c5-2f7854c10a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248746755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1248746755
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.290765280
Short name T197
Test name
Test status
Simulation time 127285789 ps
CPU time 7.56 seconds
Started Jul 29 05:22:54 PM PDT 24
Finished Jul 29 05:23:02 PM PDT 24
Peak memory 199836 kb
Host smart-9c3c8ca3-fa9f-4e9e-9f4d-bbcc61e0488c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290765280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.290765280
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2841560929
Short name T343
Test name
Test status
Simulation time 1887559844 ps
CPU time 49.06 seconds
Started Jul 29 05:22:54 PM PDT 24
Finished Jul 29 05:23:43 PM PDT 24
Peak memory 199772 kb
Host smart-00daa162-61b6-4d2b-b7cb-b4526a08c00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841560929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2841560929
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.4220757315
Short name T178
Test name
Test status
Simulation time 5006504124 ps
CPU time 826.77 seconds
Started Jul 29 05:22:53 PM PDT 24
Finished Jul 29 05:36:40 PM PDT 24
Peak memory 695768 kb
Host smart-dabbc567-97e0-4326-806b-98fee7c565f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220757315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.4220757315
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3547223162
Short name T253
Test name
Test status
Simulation time 611047785 ps
CPU time 16.61 seconds
Started Jul 29 05:22:53 PM PDT 24
Finished Jul 29 05:23:10 PM PDT 24
Peak memory 199792 kb
Host smart-177f68ef-a337-4bb7-b8e3-86a93b6d9d9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547223162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3547223162
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3801429175
Short name T39
Test name
Test status
Simulation time 26437380879 ps
CPU time 183.12 seconds
Started Jul 29 05:22:53 PM PDT 24
Finished Jul 29 05:25:56 PM PDT 24
Peak memory 200392 kb
Host smart-d4ce86f4-773b-459d-9c7a-81352e04eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801429175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3801429175
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.481735235
Short name T422
Test name
Test status
Simulation time 1897573256 ps
CPU time 7.26 seconds
Started Jul 29 05:22:55 PM PDT 24
Finished Jul 29 05:23:02 PM PDT 24
Peak memory 199920 kb
Host smart-4e2ffe5a-3b01-4d31-971c-5ce7d4aea02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481735235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.481735235
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3359268604
Short name T446
Test name
Test status
Simulation time 47052688630 ps
CPU time 104.83 seconds
Started Jul 29 05:22:53 PM PDT 24
Finished Jul 29 05:24:38 PM PDT 24
Peak memory 200160 kb
Host smart-f1c34683-649e-4ec6-9ddf-120d75981c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359268604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3359268604
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3026258870
Short name T450
Test name
Test status
Simulation time 12617892 ps
CPU time 0.59 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:22:59 PM PDT 24
Peak memory 195844 kb
Host smart-caf3d015-0702-4dd0-b34b-1414f03ce277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026258870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3026258870
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1323552508
Short name T486
Test name
Test status
Simulation time 2290979767 ps
CPU time 64.73 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:24:07 PM PDT 24
Peak memory 199900 kb
Host smart-3b79e342-7b5d-4740-9d2d-57a3898d9bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323552508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1323552508
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.740048446
Short name T499
Test name
Test status
Simulation time 1400026322 ps
CPU time 17.85 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:23:20 PM PDT 24
Peak memory 199684 kb
Host smart-9d48a79e-c815-438c-92e4-04079bced3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740048446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.740048446
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3047173024
Short name T512
Test name
Test status
Simulation time 6332828354 ps
CPU time 1111.46 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:41:33 PM PDT 24
Peak memory 774552 kb
Host smart-df22a3ac-58b0-4df9-b587-ce1a5863ea4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047173024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3047173024
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3124335217
Short name T87
Test name
Test status
Simulation time 1140045939 ps
CPU time 57.8 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:23:57 PM PDT 24
Peak memory 199832 kb
Host smart-9a324679-178f-4fe9-aa02-3116ffaad953
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124335217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3124335217
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2052984712
Short name T177
Test name
Test status
Simulation time 10044615719 ps
CPU time 119.96 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:24:59 PM PDT 24
Peak memory 199888 kb
Host smart-2c10814e-b33c-4385-907d-7a363157fbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052984712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2052984712
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1219731381
Short name T239
Test name
Test status
Simulation time 3102294111 ps
CPU time 10.36 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:23:13 PM PDT 24
Peak memory 199756 kb
Host smart-20856abf-57e0-4eee-95ea-d199e9cf76ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219731381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1219731381
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3722102753
Short name T374
Test name
Test status
Simulation time 39944166888 ps
CPU time 824.74 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:36:44 PM PDT 24
Peak memory 627876 kb
Host smart-3eb3107c-b130-48b5-aee5-ee519f25df23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722102753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3722102753
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2156817324
Short name T102
Test name
Test status
Simulation time 4229356665 ps
CPU time 44.9 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:23:44 PM PDT 24
Peak memory 199900 kb
Host smart-926b8eaa-5f51-4998-a70e-f47c183be8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156817324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2156817324
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2368766474
Short name T345
Test name
Test status
Simulation time 14412342 ps
CPU time 0.6 seconds
Started Jul 29 05:23:06 PM PDT 24
Finished Jul 29 05:23:07 PM PDT 24
Peak memory 194832 kb
Host smart-a50753a0-a583-45a2-b260-5d04af302121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368766474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2368766474
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2668711881
Short name T20
Test name
Test status
Simulation time 259500080 ps
CPU time 2.62 seconds
Started Jul 29 05:23:00 PM PDT 24
Finished Jul 29 05:23:02 PM PDT 24
Peak memory 199912 kb
Host smart-fb10418c-611b-490e-a5ff-c4441644e2d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668711881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2668711881
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.90773094
Short name T336
Test name
Test status
Simulation time 1614344393 ps
CPU time 8.2 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:23:07 PM PDT 24
Peak memory 199868 kb
Host smart-cfd5511f-2668-45f1-b8e7-1f2dc1c0c337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90773094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.90773094
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.718050405
Short name T432
Test name
Test status
Simulation time 32552149725 ps
CPU time 964.69 seconds
Started Jul 29 05:23:01 PM PDT 24
Finished Jul 29 05:39:06 PM PDT 24
Peak memory 743760 kb
Host smart-c3edd866-399b-4127-9a18-b030b450b5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718050405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.718050405
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1592540406
Short name T159
Test name
Test status
Simulation time 22518151027 ps
CPU time 63.29 seconds
Started Jul 29 05:23:04 PM PDT 24
Finished Jul 29 05:24:07 PM PDT 24
Peak memory 199984 kb
Host smart-dd38e7f5-bf3c-4180-a234-6d435d3bc2d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592540406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1592540406
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3536308642
Short name T383
Test name
Test status
Simulation time 8864682551 ps
CPU time 109.72 seconds
Started Jul 29 05:22:59 PM PDT 24
Finished Jul 29 05:24:49 PM PDT 24
Peak memory 199968 kb
Host smart-7d418052-ff26-4569-a112-bde42dc1037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536308642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3536308642
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.484286423
Short name T161
Test name
Test status
Simulation time 558949677 ps
CPU time 2.26 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:23:04 PM PDT 24
Peak memory 199808 kb
Host smart-608cdf87-f055-474e-9d05-825ccc69c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484286423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.484286423
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3129184170
Short name T183
Test name
Test status
Simulation time 117275213181 ps
CPU time 1288.33 seconds
Started Jul 29 05:23:03 PM PDT 24
Finished Jul 29 05:44:32 PM PDT 24
Peak memory 661724 kb
Host smart-5ba77dae-81e6-453d-ac7e-fc86a3c00faa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129184170 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3129184170
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.194377546
Short name T288
Test name
Test status
Simulation time 8771405405 ps
CPU time 58.53 seconds
Started Jul 29 05:23:07 PM PDT 24
Finished Jul 29 05:24:06 PM PDT 24
Peak memory 199768 kb
Host smart-bb987430-f080-4121-ae7c-d215337508b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194377546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.194377546
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2586431250
Short name T191
Test name
Test status
Simulation time 40821098 ps
CPU time 0.55 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:23:02 PM PDT 24
Peak memory 194756 kb
Host smart-7dc71862-4b91-4feb-bf5d-f94aabee3933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586431250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2586431250
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.179134628
Short name T510
Test name
Test status
Simulation time 807517203 ps
CPU time 47.63 seconds
Started Jul 29 05:23:04 PM PDT 24
Finished Jul 29 05:23:51 PM PDT 24
Peak memory 199780 kb
Host smart-be4f1279-663c-4ab3-a380-081533f53b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179134628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.179134628
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.926462008
Short name T74
Test name
Test status
Simulation time 942563669 ps
CPU time 48.51 seconds
Started Jul 29 05:23:06 PM PDT 24
Finished Jul 29 05:23:55 PM PDT 24
Peak memory 199848 kb
Host smart-e137af74-5b6c-4015-8999-fa1a661cd439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926462008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.926462008
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2080092587
Short name T357
Test name
Test status
Simulation time 9914404553 ps
CPU time 380.01 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:29:22 PM PDT 24
Peak memory 503352 kb
Host smart-5fddb5e2-8533-4ae7-9122-753d2673f955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080092587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2080092587
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3994009450
Short name T494
Test name
Test status
Simulation time 5470334943 ps
CPU time 163.8 seconds
Started Jul 29 05:23:04 PM PDT 24
Finished Jul 29 05:25:48 PM PDT 24
Peak memory 199996 kb
Host smart-4977812c-9cf6-4078-88ae-49f3cc5d4cde
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994009450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3994009450
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3863348974
Short name T186
Test name
Test status
Simulation time 7169193690 ps
CPU time 30.81 seconds
Started Jul 29 05:23:05 PM PDT 24
Finished Jul 29 05:23:36 PM PDT 24
Peak memory 199964 kb
Host smart-dec6d038-8ecd-4912-abad-e8fff2334577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863348974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3863348974
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3656895631
Short name T172
Test name
Test status
Simulation time 1355434287 ps
CPU time 16.85 seconds
Started Jul 29 05:23:05 PM PDT 24
Finished Jul 29 05:23:22 PM PDT 24
Peak memory 199860 kb
Host smart-25839789-6346-42fc-b998-1467531f719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656895631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3656895631
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1326548356
Short name T85
Test name
Test status
Simulation time 170632343079 ps
CPU time 1082.5 seconds
Started Jul 29 05:23:05 PM PDT 24
Finished Jul 29 05:41:08 PM PDT 24
Peak memory 711048 kb
Host smart-b5314c49-122f-4f7f-b447-1c51601fcadf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326548356 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1326548356
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3820116957
Short name T368
Test name
Test status
Simulation time 14213438507 ps
CPU time 100.52 seconds
Started Jul 29 05:23:10 PM PDT 24
Finished Jul 29 05:24:51 PM PDT 24
Peak memory 199928 kb
Host smart-94193b83-dd0e-42cb-bada-34c6396d219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820116957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3820116957
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.250593810
Short name T232
Test name
Test status
Simulation time 16096621 ps
CPU time 0.57 seconds
Started Jul 29 05:23:12 PM PDT 24
Finished Jul 29 05:23:13 PM PDT 24
Peak memory 195596 kb
Host smart-90b01d5e-0862-44c1-9198-b16f5cdd6842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250593810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.250593810
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1998475826
Short name T5
Test name
Test status
Simulation time 2827418997 ps
CPU time 75.43 seconds
Started Jul 29 05:23:06 PM PDT 24
Finished Jul 29 05:24:22 PM PDT 24
Peak memory 200036 kb
Host smart-8e4af0c1-f6cb-4546-a53c-dd17381a678e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998475826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1998475826
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3222879349
Short name T277
Test name
Test status
Simulation time 423407923 ps
CPU time 6.15 seconds
Started Jul 29 05:23:08 PM PDT 24
Finished Jul 29 05:23:15 PM PDT 24
Peak memory 199820 kb
Host smart-9e9e459f-9624-4bdf-baca-0bdadd6c2a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222879349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3222879349
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3777981084
Short name T389
Test name
Test status
Simulation time 29011536264 ps
CPU time 1297.61 seconds
Started Jul 29 05:23:08 PM PDT 24
Finished Jul 29 05:44:46 PM PDT 24
Peak memory 755856 kb
Host smart-63f1bbc6-0bae-4b19-85be-56784a1bb56e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777981084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3777981084
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2177734605
Short name T251
Test name
Test status
Simulation time 242172838 ps
CPU time 11.67 seconds
Started Jul 29 05:23:07 PM PDT 24
Finished Jul 29 05:23:19 PM PDT 24
Peak memory 199812 kb
Host smart-c6ef2b80-2267-4ec6-83b2-8d4378861ef4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177734605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2177734605
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1461896557
Short name T443
Test name
Test status
Simulation time 2836548145 ps
CPU time 40.81 seconds
Started Jul 29 05:23:10 PM PDT 24
Finished Jul 29 05:23:51 PM PDT 24
Peak memory 199956 kb
Host smart-99597ca6-8cc5-4e4a-b5b6-720ae0780ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461896557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1461896557
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2564649751
Short name T456
Test name
Test status
Simulation time 8595670341 ps
CPU time 11.72 seconds
Started Jul 29 05:23:02 PM PDT 24
Finished Jul 29 05:23:14 PM PDT 24
Peak memory 199924 kb
Host smart-cd1fafca-1d90-46a1-8062-753f3286f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564649751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2564649751
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.392948292
Short name T293
Test name
Test status
Simulation time 191203553326 ps
CPU time 1197.73 seconds
Started Jul 29 05:23:11 PM PDT 24
Finished Jul 29 05:43:09 PM PDT 24
Peak memory 676856 kb
Host smart-10277861-f79f-4d11-ac42-7a0f9da4291d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392948292 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.392948292
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2624596757
Short name T300
Test name
Test status
Simulation time 1531653095 ps
CPU time 2.79 seconds
Started Jul 29 05:23:09 PM PDT 24
Finished Jul 29 05:23:12 PM PDT 24
Peak memory 199804 kb
Host smart-699036cf-9d0f-4d0a-8469-d4c0bb3915a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624596757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2624596757
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3682619042
Short name T243
Test name
Test status
Simulation time 12003771 ps
CPU time 0.57 seconds
Started Jul 29 05:23:14 PM PDT 24
Finished Jul 29 05:23:15 PM PDT 24
Peak memory 195524 kb
Host smart-85373db7-7f73-49d4-a9d8-d6f6ecd28a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682619042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3682619042
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.74779528
Short name T482
Test name
Test status
Simulation time 3358029726 ps
CPU time 103.73 seconds
Started Jul 29 05:23:08 PM PDT 24
Finished Jul 29 05:24:52 PM PDT 24
Peak memory 208156 kb
Host smart-059f0425-4d51-41bd-9a03-00bb648b4368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74779528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.74779528
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3881332129
Short name T503
Test name
Test status
Simulation time 26496963970 ps
CPU time 1128.04 seconds
Started Jul 29 05:23:10 PM PDT 24
Finished Jul 29 05:41:58 PM PDT 24
Peak memory 679196 kb
Host smart-d198eb41-859b-460f-b9d1-b3d88f5566f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881332129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3881332129
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3682942368
Short name T414
Test name
Test status
Simulation time 471752960 ps
CPU time 9.05 seconds
Started Jul 29 05:23:08 PM PDT 24
Finished Jul 29 05:23:17 PM PDT 24
Peak memory 199792 kb
Host smart-1a84c7b6-efa4-48ae-9e99-8e30c04d109a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682942368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3682942368
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3100619679
Short name T435
Test name
Test status
Simulation time 2708005481 ps
CPU time 15.09 seconds
Started Jul 29 05:23:08 PM PDT 24
Finished Jul 29 05:23:23 PM PDT 24
Peak memory 199928 kb
Host smart-78c8310f-643a-4ce4-aedd-8c17fbc31423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100619679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3100619679
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2171036749
Short name T212
Test name
Test status
Simulation time 8878336787 ps
CPU time 12.85 seconds
Started Jul 29 05:23:10 PM PDT 24
Finished Jul 29 05:23:23 PM PDT 24
Peak memory 199948 kb
Host smart-3d4d8d55-ab48-4cbf-b53e-d059e14288d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171036749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2171036749
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2224464839
Short name T394
Test name
Test status
Simulation time 1810972915 ps
CPU time 96.02 seconds
Started Jul 29 05:23:12 PM PDT 24
Finished Jul 29 05:24:49 PM PDT 24
Peak memory 199804 kb
Host smart-6bc4c714-5663-4376-b2ed-2f0344ab4b01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224464839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2224464839
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.4090978564
Short name T387
Test name
Test status
Simulation time 806674818 ps
CPU time 34.85 seconds
Started Jul 29 05:23:11 PM PDT 24
Finished Jul 29 05:23:46 PM PDT 24
Peak memory 199848 kb
Host smart-08ee36f7-7a58-447d-85f9-1190742048e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090978564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.4090978564
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3420571371
Short name T328
Test name
Test status
Simulation time 33590061 ps
CPU time 0.58 seconds
Started Jul 29 05:23:19 PM PDT 24
Finished Jul 29 05:23:20 PM PDT 24
Peak memory 195840 kb
Host smart-ef7c3319-5c38-451e-af80-2e32d78a75d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420571371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3420571371
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.696064600
Short name T465
Test name
Test status
Simulation time 15993854819 ps
CPU time 57.13 seconds
Started Jul 29 05:23:15 PM PDT 24
Finished Jul 29 05:24:12 PM PDT 24
Peak memory 199892 kb
Host smart-a5ccd879-a3ed-464a-9be7-6f967e62a171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696064600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.696064600
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2507976224
Short name T470
Test name
Test status
Simulation time 8739251783 ps
CPU time 27.79 seconds
Started Jul 29 05:23:19 PM PDT 24
Finished Jul 29 05:23:47 PM PDT 24
Peak memory 215484 kb
Host smart-e9f47582-dfbf-4581-a67d-23a30b3ad027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507976224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2507976224
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3429963391
Short name T205
Test name
Test status
Simulation time 10001628447 ps
CPU time 989.41 seconds
Started Jul 29 05:23:17 PM PDT 24
Finished Jul 29 05:39:46 PM PDT 24
Peak memory 686148 kb
Host smart-e1b492ef-6140-403b-a0c2-47e9c3991883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3429963391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3429963391
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3605996735
Short name T195
Test name
Test status
Simulation time 88280263591 ps
CPU time 265.27 seconds
Started Jul 29 05:23:19 PM PDT 24
Finished Jul 29 05:27:44 PM PDT 24
Peak memory 199936 kb
Host smart-5c92dad5-af1f-47c5-b63e-a9d2543795e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605996735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3605996735
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2472168423
Short name T88
Test name
Test status
Simulation time 17154594256 ps
CPU time 90.86 seconds
Started Jul 29 05:23:16 PM PDT 24
Finished Jul 29 05:24:47 PM PDT 24
Peak memory 199952 kb
Host smart-a33ba9af-6f9d-47fe-8b32-a4b30a638938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472168423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2472168423
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2952545419
Short name T217
Test name
Test status
Simulation time 3839333956 ps
CPU time 12.78 seconds
Started Jul 29 05:23:13 PM PDT 24
Finished Jul 29 05:23:26 PM PDT 24
Peak memory 199944 kb
Host smart-f84256a6-f994-4e58-aaf8-f930cbf9ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952545419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2952545419
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1580498579
Short name T333
Test name
Test status
Simulation time 23295837828 ps
CPU time 3309.11 seconds
Started Jul 29 05:23:21 PM PDT 24
Finished Jul 29 06:18:30 PM PDT 24
Peak memory 840540 kb
Host smart-3cf4d1fc-5d4d-495d-937c-5ccf4a799361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580498579 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1580498579
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.116100065
Short name T54
Test name
Test status
Simulation time 34583265991 ps
CPU time 118.3 seconds
Started Jul 29 05:23:22 PM PDT 24
Finished Jul 29 05:25:20 PM PDT 24
Peak memory 199976 kb
Host smart-e2e52d01-ad3a-4fe2-9c68-6c654b254fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116100065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.116100065
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2294046338
Short name T185
Test name
Test status
Simulation time 11074649 ps
CPU time 0.54 seconds
Started Jul 29 05:23:24 PM PDT 24
Finished Jul 29 05:23:25 PM PDT 24
Peak memory 194888 kb
Host smart-81657a90-0d5d-4d4b-8709-3b69eae29888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294046338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2294046338
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1141658738
Short name T279
Test name
Test status
Simulation time 5455057482 ps
CPU time 39.62 seconds
Started Jul 29 05:23:18 PM PDT 24
Finished Jul 29 05:23:58 PM PDT 24
Peak memory 199960 kb
Host smart-298c8340-7340-4478-b209-66a2369544b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141658738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1141658738
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3497589688
Short name T380
Test name
Test status
Simulation time 655936382 ps
CPU time 11.06 seconds
Started Jul 29 05:23:22 PM PDT 24
Finished Jul 29 05:23:34 PM PDT 24
Peak memory 199888 kb
Host smart-800c945e-447b-4d3a-aa69-80b04312bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497589688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3497589688
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3159958872
Short name T297
Test name
Test status
Simulation time 12870827044 ps
CPU time 594.69 seconds
Started Jul 29 05:23:19 PM PDT 24
Finished Jul 29 05:33:14 PM PDT 24
Peak memory 513028 kb
Host smart-4a0dec98-3b2a-48d1-9521-24d9111e2342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159958872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3159958872
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.789042813
Short name T295
Test name
Test status
Simulation time 7180215987 ps
CPU time 108.6 seconds
Started Jul 29 05:23:29 PM PDT 24
Finished Jul 29 05:25:18 PM PDT 24
Peak memory 199996 kb
Host smart-fd6bc1f5-496b-436f-bc93-5a01a855cd04
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789042813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.789042813
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4099991088
Short name T344
Test name
Test status
Simulation time 1456606215 ps
CPU time 27.1 seconds
Started Jul 29 05:23:20 PM PDT 24
Finished Jul 29 05:23:47 PM PDT 24
Peak memory 199816 kb
Host smart-3ff4aa8d-7fcd-40cc-af2e-3c022e369da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099991088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4099991088
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3269113400
Short name T337
Test name
Test status
Simulation time 4429886374 ps
CPU time 15.1 seconds
Started Jul 29 05:23:19 PM PDT 24
Finished Jul 29 05:23:34 PM PDT 24
Peak memory 199992 kb
Host smart-bfc5e95b-4ce1-4788-9b75-ba9508f24dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269113400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3269113400
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.4227845000
Short name T529
Test name
Test status
Simulation time 526888553463 ps
CPU time 2714.3 seconds
Started Jul 29 05:23:24 PM PDT 24
Finished Jul 29 06:08:38 PM PDT 24
Peak memory 723672 kb
Host smart-58449763-2ef5-43b3-8003-5d439c6e61b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227845000 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.4227845000
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.63995152
Short name T77
Test name
Test status
Simulation time 8374724365 ps
CPU time 119.13 seconds
Started Jul 29 05:23:23 PM PDT 24
Finished Jul 29 05:25:22 PM PDT 24
Peak memory 199920 kb
Host smart-c41b288e-e047-43ff-b4a3-b44a801c5c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63995152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.63995152
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1128838996
Short name T468
Test name
Test status
Simulation time 15062067 ps
CPU time 0.65 seconds
Started Jul 29 05:23:30 PM PDT 24
Finished Jul 29 05:23:30 PM PDT 24
Peak memory 195860 kb
Host smart-9d5714a7-aee9-445c-9aec-74c9cd589c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128838996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1128838996
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.255077917
Short name T312
Test name
Test status
Simulation time 601433853 ps
CPU time 34.73 seconds
Started Jul 29 05:23:25 PM PDT 24
Finished Jul 29 05:24:00 PM PDT 24
Peak memory 199820 kb
Host smart-2b8f00dc-9caa-4f1c-96a6-9615a8695c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255077917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.255077917
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1833412338
Short name T437
Test name
Test status
Simulation time 16351514337 ps
CPU time 24.06 seconds
Started Jul 29 05:23:29 PM PDT 24
Finished Jul 29 05:23:53 PM PDT 24
Peak memory 199964 kb
Host smart-26d86f6f-a4d0-4ed1-91bd-75e34e0109ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833412338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1833412338
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3886349148
Short name T338
Test name
Test status
Simulation time 8701216279 ps
CPU time 458.96 seconds
Started Jul 29 05:23:41 PM PDT 24
Finished Jul 29 05:31:20 PM PDT 24
Peak memory 693336 kb
Host smart-8267a61d-2f75-4dd0-9133-59cca19194e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886349148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3886349148
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1928194394
Short name T278
Test name
Test status
Simulation time 58173482179 ps
CPU time 179.05 seconds
Started Jul 29 05:23:24 PM PDT 24
Finished Jul 29 05:26:23 PM PDT 24
Peak memory 199988 kb
Host smart-bb485ed4-2d44-4ad6-a568-ea92fa6cb2fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928194394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1928194394
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.140737925
Short name T94
Test name
Test status
Simulation time 1423279924 ps
CPU time 86.38 seconds
Started Jul 29 05:23:24 PM PDT 24
Finished Jul 29 05:24:50 PM PDT 24
Peak memory 199836 kb
Host smart-61df32fa-2c18-4c1b-ae46-290c304286a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140737925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.140737925
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.832445760
Short name T262
Test name
Test status
Simulation time 1243487097 ps
CPU time 12.34 seconds
Started Jul 29 05:23:25 PM PDT 24
Finished Jul 29 05:23:37 PM PDT 24
Peak memory 199840 kb
Host smart-7271398b-9951-4fec-bf23-fefea9184042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832445760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.832445760
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2806852053
Short name T80
Test name
Test status
Simulation time 36267898975 ps
CPU time 434.28 seconds
Started Jul 29 05:23:30 PM PDT 24
Finished Jul 29 05:30:44 PM PDT 24
Peak memory 216304 kb
Host smart-876e1e3e-40e3-4e5b-b3f1-0f5a2c37545d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806852053 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2806852053
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.510624757
Short name T504
Test name
Test status
Simulation time 11787652458 ps
CPU time 139.55 seconds
Started Jul 29 05:23:29 PM PDT 24
Finished Jul 29 05:25:49 PM PDT 24
Peak memory 200000 kb
Host smart-c5090ab4-af9d-40e5-b2fa-862248460db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510624757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.510624757
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3366035576
Short name T285
Test name
Test status
Simulation time 11693563 ps
CPU time 0.6 seconds
Started Jul 29 05:23:33 PM PDT 24
Finished Jul 29 05:23:33 PM PDT 24
Peak memory 195904 kb
Host smart-d5db1048-9a5d-4645-9d44-7dc313748d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366035576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3366035576
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1784131760
Short name T491
Test name
Test status
Simulation time 497616676 ps
CPU time 29.59 seconds
Started Jul 29 05:23:27 PM PDT 24
Finished Jul 29 05:23:57 PM PDT 24
Peak memory 199824 kb
Host smart-14c6bfb8-a235-44e6-aeea-ff1a17bdb06d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784131760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1784131760
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2126106958
Short name T361
Test name
Test status
Simulation time 4588495497 ps
CPU time 58.63 seconds
Started Jul 29 05:23:30 PM PDT 24
Finished Jul 29 05:24:28 PM PDT 24
Peak memory 200048 kb
Host smart-08308667-0f6a-4989-8068-5862d5e3eab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126106958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2126106958
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1319348471
Short name T223
Test name
Test status
Simulation time 170474616 ps
CPU time 17.67 seconds
Started Jul 29 05:23:31 PM PDT 24
Finished Jul 29 05:23:48 PM PDT 24
Peak memory 236528 kb
Host smart-0586d993-5035-4fce-adea-8a84af2e495d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319348471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1319348471
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2631460818
Short name T407
Test name
Test status
Simulation time 25358305779 ps
CPU time 126.09 seconds
Started Jul 29 05:23:30 PM PDT 24
Finished Jul 29 05:25:37 PM PDT 24
Peak memory 200132 kb
Host smart-146d7c45-b1f5-4bd4-858f-34cbc50620ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631460818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2631460818
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2126652319
Short name T324
Test name
Test status
Simulation time 2033535280 ps
CPU time 113.83 seconds
Started Jul 29 05:23:29 PM PDT 24
Finished Jul 29 05:25:23 PM PDT 24
Peak memory 199848 kb
Host smart-433124ac-d769-4334-a66c-64ac9682af07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126652319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2126652319
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2680537256
Short name T523
Test name
Test status
Simulation time 153171883 ps
CPU time 2.84 seconds
Started Jul 29 05:23:28 PM PDT 24
Finished Jul 29 05:23:31 PM PDT 24
Peak memory 199848 kb
Host smart-fee2bfe2-41a1-4f64-8a41-5b7d4b8b2201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680537256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2680537256
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3123246099
Short name T35
Test name
Test status
Simulation time 9165257303 ps
CPU time 526.98 seconds
Started Jul 29 05:23:33 PM PDT 24
Finished Jul 29 05:32:20 PM PDT 24
Peak memory 199988 kb
Host smart-9e97c135-520e-4913-a716-9110cad5c9e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123246099 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3123246099
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.44600711
Short name T459
Test name
Test status
Simulation time 7922379203 ps
CPU time 94.79 seconds
Started Jul 29 05:23:34 PM PDT 24
Finished Jul 29 05:25:09 PM PDT 24
Peak memory 200012 kb
Host smart-f31ffb91-f06a-418d-9002-fad9a06cac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44600711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.44600711
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3466921955
Short name T384
Test name
Test status
Simulation time 38006637 ps
CPU time 0.55 seconds
Started Jul 29 05:22:23 PM PDT 24
Finished Jul 29 05:22:24 PM PDT 24
Peak memory 194756 kb
Host smart-ab564e00-1722-4585-8166-7493962b836b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466921955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3466921955
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.514124605
Short name T37
Test name
Test status
Simulation time 23943938599 ps
CPU time 83.65 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:23:37 PM PDT 24
Peak memory 200244 kb
Host smart-205ca09f-1500-4c7d-9293-6e6409e09768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514124605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.514124605
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2175131555
Short name T305
Test name
Test status
Simulation time 3372151123 ps
CPU time 45.16 seconds
Started Jul 29 05:22:18 PM PDT 24
Finished Jul 29 05:23:04 PM PDT 24
Peak memory 200236 kb
Host smart-a19f18b8-ae4a-4114-a214-a04df46676bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175131555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2175131555
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3473950316
Short name T176
Test name
Test status
Simulation time 4582468087 ps
CPU time 745.74 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:34:41 PM PDT 24
Peak memory 702080 kb
Host smart-59cd401f-7033-4d75-85ab-2c6041df6557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3473950316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3473950316
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2157655332
Short name T509
Test name
Test status
Simulation time 12789542083 ps
CPU time 181.79 seconds
Started Jul 29 05:22:18 PM PDT 24
Finished Jul 29 05:25:20 PM PDT 24
Peak memory 199916 kb
Host smart-5c157be5-a760-4de0-955e-22d635d3c833
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157655332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2157655332
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2504403677
Short name T424
Test name
Test status
Simulation time 175423644 ps
CPU time 3.56 seconds
Started Jul 29 05:22:13 PM PDT 24
Finished Jul 29 05:22:17 PM PDT 24
Peak memory 199852 kb
Host smart-9f83cf45-246c-429a-901b-0181056b35a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504403677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2504403677
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3304702880
Short name T48
Test name
Test status
Simulation time 121765684 ps
CPU time 0.94 seconds
Started Jul 29 05:22:23 PM PDT 24
Finished Jul 29 05:22:24 PM PDT 24
Peak memory 219288 kb
Host smart-0632e8bd-5d1c-483b-9570-af9e9a2cf170
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304702880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3304702880
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.189907189
Short name T302
Test name
Test status
Simulation time 1372091731 ps
CPU time 15.38 seconds
Started Jul 29 05:22:17 PM PDT 24
Finished Jul 29 05:22:32 PM PDT 24
Peak memory 199872 kb
Host smart-697d3525-6723-4839-910c-cf64addfba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189907189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.189907189
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2602356208
Short name T348
Test name
Test status
Simulation time 118898448177 ps
CPU time 820.9 seconds
Started Jul 29 05:22:21 PM PDT 24
Finished Jul 29 05:36:03 PM PDT 24
Peak memory 669504 kb
Host smart-145ab6a7-4583-416d-b60a-0da1728dba99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602356208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2602356208
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2042099733
Short name T427
Test name
Test status
Simulation time 1601303992 ps
CPU time 66.33 seconds
Started Jul 29 05:22:14 PM PDT 24
Finished Jul 29 05:23:21 PM PDT 24
Peak memory 199844 kb
Host smart-6b409957-8946-4326-a872-d68759102300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2042099733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2042099733
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.687724590
Short name T514
Test name
Test status
Simulation time 2301293705 ps
CPU time 82.5 seconds
Started Jul 29 05:22:18 PM PDT 24
Finished Jul 29 05:23:40 PM PDT 24
Peak memory 199912 kb
Host smart-14fd1fb2-24d3-4acb-8b35-4a660d67cd43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=687724590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.687724590
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1053991543
Short name T97
Test name
Test status
Simulation time 18984848805 ps
CPU time 113.12 seconds
Started Jul 29 05:22:23 PM PDT 24
Finished Jul 29 05:24:16 PM PDT 24
Peak memory 199936 kb
Host smart-e16b9d1b-e576-47d1-a477-7579e79cd80c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1053991543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1053991543
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.188440370
Short name T342
Test name
Test status
Simulation time 27574332420 ps
CPU time 613.21 seconds
Started Jul 29 05:22:15 PM PDT 24
Finished Jul 29 05:32:29 PM PDT 24
Peak memory 199984 kb
Host smart-46d00e2c-f1ff-49bb-b672-522937a4f582
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=188440370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.188440370
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.305254047
Short name T498
Test name
Test status
Simulation time 705552751122 ps
CPU time 2347.34 seconds
Started Jul 29 05:22:18 PM PDT 24
Finished Jul 29 06:01:26 PM PDT 24
Peak memory 215928 kb
Host smart-42d52aae-f5d3-459a-88b4-d82ad8bf2bef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=305254047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.305254047
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3849186763
Short name T142
Test name
Test status
Simulation time 130245960271 ps
CPU time 2188.47 seconds
Started Jul 29 05:22:14 PM PDT 24
Finished Jul 29 05:58:43 PM PDT 24
Peak memory 215372 kb
Host smart-6f01b8aa-4268-435a-b64d-3fd2918765c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3849186763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3849186763
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.430683534
Short name T101
Test name
Test status
Simulation time 47442355071 ps
CPU time 50.3 seconds
Started Jul 29 05:22:18 PM PDT 24
Finished Jul 29 05:23:08 PM PDT 24
Peak memory 199988 kb
Host smart-303a24a6-db51-4e8a-87f1-a1796e9e2ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430683534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.430683534
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.674437933
Short name T286
Test name
Test status
Simulation time 16987681 ps
CPU time 0.59 seconds
Started Jul 29 05:23:39 PM PDT 24
Finished Jul 29 05:23:39 PM PDT 24
Peak memory 195868 kb
Host smart-8ae2d644-8f40-4693-aac5-eced75b40cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674437933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.674437933
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1314151321
Short name T283
Test name
Test status
Simulation time 8994635058 ps
CPU time 97.3 seconds
Started Jul 29 05:23:36 PM PDT 24
Finished Jul 29 05:25:13 PM PDT 24
Peak memory 200008 kb
Host smart-5175a996-12af-4759-8d96-12f2d8d7488a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314151321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1314151321
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1544955888
Short name T489
Test name
Test status
Simulation time 1929838517 ps
CPU time 38.25 seconds
Started Jul 29 05:23:35 PM PDT 24
Finished Jul 29 05:24:13 PM PDT 24
Peak memory 199852 kb
Host smart-ac83f1a9-4c56-41f5-ae3d-3fc8a0fcacbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544955888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1544955888
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2657853144
Short name T301
Test name
Test status
Simulation time 1048952000 ps
CPU time 155.61 seconds
Started Jul 29 05:23:35 PM PDT 24
Finished Jul 29 05:26:10 PM PDT 24
Peak memory 351276 kb
Host smart-c9e85206-e8fa-4a75-9458-3eade79f6577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657853144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2657853144
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3532816472
Short name T75
Test name
Test status
Simulation time 14652573886 ps
CPU time 84.23 seconds
Started Jul 29 05:23:34 PM PDT 24
Finished Jul 29 05:24:58 PM PDT 24
Peak memory 199968 kb
Host smart-12bd3d0c-731f-43c6-af7c-418a5673a5de
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532816472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3532816472
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1119521906
Short name T38
Test name
Test status
Simulation time 6400695537 ps
CPU time 86.11 seconds
Started Jul 29 05:23:33 PM PDT 24
Finished Jul 29 05:24:59 PM PDT 24
Peak memory 199956 kb
Host smart-3e946c9f-86b2-4c7a-ba01-82e55306904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119521906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1119521906
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2155359760
Short name T347
Test name
Test status
Simulation time 337246678 ps
CPU time 3.5 seconds
Started Jul 29 05:23:33 PM PDT 24
Finished Jul 29 05:23:36 PM PDT 24
Peak memory 199812 kb
Host smart-16567986-8dd1-4f5f-8814-6447f939847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155359760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2155359760
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3633745327
Short name T373
Test name
Test status
Simulation time 135585714293 ps
CPU time 3143.49 seconds
Started Jul 29 05:23:35 PM PDT 24
Finished Jul 29 06:15:59 PM PDT 24
Peak memory 804016 kb
Host smart-c8e4aa04-9437-4bc0-920b-4da780ae7bce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633745327 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3633745327
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2546832338
Short name T207
Test name
Test status
Simulation time 29873882138 ps
CPU time 93.68 seconds
Started Jul 29 05:23:34 PM PDT 24
Finished Jul 29 05:25:08 PM PDT 24
Peak memory 199968 kb
Host smart-e2bc65e8-7e27-4062-ad6f-08c54f279cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546832338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2546832338
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1327369414
Short name T506
Test name
Test status
Simulation time 40442636 ps
CPU time 0.64 seconds
Started Jul 29 05:23:39 PM PDT 24
Finished Jul 29 05:23:40 PM PDT 24
Peak memory 196124 kb
Host smart-3370bd45-f3c8-48ab-84aa-7b4c72c03ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327369414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1327369414
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3419826488
Short name T13
Test name
Test status
Simulation time 497484156 ps
CPU time 28.12 seconds
Started Jul 29 05:23:43 PM PDT 24
Finished Jul 29 05:24:11 PM PDT 24
Peak memory 199828 kb
Host smart-2cd6161d-195f-41ad-8497-7d2cc84a0a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419826488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3419826488
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1957448340
Short name T444
Test name
Test status
Simulation time 16103941437 ps
CPU time 54.1 seconds
Started Jul 29 05:23:40 PM PDT 24
Finished Jul 29 05:24:35 PM PDT 24
Peak memory 199980 kb
Host smart-fdbc7325-c342-4c18-846e-a7f28adcfc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957448340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1957448340
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.990855567
Short name T90
Test name
Test status
Simulation time 881244612 ps
CPU time 144.9 seconds
Started Jul 29 05:23:39 PM PDT 24
Finished Jul 29 05:26:04 PM PDT 24
Peak memory 458916 kb
Host smart-6ed8817b-4fac-44a9-93a3-72aa3a9e6c63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=990855567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.990855567
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.4124128804
Short name T271
Test name
Test status
Simulation time 28222885135 ps
CPU time 177.71 seconds
Started Jul 29 05:23:39 PM PDT 24
Finished Jul 29 05:26:36 PM PDT 24
Peak memory 199984 kb
Host smart-edb06755-7767-4c14-9c6e-7ce4c85c76f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124128804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4124128804
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.714822813
Short name T403
Test name
Test status
Simulation time 10129197772 ps
CPU time 173.29 seconds
Started Jul 29 05:23:39 PM PDT 24
Finished Jul 29 05:26:32 PM PDT 24
Peak memory 199952 kb
Host smart-7291feb0-001b-41d7-b8fd-626d821bc4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714822813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.714822813
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1785007904
Short name T15
Test name
Test status
Simulation time 163000441 ps
CPU time 3.44 seconds
Started Jul 29 05:23:41 PM PDT 24
Finished Jul 29 05:23:45 PM PDT 24
Peak memory 199860 kb
Host smart-c0a3150c-f460-4e20-bbb7-4e095e238632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785007904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1785007904
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.832148496
Short name T434
Test name
Test status
Simulation time 37462234281 ps
CPU time 524.57 seconds
Started Jul 29 05:23:38 PM PDT 24
Finished Jul 29 05:32:23 PM PDT 24
Peak memory 199748 kb
Host smart-1d6fb425-0822-4910-ada4-96a6637e19fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832148496 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.832148496
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.504780564
Short name T100
Test name
Test status
Simulation time 5233101880 ps
CPU time 70.1 seconds
Started Jul 29 05:23:39 PM PDT 24
Finished Jul 29 05:24:50 PM PDT 24
Peak memory 199960 kb
Host smart-65abe4d4-8671-4e2e-a5b8-07bc02e344e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504780564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.504780564
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3130002382
Short name T173
Test name
Test status
Simulation time 16481863 ps
CPU time 0.61 seconds
Started Jul 29 05:23:46 PM PDT 24
Finished Jul 29 05:23:47 PM PDT 24
Peak memory 196596 kb
Host smart-5b97dd0a-fd1a-42a5-b438-47368cfeba41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130002382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3130002382
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3413658009
Short name T426
Test name
Test status
Simulation time 31664963 ps
CPU time 1.63 seconds
Started Jul 29 05:23:43 PM PDT 24
Finished Jul 29 05:23:45 PM PDT 24
Peak memory 199796 kb
Host smart-ede2d72d-e269-4b00-b981-424e8f9c37b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413658009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3413658009
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3642548277
Short name T511
Test name
Test status
Simulation time 1981369880 ps
CPU time 34.6 seconds
Started Jul 29 05:23:47 PM PDT 24
Finished Jul 29 05:24:22 PM PDT 24
Peak memory 199808 kb
Host smart-10d71ed2-4bf0-470b-99c5-1868af396f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642548277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3642548277
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.744182204
Short name T128
Test name
Test status
Simulation time 9890489578 ps
CPU time 1020.32 seconds
Started Jul 29 05:23:46 PM PDT 24
Finished Jul 29 05:40:46 PM PDT 24
Peak memory 723452 kb
Host smart-d23db6a3-1667-4815-9442-0cd6b09c86e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744182204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.744182204
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3412319548
Short name T462
Test name
Test status
Simulation time 18631642318 ps
CPU time 69 seconds
Started Jul 29 05:23:47 PM PDT 24
Finished Jul 29 05:24:56 PM PDT 24
Peak memory 199952 kb
Host smart-6ce2ef4e-4d1a-4ba6-9723-dc6f8f966f21
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412319548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3412319548
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.4062107326
Short name T356
Test name
Test status
Simulation time 10414257739 ps
CPU time 61.4 seconds
Started Jul 29 05:23:40 PM PDT 24
Finished Jul 29 05:24:41 PM PDT 24
Peak memory 200160 kb
Host smart-c16ffbed-bbfe-4fcf-a46c-4e457ed3fe81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062107326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4062107326
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1107260154
Short name T250
Test name
Test status
Simulation time 1492503201 ps
CPU time 6.74 seconds
Started Jul 29 05:23:40 PM PDT 24
Finished Jul 29 05:23:47 PM PDT 24
Peak memory 199860 kb
Host smart-0f2f429e-5b93-4c6b-a927-e69652990c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107260154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1107260154
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2044627792
Short name T354
Test name
Test status
Simulation time 82459608590 ps
CPU time 1083.05 seconds
Started Jul 29 05:23:45 PM PDT 24
Finished Jul 29 05:41:49 PM PDT 24
Peak memory 199972 kb
Host smart-683ad8c9-f595-4896-8872-d9fff3b170fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044627792 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2044627792
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.776478404
Short name T346
Test name
Test status
Simulation time 1845888866 ps
CPU time 26.05 seconds
Started Jul 29 05:23:47 PM PDT 24
Finished Jul 29 05:24:13 PM PDT 24
Peak memory 199860 kb
Host smart-3bd38d8a-599a-4e76-9e96-f784826c3f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776478404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.776478404
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.118297110
Short name T192
Test name
Test status
Simulation time 32591941 ps
CPU time 0.57 seconds
Started Jul 29 05:23:48 PM PDT 24
Finished Jul 29 05:23:49 PM PDT 24
Peak memory 196584 kb
Host smart-f1dd2bc5-e40e-4cca-8cb0-a120f1e9789c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118297110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.118297110
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2942047362
Short name T270
Test name
Test status
Simulation time 5515081378 ps
CPU time 80.1 seconds
Started Jul 29 05:23:45 PM PDT 24
Finished Jul 29 05:25:05 PM PDT 24
Peak memory 199912 kb
Host smart-862a1033-02d8-4694-b494-8deae9497450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942047362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2942047362
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1444207982
Short name T395
Test name
Test status
Simulation time 15667281023 ps
CPU time 51.88 seconds
Started Jul 29 05:23:47 PM PDT 24
Finished Jul 29 05:24:39 PM PDT 24
Peak memory 199988 kb
Host smart-1015ffe3-1f88-4d1f-a775-526bdcd59c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444207982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1444207982
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2363664304
Short name T481
Test name
Test status
Simulation time 7671625757 ps
CPU time 211.99 seconds
Started Jul 29 05:23:46 PM PDT 24
Finished Jul 29 05:27:18 PM PDT 24
Peak memory 364796 kb
Host smart-dbe39e18-98e1-421f-9ec3-01fbac36d10d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363664304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2363664304
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.735272201
Short name T58
Test name
Test status
Simulation time 1625357428 ps
CPU time 45.42 seconds
Started Jul 29 05:23:46 PM PDT 24
Finished Jul 29 05:24:31 PM PDT 24
Peak memory 199852 kb
Host smart-962f4437-e7e1-4585-bfb8-146bb01e52f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735272201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.735272201
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.789368239
Short name T430
Test name
Test status
Simulation time 980416489 ps
CPU time 14.64 seconds
Started Jul 29 05:23:45 PM PDT 24
Finished Jul 29 05:23:59 PM PDT 24
Peak memory 200052 kb
Host smart-912ec195-0fff-4790-9e48-db1d8f696f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789368239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.789368239
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2465353161
Short name T216
Test name
Test status
Simulation time 1213626766 ps
CPU time 7.73 seconds
Started Jul 29 05:23:45 PM PDT 24
Finished Jul 29 05:23:53 PM PDT 24
Peak memory 199832 kb
Host smart-014eeb50-744e-4571-b5a9-80421a8e9d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465353161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2465353161
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3921751377
Short name T148
Test name
Test status
Simulation time 53314779740 ps
CPU time 1186.83 seconds
Started Jul 29 05:23:44 PM PDT 24
Finished Jul 29 05:43:31 PM PDT 24
Peak memory 508468 kb
Host smart-0c49d388-b50b-483b-ac6d-ba7a40087bc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921751377 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3921751377
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4037791180
Short name T533
Test name
Test status
Simulation time 9871627371 ps
CPU time 115.84 seconds
Started Jul 29 05:23:47 PM PDT 24
Finished Jul 29 05:25:43 PM PDT 24
Peak memory 199928 kb
Host smart-b20a6fe2-1a73-4ecb-8b50-a95032284f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037791180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4037791180
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2022955817
Short name T237
Test name
Test status
Simulation time 23229635 ps
CPU time 0.61 seconds
Started Jul 29 05:23:50 PM PDT 24
Finished Jul 29 05:23:51 PM PDT 24
Peak memory 196528 kb
Host smart-358ec759-4803-49e9-b8de-3265948cc6f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022955817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2022955817
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.424272798
Short name T406
Test name
Test status
Simulation time 4836864329 ps
CPU time 95.96 seconds
Started Jul 29 05:23:51 PM PDT 24
Finished Jul 29 05:25:27 PM PDT 24
Peak memory 200084 kb
Host smart-138f260f-d475-4889-a780-0f8772091ef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424272798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.424272798
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1752196982
Short name T193
Test name
Test status
Simulation time 9343235764 ps
CPU time 40.88 seconds
Started Jul 29 05:23:50 PM PDT 24
Finished Jul 29 05:24:31 PM PDT 24
Peak memory 208204 kb
Host smart-ac0beb82-dd04-41df-bbdc-6a993a503050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752196982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1752196982
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3666793722
Short name T478
Test name
Test status
Simulation time 584946174 ps
CPU time 118.91 seconds
Started Jul 29 05:23:53 PM PDT 24
Finished Jul 29 05:25:52 PM PDT 24
Peak memory 595596 kb
Host smart-1045e27d-126e-4549-a071-3a139578b29c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666793722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3666793722
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.472837429
Short name T322
Test name
Test status
Simulation time 14053222119 ps
CPU time 167.38 seconds
Started Jul 29 05:23:49 PM PDT 24
Finished Jul 29 05:26:37 PM PDT 24
Peak memory 199928 kb
Host smart-c01a8806-eca5-454d-a879-2624c95b9661
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472837429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.472837429
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2997628104
Short name T255
Test name
Test status
Simulation time 20641162910 ps
CPU time 70.59 seconds
Started Jul 29 05:23:50 PM PDT 24
Finished Jul 29 05:25:00 PM PDT 24
Peak memory 200008 kb
Host smart-f9243b5f-5668-4d6d-b1cc-c5f9b020597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997628104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2997628104
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1105637438
Short name T184
Test name
Test status
Simulation time 299097375 ps
CPU time 12.59 seconds
Started Jul 29 05:23:44 PM PDT 24
Finished Jul 29 05:23:57 PM PDT 24
Peak memory 199860 kb
Host smart-de768741-ca07-4ca3-a134-ab520bec6732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105637438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1105637438
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2705973756
Short name T83
Test name
Test status
Simulation time 282481433403 ps
CPU time 1798.2 seconds
Started Jul 29 05:23:50 PM PDT 24
Finished Jul 29 05:53:49 PM PDT 24
Peak memory 781556 kb
Host smart-03ff5982-2195-4f25-b514-77db8b75167b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705973756 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2705973756
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.754929143
Short name T131
Test name
Test status
Simulation time 669232807 ps
CPU time 19.37 seconds
Started Jul 29 05:23:53 PM PDT 24
Finished Jul 29 05:24:12 PM PDT 24
Peak memory 199860 kb
Host smart-1ccf7346-4bac-4f3c-b2f2-1f3c6b0acc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754929143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.754929143
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.296342332
Short name T309
Test name
Test status
Simulation time 16589325 ps
CPU time 0.6 seconds
Started Jul 29 05:23:55 PM PDT 24
Finished Jul 29 05:23:55 PM PDT 24
Peak memory 196580 kb
Host smart-36cf826d-ca9e-4fcc-9755-e75453363467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296342332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.296342332
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3246637258
Short name T238
Test name
Test status
Simulation time 483094225 ps
CPU time 28.86 seconds
Started Jul 29 05:23:49 PM PDT 24
Finished Jul 29 05:24:18 PM PDT 24
Peak memory 199816 kb
Host smart-affc9079-84d5-415b-a5cf-cdab0bb3f001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246637258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3246637258
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1591846233
Short name T299
Test name
Test status
Simulation time 1080317682 ps
CPU time 13.61 seconds
Started Jul 29 05:23:53 PM PDT 24
Finished Jul 29 05:24:07 PM PDT 24
Peak memory 199832 kb
Host smart-a50fe8e2-d4b5-433b-98a9-b029de3f1273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591846233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1591846233
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3625074578
Short name T451
Test name
Test status
Simulation time 2767092011 ps
CPU time 577.39 seconds
Started Jul 29 05:23:55 PM PDT 24
Finished Jul 29 05:33:32 PM PDT 24
Peak memory 693428 kb
Host smart-f879c0f8-3695-412f-bad5-65b39555207d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625074578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3625074578
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1449340798
Short name T199
Test name
Test status
Simulation time 10741317598 ps
CPU time 144.47 seconds
Started Jul 29 05:23:51 PM PDT 24
Finished Jul 29 05:26:16 PM PDT 24
Peak memory 199736 kb
Host smart-99aa87b8-9995-4f6d-a17d-644f57caadaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449340798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1449340798
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1977838955
Short name T145
Test name
Test status
Simulation time 20191822852 ps
CPU time 181.74 seconds
Started Jul 29 05:23:53 PM PDT 24
Finished Jul 29 05:26:55 PM PDT 24
Peak memory 216400 kb
Host smart-f37d01de-9ab7-45d4-aebe-cf2a027e3eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977838955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1977838955
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2179329433
Short name T519
Test name
Test status
Simulation time 872495955 ps
CPU time 11.88 seconds
Started Jul 29 05:23:50 PM PDT 24
Finished Jul 29 05:24:02 PM PDT 24
Peak memory 199784 kb
Host smart-81001b7d-6a75-4b72-8dd2-9b4f75a0fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179329433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2179329433
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2206605449
Short name T388
Test name
Test status
Simulation time 2517959750 ps
CPU time 398.1 seconds
Started Jul 29 05:23:51 PM PDT 24
Finished Jul 29 05:30:29 PM PDT 24
Peak memory 501744 kb
Host smart-c9be4fe9-c28b-4716-bc25-5795e190aa70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206605449 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2206605449
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2230495865
Short name T264
Test name
Test status
Simulation time 606367013 ps
CPU time 28.26 seconds
Started Jul 29 05:23:54 PM PDT 24
Finished Jul 29 05:24:22 PM PDT 24
Peak memory 199776 kb
Host smart-6d942663-bb25-4730-8c7c-3c92e8ece378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230495865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2230495865
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1708313167
Short name T401
Test name
Test status
Simulation time 44166795 ps
CPU time 0.58 seconds
Started Jul 29 05:23:56 PM PDT 24
Finished Jul 29 05:23:56 PM PDT 24
Peak memory 196540 kb
Host smart-236378ab-e0d9-4fc3-9b87-a60f8a6b1784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708313167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1708313167
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2283852493
Short name T520
Test name
Test status
Simulation time 1194255301 ps
CPU time 68.49 seconds
Started Jul 29 05:23:54 PM PDT 24
Finished Jul 29 05:25:03 PM PDT 24
Peak memory 199804 kb
Host smart-b13245d9-7396-46af-9175-eb9fcbf13b62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283852493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2283852493
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.994963573
Short name T307
Test name
Test status
Simulation time 7518556246 ps
CPU time 68.48 seconds
Started Jul 29 05:23:56 PM PDT 24
Finished Jul 29 05:25:04 PM PDT 24
Peak memory 199940 kb
Host smart-7ec8a964-f215-4dd9-94ff-a133cf33f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994963573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.994963573
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1226200188
Short name T259
Test name
Test status
Simulation time 1178849343 ps
CPU time 91.32 seconds
Started Jul 29 05:23:56 PM PDT 24
Finished Jul 29 05:25:28 PM PDT 24
Peak memory 357396 kb
Host smart-bd3f0fb0-05a8-4a7a-ae61-5e87cc9e66ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1226200188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1226200188
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2570460050
Short name T152
Test name
Test status
Simulation time 9822416793 ps
CPU time 165.1 seconds
Started Jul 29 05:23:57 PM PDT 24
Finished Jul 29 05:26:42 PM PDT 24
Peak memory 199940 kb
Host smart-64f4cf15-48a3-410e-a3e0-d31cdcfab19a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570460050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2570460050
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.713791313
Short name T179
Test name
Test status
Simulation time 32380532053 ps
CPU time 153.58 seconds
Started Jul 29 05:23:54 PM PDT 24
Finished Jul 29 05:26:28 PM PDT 24
Peak memory 199920 kb
Host smart-bb587d59-5acb-45e3-aba7-ac25c34e6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713791313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.713791313
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2631447166
Short name T466
Test name
Test status
Simulation time 3526141039 ps
CPU time 16.71 seconds
Started Jul 29 05:23:55 PM PDT 24
Finished Jul 29 05:24:12 PM PDT 24
Peak memory 199916 kb
Host smart-50d7070b-5b27-4133-8bb3-426ccc19a448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631447166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2631447166
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2935681465
Short name T362
Test name
Test status
Simulation time 48463407669 ps
CPU time 947.4 seconds
Started Jul 29 05:23:55 PM PDT 24
Finished Jul 29 05:39:43 PM PDT 24
Peak memory 434340 kb
Host smart-2b078c60-d4fc-471c-ae54-42b35cd39ebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935681465 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2935681465
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1543490799
Short name T76
Test name
Test status
Simulation time 3742525328 ps
CPU time 39.59 seconds
Started Jul 29 05:23:56 PM PDT 24
Finished Jul 29 05:24:35 PM PDT 24
Peak memory 199908 kb
Host smart-6d21ca00-0601-43b0-ba00-2e84367af4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543490799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1543490799
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1194816053
Short name T296
Test name
Test status
Simulation time 51094555 ps
CPU time 0.6 seconds
Started Jul 29 05:24:04 PM PDT 24
Finished Jul 29 05:24:05 PM PDT 24
Peak memory 195900 kb
Host smart-6103ab7b-8032-45e1-8610-4df1175b0681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194816053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1194816053
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3127488214
Short name T497
Test name
Test status
Simulation time 2011936653 ps
CPU time 64.89 seconds
Started Jul 29 05:24:02 PM PDT 24
Finished Jul 29 05:25:07 PM PDT 24
Peak memory 199908 kb
Host smart-8feb34e2-3d2f-4ac0-b322-8e36f69be240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127488214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3127488214
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3081293922
Short name T483
Test name
Test status
Simulation time 19726820768 ps
CPU time 71.7 seconds
Started Jul 29 05:24:03 PM PDT 24
Finished Jul 29 05:25:15 PM PDT 24
Peak memory 199952 kb
Host smart-f5af5dd9-0391-4a99-b022-5f73e4f00e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081293922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3081293922
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.633229725
Short name T210
Test name
Test status
Simulation time 5728497787 ps
CPU time 994.02 seconds
Started Jul 29 05:24:03 PM PDT 24
Finished Jul 29 05:40:37 PM PDT 24
Peak memory 691912 kb
Host smart-0c0841da-0651-42ec-9615-5c206e901a58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633229725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.633229725
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2627351750
Short name T201
Test name
Test status
Simulation time 33245661448 ps
CPU time 106.26 seconds
Started Jul 29 05:24:03 PM PDT 24
Finished Jul 29 05:25:49 PM PDT 24
Peak memory 199980 kb
Host smart-e22f045d-e177-4682-bd26-93c18f18b910
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627351750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2627351750
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2069183425
Short name T524
Test name
Test status
Simulation time 1138683280 ps
CPU time 63.55 seconds
Started Jul 29 05:24:05 PM PDT 24
Finished Jul 29 05:25:08 PM PDT 24
Peak memory 199868 kb
Host smart-de35472e-8d59-4bc5-a315-beb189f06afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069183425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2069183425
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.226103221
Short name T464
Test name
Test status
Simulation time 291459217 ps
CPU time 12.76 seconds
Started Jul 29 05:23:55 PM PDT 24
Finished Jul 29 05:24:08 PM PDT 24
Peak memory 199884 kb
Host smart-674412c0-68e8-42a4-a092-cb99067e8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226103221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.226103221
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.662262220
Short name T130
Test name
Test status
Simulation time 2258430975 ps
CPU time 118.09 seconds
Started Jul 29 05:24:03 PM PDT 24
Finished Jul 29 05:26:01 PM PDT 24
Peak memory 199948 kb
Host smart-a9280cfe-d99e-4d75-8cf2-a4f785ba285c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662262220 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.662262220
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.221086424
Short name T292
Test name
Test status
Simulation time 2719597213 ps
CPU time 17.57 seconds
Started Jul 29 05:24:02 PM PDT 24
Finished Jul 29 05:24:20 PM PDT 24
Peak memory 200212 kb
Host smart-d615900e-34ad-422f-9cfb-001b2dab4311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221086424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.221086424
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.851748438
Short name T218
Test name
Test status
Simulation time 12346151 ps
CPU time 0.58 seconds
Started Jul 29 05:24:09 PM PDT 24
Finished Jul 29 05:24:10 PM PDT 24
Peak memory 195520 kb
Host smart-348f3c79-a468-4690-b80f-2dd61ec47575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851748438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.851748438
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3347299820
Short name T6
Test name
Test status
Simulation time 7220935039 ps
CPU time 92.5 seconds
Started Jul 29 05:24:03 PM PDT 24
Finished Jul 29 05:25:36 PM PDT 24
Peak memory 199888 kb
Host smart-2d4dcf0d-2d82-4e68-8e26-e6b49e9ae7e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347299820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3347299820
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.217112975
Short name T4
Test name
Test status
Simulation time 1053076610 ps
CPU time 13.34 seconds
Started Jul 29 05:24:06 PM PDT 24
Finished Jul 29 05:24:20 PM PDT 24
Peak memory 199744 kb
Host smart-d0c6b5d8-bb8d-457c-a5c9-eb70fe903fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217112975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.217112975
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2050359991
Short name T170
Test name
Test status
Simulation time 5393167494 ps
CPU time 1009.13 seconds
Started Jul 29 05:24:03 PM PDT 24
Finished Jul 29 05:40:53 PM PDT 24
Peak memory 651832 kb
Host smart-b517baab-f2ff-44e9-b675-98c490fc921b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2050359991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2050359991
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.953440197
Short name T327
Test name
Test status
Simulation time 14736115112 ps
CPU time 184.72 seconds
Started Jul 29 05:24:09 PM PDT 24
Finished Jul 29 05:27:14 PM PDT 24
Peak memory 199952 kb
Host smart-56981d10-497d-46c2-a3ea-16de54483842
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953440197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.953440197
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1753292903
Short name T516
Test name
Test status
Simulation time 20922350173 ps
CPU time 82.37 seconds
Started Jul 29 05:24:02 PM PDT 24
Finished Jul 29 05:25:25 PM PDT 24
Peak memory 200008 kb
Host smart-2ae4f0df-2358-41eb-8c85-3dfd11f7cf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753292903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1753292903
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1808726043
Short name T140
Test name
Test status
Simulation time 282188980 ps
CPU time 11.62 seconds
Started Jul 29 05:24:03 PM PDT 24
Finished Jul 29 05:24:14 PM PDT 24
Peak memory 199888 kb
Host smart-f2f3fa18-2b02-48ef-b20e-394c094b944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808726043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1808726043
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1469976908
Short name T467
Test name
Test status
Simulation time 196219702461 ps
CPU time 685.9 seconds
Started Jul 29 05:24:05 PM PDT 24
Finished Jul 29 05:35:31 PM PDT 24
Peak memory 199988 kb
Host smart-b6c855f2-6760-4927-8f0d-fc8e856336db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469976908 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1469976908
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1630626343
Short name T411
Test name
Test status
Simulation time 833176432 ps
CPU time 4.04 seconds
Started Jul 29 05:24:09 PM PDT 24
Finished Jul 29 05:24:13 PM PDT 24
Peak memory 199788 kb
Host smart-f3dd1716-2442-40d3-a56a-fda641deba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630626343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1630626343
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2431058691
Short name T480
Test name
Test status
Simulation time 39101820 ps
CPU time 0.56 seconds
Started Jul 29 05:24:09 PM PDT 24
Finished Jul 29 05:24:10 PM PDT 24
Peak memory 194620 kb
Host smart-e3a197a9-8fe3-49a4-999c-47c4af4d28ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431058691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2431058691
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2368056655
Short name T452
Test name
Test status
Simulation time 466768037 ps
CPU time 28.85 seconds
Started Jul 29 05:24:08 PM PDT 24
Finished Jul 29 05:24:37 PM PDT 24
Peak memory 199856 kb
Host smart-c5710e45-5f82-449e-846c-8ac6d0b3a093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368056655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2368056655
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1413920953
Short name T144
Test name
Test status
Simulation time 1733856045 ps
CPU time 43.53 seconds
Started Jul 29 05:24:08 PM PDT 24
Finished Jul 29 05:24:51 PM PDT 24
Peak memory 199812 kb
Host smart-896692f6-8393-40af-9398-f084f7de59e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413920953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1413920953
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2644461014
Short name T386
Test name
Test status
Simulation time 2371924634 ps
CPU time 413.21 seconds
Started Jul 29 05:24:06 PM PDT 24
Finished Jul 29 05:30:59 PM PDT 24
Peak memory 650052 kb
Host smart-1cde7017-06e6-4ed6-ac76-f48e5ab4f0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644461014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2644461014
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.4268727659
Short name T425
Test name
Test status
Simulation time 2963566721 ps
CPU time 159.11 seconds
Started Jul 29 05:24:07 PM PDT 24
Finished Jul 29 05:26:46 PM PDT 24
Peak memory 200152 kb
Host smart-6bdcee11-08af-4aae-9342-9e80966455ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268727659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.4268727659
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3756424325
Short name T526
Test name
Test status
Simulation time 28864179388 ps
CPU time 191.74 seconds
Started Jul 29 05:24:09 PM PDT 24
Finished Jul 29 05:27:21 PM PDT 24
Peak memory 199932 kb
Host smart-0fa863f1-6ebd-4719-a34b-6b672ea0e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756424325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3756424325
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1773001852
Short name T196
Test name
Test status
Simulation time 1392775570 ps
CPU time 12.17 seconds
Started Jul 29 05:24:06 PM PDT 24
Finished Jul 29 05:24:18 PM PDT 24
Peak memory 199848 kb
Host smart-664625d4-e748-4f42-9c17-5b17de5d1104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773001852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1773001852
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.939431303
Short name T350
Test name
Test status
Simulation time 522656825027 ps
CPU time 368.03 seconds
Started Jul 29 05:24:08 PM PDT 24
Finished Jul 29 05:30:16 PM PDT 24
Peak memory 208124 kb
Host smart-b5c50439-1f5a-416a-8f59-0238b4f52ab9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939431303 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.939431303
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3050268624
Short name T202
Test name
Test status
Simulation time 4271243884 ps
CPU time 109.92 seconds
Started Jul 29 05:24:09 PM PDT 24
Finished Jul 29 05:25:59 PM PDT 24
Peak memory 199936 kb
Host smart-6985a79a-65f1-4676-b17a-a38e5b6c0d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050268624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3050268624
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2007230531
Short name T200
Test name
Test status
Simulation time 25743943 ps
CPU time 0.57 seconds
Started Jul 29 05:22:21 PM PDT 24
Finished Jul 29 05:22:22 PM PDT 24
Peak memory 194820 kb
Host smart-57e1dc51-79d0-4da6-9eef-bbda1381a0d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007230531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2007230531
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3609899110
Short name T86
Test name
Test status
Simulation time 127913381 ps
CPU time 3.58 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:22:26 PM PDT 24
Peak memory 199764 kb
Host smart-88c4980f-f52f-4604-bdb4-95dbee8f22a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609899110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3609899110
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.103159271
Short name T29
Test name
Test status
Simulation time 7662307340 ps
CPU time 53.91 seconds
Started Jul 29 05:22:20 PM PDT 24
Finished Jul 29 05:23:14 PM PDT 24
Peak memory 199972 kb
Host smart-7baddb15-8777-4c8f-a9ad-b980fda23501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103159271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.103159271
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.4139360884
Short name T329
Test name
Test status
Simulation time 15230342 ps
CPU time 0.68 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:22:23 PM PDT 24
Peak memory 198188 kb
Host smart-fd4c3ae6-f90c-4529-af80-5a8ef06820a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139360884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.4139360884
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1194173153
Short name T417
Test name
Test status
Simulation time 912826124 ps
CPU time 26.65 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:22:49 PM PDT 24
Peak memory 199804 kb
Host smart-969dfb2e-22a5-4b68-88f9-30dc0a457e1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194173153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1194173153
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3802824110
Short name T359
Test name
Test status
Simulation time 814564909 ps
CPU time 10.17 seconds
Started Jul 29 05:22:24 PM PDT 24
Finished Jul 29 05:22:34 PM PDT 24
Peak memory 199772 kb
Host smart-91bc4e03-9c9b-4a13-8804-d4354b687812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802824110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3802824110
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.3923829219
Short name T227
Test name
Test status
Simulation time 1639079316 ps
CPU time 13.87 seconds
Started Jul 29 05:22:24 PM PDT 24
Finished Jul 29 05:22:38 PM PDT 24
Peak memory 199876 kb
Host smart-94481d71-8fab-4c12-9581-975e0ae1fa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923829219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3923829219
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1024118767
Short name T445
Test name
Test status
Simulation time 371211058957 ps
CPU time 2382.11 seconds
Started Jul 29 05:22:20 PM PDT 24
Finished Jul 29 06:02:03 PM PDT 24
Peak memory 768772 kb
Host smart-f5bb3edd-f080-43df-81d1-d7036d84a73b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024118767 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1024118767
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.783805083
Short name T18
Test name
Test status
Simulation time 79462598484 ps
CPU time 1170.03 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:41:53 PM PDT 24
Peak memory 585728 kb
Host smart-acf44c61-5590-410f-98fe-1490ccf1e75e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783805083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.783805083
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.645682450
Short name T303
Test name
Test status
Simulation time 3912756911 ps
CPU time 42.59 seconds
Started Jul 29 05:22:20 PM PDT 24
Finished Jul 29 05:23:03 PM PDT 24
Peak memory 199900 kb
Host smart-25d8889b-5e2d-4801-bcbe-4294bc8c247f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=645682450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.645682450
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3579738013
Short name T266
Test name
Test status
Simulation time 6646476643 ps
CPU time 106.19 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:24:09 PM PDT 24
Peak memory 199976 kb
Host smart-29bd199d-5a83-4b0f-a1c4-10e4da9904b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3579738013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3579738013
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3126803991
Short name T160
Test name
Test status
Simulation time 11935714732 ps
CPU time 107.72 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:24:10 PM PDT 24
Peak memory 199896 kb
Host smart-5648c22c-0640-46bf-b2f5-bd4424a0f8fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3126803991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3126803991
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3574074411
Short name T167
Test name
Test status
Simulation time 245282803775 ps
CPU time 742.42 seconds
Started Jul 29 05:22:24 PM PDT 24
Finished Jul 29 05:34:47 PM PDT 24
Peak memory 199944 kb
Host smart-6cddea87-5763-4a4f-aa9f-51cb9c72b148
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3574074411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3574074411
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2465760705
Short name T287
Test name
Test status
Simulation time 212919069811 ps
CPU time 2582.51 seconds
Started Jul 29 05:22:20 PM PDT 24
Finished Jul 29 06:05:23 PM PDT 24
Peak memory 215404 kb
Host smart-105d470e-d632-42aa-a4a4-84180e47ec05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2465760705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2465760705
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2534865435
Short name T263
Test name
Test status
Simulation time 889418176711 ps
CPU time 2433.02 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 06:02:55 PM PDT 24
Peak memory 216276 kb
Host smart-2071f9c4-c28a-45fd-bf79-87abea454209
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2534865435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2534865435
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2189931633
Short name T458
Test name
Test status
Simulation time 13858870453 ps
CPU time 67.2 seconds
Started Jul 29 05:22:21 PM PDT 24
Finished Jul 29 05:23:29 PM PDT 24
Peak memory 199952 kb
Host smart-56a16cde-3efb-4c7d-92e7-e94772d283b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189931633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2189931633
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3309742181
Short name T215
Test name
Test status
Simulation time 42033609 ps
CPU time 0.59 seconds
Started Jul 29 05:24:20 PM PDT 24
Finished Jul 29 05:24:20 PM PDT 24
Peak memory 195856 kb
Host smart-0bdfe080-e572-48be-a4c9-bcc8485d224e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309742181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3309742181
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3511837248
Short name T323
Test name
Test status
Simulation time 6637427018 ps
CPU time 48.46 seconds
Started Jul 29 05:24:11 PM PDT 24
Finished Jul 29 05:24:59 PM PDT 24
Peak memory 199920 kb
Host smart-0e4a24bd-391c-4326-9ae3-93617d48dedb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511837248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3511837248
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3287240655
Short name T400
Test name
Test status
Simulation time 2925981309 ps
CPU time 17.39 seconds
Started Jul 29 05:24:11 PM PDT 24
Finished Jul 29 05:24:29 PM PDT 24
Peak memory 200012 kb
Host smart-fbcf18ef-abea-4247-b80c-d4789866500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287240655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3287240655
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2657202678
Short name T379
Test name
Test status
Simulation time 1949356593 ps
CPU time 347.69 seconds
Started Jul 29 05:24:13 PM PDT 24
Finished Jul 29 05:30:01 PM PDT 24
Peak memory 658944 kb
Host smart-06c53d70-8971-4be2-b009-6f37dcafd2d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657202678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2657202678
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3500781434
Short name T168
Test name
Test status
Simulation time 2007274035 ps
CPU time 113.62 seconds
Started Jul 29 05:24:11 PM PDT 24
Finished Jul 29 05:26:05 PM PDT 24
Peak memory 199864 kb
Host smart-84176e04-858c-403c-a475-23b9477879d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500781434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3500781434
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.536495857
Short name T181
Test name
Test status
Simulation time 9864668576 ps
CPU time 91.7 seconds
Started Jul 29 05:24:12 PM PDT 24
Finished Jul 29 05:25:44 PM PDT 24
Peak memory 200036 kb
Host smart-d6ee2d67-c50d-4456-bf6a-66367f7505a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536495857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.536495857
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.963376602
Short name T398
Test name
Test status
Simulation time 2964277491 ps
CPU time 11.83 seconds
Started Jul 29 05:24:13 PM PDT 24
Finished Jul 29 05:24:25 PM PDT 24
Peak memory 200028 kb
Host smart-063dbe73-507c-4ca4-8233-b52db440d9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963376602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.963376602
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3858649822
Short name T84
Test name
Test status
Simulation time 9856851043 ps
CPU time 66.28 seconds
Started Jul 29 05:24:13 PM PDT 24
Finished Jul 29 05:25:20 PM PDT 24
Peak memory 208284 kb
Host smart-4e415009-9b5b-4759-bfac-abfcf50f6926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858649822 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3858649822
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1748633118
Short name T455
Test name
Test status
Simulation time 28949507224 ps
CPU time 163.75 seconds
Started Jul 29 05:24:12 PM PDT 24
Finished Jul 29 05:26:55 PM PDT 24
Peak memory 199964 kb
Host smart-23ead552-a7e8-4192-9c37-7ea80bbe95a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748633118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1748633118
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1579142064
Short name T242
Test name
Test status
Simulation time 135701795 ps
CPU time 0.59 seconds
Started Jul 29 05:24:20 PM PDT 24
Finished Jul 29 05:24:21 PM PDT 24
Peak memory 195912 kb
Host smart-e555ab07-d820-445b-8535-f47012df5091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579142064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1579142064
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3321762040
Short name T260
Test name
Test status
Simulation time 444519168 ps
CPU time 25.04 seconds
Started Jul 29 05:24:18 PM PDT 24
Finished Jul 29 05:24:43 PM PDT 24
Peak memory 199888 kb
Host smart-1cf97fbd-2e35-4763-90e6-9e5ec712493f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321762040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3321762040
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3779208224
Short name T485
Test name
Test status
Simulation time 3800029761 ps
CPU time 14.24 seconds
Started Jul 29 05:24:18 PM PDT 24
Finished Jul 29 05:24:33 PM PDT 24
Peak memory 199920 kb
Host smart-4ad2c4e6-99b5-4e88-aac5-f506bcdd22a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779208224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3779208224
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3719215975
Short name T304
Test name
Test status
Simulation time 12163535184 ps
CPU time 337.81 seconds
Started Jul 29 05:24:18 PM PDT 24
Finished Jul 29 05:29:56 PM PDT 24
Peak memory 606120 kb
Host smart-837443d8-9f79-494c-b588-5a5b1366acd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719215975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3719215975
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3187505778
Short name T531
Test name
Test status
Simulation time 52244549847 ps
CPU time 222.78 seconds
Started Jul 29 05:24:22 PM PDT 24
Finished Jul 29 05:28:05 PM PDT 24
Peak memory 199940 kb
Host smart-54bef7b3-55a7-4b1c-99d4-6dfaf8ee9882
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187505778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3187505778
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2063670442
Short name T416
Test name
Test status
Simulation time 4346399571 ps
CPU time 35.86 seconds
Started Jul 29 05:24:18 PM PDT 24
Finished Jul 29 05:24:54 PM PDT 24
Peak memory 199944 kb
Host smart-3aed888e-7c39-4a78-88c7-fcaaf901445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063670442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2063670442
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2388045858
Short name T508
Test name
Test status
Simulation time 121988036 ps
CPU time 5.72 seconds
Started Jul 29 05:24:19 PM PDT 24
Finished Jul 29 05:24:25 PM PDT 24
Peak memory 199836 kb
Host smart-b245a76b-80fe-4252-b8fd-b8710c6ef2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388045858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2388045858
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2736934610
Short name T487
Test name
Test status
Simulation time 41932076787 ps
CPU time 150.64 seconds
Started Jul 29 05:24:21 PM PDT 24
Finished Jul 29 05:26:52 PM PDT 24
Peak memory 200012 kb
Host smart-990ad0a8-5e24-4cbd-b031-f953fa727a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736934610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2736934610
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2959582165
Short name T438
Test name
Test status
Simulation time 12180375 ps
CPU time 0.56 seconds
Started Jul 29 05:24:25 PM PDT 24
Finished Jul 29 05:24:26 PM PDT 24
Peak memory 194844 kb
Host smart-de35c728-58bd-4c8f-ab5a-c1573fc64f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959582165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2959582165
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1363246225
Short name T95
Test name
Test status
Simulation time 145164921 ps
CPU time 8.22 seconds
Started Jul 29 05:24:25 PM PDT 24
Finished Jul 29 05:24:33 PM PDT 24
Peak memory 199696 kb
Host smart-e2dc2bb4-0a6a-4f04-a7be-2a2dc8e48bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363246225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1363246225
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.457004317
Short name T393
Test name
Test status
Simulation time 6288192305 ps
CPU time 53.07 seconds
Started Jul 29 05:24:26 PM PDT 24
Finished Jul 29 05:25:19 PM PDT 24
Peak memory 199976 kb
Host smart-9858082b-eea8-41f5-b0ca-46301ef118e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457004317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.457004317
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.463097217
Short name T490
Test name
Test status
Simulation time 4778882984 ps
CPU time 234.19 seconds
Started Jul 29 05:24:22 PM PDT 24
Finished Jul 29 05:28:16 PM PDT 24
Peak memory 621292 kb
Host smart-1c241831-0bfa-4b9c-9cb8-b30ce2c4469d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463097217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.463097217
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1963718055
Short name T527
Test name
Test status
Simulation time 7601607039 ps
CPU time 72.12 seconds
Started Jul 29 05:24:22 PM PDT 24
Finished Jul 29 05:25:34 PM PDT 24
Peak memory 200044 kb
Host smart-7f78147d-762d-4395-8b58-490ecda961c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963718055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1963718055
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4101985697
Short name T428
Test name
Test status
Simulation time 6474104153 ps
CPU time 68.07 seconds
Started Jul 29 05:24:23 PM PDT 24
Finished Jul 29 05:25:31 PM PDT 24
Peak memory 216220 kb
Host smart-434a0c8f-021a-4f5f-8c99-56dfc106eb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101985697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4101985697
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3653610315
Short name T410
Test name
Test status
Simulation time 248920583 ps
CPU time 11.55 seconds
Started Jul 29 05:24:26 PM PDT 24
Finished Jul 29 05:24:38 PM PDT 24
Peak memory 199816 kb
Host smart-06fecb8a-c8d3-4a69-8a9a-1894a8f5fecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653610315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3653610315
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2510141451
Short name T234
Test name
Test status
Simulation time 10015944161 ps
CPU time 188.86 seconds
Started Jul 29 05:24:24 PM PDT 24
Finished Jul 29 05:27:33 PM PDT 24
Peak memory 199948 kb
Host smart-0318a3e6-1d3f-428f-bbb9-82f895d64d40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510141451 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2510141451
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.4020795071
Short name T501
Test name
Test status
Simulation time 2859267550 ps
CPU time 28.45 seconds
Started Jul 29 05:24:28 PM PDT 24
Finished Jul 29 05:24:57 PM PDT 24
Peak memory 199936 kb
Host smart-dd032367-9e17-4c37-939d-baa7218d71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020795071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.4020795071
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.830024273
Short name T43
Test name
Test status
Simulation time 64668581 ps
CPU time 0.58 seconds
Started Jul 29 05:24:24 PM PDT 24
Finished Jul 29 05:24:25 PM PDT 24
Peak memory 195900 kb
Host smart-d8584035-854e-4425-92ed-0896313baaf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830024273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.830024273
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2838161845
Short name T12
Test name
Test status
Simulation time 4280646903 ps
CPU time 61.57 seconds
Started Jul 29 05:24:24 PM PDT 24
Finished Jul 29 05:25:25 PM PDT 24
Peak memory 200164 kb
Host smart-ba504b4a-c977-48a4-be74-5174254db09d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838161845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2838161845
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.230200112
Short name T530
Test name
Test status
Simulation time 5525308730 ps
CPU time 29.76 seconds
Started Jul 29 05:24:22 PM PDT 24
Finished Jul 29 05:24:52 PM PDT 24
Peak memory 199944 kb
Host smart-4773fed5-9cc8-4a3d-bf0b-20a2bb2cb935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230200112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.230200112
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1233994179
Short name T206
Test name
Test status
Simulation time 3039837899 ps
CPU time 576.97 seconds
Started Jul 29 05:24:22 PM PDT 24
Finished Jul 29 05:33:59 PM PDT 24
Peak memory 730400 kb
Host smart-d74c3980-2cea-4b69-ba86-25c1c45b530b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233994179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1233994179
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1354182668
Short name T276
Test name
Test status
Simulation time 16857725074 ps
CPU time 244.27 seconds
Started Jul 29 05:24:22 PM PDT 24
Finished Jul 29 05:28:26 PM PDT 24
Peak memory 199932 kb
Host smart-da068d58-a2f7-4cb3-8751-d0dcbf2e5d3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354182668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1354182668
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1562996765
Short name T493
Test name
Test status
Simulation time 10050857939 ps
CPU time 138.28 seconds
Started Jul 29 05:24:23 PM PDT 24
Finished Jul 29 05:26:42 PM PDT 24
Peak memory 199812 kb
Host smart-62b081d7-a20e-458b-b55d-77522524b419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562996765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1562996765
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3729608628
Short name T245
Test name
Test status
Simulation time 455859277 ps
CPU time 4.67 seconds
Started Jul 29 05:24:24 PM PDT 24
Finished Jul 29 05:24:29 PM PDT 24
Peak memory 199904 kb
Host smart-74c8a06e-482b-46a1-aca8-ee5f7c79244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729608628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3729608628
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.845049645
Short name T472
Test name
Test status
Simulation time 112577511326 ps
CPU time 3606.38 seconds
Started Jul 29 05:24:24 PM PDT 24
Finished Jul 29 06:24:31 PM PDT 24
Peak memory 835988 kb
Host smart-8fd3b731-2781-4ba6-8839-13a1f6362d71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845049645 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.845049645
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2734959306
Short name T257
Test name
Test status
Simulation time 30125494674 ps
CPU time 137.06 seconds
Started Jul 29 05:24:23 PM PDT 24
Finished Jul 29 05:26:40 PM PDT 24
Peak memory 199992 kb
Host smart-b7ad7f59-b87a-4cee-8bd3-13e76c5cad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734959306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2734959306
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2325235866
Short name T364
Test name
Test status
Simulation time 13271671 ps
CPU time 0.62 seconds
Started Jul 29 05:24:33 PM PDT 24
Finished Jul 29 05:24:33 PM PDT 24
Peak memory 195900 kb
Host smart-a61f0727-e55d-4f8a-a249-0fa492a4223f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325235866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2325235866
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2164552490
Short name T341
Test name
Test status
Simulation time 4883773704 ps
CPU time 85.04 seconds
Started Jul 29 05:24:29 PM PDT 24
Finished Jul 29 05:25:55 PM PDT 24
Peak memory 200060 kb
Host smart-791b4c9e-19a1-440c-aafc-f34d3323e7e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164552490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2164552490
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4249057052
Short name T52
Test name
Test status
Simulation time 18601791738 ps
CPU time 58.31 seconds
Started Jul 29 05:24:30 PM PDT 24
Finished Jul 29 05:25:28 PM PDT 24
Peak memory 208120 kb
Host smart-378cf64d-8e6d-4c3e-a56f-afbbb50cac74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249057052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4249057052
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3932258138
Short name T153
Test name
Test status
Simulation time 8015010967 ps
CPU time 656.87 seconds
Started Jul 29 05:24:30 PM PDT 24
Finished Jul 29 05:35:27 PM PDT 24
Peak memory 533588 kb
Host smart-d5ec5992-aea1-4d70-b002-cbbf6f0b36b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932258138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3932258138
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3654960079
Short name T164
Test name
Test status
Simulation time 99641206453 ps
CPU time 90.73 seconds
Started Jul 29 05:24:32 PM PDT 24
Finished Jul 29 05:26:02 PM PDT 24
Peak memory 199960 kb
Host smart-39af595f-3f18-4a3e-b11e-4123d8f4d292
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654960079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3654960079
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4140046058
Short name T273
Test name
Test status
Simulation time 11236797935 ps
CPU time 123.43 seconds
Started Jul 29 05:24:29 PM PDT 24
Finished Jul 29 05:26:33 PM PDT 24
Peak memory 199956 kb
Host smart-51d5c5cc-8bdf-4f5f-9b37-21497c2ac978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140046058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4140046058
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3503125963
Short name T230
Test name
Test status
Simulation time 669821914 ps
CPU time 5.78 seconds
Started Jul 29 05:24:31 PM PDT 24
Finished Jul 29 05:24:37 PM PDT 24
Peak memory 199848 kb
Host smart-acb59eaa-07e7-41c5-82cb-b79a9f46978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503125963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3503125963
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1303883505
Short name T22
Test name
Test status
Simulation time 69346625877 ps
CPU time 5824.5 seconds
Started Jul 29 05:24:30 PM PDT 24
Finished Jul 29 07:01:36 PM PDT 24
Peak memory 899108 kb
Host smart-808e1071-d9d9-403d-b4ce-6cfd0b4480a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303883505 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1303883505
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1807606370
Short name T189
Test name
Test status
Simulation time 2162318765 ps
CPU time 30.24 seconds
Started Jul 29 05:24:29 PM PDT 24
Finished Jul 29 05:24:59 PM PDT 24
Peak memory 199884 kb
Host smart-e0c7eebd-db8d-4664-90f5-dde1a80d5978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807606370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1807606370
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.161041741
Short name T320
Test name
Test status
Simulation time 20608396 ps
CPU time 0.58 seconds
Started Jul 29 05:24:40 PM PDT 24
Finished Jul 29 05:24:40 PM PDT 24
Peak memory 195460 kb
Host smart-3a16f7c3-6664-4fab-9d5d-8f40724bf602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161041741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.161041741
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.278160453
Short name T289
Test name
Test status
Simulation time 1619632770 ps
CPU time 25.95 seconds
Started Jul 29 05:24:37 PM PDT 24
Finished Jul 29 05:25:03 PM PDT 24
Peak memory 199812 kb
Host smart-503fb7c6-6221-4039-bd19-289d855c3f8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278160453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.278160453
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3600724789
Short name T146
Test name
Test status
Simulation time 3430787774 ps
CPU time 43.87 seconds
Started Jul 29 05:24:37 PM PDT 24
Finished Jul 29 05:25:21 PM PDT 24
Peak memory 199992 kb
Host smart-debc8e79-164c-47c5-add8-d2fecc2592da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600724789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3600724789
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2960039902
Short name T247
Test name
Test status
Simulation time 4226129877 ps
CPU time 817.13 seconds
Started Jul 29 05:24:38 PM PDT 24
Finished Jul 29 05:38:16 PM PDT 24
Peak memory 688440 kb
Host smart-d6abad82-2bab-46ad-af07-9f67c2508c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960039902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2960039902
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.776712982
Short name T475
Test name
Test status
Simulation time 287537450 ps
CPU time 16.24 seconds
Started Jul 29 05:24:37 PM PDT 24
Finished Jul 29 05:24:54 PM PDT 24
Peak memory 199896 kb
Host smart-2e62c45e-354f-4937-aa7c-31e3e9b4489c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776712982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.776712982
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2524789484
Short name T241
Test name
Test status
Simulation time 45178370790 ps
CPU time 189.29 seconds
Started Jul 29 05:24:37 PM PDT 24
Finished Jul 29 05:27:46 PM PDT 24
Peak memory 199980 kb
Host smart-4b88bed5-9452-4b42-95a1-ea2949fb2080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524789484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2524789484
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4096725548
Short name T141
Test name
Test status
Simulation time 5651973471 ps
CPU time 16.12 seconds
Started Jul 29 05:24:30 PM PDT 24
Finished Jul 29 05:24:46 PM PDT 24
Peak memory 199920 kb
Host smart-33537ba1-59c9-4983-967a-aafc30e0ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096725548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4096725548
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2726684243
Short name T517
Test name
Test status
Simulation time 7636022767 ps
CPU time 394.17 seconds
Started Jul 29 05:24:39 PM PDT 24
Finished Jul 29 05:31:13 PM PDT 24
Peak memory 216376 kb
Host smart-9c194ae9-5af4-462e-8b01-4ba58e4611b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726684243 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2726684243
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.746852319
Short name T390
Test name
Test status
Simulation time 2962638438 ps
CPU time 40.52 seconds
Started Jul 29 05:24:38 PM PDT 24
Finished Jul 29 05:25:19 PM PDT 24
Peak memory 199960 kb
Host smart-6d054e80-a5b5-4554-aba9-e162527350c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746852319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.746852319
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1881809459
Short name T513
Test name
Test status
Simulation time 44281744 ps
CPU time 0.6 seconds
Started Jul 29 05:24:40 PM PDT 24
Finished Jul 29 05:24:41 PM PDT 24
Peak memory 195700 kb
Host smart-e4eea65c-dc44-40f0-952f-401c79085094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881809459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1881809459
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2511456481
Short name T182
Test name
Test status
Simulation time 1293927132 ps
CPU time 73.34 seconds
Started Jul 29 05:24:37 PM PDT 24
Finished Jul 29 05:25:51 PM PDT 24
Peak memory 199848 kb
Host smart-6c929620-41ef-41b1-8e66-54fc37b79276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511456481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2511456481
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3426916570
Short name T269
Test name
Test status
Simulation time 2033294766 ps
CPU time 7.22 seconds
Started Jul 29 05:24:38 PM PDT 24
Finished Jul 29 05:24:45 PM PDT 24
Peak memory 199836 kb
Host smart-1593164e-6566-4241-a057-b0da3cada639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426916570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3426916570
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.923159741
Short name T318
Test name
Test status
Simulation time 28031324441 ps
CPU time 1399.85 seconds
Started Jul 29 05:24:38 PM PDT 24
Finished Jul 29 05:47:58 PM PDT 24
Peak memory 763592 kb
Host smart-4bf7e0f8-da6b-4a71-834a-693848eadd6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923159741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.923159741
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2429330759
Short name T21
Test name
Test status
Simulation time 3955830237 ps
CPU time 53.95 seconds
Started Jul 29 05:24:38 PM PDT 24
Finished Jul 29 05:25:32 PM PDT 24
Peak memory 200200 kb
Host smart-c6c14b54-66ce-435f-b2a5-9d6ae5ddabbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429330759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2429330759
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1871383179
Short name T63
Test name
Test status
Simulation time 11436097214 ps
CPU time 163.16 seconds
Started Jul 29 05:24:40 PM PDT 24
Finished Jul 29 05:27:23 PM PDT 24
Peak memory 199980 kb
Host smart-ca07e1f8-8ea4-42f6-9247-75d0507eb435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871383179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1871383179
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.4121612168
Short name T477
Test name
Test status
Simulation time 273132311 ps
CPU time 13.26 seconds
Started Jul 29 05:24:38 PM PDT 24
Finished Jul 29 05:24:52 PM PDT 24
Peak memory 199872 kb
Host smart-0cef8044-d427-407d-bfe1-c3db80b66417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121612168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4121612168
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1070350598
Short name T366
Test name
Test status
Simulation time 77715818020 ps
CPU time 1509.04 seconds
Started Jul 29 05:24:39 PM PDT 24
Finished Jul 29 05:49:48 PM PDT 24
Peak memory 459352 kb
Host smart-4f3119d8-3e32-4701-8092-ad50f2191291
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070350598 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1070350598
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2281273488
Short name T103
Test name
Test status
Simulation time 21563816313 ps
CPU time 68.93 seconds
Started Jul 29 05:24:38 PM PDT 24
Finished Jul 29 05:25:47 PM PDT 24
Peak memory 199904 kb
Host smart-28a82bc0-830a-48fc-8773-58d478805bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281273488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2281273488
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4065055206
Short name T252
Test name
Test status
Simulation time 14093888 ps
CPU time 0.59 seconds
Started Jul 29 05:24:43 PM PDT 24
Finished Jul 29 05:24:44 PM PDT 24
Peak memory 194880 kb
Host smart-19ee73c3-68e5-4300-8b1f-2b275483c5b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065055206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4065055206
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3859895018
Short name T188
Test name
Test status
Simulation time 574700768 ps
CPU time 14.01 seconds
Started Jul 29 05:24:40 PM PDT 24
Finished Jul 29 05:24:54 PM PDT 24
Peak memory 199820 kb
Host smart-ff1561a3-a0cf-48cc-bfaa-ab248ff76666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859895018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3859895018
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2941432970
Short name T330
Test name
Test status
Simulation time 8937288506 ps
CPU time 40.68 seconds
Started Jul 29 05:24:45 PM PDT 24
Finished Jul 29 05:25:26 PM PDT 24
Peak memory 199960 kb
Host smart-84e91cdd-75bd-46ea-8768-a5d3d51fa3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941432970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2941432970
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1284239577
Short name T319
Test name
Test status
Simulation time 2633532490 ps
CPU time 485 seconds
Started Jul 29 05:24:39 PM PDT 24
Finished Jul 29 05:32:44 PM PDT 24
Peak memory 689160 kb
Host smart-4989a121-17ab-474b-bac4-d1dcfea317bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1284239577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1284239577
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.696160998
Short name T351
Test name
Test status
Simulation time 1857892953 ps
CPU time 96.64 seconds
Started Jul 29 05:24:45 PM PDT 24
Finished Jul 29 05:26:22 PM PDT 24
Peak memory 199668 kb
Host smart-89f749de-a322-48d9-bc54-e11b85bc8ebb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696160998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.696160998
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2508838098
Short name T405
Test name
Test status
Simulation time 4087113468 ps
CPU time 56.41 seconds
Started Jul 29 05:24:43 PM PDT 24
Finished Jul 29 05:25:39 PM PDT 24
Peak memory 199760 kb
Host smart-b9735470-130c-4055-83be-23a9291a5329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508838098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2508838098
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1181647995
Short name T57
Test name
Test status
Simulation time 884454645 ps
CPU time 5.43 seconds
Started Jul 29 05:24:40 PM PDT 24
Finished Jul 29 05:24:46 PM PDT 24
Peak memory 199836 kb
Host smart-fc6cf83b-47a6-4cfc-b843-229bcc626796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181647995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1181647995
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1808908187
Short name T17
Test name
Test status
Simulation time 43371222237 ps
CPU time 1637.88 seconds
Started Jul 29 05:24:44 PM PDT 24
Finished Jul 29 05:52:02 PM PDT 24
Peak memory 687736 kb
Host smart-4fcacf3e-58b0-4086-a4ce-9cd20bf78093
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808908187 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1808908187
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4090895139
Short name T282
Test name
Test status
Simulation time 26600212553 ps
CPU time 112.21 seconds
Started Jul 29 05:24:47 PM PDT 24
Finished Jul 29 05:26:39 PM PDT 24
Peak memory 199984 kb
Host smart-c986dfbb-d7db-433c-a9ae-60b6c419b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090895139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4090895139
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4005180494
Short name T358
Test name
Test status
Simulation time 14323435 ps
CPU time 0.58 seconds
Started Jul 29 05:24:46 PM PDT 24
Finished Jul 29 05:24:47 PM PDT 24
Peak memory 195512 kb
Host smart-21505b61-2a9a-407b-abd3-e1e082b4b3e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005180494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4005180494
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1320650268
Short name T476
Test name
Test status
Simulation time 2592007428 ps
CPU time 14.07 seconds
Started Jul 29 05:24:43 PM PDT 24
Finished Jul 29 05:24:57 PM PDT 24
Peak memory 199936 kb
Host smart-a2cb60a4-5a06-4991-90e7-0dca98ff6f05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320650268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1320650268
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1131724127
Short name T353
Test name
Test status
Simulation time 660128187 ps
CPU time 34.88 seconds
Started Jul 29 05:24:45 PM PDT 24
Finished Jul 29 05:25:20 PM PDT 24
Peak memory 199828 kb
Host smart-58fa946e-7cb1-44ea-8976-e5c7718b9369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131724127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1131724127
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.4277801493
Short name T355
Test name
Test status
Simulation time 1870793575 ps
CPU time 348.23 seconds
Started Jul 29 05:24:46 PM PDT 24
Finished Jul 29 05:30:34 PM PDT 24
Peak memory 669072 kb
Host smart-63353b06-c714-43b4-b907-648422d2921d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277801493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.4277801493
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.781803534
Short name T40
Test name
Test status
Simulation time 20551568442 ps
CPU time 90.81 seconds
Started Jul 29 05:24:47 PM PDT 24
Finished Jul 29 05:26:18 PM PDT 24
Peak memory 199932 kb
Host smart-421d6b1b-efd1-4c5b-adcd-002306ba4f83
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781803534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.781803534
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2257771706
Short name T463
Test name
Test status
Simulation time 9402186789 ps
CPU time 138.61 seconds
Started Jul 29 05:24:43 PM PDT 24
Finished Jul 29 05:27:01 PM PDT 24
Peak memory 200156 kb
Host smart-3a4d6e9b-6830-4b27-9ab8-300637a5c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257771706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2257771706
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2933473341
Short name T240
Test name
Test status
Simulation time 64929398 ps
CPU time 3.27 seconds
Started Jul 29 05:24:45 PM PDT 24
Finished Jul 29 05:24:48 PM PDT 24
Peak memory 199832 kb
Host smart-3b6625cc-2dfa-4cab-b221-e2d161ee98cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933473341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2933473341
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3554480771
Short name T149
Test name
Test status
Simulation time 33330304823 ps
CPU time 5007.32 seconds
Started Jul 29 05:24:45 PM PDT 24
Finished Jul 29 06:48:13 PM PDT 24
Peak memory 855632 kb
Host smart-221b2bbb-100f-4e99-ade3-77e7647aeb60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554480771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3554480771
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3687163103
Short name T397
Test name
Test status
Simulation time 651168873 ps
CPU time 38.2 seconds
Started Jul 29 05:24:42 PM PDT 24
Finished Jul 29 05:25:20 PM PDT 24
Peak memory 199876 kb
Host smart-354dd5a4-1ab9-4263-b28d-49c4c0dc7817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687163103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3687163103
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3099619711
Short name T367
Test name
Test status
Simulation time 117558132 ps
CPU time 0.6 seconds
Started Jul 29 05:24:51 PM PDT 24
Finished Jul 29 05:24:52 PM PDT 24
Peak memory 196516 kb
Host smart-e01ffe82-d44a-47bb-90cc-78497b46c5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099619711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3099619711
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3593718970
Short name T180
Test name
Test status
Simulation time 21063989522 ps
CPU time 69.54 seconds
Started Jul 29 05:24:43 PM PDT 24
Finished Jul 29 05:25:53 PM PDT 24
Peak memory 199980 kb
Host smart-b0e0768d-8a3f-407a-bdf4-4ca15b8778c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593718970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3593718970
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3573952700
Short name T415
Test name
Test status
Simulation time 11844441094 ps
CPU time 37.95 seconds
Started Jul 29 05:24:51 PM PDT 24
Finished Jul 29 05:25:30 PM PDT 24
Peak memory 199948 kb
Host smart-1892dfac-d480-4d15-b6da-e3178bd5e966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573952700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3573952700
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.557229427
Short name T442
Test name
Test status
Simulation time 2901802831 ps
CPU time 273.33 seconds
Started Jul 29 05:24:49 PM PDT 24
Finished Jul 29 05:29:23 PM PDT 24
Peak memory 647752 kb
Host smart-3f05b0c0-875c-4258-b647-98caf48455e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=557229427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.557229427
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2895819907
Short name T474
Test name
Test status
Simulation time 2348908997 ps
CPU time 139.17 seconds
Started Jul 29 05:24:50 PM PDT 24
Finished Jul 29 05:27:10 PM PDT 24
Peak memory 199980 kb
Host smart-dfb73f8a-d8ed-4160-a186-7c6422170dcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895819907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2895819907
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2309849470
Short name T3
Test name
Test status
Simulation time 3678472421 ps
CPU time 54.57 seconds
Started Jul 29 05:24:43 PM PDT 24
Finished Jul 29 05:25:38 PM PDT 24
Peak memory 199984 kb
Host smart-db3735a1-2636-40f2-82b2-b2a93b732c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309849470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2309849470
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1875818988
Short name T461
Test name
Test status
Simulation time 148246166 ps
CPU time 6.93 seconds
Started Jul 29 05:24:46 PM PDT 24
Finished Jul 29 05:24:53 PM PDT 24
Peak memory 199840 kb
Host smart-3b6e14a0-999a-48c6-9ef3-791548084ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875818988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1875818988
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2727531547
Short name T294
Test name
Test status
Simulation time 69807790078 ps
CPU time 1631.57 seconds
Started Jul 29 05:24:51 PM PDT 24
Finished Jul 29 05:52:03 PM PDT 24
Peak memory 688192 kb
Host smart-13864644-cd73-43df-b298-343c7e23154a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727531547 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2727531547
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3573736213
Short name T31
Test name
Test status
Simulation time 5337650629 ps
CPU time 74.49 seconds
Started Jul 29 05:24:52 PM PDT 24
Finished Jul 29 05:26:07 PM PDT 24
Peak memory 199916 kb
Host smart-a19f6570-3adb-4cff-a3b0-b6acde52d235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573736213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3573736213
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.528043959
Short name T198
Test name
Test status
Simulation time 14335549 ps
CPU time 0.6 seconds
Started Jul 29 05:22:23 PM PDT 24
Finished Jul 29 05:22:24 PM PDT 24
Peak memory 195920 kb
Host smart-5b950fef-053f-4650-bb5a-233a4619e452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528043959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.528043959
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2275679009
Short name T334
Test name
Test status
Simulation time 8502225240 ps
CPU time 57.27 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:23:20 PM PDT 24
Peak memory 200048 kb
Host smart-400154ad-5021-4108-8cac-a1c555af1e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275679009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2275679009
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3861877022
Short name T500
Test name
Test status
Simulation time 1855746463 ps
CPU time 342.51 seconds
Started Jul 29 05:22:21 PM PDT 24
Finished Jul 29 05:28:04 PM PDT 24
Peak memory 632120 kb
Host smart-eb99eeaf-2892-4724-b480-b7ff912b79cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861877022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3861877022
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1322189038
Short name T14
Test name
Test status
Simulation time 3773090815 ps
CPU time 205.44 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:25:48 PM PDT 24
Peak memory 200028 kb
Host smart-0dae46b8-f81a-4750-85f9-0e8f140a848b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322189038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1322189038
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1908537134
Short name T496
Test name
Test status
Simulation time 61470008137 ps
CPU time 191.27 seconds
Started Jul 29 05:22:25 PM PDT 24
Finished Jul 29 05:25:36 PM PDT 24
Peak memory 199924 kb
Host smart-a2ca5be6-14ba-423c-ae42-31b39d76db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908537134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1908537134
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3370868338
Short name T308
Test name
Test status
Simulation time 261219946 ps
CPU time 11.71 seconds
Started Jul 29 05:22:24 PM PDT 24
Finished Jul 29 05:22:36 PM PDT 24
Peak memory 199836 kb
Host smart-05b9366b-09e4-408c-a25e-0327392a89fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370868338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3370868338
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3519400398
Short name T151
Test name
Test status
Simulation time 13249418348 ps
CPU time 530.38 seconds
Started Jul 29 05:22:24 PM PDT 24
Finished Jul 29 05:31:15 PM PDT 24
Peak memory 637828 kb
Host smart-84e12f53-6aaf-497e-be1c-4bf61440a5c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519400398 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3519400398
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.401341202
Short name T33
Test name
Test status
Simulation time 62730899395 ps
CPU time 1897.25 seconds
Started Jul 29 05:22:20 PM PDT 24
Finished Jul 29 05:53:57 PM PDT 24
Peak memory 707012 kb
Host smart-da239a8d-9e72-4c90-8cf9-734d333eb04a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401341202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.401341202
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3892558656
Short name T53
Test name
Test status
Simulation time 4716714342 ps
CPU time 31.56 seconds
Started Jul 29 05:22:22 PM PDT 24
Finished Jul 29 05:22:53 PM PDT 24
Peak memory 199980 kb
Host smart-240e93e8-b322-420e-820b-bdd358ae65d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892558656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3892558656
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1420103671
Short name T418
Test name
Test status
Simulation time 22154130 ps
CPU time 0.65 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:22:29 PM PDT 24
Peak memory 196624 kb
Host smart-89d40ac6-be8b-449e-b18c-108a931f1ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420103671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1420103671
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4188743658
Short name T382
Test name
Test status
Simulation time 275777343 ps
CPU time 16.39 seconds
Started Jul 29 05:22:29 PM PDT 24
Finished Jul 29 05:22:45 PM PDT 24
Peak memory 199760 kb
Host smart-0ebb50f0-7676-4f59-86e3-21825a86e478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188743658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4188743658
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2015362443
Short name T392
Test name
Test status
Simulation time 1094911420 ps
CPU time 28.48 seconds
Started Jul 29 05:22:26 PM PDT 24
Finished Jul 29 05:22:55 PM PDT 24
Peak memory 199772 kb
Host smart-e1b503ca-0093-4d72-841e-10163367fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015362443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2015362443
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3501916983
Short name T331
Test name
Test status
Simulation time 13906775038 ps
CPU time 1283.36 seconds
Started Jul 29 05:22:27 PM PDT 24
Finished Jul 29 05:43:51 PM PDT 24
Peak memory 743308 kb
Host smart-f5a1f6f9-fa06-443e-b034-a7d81602fe32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3501916983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3501916983
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1693928332
Short name T228
Test name
Test status
Simulation time 81536761281 ps
CPU time 106.71 seconds
Started Jul 29 05:22:29 PM PDT 24
Finished Jul 29 05:24:16 PM PDT 24
Peak memory 199952 kb
Host smart-75397f6e-6f93-43eb-829f-5a555546c0f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693928332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1693928332
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3268805257
Short name T479
Test name
Test status
Simulation time 50924021275 ps
CPU time 156.96 seconds
Started Jul 29 05:22:33 PM PDT 24
Finished Jul 29 05:25:10 PM PDT 24
Peak memory 216340 kb
Host smart-ae4d4de7-3c9f-4acb-93e4-cb2045d03129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268805257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3268805257
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3595897458
Short name T291
Test name
Test status
Simulation time 1608971671 ps
CPU time 13.19 seconds
Started Jul 29 05:22:21 PM PDT 24
Finished Jul 29 05:22:35 PM PDT 24
Peak memory 199804 kb
Host smart-ad43c3ea-e866-4993-8979-20e873024d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595897458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3595897458
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3570007463
Short name T522
Test name
Test status
Simulation time 18825661609 ps
CPU time 311.22 seconds
Started Jul 29 05:22:31 PM PDT 24
Finished Jul 29 05:27:43 PM PDT 24
Peak memory 634928 kb
Host smart-6e3e3a8e-ba9e-4928-a81c-c3a3a2d318c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570007463 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3570007463
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.776332214
Short name T69
Test name
Test status
Simulation time 67460755708 ps
CPU time 6002.04 seconds
Started Jul 29 05:22:27 PM PDT 24
Finished Jul 29 07:02:30 PM PDT 24
Peak memory 836968 kb
Host smart-22c93f09-3dae-4fbf-a13a-c39e70bf32d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776332214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.776332214
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2197900003
Short name T284
Test name
Test status
Simulation time 8794717547 ps
CPU time 78.35 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:23:47 PM PDT 24
Peak memory 200032 kb
Host smart-5a5e996a-1a4a-45c4-9f15-974007c5ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197900003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2197900003
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3552406698
Short name T190
Test name
Test status
Simulation time 13126791 ps
CPU time 0.6 seconds
Started Jul 29 05:22:31 PM PDT 24
Finished Jul 29 05:22:32 PM PDT 24
Peak memory 196800 kb
Host smart-8b891c0c-a25b-40a7-86ca-a5af6be5e7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552406698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3552406698
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1724815395
Short name T235
Test name
Test status
Simulation time 877124553 ps
CPU time 48.63 seconds
Started Jul 29 05:22:30 PM PDT 24
Finished Jul 29 05:23:18 PM PDT 24
Peak memory 199788 kb
Host smart-401f6fcc-7856-461d-b5b8-a96343e43004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724815395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1724815395
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2367586957
Short name T306
Test name
Test status
Simulation time 1094597418 ps
CPU time 28.79 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:22:57 PM PDT 24
Peak memory 199788 kb
Host smart-f9974613-01f0-4b9f-a0ea-387e7799f26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367586957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2367586957
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2527471300
Short name T448
Test name
Test status
Simulation time 8422540750 ps
CPU time 373.63 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:28:42 PM PDT 24
Peak memory 639580 kb
Host smart-ba3dc937-4f40-41f2-8ed0-d560003d8d9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527471300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2527471300
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2515462785
Short name T254
Test name
Test status
Simulation time 5870803053 ps
CPU time 166.35 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:25:15 PM PDT 24
Peak memory 199880 kb
Host smart-1ca7847f-739d-493e-94f9-e068506f0bc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515462785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2515462785
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.445283903
Short name T441
Test name
Test status
Simulation time 21655275878 ps
CPU time 74.46 seconds
Started Jul 29 05:22:32 PM PDT 24
Finished Jul 29 05:23:46 PM PDT 24
Peak memory 199952 kb
Host smart-a84995bb-cecf-4cbc-913f-0d22a4a94e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445283903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.445283903
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2837806683
Short name T163
Test name
Test status
Simulation time 628470030 ps
CPU time 4.82 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:22:33 PM PDT 24
Peak memory 199780 kb
Host smart-13ebb361-6d2a-48e4-ab07-9866296c44d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837806683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2837806683
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1739161076
Short name T396
Test name
Test status
Simulation time 29939111920 ps
CPU time 2393.02 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 06:02:21 PM PDT 24
Peak memory 717984 kb
Host smart-9359b198-1d2f-4c39-b5f8-8e36a961dc10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739161076 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1739161076
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.51714564
Short name T70
Test name
Test status
Simulation time 113596476485 ps
CPU time 4588 seconds
Started Jul 29 05:22:27 PM PDT 24
Finished Jul 29 06:38:55 PM PDT 24
Peak memory 812260 kb
Host smart-ba4b0c49-c521-4180-9c52-766aa0c9339e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51714564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.51714564
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4282694509
Short name T413
Test name
Test status
Simulation time 10110643969 ps
CPU time 126.28 seconds
Started Jul 29 05:22:26 PM PDT 24
Finished Jul 29 05:24:33 PM PDT 24
Peak memory 200020 kb
Host smart-001313c5-e35b-43d7-8469-27efe363137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282694509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4282694509
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2470250139
Short name T272
Test name
Test status
Simulation time 24250561 ps
CPU time 0.57 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:22:29 PM PDT 24
Peak memory 195920 kb
Host smart-9721bb90-cae0-4c2c-9cbf-40c83912c232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470250139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2470250139
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3138958290
Short name T365
Test name
Test status
Simulation time 3379028410 ps
CPU time 96.91 seconds
Started Jul 29 05:22:32 PM PDT 24
Finished Jul 29 05:24:09 PM PDT 24
Peak memory 200176 kb
Host smart-c65c8eb9-ba8f-447c-bc74-11a838d4dfcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138958290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3138958290
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.628331576
Short name T36
Test name
Test status
Simulation time 300149982 ps
CPU time 7.08 seconds
Started Jul 29 05:22:29 PM PDT 24
Finished Jul 29 05:22:36 PM PDT 24
Peak memory 199820 kb
Host smart-5efbb28a-1d4f-4ae9-9f6f-000fc43ec4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628331576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.628331576
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3634938798
Short name T79
Test name
Test status
Simulation time 2498520761 ps
CPU time 401.39 seconds
Started Jul 29 05:22:27 PM PDT 24
Finished Jul 29 05:29:09 PM PDT 24
Peak memory 615724 kb
Host smart-3702aa55-947f-4f46-8b75-065e5bd67326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634938798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3634938798
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2411052719
Short name T72
Test name
Test status
Simulation time 23542640877 ps
CPU time 142.53 seconds
Started Jul 29 05:22:25 PM PDT 24
Finished Jul 29 05:24:48 PM PDT 24
Peak memory 199960 kb
Host smart-49d807d8-ddf8-439b-a977-d6177514ce96
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411052719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2411052719
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3601914051
Short name T360
Test name
Test status
Simulation time 2631411430 ps
CPU time 46.56 seconds
Started Jul 29 05:22:26 PM PDT 24
Finished Jul 29 05:23:13 PM PDT 24
Peak memory 199960 kb
Host smart-a6d09cc0-472b-4f63-b3c4-b1e1fd38741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601914051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3601914051
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.170438421
Short name T158
Test name
Test status
Simulation time 405038525 ps
CPU time 1.29 seconds
Started Jul 29 05:22:26 PM PDT 24
Finished Jul 29 05:22:28 PM PDT 24
Peak memory 199908 kb
Host smart-4285d1ea-98d2-4f84-8b68-6b63ac4e89b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170438421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.170438421
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1471954329
Short name T92
Test name
Test status
Simulation time 47968951009 ps
CPU time 1288.82 seconds
Started Jul 29 05:22:36 PM PDT 24
Finished Jul 29 05:44:06 PM PDT 24
Peak memory 764840 kb
Host smart-4c479e4a-dd75-4e3b-ae01-0ccd39004389
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471954329 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1471954329
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2261625663
Short name T249
Test name
Test status
Simulation time 17288132340 ps
CPU time 77.88 seconds
Started Jul 29 05:22:28 PM PDT 24
Finished Jul 29 05:23:46 PM PDT 24
Peak memory 199960 kb
Host smart-8b96fa13-b866-4b90-aab5-ed781c31256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261625663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2261625663
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2960103942
Short name T447
Test name
Test status
Simulation time 12735698 ps
CPU time 0.6 seconds
Started Jul 29 05:22:41 PM PDT 24
Finished Jul 29 05:22:42 PM PDT 24
Peak memory 194876 kb
Host smart-043d631c-3238-48df-a422-fdbe9d690157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960103942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2960103942
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1206849092
Short name T457
Test name
Test status
Simulation time 346748918 ps
CPU time 20.35 seconds
Started Jul 29 05:22:34 PM PDT 24
Finished Jul 29 05:22:55 PM PDT 24
Peak memory 199840 kb
Host smart-66ae5c7d-2e2c-440b-a945-74a42888c028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206849092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1206849092
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1324479243
Short name T265
Test name
Test status
Simulation time 36334706301 ps
CPU time 63.88 seconds
Started Jul 29 05:22:37 PM PDT 24
Finished Jul 29 05:23:41 PM PDT 24
Peak memory 216360 kb
Host smart-bd8d6298-dda5-45bc-b151-1f55f13a6ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324479243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1324479243
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3358614450
Short name T369
Test name
Test status
Simulation time 8906277659 ps
CPU time 1681.34 seconds
Started Jul 29 05:22:33 PM PDT 24
Finished Jul 29 05:50:34 PM PDT 24
Peak memory 794640 kb
Host smart-6e86b5f0-33d1-4654-97c8-f97e5038a827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3358614450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3358614450
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.4090923005
Short name T24
Test name
Test status
Simulation time 42023353046 ps
CPU time 108.84 seconds
Started Jul 29 05:22:31 PM PDT 24
Finished Jul 29 05:24:20 PM PDT 24
Peak memory 199980 kb
Host smart-5677897e-a840-444e-9241-de5bfb462940
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090923005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.4090923005
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.463683695
Short name T96
Test name
Test status
Simulation time 17531364179 ps
CPU time 157.54 seconds
Started Jul 29 05:22:32 PM PDT 24
Finished Jul 29 05:25:10 PM PDT 24
Peak memory 200204 kb
Host smart-60481486-05a0-403d-8fe5-fc8900a670b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463683695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.463683695
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.251398634
Short name T280
Test name
Test status
Simulation time 888347523 ps
CPU time 13.08 seconds
Started Jul 29 05:22:27 PM PDT 24
Finished Jul 29 05:22:40 PM PDT 24
Peak memory 199880 kb
Host smart-3ae56012-1e62-4258-842f-8e079d07144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251398634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.251398634
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1077183306
Short name T221
Test name
Test status
Simulation time 324570052574 ps
CPU time 3059.21 seconds
Started Jul 29 05:22:32 PM PDT 24
Finished Jul 29 06:13:31 PM PDT 24
Peak memory 744656 kb
Host smart-687f7bfc-e528-44d3-b8b9-58fd29e19707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077183306 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1077183306
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3235364782
Short name T68
Test name
Test status
Simulation time 88295411100 ps
CPU time 684.38 seconds
Started Jul 29 05:22:35 PM PDT 24
Finished Jul 29 05:34:00 PM PDT 24
Peak memory 216064 kb
Host smart-ba254cc5-8cbe-4e3d-91e5-4fee92194dae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235364782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3235364782
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3219691519
Short name T91
Test name
Test status
Simulation time 14025330284 ps
CPU time 124.44 seconds
Started Jul 29 05:22:33 PM PDT 24
Finished Jul 29 05:24:38 PM PDT 24
Peak memory 200020 kb
Host smart-b9768598-d60e-4478-9113-e9bc286a1f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219691519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3219691519
Directory /workspace/9.hmac_wipe_secret/latest
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